Semiconductor structure and forming method thereof

Abstract

The semiconductor structure includes bit line structures laterally spaced on a substrate, buried contacts between the bit line structures, and landing pads on the buried contacts. The buried contact includes a first conductive layer and a second conductive layer on the first conductive layer. The second conductive layer includes a main portion and a protruding portion extending from the main portion into the first conductive layer. Methods of forming semiconductor structures are also disclosed. The semiconductor structure can avoid generation of holes, and contact resistance can be further reduced due to deposition of more conductive materials, so that the operation speed of the DRAM is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure and a method of forming the same. In particular, the present disclosure relates to a dynamic random-access memory (DRAM) and a method of forming the same. BACKGROUND

[0002] As technology advances, the pitch of semiconductor structures in a dynamic random-access memory (DRAM) is reduced and the integration is increased to improve the performance of the DRAM. As the distance between elements in a semiconductor device is closer, it becomes more difficult to deposit in such a reduced distance, for example, forming a hole, which can increase the resistance and reduce the operating speed of the DRAM.

[0003] Therefore, in the formation of a semiconductor device, it is important to improve the performance of the DRAM and reduce the contact resistance. SUMMARY

[0004] The present disclosure provides a semiconductor structure. The semiconductor structure includes bit line structures laterally spaced apart on a substrate, a buried contact located between the bit line structures, and a landing pad on the buried contact. The buried contact further includes a first conductive layer and a second conductive layer on the first conductive layer. The second conductive layer includes a main portion and a protruding portion extending from the main portion into the first conductive layer.

[0005] In some embodiments, the first conductive layer surrounds and contacts the protruding portion.

[0006] In some embodiments, the resistance of the second conductive layer is less than the resistance of the first conductive layer.

[0007] In some embodiments, the second conductive layer includes cobalt, and the first conductive layer includes polysilicon.

[0008] In some embodiments, the vertical thickness of the main portion is between 5 nm and 10 nm.

[0009] In some embodiments, the vertical length of the protruding portion is between 20 nm and 50 nm.

[0010] In some embodiments, the vertical length of the protruding portion is 0.6 to 1.5 times the diameter of the first conductive layer.

[0011] In some embodiments, the substrate includes an active region, and the buried contact is partially embedded in the substrate and contacts the active region.

[0012] In some embodiments, each bit line structure includes a conductive stack and an insulating layer on the conductive stack, and a top surface of the conductive stack and a top surface of the second conductive layer are substantially coplanar.

[0013] A method of forming a semiconductor structure is provided. The method includes forming bit line structures on a substrate, forming trenches between the bit line structures, forming a first conductive layer in the trenches, and forming a second conductive layer on the first conductive layer. The first conductive layer is of a different material than the second conductive layer. The second conductive layer further includes a main portion and a protruding portion extending from the main portion into the first conductive layer.

[0014] In some embodiments, forming the first conductive layer in the trenches includes depositing a material of the first conductive layer in the trenches, forming a hole in the material of the first conductive layer, and removing a top portion of the material of the first conductive layer to expose the hole.

[0015] In some embodiments, removing the top portion of the material of the first conductive layer to expose the hole is performed with a dry etch.

[0016] In some embodiments, forming the second conductive layer on the first conductive layer includes depositing a material of the second conductive layer to cover the first conductive layer and fill the hole.

[0017] In some embodiments, the second conductive layer has a lower electrical resistance than the first conductive layer.

[0018] In some embodiments, the method further includes forming a landing pad on the second conductive layer.

[0019] In some embodiments, forming the trenches in the substrate and between the bit line structures includes etching the substrate to form the trenches between the bit line structures and expose an active region of the substrate.

[0020] It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the application claimed. BRIEF DESCRIPTION OF DRAWINGS

[0021] The application can be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:

[0022] Figures 1 to 6 Cross-sectional views of various formation stages of a method of forming a semiconductor structure in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] Reference will now be made to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0024] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0025] Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" are used herein to describe the relationship of an element to another element as shown in the figures. It should be understood that these relative terms are intended to encompass different orientations of the device in addition to the orientations depicted in the figures. For example, if the device in a figure is flipped over, an element that would be described as being on the "lower" side of the other elements would be oriented to be on the "upper" side of the other elements. The exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in a figure is flipped over, an element that would be described as being "below" or "beneath" other elements would be oriented to be "above" the other elements. The exemplary term "lower" can include both "above" and "below" orientations.

[0026] As used herein, "about," "approximately," or "roughly approximately" generally refers to within about 20 percent, preferably within about 10 percent, and more preferably within about 5 percent of a given value or range. Unless otherwise specified, the values ​​mentioned are considered approximate, that is, the error or range indicated by "about," "approximately," or "roughly approximately."

[0027] Figures 1 to 6 1 is a cross-sectional view of various stages in a method of forming a semiconductor structure 10 according to some embodiments of the present disclosure.

[0028] refer to Figure 1 The method begins with step S10. Bit line structures 110 are formed on a substrate 100. The semiconductor structure 10 includes a substrate 100. The substrate 100 further includes an active region 102 and an isolation region 104 separating the active region 102. An isolation layer 106 is formed on the substrate 100, covering the top surfaces of the active region 102 and the isolation region 104, for isolating subsequently formed components from the substrate 100. The bit line structures 110 are laterally spaced apart from each other on the substrate 100. In some embodiments, each bit line structure 110 may include a conductive stack 112 and an insulating layer 114 disposed on the conductive stack 112 in a direction perpendicular to the substrate 100.

[0029] The substrate 100 may comprise silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 100 may comprise an elementary semiconductor, an alloy semiconductor, a compound semiconductor, or other suitable materials. Furthermore, the substrate 100 may optionally comprise a silicon-on-insulator (SOI) structure.

[0030] An ion implantation process may be performed on the substrate 100 to dope n-type or p-type dopants. In some embodiments, source / drain regions (in the substrate 100) are formed by doping the active region 102 with n-type or p-type dopants. Figure 1 not shown).

[0031] Isolation region 104 may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride. Isolation region 104 may be a single layer or multiple layers. In some embodiments, isolation region 104 may be formed using a shallow trench isolation (STI) process.

[0032] The isolation layer 106 may be formed of any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass (USG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), other suitable materials, or combinations thereof.

[0033] The bit line structure 110 is disposed on the substrate 100. In some embodiments, according to Figure 1 Each bit line structure 110 protrudes in a vertical direction of the substrate 100 and has a linear structure that extends in a direction parallel to the substrate 100 .

[0034] refer to Figure 2The method proceeds to step S20. Trenches 108 are formed between bit line structures 110 on substrate 100, and trenches 108 extend through isolation layer 106 to expose portions of active region 102 of substrate 100.

[0035] Trenches 108 are disposed along a direction perpendicular to substrate 100. In some embodiments, a bottom surface of trenches 108 is lower than isolation layer 106. Trenches 108 can expose portions of active region 102 for electrically connecting elements (e.g., buried contacts 116 formed later) to active region 102.

[0036] Referring to FIG. 1C, Figure 3 The method proceeds to step S30. After forming trenches 108, a first conductive layer 118 is formed in trenches 108. It is noted that the material of first conductive layer 118 is deposited in trenches 108, and at the same time, holes 120 are formed inside first conductive layer 118. Thus, each first conductive layer 118 further includes holes 120. Due to the development of semiconductor structures, the size of semiconductor structures becomes smaller, resulting in trenches having a higher aspect ratio than ever. Depositing material in trenches having such a high aspect ratio can easily form holes. It is worth mentioning that the formation of holes can cause the contact resistance of semiconductor structures to increase, and further reduce the operating speed of DRAMs. Generally speaking, holes should be avoided in the formation of semiconductor structures.

[0037] The material of first conductive layer 118 fills into portions of each trench 108 between bit line structures 110. The top of first conductive layer 118 on isolation layer 106 is surrounded by bit line structures 110. In some embodiments, a top surface of first conductive layer 118 is higher than a top surface of conductive stack 112, but lower than a top surface of bit line structure 110.

[0038] In some embodiments, the material of first conductive layer 118 can be deposited by any suitable operation, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. Furthermore, the material of first conductive layer 118 can be any suitable conductive material, such as polysilicon.

[0039] Holes 120 having an elongated shape are formed within the first conductive layer 118 along the direction of the trenches 108. In some embodiments, both ends of each hole 120 can be pointed, rounded or blunt profile, etc. Each hole 120 is surrounded by each first conductive layer 118. A portion of each first conductive layer 118 covers the top of each hole 120. Such holes 120 are not exposed to air. To avoid the presence of the holes 120, the top of the material of the first conductive layer 118 is removed to expose the holes 120, followed by forming a second conductive layer 122 on the first conductive layer 118, with reference to Figure 4 and Figure 5 .

[0040] With reference to Figure 4 , the method proceeds to step S40. After forming the first conductive layer 118, the top of the first conductive layer 118 is removed to form a first conductive layer 118' and expose the holes 120'.

[0041] The holes 120' are exposed and surrounded only by the first conductive layer 118'. In some embodiments, the top surface of the first conductive layer 118' is lower than the top surface of the conductive stack 112. In some embodiments, removing the top of the material of the first conductive layer 118 can include any suitable etching process, such as dry etching and / or wet etching, etc.

[0042] With reference to Figure 5 , the method proceeds to step S50. After removing the top of the material of the first conductive layer 118, a second conductive layer 122 is formed on the first conductive layer 118'. To eliminate the holes 120 and improve the contact resistance, the second conductive layer 122 is disposed on the first conductive layer 118' and further fills the holes 120' (as shown in Figure 4 In some embodiments, the holes 120' are filled with the second conductive layer 122 without any voids.

[0043] Each second conductive layer 122 further includes a main portion 124 and a protruding portion 126 extending from the main portion 124 into each first conductive layer 118'. The main portion 124 covers the first conductive layer 118'. In some embodiments, a top surface of the main portion 124 is coplanar with a top surface of the conductive stack 112. The protruding portion 126 is formed by filling the second conductive layer 122 into the hole 120'. The protruding portion 126 is surrounded by and in contact with the first conductive layer 118'. For example, each main portion 124 has a vertical thickness Tl in a direction perpendicular to the substrate 100. The vertical thickness Tl of the main portion 124 is between about 5 nm and about 10 nm. Each protruding portion 126 has a vertical length Ll in a direction perpendicular to the substrate 100. The vertical length Ll of the protruding portion 126 is between about 20 nm and about 50 nm. Further, each first conductive layer 118' has a diameter Dl in a plane parallel to the substrate 100. The vertical length Ll of the protruding portion 126 is about 0.6 times to about 1.5 times the diameter Dl of the first conductive layer 118'.

[0044] The material of the first conductive layer 118' can be the same as or different from the material of the second conductive layer 122. In some embodiments, the material of the first conductive layer 118' is the same as the material of the second conductive layer 122, such as polysilicon. Although the hole 120' is filled with the same material, a higher contact resistance can still result. In some embodiments, the material of the first conductive layer 118' is different from the material of the second conductive layer 122. For example, the first conductive layer 118' can include polysilicon, and the second conductive layer 122 can include cobalt. The material of the second conductive layer 122 has a lower resistance than the material of the first conductive layer 118'. That is, the second conductive layer 122 has a lower resistance than the first conductive layer 118'. In this way, the material of the second conductive layer 122 having a lower resistance than the material of the first conductive layer 118' is deposited into the hole 120', and the contact resistance can be further reduced due to the presence of more conductive material. Thus, the operating speed of the DRAM can be improved. In some embodiments, the material of the second conductive layer 122 can be deposited by other suitable processes, such as CVD, ALD, PVD, etc.

[0045] Referring to Figure 6 , the method proceeds to step S60. After the second conductive layer 122 is formed, a landing pad 128 is formed on the second conductive layer 122 between the bit line structures 110 and covers a portion of the bit line structures 110.

[0046] A landing pad 128 is deposited to fill the remaining trench 108' between the bit line structures 110. The top surface of the landing pad 128 is higher than the top surface of the bit line structures 110. The bottom surface of the landing pad 128 contacts the top surface of the second conductive layer 122. The sidewalls of the landing pad 128 in the trench 108' contact the sidewalls of the bit line structures 110.

[0047] In some embodiments, the material of the landing pad 128 can include a conductive material, such as tungsten, copper, aluminum, an alloy, or other suitable conductive material. The material of the landing pad 128 can be blanket deposited. The deposition operation can include any suitable deposition operation, such as CVD, PVD, ALD, etc.

[0048] In Figure 6 , a semiconductor structure 10 is formed by a method of forming a semiconductor structure. The semiconductor structure 10 includes a substrate 100 including an active region 102 and an isolation region 104 spaced apart from the active region 102. An isolation layer 106 is deposited on the top surface of the active region 102 and the isolation region 104. Bit line structures 110 are laterally disposed on the isolation layer 106 on the substrate 100 and spaced apart from each other. Buried contacts 116 are disposed between the bit line structures 110 and the landing pad 128 is formed on the buried contacts 116 and covers portions of the bit line structures 110.

[0049] According to Figure 6 , each bit line structure 110 includes a conductive stack 112 and an insulating layer 114 on the conductive stack 112 in a plane perpendicular to the substrate 100. The bottom of the buried contact 116 is embedded in the substrate 100 and partially contacts the active region 102.

[0050] Each buried contact 116 further includes a first conductive layer 118' and a second conductive layer 122 on the first conductive layer 118' in a cross-sectional view in a plane perpendicular to the substrate 100. The first conductive layer 118' includes a hole 120' extending from the top surface of the first conductive layer 118'. To eliminate the hole 120', the second conductive layer 122 is disposed on the first conductive layer 118' and fills in the first conductive layer 118'. Due to the presence of the hole 120', the contact resistance of the semiconductor structure 10 can be increased. Each second conductive layer 122 further includes a main portion 124 and a protruding portion 126. The protruding portion 126 extends from the main portion 124 and into the first conductive layer 118'. That is, the bottom surface of the main portion 124 contacts the top surface of the first conductive layer 118'. The protruding portion 126 is surrounded by and in contact with the first conductive layer 118'. In some embodiments, the top surface of the main portion 124 and the top surface of the conductive stack 112 are coplanar.

[0051] In a plane perpendicular to the substrate 100, each main portion 124 has a vertical thickness T1 and each protruding portion 126 has a vertical length L1. In some embodiments, the vertical thickness T1 of the main portion 124 is between about 5 nm and about 10 nm. The vertical length L1 of the protruding portion 126 is between about 20 nm and about 50 nm. Further, in a plane parallel to the substrate 100, a cross-sectional view of each first conductive layer 118' has a diameter D1. In some embodiments, the diameter D1 along the buried contact 116 is uniform. The vertical length L1 of the protruding portion 126 is about 0.6 times to about 1.5 times the diameter D1 of the first conductive layer 118'.

[0052] A material of the second conductive layer 122 can be disposed on the first conductive layer 118'. Further, the material of the second conductive layer 122 can be the same as or different from the material of the first conductive layer 118'. In some embodiments, the material of the first conductive layer 118' can be selected from polysilicon, and the material of the second conductive layer 122 can be selected from cobalt, such that the resistance of the second conductive layer 122 is lower than the resistance of the first conductive layer 118'. The second conductive layer 122 using the material with lower resistance can reduce the contact resistance to further improve the operating speed of the DRAM.

[0053] A landing pad 128 is disposed on the buried contact 116, as shown. Figure 6 The landing pad 128 can be electrically connected to the buried contact 116, and further connect the storage node / capacitor of the bottom electrode (not shown) to the active area 102. In other words, the storage node / capacitor of the bottom electrode (not shown) is electrically connected to the active area 102 through the buried contact 116.

[0054] While the disclosure has been described in detail with respect to certain embodiments thereof, it will be apparent to those skilled in the art that other embodiments of the disclosure exist. Therefore, the scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0055] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of the disclosure provided they fall within the scope of the appended claims.

[0056] [SYMBOL DESCRIPTION]

[0057] S10, S20, S30, S40, S50, S60: Step 10: Semiconductor structure

[0058] 100: Substrate

[0059] 102: Active area

[0060] 104: isolation region

[0061] 106: isolation layer

[0062] 108, 108': trench

[0063] 110: bitline structure

[0064] 112: conductive stack

[0065] 114: insulating layer

[0066] 116: buried contact

[0067] 118, 118': first conductive layer

[0068] 120, 120': hole

[0069] 122: second conductive layer

[0070] 124: main portion

[0071] 126: protruding portion

[0072] 128: landing pad

[0073] T1: thickness

[0074] L1: length

[0075] D1: diameter

Claims

1. A semiconductor structure, characterized by, comprise: a plurality of bitline structures laterally spaced apart on a substrate; a buried contact between the plurality of bitline structures, wherein the buried contact comprises: a first conductive layer; and a second conductive layer on the first conductive layer, wherein the second conductive layer comprises: a main portion; and a protruding portion extending from the main portion into the first conductive layer; and a landing pad on the buried contact.

2. The semiconductor structure of claim 1, wherein the first conductive layer surrounds and contacts the protruding portion.

3. The semiconductor structure of claim 1, wherein a resistance of the second conductive layer is less than a resistance of the first conductive layer.

4. The semiconductor structure of claim 1, wherein the second conductive layer comprises cobalt and the first conductive layer comprises polysilicon.

5. The semiconductor structure of claim 1, wherein a vertical thickness of the main portion is between 5 nm and 10 nm.

6. The semiconductor structure of claim 1, wherein a vertical length of the protruding portion is between 20 nm and 50 nm.

7. The semiconductor structure of claim 1, wherein the vertical length of the protruding portion is 0.6 times to 1.5 times a diameter of the first conductive layer.

8. The semiconductor structure of claim 1, wherein the substrate comprises an active region, the buried contact partially embedded in the substrate and contacting the active region.

9. The semiconductor structure of claim 1, wherein each of the bitline structures comprises a conductive stack and an insulating layer on the conductive stack, and a top surface of the conductive stack and a top surface of the second conductive layer are substantially coplanar.

10. A method of forming a semiconductor structure, comprising: comprising: forming a plurality of bitline structures on a substrate; forming a trench in the substrate and between the plurality of bitline structures; forming a first conductive layer in the trench; and forming a second conductive layer on the first conductive layer, wherein a material of the first conductive layer is different from a material of the second conductive layer, and the second conductive layer comprises: a main portion; and a protruding portion extending from the main portion into the first conductive layer.

11. The method of claim 10, wherein forming the first conductive layer in the trench comprises: depositing the material of the first conductive layer in the trench, wherein a hole is formed within the material of the first conductive layer; and removing a top portion of the material of the first conductive layer to expose the hole.

12. The method of claim 11, wherein removing the top portion of the material of the first conductive layer to expose the hole is performed with a dry etch.

13. The method of claim 11, wherein forming the second conductive layer on the first conductive layer comprises: depositing the material of the second conductive layer to cover the first conductive layer and fill in the hole.

14. The method of claim 10, wherein a resistance of the second conductive layer is less than a resistance of the first conductive layer. further comprising forming a landing pad on the second conductive layer.

15. The method of claim 10, wherein, ​ 16. The method of claim 10, wherein forming the trench in the substrate and between the plurality of bit line structures comprises: etching the substrate to form the trench between the plurality of bit line structures and expose an active region of the substrate.

Images