Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate including an active pattern; the bit line is positioned on the substrate and is crossed with the active pattern; a bit line contact disposed between the bit line and the active pattern; a first silicide layer, wherein the first silicide layer is arranged between the bit line contact and the bit line; and a second silicide layer, wherein the second silicide layer is arranged between the first silicide layer and the bit line. Each of the first silicide layer and the second silicide layer includes a first metal element, silicon (Si), and nitrogen (N). The first silicide layer has a first nitrogen concentration, and the second silicide layer has a second nitrogen concentration greater than the first nitrogen concentration.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a silicide layer. BACKGROUND

[0002] A semiconductor device includes an integrated circuit having a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rule of the semiconductor device gradually decrease, the MOSFET is being rapidly scaled down in size. The scaled-down size of the MOSFET can cause a short channel effect, thereby degrading the operating characteristics of the semiconductor device. Therefore, various methods for forming a semiconductor device having better performance by overcoming limitations due to an increase in the integration density of the semiconductor device have been continuously researched. SUMMARY

[0003] One or more example embodiments provide a semiconductor device having improved reliability and electrical characteristics.

[0004] According to an aspect of example embodiments, a semiconductor device includes a substrate including an active pattern, a bit line located on the substrate to cross the active pattern, a bit line contact disposed between the bit line and the active pattern, a first silicide layer disposed between the bit line contact and the bit line, and a second silicide layer disposed between the first silicide layer and the bit line. Each of the first silicide layer and the second silicide layer includes a first metal element, silicon (Si), and nitrogen (N). The first silicide layer has a first nitrogen concentration, and the second silicide layer has a second nitrogen concentration greater than the first nitrogen concentration.

[0005] According to another aspect of example embodiments, a semiconductor device includes a substrate including an active pattern, a bit line located on the substrate to cross the active pattern, a bit line contact disposed between the bit line and the active pattern, and a silicide layer disposed between the bit line contact and the bit line, the silicide layer including a first region adjacent to the bit line contact and a second region adjacent to the bit line. The silicide layer includes a first metal element, silicon (Si), and nitrogen (N). A nitrogen concentration of the silicide layer increases upward along a direction perpendicular to an upper surface of the substrate.

[0006] According to another aspect of example embodiments, a semiconductor device includes: a device isolation pattern defining a plurality of active patterns on a substrate; a plurality of word lines crossing the plurality of active patterns on the substrate; a plurality of bit lines crossing the plurality of active patterns and intersecting the plurality of word lines; a bit line contact disposed between a central portion of one of the plurality of active patterns and one of the plurality of bit lines; a first silicide layer disposed between the bit line contact and the one of the plurality of bit lines; a second silicide layer disposed between the first silicide layer and the one of the plurality of bit lines; a storage node contact disposed on the plurality of active patterns on both sides of the one of the plurality of bit lines; a landing pad on the storage node contact; and a data storage pattern on the landing pad. Each of the first silicide layer and the second silicide layer includes a metal element, silicon (Si), and nitrogen (N). The first silicide layer has a first nitrogen concentration, and the second silicide layer has a second nitrogen concentration greater than the first nitrogen concentration. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above described and other aspects and features are achieved by example embodiments, which will become apparent from the following description taken in conjunction with the accompanying drawings, by the way of example, in which: Figure 1A is a plan view of a semiconductor device according to example embodiments; Figure 1B is a view illustrating a semiconductor device according to example embodiments, and is a plan view corresponding to a region "M" of Figure 1A ; Figure 2 is a view illustrating a semiconductor device according to example embodiments, and is a plan view corresponding to a region "M1" of Figure 1B ; Figure 3 is a view illustrating a semiconductor device according to example embodiments, and is a cross-sectional view corresponding to a line A-A' of Figure 2 ; Figure 4 is a view illustrating a semiconductor device according to example embodiments, and is a cross-sectional view corresponding to a line B-B' of Figure 2 ; Figure 5 and Figure 6 is a view illustrating a semiconductor device according to example embodiments, and is a plan view corresponding to a region "M2" of Figure 4 ; Figure 7 is a view illustrating a semiconductor device according to example embodiments, and is a plan view corresponding to a region "M2" ofFigure 2 A cross-sectional view corresponding to the line AA' in FIG. Figure 8 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 2 The cross-sectional view corresponding to the line BB' in FIG. Figure 9 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 8 The enlarged image corresponding to the area “M3” in FIG; Figure 10 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 2 A cross-sectional view corresponding to the line AA' in FIG. Figure 11 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 2 The cross-sectional view corresponding to the line BB' in FIG. Figure 12 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 11 The enlarged image corresponding to the area "M4" in the figure; Figure 13 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 2 A cross-sectional view corresponding to the line AA' in FIG. Figure 14 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 2 The cross-sectional view corresponding to the line BB' in FIG. Figure 15 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 14 The enlarged image corresponds to the area "M5" in the figure. DETAILED DESCRIPTION

[0008] Hereinafter, example embodiments are described in detail with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the specification, and repeated description thereof is omitted. It will be understood that when a component or layer is referred to as being "on" another component or layer, "connected to" or "coupled to" another component or layer, it can be directly on, connected or coupled to the other component or layer, or intervening components or layers can be present. In contrast, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component or layer, there are no intervening components or layers present. Expressions such as "at least one of... and" and "one or more of... " when preceding a list of two or more items, modify the entire list of items and do not modify the individual items of the list. For example, the phrase "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. The embodiments described herein are example embodiments, and thus the present disclosure is not limited thereto and can be implemented in various other forms. Each of the example embodiments provided in the following description are not mutually exclusive of one or more features of another example or another embodiment provided herein or not provided herein but consistent with the present disclosure.

[0009] Figure 1A is a plan view of a semiconductor device according to an example embodiment. Figure 1B is a view illustrating a semiconductor device according to an example embodiment, and is a plan view corresponding to a region "M" of Figure 1A is an enlarged view of the region "M" of

[0010] Referring to Figure 1A and Figure 1B , the semiconductor device 1 can include a plurality of memory banks BA and a peripheral region PER. The peripheral region PER can be disposed between the memory banks BA. A peripheral circuit for inputting / outputting data or a command or inputting power / ground can be disposed in the peripheral region PER.

[0011] Each memory bank BA can include a cell block region CR and an extension region EXT located between the cell block regions CR. Each cell block region CR can include a memory cell array, a sense amplifier region, and a sub word line driver region. A sense amplifier (i.e., a sense amplifier circuit) can be disposed in the sense amplifier region. A sub word line driver (i.e., a sub word line driver circuit) can be disposed in the sub word line driver region.

[0012] Figure 2 is a view illustrating a semiconductor device according to an example embodiment, and is a plan view corresponding to a region "M1" of Figure 1B is an enlarged view of the region "M1" of Figure 3is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 2 The cross-sectional view corresponding to the line AA' in FIG. Figure 4 is a view illustrating a semiconductor device according to example embodiments, and is similar to Figure 2 The cross-sectional view corresponding to the line BB' in FIG.

[0013] refer to Figures 2 to 4 , device isolation patterns STI may be provided on the substrate 100. The device isolation patterns STI may define active patterns ACT on the substrate 100. Each active pattern ACT may protrude in a third direction D3 perpendicular to the substrate 100. As an example, the device isolation patterns STI may be provided in the substrate 100, and the active pattern ACT may be a portion of the substrate 100 surrounded by the device isolation patterns STI. For ease of explanation, unless otherwise specified, in this example embodiment, the substrate 100 is defined as referring to other portions of the substrate 100 excluding the active patterns ACT.

[0014] The active patterns ACT may be arranged to be spaced apart from each other in the first direction D1 and the second direction D2. Each active pattern ACT may have an island shape separated from the other active patterns ACT and may have a bar shape elongated in the fourth direction D4. The fourth direction D4 may be parallel to the lower surface of the substrate 100 and may intersect the first direction D1 and the second direction D2.

[0015] Each active pattern ACT may include a pair of edge portions EA and a central portion CA. The pair of edge portions EA may be both ends of the active pattern ACT in the fourth direction D4. The central portion CA may be a portion of the active pattern ACT between the pair of edge portions EA, and more specifically, may be a portion of the active pattern ACT between a pair of word lines WL, which will be described later. Each of the pair of edge portions EA and the central portion CA may include an impurity region doped with impurities (e.g., n-type impurities or p-type impurities).

[0016] The device isolation pattern STI may include an insulating material. As an example, the device isolation pattern STI may include at least one of silicon oxide and silicon nitride. As an example, the device isolation pattern STI may be a single layer formed of any of the above materials or a composite layer formed of two or more materials.

[0017] The word line WL can cross the active pattern ACT. As an example, the word line WL can cross the active pattern ACT and the device isolation pattern STI in the first direction D1. A plurality of word lines WL can be provided. The plurality of word lines WL can be spaced apart from each other in the second direction D2. For example, pairs of word lines WL adjacent to each other in the second direction D2 can cross one active pattern ACT.

[0018] For example, each word line WL can include a gate electrode GE, a gate insulating pattern GI, and a gate cover pattern GC. The gate electrode GE can cross the active pattern ACT and the device isolation pattern STI in the first direction D1. The gate insulating pattern GI can be interposed between the gate electrode GE and the active pattern ACT. The gate cover pattern GC can cover an upper surface of the gate electrode GE.

[0019] A buffer pattern 210 can be provided on the substrate 100. The buffer pattern 210 can cover the active pattern ACT, the device isolation pattern STI, and the word line WL. As an example, the buffer pattern 210 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buffer pattern 210 can be a single layer formed of a single material or a composite layer including two or more materials.

[0020] A bit line contact DC can be provided on each active pattern ACT, and the bit line contact DC can be provided as a plurality. Each bit line contact DC can be connected to a corresponding one of the central portions CA of the active pattern ACT. The bit line contacts DC can be spaced apart from each other in the first direction D1 and the second direction D2. The bit line contact DC can be interposed between the active pattern ACT and a bit line BL to be described later. The bit line contact DC can connect a corresponding bit line BL among the bit lines BL and the central portion CA of the corresponding active pattern ACT. As an example, the bit line contact DC can include polysilicon doped with impurities.

[0021] The bit line contacts DC can be respectively provided in first recessed regions RS1. The first recessed regions RS1 can be provided on the active pattern ACT and the device isolation pattern STI adjacent to the active pattern ACT. The first recessed regions RS1 can be spaced apart from each other in the first direction D1 and the second direction D2.

[0022] The buried insulating pattern 250 can fill each first recessed region RS1 around the bit line contact DC. The buried insulating pattern 250 can fill an interior of the first recessed region RS1. As an example, the buried insulating pattern 250 can cover at least a portion of an inner surface of the first recessed region RS1 and at least a portion of a side surface of the bit line contact DC (e.g., at least a portion of the side surface of the bit line contact DC in the first recessed region RS1). The buried insulating pattern 250 can include at least one of silicon oxide, silicon nitride, or a combination thereof. The buried insulating pattern 250 can be a single layer formed of a single material or a composite layer including two or more materials.

[0023] The bit line BL can be disposed on the bit line contact DC. The bit line BL can be disposed on a row of the bit line contacts DC arranged along the second direction D2. A plurality of bit lines BL can be disposed. The bit lines BL can be spaced apart from each other in the first direction D1. The bit line BL crosses the active pattern ACT and intersects the word line. The bit line BL can include a metal element. As an example, the metal element can be any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.

[0024] The polysilicon pattern 310 can be interposed between the bit line BL and the buffer pattern 210. An upper surface of the polysilicon pattern 310 can be positioned at substantially the same height as an upper surface of the bit line contact DC. The polysilicon pattern 310 can include polysilicon doped with an impurity.

[0025] The ohmic pattern 320 can be interposed between the bit line BL and the bit line contact DC and between the bit line BL and the polysilicon pattern 310. The ohmic pattern 320 can include a first silicide layer SC1 and a second silicide layer SC2. The first silicide layer SC1 and the second silicide layer SC2 can vertically overlap the corresponding polysilicon pattern 310 or the bit line contact DC. The first silicide layer SC1 can be interposed between the second silicide layer SC2 and the bit line contact DC and between the second silicide layer SC2 and the polysilicon pattern 310. The second silicide layer SC2 can be interposed between the first silicide layer SC1 and the bit line BL. Each of the first silicide layer SC1 and the second silicide layer SC2 can include a metal element (e.g., any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), silicon (Si), and nitrogen (N).

[0026] Bit line cover patterns 350 can be disposed on the bit lines BL. As an example, each bit line cover pattern 350 can be disposed on an upper surface of a corresponding bit line BL. As an example, the bit line cover patterns 350 can each extend along the corresponding bit line BL in the second direction D2 and can be spaced apart from one another in the first direction Dl. Each bit line cover pattern 350 can vertically overlap the corresponding bit line BL. The bit line cover patterns 350 can be composed of a single layer or multiple layers. As an example, the bit line cover patterns 350 can include a first cover pattern, a second cover pattern, and a third cover pattern that are sequentially stacked. As an example, each of the first cover pattern through the third cover pattern can include silicon nitride. As another example, the bit line cover patterns can further include additional cover patterns such as a fourth cover pattern and a fifth cover pattern.

[0027] Bit line spacers 360 can be disposed on side surfaces of the bit lines BL and side surfaces of the bit line cover patterns 350. Each bit line spacer 360 can cover the side surfaces of the bit line BL and the side surfaces of the bit line cover patterns 350. The bit line spacers 360 can extend along the second direction D2 on the side surfaces of the bit lines BL.

[0028] Each bit line spacer 360 can include a plurality of sub-spacers. As an example, each bit line spacer 360 can include three or more layers of sub-spacers that are sequentially disposed on the side surfaces of the bit line BL. For example, each sub-spacer can independently include at least one of silicon nitride, silicon oxide, and silicon oxynitride. As another example, at least some of the sub-spacers can include an air gap that separates other sub-spacers from one another.

[0029] Storage node contacts BC can be disposed between adjacent bit lines BL. A plurality of storage node contacts BC can be disposed and the storage node contacts BC can be spaced apart from one another in the first direction Dl and the second direction D2. The storage node contacts BC can fill the second recessed regions RS2 located on the edge portions EA of the active patterns ACT. The storage node contacts BC can be electrically connected to the edge portions EA. The storage node contacts BC can include a conductive material. As an example, the storage node contacts BC can include polysilicon with impurities and at least one of metal elements (e.g., any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.).

[0030] Fence patterns FN can separate the storage node contacts BC from one another along the second direction D2 on the word lines WL. As an example, the fence patterns FN can be spaced apart from one another in the second direction D2 and the storage node contacts BC are interposed between the fence patterns FN. As an example, the fence patterns FN can include silicon nitride.

[0031] The barrier pattern 410 can conformally cover the storage node contact BC and the bit line spacer 360. The barrier pattern 410 can include a conductive metal nitride. The metal element of the metal nitride can be any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc. A metal silicide layer can be further interposed between the barrier pattern 410 and the storage node contact BC.

[0032] The landing pad LP can be disposed on the storage node contact BC. A plurality of landing pads LP can be disposed, and the landing pads LP can be spaced apart from each other in the first direction D1 and the second direction D2. The landing pad LP can be connected to the corresponding storage node contact BC. The landing pad LP can cover an upper surface of the bit line coverage pattern 350. For example, a lower portion of the landing pad LP can vertically overlap the storage node contact BC, and an upper portion of the landing pad LP can be shifted from the lower portion in the second direction D2 or an opposite direction. The landing pad LP can include a metal element (e.g., any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.).

[0033] The fill pattern 440 can surround the landing pad LP. The fill pattern 440 can be interposed between adjacent landing pads LP. When viewed in a top-down view, the fill pattern 440 can have a mesh shape including holes that are penetrated by the landing pad LP. As an example, the fill pattern 440 can include at least one of silicon nitride, silicon oxide, and silicon oxynitride. As another example, the fill pattern 440 can include empty spaces that include an air layer (i.e., an air gap).

[0034] The data storage pattern DSP can be disposed on the landing pad LP. A plurality of data storage patterns DSP can be disposed. The plurality of data storage patterns DSP can be spaced apart from each other in the first direction D1 and the second direction D2. Each data storage pattern DSP can be connected to the corresponding edge portion EA through the corresponding landing pad LP and the corresponding storage node contact BC.

[0035] The data storage pattern DSP can be, for example, a capacitor including a lower electrode, a dielectric layer, and an upper electrode. In this case, the semiconductor memory device can be a dynamic random access memory (DRAM). As another example, the data storage pattern DSP can include a magnetic tunnel junction pattern. In this case, the semiconductor memory device can be a magnetic random access memory (MRAM). As another example, the data storage pattern DSP can include a phase change material or a variable resistance material. In this case, the semiconductor memory device can be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). However, example embodiments are not limited thereto, and the data storage pattern DSP can include various structures and / or materials capable of storing data.

[0036] Figure 5 is a view illustrating a semiconductor device according to an example embodiment, and is a close-up view corresponding to a region "M2" in Figure 4 .

[0037] Referring to Figure 5 , a first silicide layer SC1 and a second silicide layer SC2 can be interposed between the bit line BL and the bit line contact DC. The first silicide layer SC1 can have a first thickness TH1 in a third direction D3 perpendicular to the substrate 100, and the second silicide layer SC2 can have a second thickness TH2 in the third direction D3. The first thickness TH1 and the second thickness TH2 can be substantially the same. The sum of the first thickness TH1 and the second thickness TH2 can be greater than 0 nm and less than or equal to 5 nm.

[0038] As an example, the ratio of silicon (Si) to a metal element (e.g., any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.) can be 0.5 to 3 (greater than or equal to 0.5 and less than or equal to 3) for each of the first silicide layer SC1 and the second silicide layer SC2.

[0039] The first silicide layer SC1 can have a first nitrogen concentration, and the second silicide layer SC2 can have a second nitrogen concentration. The first nitrogen concentration can be defined as an elemental ratio of nitrogen (N) in the first silicide layer SC1, and the second nitrogen concentration can be defined as an elemental ratio of nitrogen (N) in the second silicide layer SC2. The second nitrogen concentration of the second silicide layer SC2 can be greater than the first nitrogen concentration of the first silicide layer SC1.

[0040] The first silicide layer SCI and the second silicide layer SC2 can be formed by a deposition process and a thermal treatment process. For example, the deposition process can be a physical vapor deposition (PVD) process or a physical vapor deposition (PVD) sputtering process. As an example, in the PVD process, nitrogen gas (N2) can be used. During the deposition process, the flow rate of the nitrogen gas (N2) can be adjusted to independently control the first nitrogen concentration in the first silicide layer SCI and the second nitrogen concentration in the second silicide layer SC2.

[0041] For example, a nitrogen plasma treatment process can be used to control the first nitrogen concentration and the second nitrogen concentration. The nitrogen plasma treatment process can initially control the first nitrogen concentration to be greater than 0 at% and less than or equal to 32 at%. The nitrogen plasma treatment process can increase the second nitrogen concentration of the second silicide layer SC2 to 44 at% or above. That is, by the nitrogen plasma treatment process, the nitrogen concentration in the first silicide layer SCI can be initially controlled to a relatively low level, and the nitrogen concentration in the second silicide layer SC2 can be increased. For example, by the nitrogen plasma treatment process, the nitrogen concentration of the second silicide layer SC2 can be increased from 32 at% or below (i.e., for the first silicide layer SCI) to 44 at% to 70 at% (i.e., for the second silicide layer SC2). As another example, by the nitrogen plasma treatment process, the nitrogen concentration of the second silicide layer SC2 can be increased from 44 at% to greater than 44 at% and less than or equal to 70 at%.

[0042] In some example embodiments, the first nitrogen concentration can be greater than 0 at% and less than or equal to 32 at%, and the second nitrogen concentration can be greater than or equal to 44 at% and less than or equal to 70 at%. More preferably, the first nitrogen concentration can be greater than 0 at% and less than or equal to 24 at%.

[0043] For example, the contact resistance between the bit line BL and the bit line contact DC can be reduced in a range where the first nitrogen concentration is greater than 0 at% and less than or equal to 32 at%, as compared to when the first nitrogen concentration is greater than 32 at%.

[0044] The nitrogen concentration in the second silicide layer SC2 can affect the grain size and sheet resistance of the bit line BL. For example, the grain size of the bit line BL can be larger when the second nitrogen concentration is greater than or equal to 44 at% and less than or equal to 70 at% than when the second nitrogen concentration is 0 at%. Accordingly, the sheet resistance of the bit line BL can be reduced when the second nitrogen concentration is greater than or equal to 44 at% and less than or equal to 70 at%, thereby reducing signal transmission delay (RC delay). As an example, the bit line BL can include tungsten (W), and in this case, the array of (110)-oriented tungsten (W) crystals having low resistance characteristics inside the bit line BL can increase in the range where the second nitrogen concentration is greater than or equal to 44 at% and less than or equal to 70 at%. As a result, the sheet resistance of the bit line BL can be reduced when the second nitrogen concentration is greater than or equal to 44 at% and less than or equal to 70 at%, thereby reducing signal transmission delay (RC delay).

[0045] That is, when the first nitrogen concentration of the first silicide layer SC1 has a value in the range of greater than 0 at% and less than or equal to 32 at%, and the second nitrogen concentration of the second silicide layer SC2 has a value in the range of greater than or equal to 44 at% and less than or equal to 70 at%, the contact resistance between the bit line BL and the bit line contact DC can be reduced, and at the same time, the sheet resistance of the bit line BL can be reduced. As a result, the total resistance including the bit line BL, the ohmic pattern 320, and the bit line contact DC can be reduced, and signal transmission delay (RC delay) can be reduced.

[0046] In another example, the first nitrogen concentration can be 0 at%, and the second nitrogen concentration can be greater than or equal to 44 at% and less than or equal to 70 at%. In more detail, the first silicide layer SC1 can not include nitrogen (N).

[0047] That is, the first silicide layer SC1 not including nitrogen (N) can be disposed on the bit line contact DC, and the second nitrogen concentration of the second silicide layer SC2 can have a value in the range of greater than or equal to 44 at% and less than or equal to 70 at%.

[0048] Figure 6 is a view illustrating a semiconductor device according to an example embodiment, and is a close-up view corresponding to the region "M2" in Figure 4 will mainly describe differences from the semiconductor device according to the above-described example embodiment. Detailed description of configurations identical / similar to those described above can be omitted for the sake of brief description.

[0049] Reference will be made to Figure 6The first thickness TH1 of the first silicide layer SC1 can be greater than a second thickness TH2 of the second silicide layer SC2. A ratio of the second thickness TH2 to the first thickness TH1 can be less than or equal to 1 and greater than or equal to 0.9.

[0050] The resistance of the first silicide layer SC1 can be less than the resistance of the second silicide layer SC2. Accordingly, the resistance of the ohmic pattern 320 can be reduced in a range where the ratio of the second thickness TH2 to the first thickness TH1 is 1 or less.

[0051] Figure 7 is a view illustrating a semiconductor device according to an example embodiment, and is a cross-sectional view corresponding to line A-A' of Figure 2 . Figure 8 is a view illustrating a semiconductor device according to an example embodiment, and is a cross-sectional view corresponding to line B-B' of Figure 2 . Figure 9 is a view illustrating a semiconductor device according to an example embodiment, and is an enlarged view corresponding to a region "M3" of Figure 8 . Differences from the above-described semiconductor device will be mainly described. Detailed description of configurations identical / similar to those described above can be omitted for the sake of brief description.

[0052] Referring to Figures 7 to 9 , the ohmic pattern 320 can include a first silicide layer SC1, a second silicide layer SC2, and a metal barrier layer BM.

[0053] The metal barrier layer BM can be interposed between the first silicide layer SC1 and the bit line contact DC and between the first silicide layer SC1 and the polysilicon pattern 310. The metal barrier layer BM can extend in the second direction D2 along the bit line BL. A plurality of metal barrier layers BM can be provided. The plurality of metal barrier layers BM can be spaced apart from each other in the first direction D1. The metal barrier layer BM can include a metal material (e.g., any one or any combination of Ti, Ta, Ni, Pt, Rh, Ir, Mo, Co, etc.). As an example, the metal barrier layer BM can include TiSiN.

[0054] Figure 10 is a view illustrating a semiconductor device according to an example embodiment, and is a cross-sectional view corresponding to line A-A' of Figure 2 . Figure 11 is a view illustrating a semiconductor device according to an example embodiment, and is a cross-sectional view corresponding to line B-B' of Figure 2 . Figure 12 is a view illustrating a semiconductor device according to an example embodiment, and is an enlarged view corresponding to a region "M3" of Figure 11The enlarged view of the region "M4" in FIG. 12B will be described. Differences from the above-described semiconductor device will be mainly described. Detailed description of configurations identical / similar to those described above can be omitted for the sake of simplicity of explanation.

[0055] Reference Figures 10 to 12 The ohmic pattern 320 can include a metal element (e.g., any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), silicon (Si), and nitrogen (N). The ohmic pattern 320 can include a first region SARI in contact with the bit line contact upper surface DCH, a third region SAR3 in contact with the bit line lower surface BLL, and a second region SAR2 between the first region SARI and the third region SAR3. The thickness of the ohmic pattern 320 in the third direction D3 can be greater than 0 nm and less than or equal to 5 nm.

[0056] The first region SARI can have a first nitrogen concentration, the second region SAR2 can have a second nitrogen concentration, and the third region SAR3 can have a third nitrogen concentration. The first nitrogen concentration can be defined as an elemental ratio of nitrogen (N) in the first region SARI, the second nitrogen concentration can be defined as an elemental ratio of nitrogen (N) in the second region SAR2, and the third nitrogen concentration can be defined as an elemental ratio of nitrogen (N) in the third region SAR3. In the ohmic pattern 320, the first region SARI, the second region SAR2, and the third region SAR3 can be distinguished by the nitrogen concentration of each region.

[0057] The nitrogen concentration can increase from the first region SARI to the third region SAR3. That is, the second nitrogen concentration can be equal to or greater than the first nitrogen concentration, and the third nitrogen concentration can be greater than the second nitrogen concentration. In one example embodiment, the first nitrogen concentration can be greater than 0 at% and less than or equal to 32 at%, the third nitrogen concentration can be greater than or equal to 44 at% and less than or equal to 70 at%, and the second nitrogen concentration can have a numerical range greater than or equal to the first nitrogen concentration and less than or equal to the third nitrogen concentration.

[0058] For example, a nitrogen plasma treatment process can be used to deposit the ohmic pattern 320.

[0059] Figure 13 FIG. 12A is a view illustrating a semiconductor device according to an example embodiment, and is a plan view corresponding to a region "M4" in FIG. 12B. Differences from the above-described semiconductor device will be mainly described. Detailed description of configurations identical / similar to those described above can be omitted for the sake of simplicity of explanation. Figure 2 FIG. 12B is a cross-sectional view corresponding to a line A-A' in FIG. 12A. Figure 14 FIG. 13A is a view illustrating a semiconductor device according to an example embodiment, and is a plan view corresponding to a region "M4" in FIG. 13B. Differences from the above-described semiconductor device will be mainly described. Detailed description of configurations identical / similar to those described above can be omitted for the sake of simplicity of explanation. Figure 2 FIG. 13B is a cross-sectional view corresponding to a line B-B' in FIG. 13A. Figure 15 FIG. 14A is a view illustrating a semiconductor device according to an example embodiment, and is a plan view corresponding to a region "M4" in FIG. 14B. Differences from the above-described semiconductor device will be mainly described. Detailed description of configurations identical / similar to those described above can be omitted for the sake of simplicity of explanation. Figure 14The region "M5" in FIG. 3B corresponds to a magnified view. Differences from the above-described semiconductor device will be mainly described. Detailed description of configurations identical / similar to the above-described configurations can be omitted for the sake of simplicity of explanation.

[0060] Reference Figures 13 to 15 The ohmic pattern 320 can include a fourth silicide layer SC4 and a metal barrier layer BM.

[0061] The fourth silicide layer SC4 can be interposed between the bit line BL and the metal barrier layer BM, and can include a metal element (e.g., any one or any combination of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), silicon (Si), and nitrogen (N). The fourth silicide layer SC4 includes a first region SAR1 in contact with the metal barrier layer upper surface BMH, a third region SAR3 in contact with the bit line lower surface BLL, and a second region SAR2 between the first region SAR1 and the third region SAR3. The fourth silicide layer SC4 can have a thickness in the third direction D3 greater than 0 nm and less than or equal to 5 nm. In the fourth silicide layer SC4, the first region SAR1, the second region SAR2, and the third region SAR3 can be divided by a nitrogen concentration of each region.

[0062] The metal barrier layer BM can be interposed between the fourth silicide layer SC4 and the bit line contact DC and between the fourth silicide layer SC4 and the polysilicon pattern 310. The metal barrier layer BM can extend in the second direction D2 along the bit line BL. A plurality of metal barrier layers BM can be provided. The plurality of metal barrier layers BM can be spaced apart from each other in the first direction D1. The metal barrier layer BM can include a metal material (e.g., any one or any combination of Ti, Ta, Ni, Pt, Rh, Ir, Mo, Co, etc.).

[0063] The semiconductor device according to the example embodiment can include one or more silicide layers between the bit line and the bit line contact, and provide different concentrations of nitrogen (N) contained in each silicide layer, thereby improving reliability and electrical characteristics of the semiconductor device.

[0064] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate including an active pattern; a bit line located on the substrate crossing the active pattern; a bit line contact provided between the bit line and the active pattern; a first silicide layer provided between the bit line contact and the bit line; and a second silicide layer provided between the first silicide layer and the bit line, wherein each of the first silicide layer and the second silicide layer includes a first metal element, silicon, and nitrogen, and wherein the first silicide layer has a first nitrogen concentration, and the second silicide layer has a second nitrogen concentration greater than the first nitrogen concentration. The first nitrogen concentration is greater than or equal to 0 at% and less than or equal to 32 at%.

2. The semiconductor device of claim 1, wherein, The second nitrogen concentration is greater than or equal to 44 at% and less than or equal to 70 at%.

3. The semiconductor device of claim 1, wherein, The first silicide layer and the second silicide layer are vertically stacked on the substrate, and 4. The semiconductor device of claim 3, wherein, wherein the first nitrogen concentration is greater than 0 at% and less than or equal to 32 at%. An elemental ratio of silicon to the first metal element for each of the first silicide layer and the second silicide layer is greater than or equal to 0.5 and less than or equal to 3.

5. The semiconductor device of claim 1, wherein, 6. The semiconductor device of claim 1, further comprising a metal barrier layer provided between the bit line contact and the first silicide layer. The bit line contact includes polysilicon, and 7. The semiconductor device of claim 6, wherein, wherein the metal barrier layer includes any one or any combination of Ti, Ta, Ni, Pt, Rh, Ir, Mo, and Co. The first silicide layer has a first thickness in a third direction perpendicular to the substrate, 8. The semiconductor device of claim 1, wherein, wherein the second silicide layer has a second thickness in the third direction, and wherein the first thickness is equal to or greater than the second thickness. A ratio of the second thickness to the first thickness is less than or equal to 1 and greater than or equal to 0.

9.

9. The semiconductor device of claim 8, wherein, A sum of the first thickness and the second thickness is greater than 0 nm and less than or equal to 5 nm.

10. The semiconductor device of claim 8, wherein, The bit line includes a second metal element, and 11. The semiconductor device of claim 1, wherein, wherein each of the first metal element and the second metal element includes any one or any combination of W, Mo, and Ru.

12. A semiconductor device comprising: a substrate including an active pattern; a bit line located on the substrate crossing the active pattern; a bit line contact provided between the bit line and the active pattern; and a silicide layer provided between the bit line contact and the bit line, the silicide layer including a first region adjacent to the bit line contact and a second region adjacent to the bit line, wherein the silicide layer includes a first metal element, silicon, and nitrogen, and wherein a nitrogen concentration of the silicide layer increases upward along a direction perpendicular to an upper surface of the substrate. The nitrogen concentration in the second region is greater than or equal to 44 at% and less than or equal to 70 at%. ​ 13. The semiconductor device of claim 12, wherein, ​ 14. The semiconductor device of claim 13, wherein, The nitrogen concentration in the first region is greater than 0 at% and less than or equal to 32 at%.

15. The semiconductor device of claim 12, further comprising a metal barrier layer disposed between the bit line contact and the silicide layer.

16. The semiconductor device of claim 15, wherein, The metal barrier layer comprises any one or any combination of Ti, Ta, Ni, Pt, Rh, Ir, Mo, and Co.

17. The semiconductor device of claim 12, wherein, The bit line comprises a second metal element, and wherein each of the first metal element and the second metal element comprises any one or any combination of W, Mo, and Ru.

18. A semiconductor device, comprising: a device isolation pattern defining a plurality of active patterns on a substrate; a plurality of word lines crossing the plurality of active patterns on the substrate; a plurality of bit lines crossing the plurality of active patterns and intersecting the plurality of word lines; a bit line contact disposed between a central portion of one of the plurality of active patterns and one of the plurality of bit lines; a first silicide layer disposed between the bit line contact and the one of the plurality of bit lines; a second silicide layer disposed between the first silicide layer and the one of the plurality of bit lines; a storage node contact disposed on the plurality of active patterns on both sides of the one of the plurality of bit lines; a landing pad on the storage node contact; and a data storage pattern on the landing pad, wherein each of the first silicide layer and the second silicide layer comprises a metal element, silicon, and nitrogen, and wherein the first silicide layer has a first nitrogen concentration and the second silicide layer has a second nitrogen concentration greater than the first nitrogen concentration.

19. The semiconductor device of claim 18, wherein, The first nitrogen concentration is greater than 0 at% and less than or equal to 32 at%, and wherein the second nitrogen concentration is greater than or equal to 44 at% and less than or equal to 70 at%.

20. The semiconductor device of claim 18, wherein, A first thickness between an upper surface and a lower surface of the first silicide layer is greater than a second thickness between an upper surface and a lower surface of the second silicide layer.

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