Semiconductor device including peripheral circuit region

Abstract

A semiconductor device includes: a memory cell region; and a peripheral circuit region adjacent to the memory cell region in the first horizontal direction. The memory cell region includes: cell channel structures extending in a first horizontal direction and spaced apart from each other in a vertical direction; a cell bit line extending in a vertical direction; and a cell gate electrode overlapping the cell channel structure in the vertical direction and extending in the second horizontal direction. The peripheral circuit region includes: a peripheral channel structure extending in a first horizontal direction; a peripheral bit line extending in a vertical direction; and a first peripheral gate electrode and a second peripheral gate electrode overlapping the peripheral channel structure in the vertical direction and extending in the second horizontal direction. At least one of the unit channel structures is located at the same level as the peripheral channel structure in the vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0050104 filed on April 15, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device including a peripheral circuit region. Background Art

[0004] As demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices has increased. In response to the demand for high integration density of semiconductor devices, when manufacturing semiconductor devices having fine patterns, it may be necessary to implement patterns having fine widths or fine spacing. In addition, it may be necessary to reduce the size of semiconductor devices. Summary of the Invention

[0005] Example embodiments of the present disclosure provide a semiconductor device including a first peripheral circuit region disposed at the same level or layer as a memory cell region of a semiconductor structure.

[0006] According to an example embodiment of the present disclosure, a semiconductor device includes: a memory cell region; and a peripheral circuit region adjacent to the memory cell region in a first horizontal direction, wherein the memory cell region includes: a cell channel structure extending in the first horizontal direction and stacked and spaced apart from each other in a vertical direction perpendicular to the first horizontal direction; a cell bit line extending in the vertical direction and in contact with the cell channel structure; and a cell gate electrode overlapping with the cell channel structure in the vertical direction and extending in a second horizontal direction intersecting the first horizontal direction, wherein the peripheral circuit region includes: a peripheral channel structure extending in the first horizontal direction; a peripheral bit line extending in the vertical direction and in contact with the peripheral channel structure; and a first peripheral gate electrode and a second peripheral gate electrode overlapping with the peripheral channel structure in the vertical direction and extending in the second horizontal direction, wherein the first peripheral gate electrode is closer to the peripheral bit line than the second peripheral gate electrode, and wherein at least one of the cell channel structures is located at the same level as the peripheral channel structure in the vertical direction.

[0007] According to example embodiments of the present disclosure, a semiconductor device includes: a first structure including a memory cell region and a first peripheral circuit region; and a second structure overlapping the first structure in a vertical direction and including a core circuit region and a second peripheral circuit region, wherein the first peripheral circuit region includes: a peripheral channel structure extending in a first horizontal direction perpendicular to the vertical direction; a peripheral bit line extending in the vertical direction and in contact with the peripheral channel structure; and a first peripheral gate electrode and a second peripheral gate electrode overlapping the peripheral channel structure in the vertical direction and extending in a second horizontal direction intersecting the first horizontal direction, wherein the first peripheral gate electrode is closer to the peripheral bit line than the second peripheral gate electrode, and wherein the first peripheral circuit region overlaps the second peripheral circuit region in the vertical direction.

[0008] According to example embodiments of the present disclosure, a semiconductor device includes: a memory cell region; and a peripheral circuit region adjacent to the memory cell region in a first horizontal direction, wherein the memory cell region includes: a cell channel structure extending in the first horizontal direction and stacked and spaced apart from each other in a vertical direction perpendicular to the first horizontal direction; a cell bit line extending in the vertical direction and in contact with the cell channel structure; a capacitor structure extending in the vertical direction and in contact with the cell channel structure; a cell gate electrode overlapping the cell channel structure in the vertical direction and extending in a second horizontal direction intersecting the first horizontal direction; a cell gate dielectric layer between the cell channel structure and the cell gate electrode; and a cell contact structure on the cell bit line, wherein the peripheral circuit region includes: a peripheral channel structure extending in the first horizontal direction; a peripheral bit line extending in the vertical direction and in contact with the peripheral channel structure; a first peripheral gate electrode and a second peripheral gate electrode overlapping the peripheral channel structure in the vertical direction and extending in the second horizontal direction, wherein the first peripheral gate electrode is closer to the peripheral bit line than the second peripheral gate electrode; a first peripheral gate dielectric layer between the peripheral channel structure and the first peripheral gate electrode; and a peripheral contact structure on the peripheral bit line, wherein at least one of the cell channel structure and the peripheral channel structure has a respective surface that is substantially coplanar, and wherein at least a portion of the peripheral contact structure and the cell contact structure have respective surfaces that are substantially coplanar. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a perspective view illustrating a semiconductor device according to an example embodiment of the present disclosure; Figure 2A is a circuit diagram illustrating a memory cell in a memory cell region according to an example embodiment of the present disclosure; Figure 2B andFigure 2C is a circuit diagram showing circuit devices in a core circuit region according to an example embodiment of the present disclosure; Figure 3 is a plan view showing a memory cell region according to an example embodiment of the present disclosure; Figure 1 is a vertical cross-sectional view showing the memory cell region shown in Figure 4 is a plan view showing a memory cell region according to an example embodiment of the present disclosure; Figure 5A is a vertical cross-sectional view showing the memory cell region shown in Figure 4 Figure 5B is an enlarged view showing a capacitor structure shown in Figure 5A Figure 6 is a perspective view showing a memory cell according to an example embodiment of the present disclosure; Figure 7 is a circuit diagram showing peripheral circuit devices in a first peripheral circuit region according to an example embodiment of the present disclosure; Figure 8 is a plan view showing a first peripheral circuit region according to an example embodiment of the present disclosure; Figure 9 is a vertical cross-sectional view showing the first peripheral circuit region shown in Figure 8 Figure 10A is a perspective view showing an antifuse memory cell in the first peripheral circuit region according to an example embodiment of the present disclosure; Figure 10B is a perspective view showing an antifuse memory cell in the first peripheral circuit region according to an example embodiment of the present disclosure; Figure 11 is a plan view showing a first peripheral circuit region according to an example embodiment of the present disclosure; Figure 12 is a vertical cross-sectional view showing the first peripheral circuit region shown in Figure 11 Figure 13 is a perspective view showing an antifuse memory cell in the first peripheral circuit region according to an example embodiment of the present disclosure; and Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A and Figure 18B ​​​​are plan views and vertical cross-sectional views showing processes of a method of manufacturing a semiconductor device in order according to example embodiments of the present disclosure. DETAILED DESCRIPTION

[0010] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. The terms "first", "second", and the like can be used herein only to distinguish one component, layer, direction, or the like from another component, layer, direction, or the like. The terms "include", "comprise", "have", and / or "contain" when used herein specify the presence of stated elements but do not preclude the presence or addition of additional elements. The term "and / or" includes any and all combinations of one or more of the associated listed items. The term "connected" can be used herein to refer to physical or electrical connections. When a component or layer is referred to herein as "directly on" or "directly contacting" or "directly connected" to another component or layer, there are no intermediate components or layers present.

[0011] Figure 1 is a perspective view showing a semiconductor device according to example embodiments.

[0012] Reference Figure 1 A semiconductor device 1 according to example embodiments can include a first structure ST1 and a second structure ST2 vertically overlapping the first structure ST1. Components or layers described with reference to "overlap" in a certain direction can be at least partially occluded from each other when viewed along a line extending in the certain direction or in a plane perpendicular to the certain direction. The second structure ST2 can be disposed on the first structure ST1 in a vertical direction (e.g., Z direction).

[0013] In example embodiments, the first structure ST1 can be configured as a first chip structure including memory cells MC, and the second structure ST2 can be configured as a second chip structure including a peripheral circuit which can operate the memory cells MC. The first structure ST1 and the second structure ST2 can be bonded by a bonding process such as a wafer bonding process. Accordingly, the first structure ST1 can be in contact with and bonded to the second structure ST2.

[0014] The semiconductor device 1 can include a plurality of memory banks BA and a peripheral circuit region PERI. The peripheral circuit region PERI can include a first peripheral circuit region PERI1 in the first structure ST1 and a second peripheral circuit region PERI2 in the second structure ST2. The peripheral circuit region PERI can be configured as a peripheral circuit region in which a peripheral circuit for input / output of data or commands, or input of power / ground is disposed.

[0015] Each of the plurality of banks BA can include a first bank region BA1 in the first structure ST1 and a second bank region BA2 in the second structure ST2.

[0016] The first bank region BA1 in the first structure ST1 can include a cell region CA. The cell region CA can be arranged in an X direction and a Y direction. The X direction and the Y direction can be perpendicular to each other. The X direction and the Y direction can be referred to as horizontal or lateral directions, and the Z direction can be referred to as a vertical direction.

[0017] The second bank region BA2 in the second structure ST2 can include a core circuit region CR. The core circuit region CR can be arranged in the X direction and the Y direction. The core circuit region CR can overlap the cell region CA in the vertical direction Z. Components or layers described with reference to “overlap” in a certain direction can be at least partially obscured from each other when viewed along a line extending in the certain direction or in a plane perpendicular to the certain direction. The core circuit region CR can include sense amplifiers SA and sub word line drivers SWD.

[0018] The first peripheral circuit region PERI1 and the second peripheral circuit region PERI2 can include control circuitry that can control the sense amplifiers SA and the sub word line drivers SWD.

[0019] Figure 2A is a circuit diagram illustrating a memory cell in a cell region according to an example embodiment.

[0020] Reference Figure 2A The cell region CA can include memory cells MC arranged in the X direction and the Y direction, word lines WL connected to the memory cells MC and extending in the Y direction, and bit lines BL connected to the memory cells MC and extending in the vertical direction.

[0021] Each memory cell MC can include a cell transistor CTR and a data storage structure DS that can store data. In a memory such as a DRAM, the data storage structure DS can be configured as a cell capacitor that can store data. Data storage structures DS adjacent to each other can share a plate electrode PP. For example, the plate electrode PP can extend in the vertical direction and can be electrically connected to the data storage structures DS.

[0022] Figure 2B and Figure 2C is a circuit diagram illustrating an example of a sub word line driver in a core circuit region according to an example embodiment, and Figure 2B is a circuit diagram illustrating an example of a sub word line driver in a core circuit region according to an example embodiment, and Figure 2C is a circuit diagram illustrating an example of a sense amplifier in a core circuit region according to an example embodiment.

[0023] Referring to Figure 2B , the sub word line driver SWD can be electrically connected to the word line WL. Each sub word line driver SWD can include a PMOS transistor PT, a first NMOS transistor NT1, and a second NMOS transistor NT2. A driving signal PXID can be connected to a source terminal of the PMOS transistor PT, the word line WL can be electrically connected to a drain terminal of the PMOS transistor PT, and a word line enable signal NWEIB can be connected to a gate terminal of the PMOS transistor PT. The PMOS transistor PT can be configured as a pull-up transistor. A pre-charge voltage corresponding to a reverse bias voltage VBB2 can be connected to a source terminal of the first NMOS transistor NT1, the word line WL can be electrically connected to a drain terminal of the first NMOS transistor NT1, and the word line enable signal NWEIB can be connected to a gate terminal of the first NMOS transistor NT1. The first NMOS transistor NT1 can be configured as a pull-down transistor. A complementary driving signal PXIB can be connected to a gate terminal of the second NMOS transistor NT2, the pre-charge voltage corresponding to the reverse bias voltage VBB2 can be connected to a source terminal of the second NMOS transistor NT2, and the word line WL can be electrically connected to a drain terminal of the second NMOS transistor NT2. The second NMOS transistor NT2 can be configured as a holding transistor for maintaining the word line WL at a ground voltage level when the word line WL is not selected. The second NMOS transistor NT2 can be connected in parallel with the first NMOS transistor NT1. The sub word line driver SWD can drive the word line WL in response to the word line enable signal NWEIB and the driving signal PXID. The PMOS transistor PT can pull up the word line WL to a level of the driving signal PXID in response to the word line enable signal NWEIB. The first NMOS transistor NT1 can pull down the word line WL to a level of the negative voltage VBB2 in response to the word line enable signal NWEIB. The second NMOS transistor NT2, which can be configured as a holding transistor, can maintain the word line WL at the level of the negative voltage VBB2 when the word line WL is deactivated. To this end, the second NMOS transistor NT2 can switch between a source provided with the negative voltage VBB2 and a drain electrically connected to the word line WL in response to the driving signal PXIB, which can be complementary to the driving signal PXID. The above-described circuit of the sub word line driver SWD is merely an example embodiment, and the circuit of the sub word line driver SWD can be implemented as various circuit components.

[0024] Referring to Figure 2CEach sense amplifier SA can include a plurality of transistors P1_a, P1_b, N1_a, and N1_b. The transistors P1_a, P1_b, N1_a, and N1_b can include P1_a and P1_b transistors as PMOS transistors, and N1_a and N1_b transistors as NMOS transistors. The P1_a and P1_b transistors can be referred to as a PMOS transistor pair, and the N1_a and N1_b transistors can be referred to as an NMOS transistor pair. The source of the P1_a transistor and the source of the P1_b transistor can be connected to a first control line LA through a first node ND1_a. The source of the N1_a transistor and the source of the N1_b transistor can be connected to a second control line LAB through a second node ND1_b. The first node ND1_a and the second node ND1_b can be referred to as a first source node and a second source node, respectively. The drain of the P1_a transistor and the drain of the N1_a transistor can be connected to a first bit line BL1 among the bit lines BL through a first drain node ND1_c. The drain of the P1_b transistor and the drain of the N1_b transistor can be connected to a complementary bit line BL2 among the bit lines BL through a second drain node ND1_d. The sense amplifier SA can sense a voltage change of the first bit line BL1 and amplify the voltage change. When the sense amplifier SA performs the sensing and amplifying operations, an internal power voltage can be applied to the first node ND1_a through the first control line LA, and the second node ND1_b can be connected to a ground terminal through the second control line LAB. The sense amplifier SA can include the PMOS transistor pair and the NMOS transistor pair, and can be implemented as a circuit component cross-coupled between the transistors, but this is only an example embodiment, and example embodiments thereof are not limited thereto. For example, the circuit of the sense amplifier SA can be implemented as various circuit components.

[0025] Figure 3 is a vertical cross-sectional view of the semiconductor device shown in FIG. 1A taken along line I-I'. Figure 1 is a vertical cross-sectional view of the semiconductor device shown in FIG. 1A taken along line I-I'.

[0026] Referring to Figure 3 The semiconductor device 1 can include a first structure ST1 and a second structure ST2 vertically overlapping the first structure ST1. The second structure ST2 can be disposed on the first structure ST1.

[0027] The first structure ST1 can include a cell area CA and a first peripheral circuit area PERI1. The first peripheral circuit area PERI1 can be spaced apart from the cell area CA in a horizontal direction and can be disposed between the cell areas CA. As described later, components of the first peripheral circuit area PERI1 can be disposed at a same level (e.g., at a same layer of the semiconductor structure ST1) as corresponding components of the cell area CA. The term “horizontal” can be used herein to refer to a distance or spacing along a Z direction (also referred to as a vertical direction herein) relative to a reference element or layer (e.g., the substrate 103). The first peripheral circuit area PERI1 can have a structure that is the same or similar to a structure of the cell area CA.

[0028] The cell area CA can include cell transistors CTR, a data storage structure DS, and a bit line BL disposed on the substrate 103. The cell area CA can also include a contact structure 165 on the bit line BL and a contact plug 180 on the data storage structure DS. The cell area CA will be described in more detail later with reference to FIGS. 2A and 2B. Figure 4 to Figure 6 The components of the cell area CA are described in more detail.

[0029] The first peripheral circuit area PERI1 can include select transistors ST, antifuses AF, a peripheral bit line PBL, and a contact structure 265 on the peripheral bit line PBL disposed on the substrate 103. At least a portion of the contact structure 265 can be disposed at a same level as the contact structure 165 and the contact plug 180, e.g., relative to the underlying substrate 103. For example, respective surfaces of at least a portion of the contact structure 265, the contact structure 165, and the contact plug 180 can be substantially coplanar. The select transistors ST and the antifuses AF can be disposed at a same level as at least one of the cell transistors CTR.

[0030] The first structure ST1 can also include an upper interconnect 190, an upper via 193, and an upper insulating layer 196 disposed on the cell transistors CTR, the select transistors ST, and the antifuses AF. The contact structure 165, the contact plug 180, and the contact structure 265 can be electrically connected to corresponding upper interconnects 190 by the upper via 193, respectively. The upper insulating layer 196 can cover the upper interconnects 190 and the upper via 193. The term “cover” (or “surround” or “fill”) as can be used herein can not require complete covering (or surrounding or filling) of the described element or layer, but can refer to, e.g., partially covering (or surrounding or filling) the described element or layer, e.g., with one or more discontinuities.

[0031] The first structure ST1 can also include a first bond pad BP1 disposed on an upper surface of the upper insulating layer 196. The cell area CA and the first peripheral circuit area PERI1 can be electrically connected to a second structure ST2 by the first bond pad BP1.

[0032] The second structure ST2 can include core circuit regions CR and second peripheral circuit regions PERI2. The second peripheral circuit regions PERI2 can be spaced apart from the core circuit regions CR in a horizontal direction, and can be disposed between the core circuit regions CR. The core circuit regions CR can overlap the memory cell regions CA in a vertical direction, and the second peripheral circuit regions PERI2 can overlap the first peripheral circuit regions PERI1 in the vertical direction.

[0033] The second structure ST2 can further include a semiconductor body 3 including peripheral active regions pACT, and device isolation regions 6 defining the peripheral active regions pACT on the semiconductor body 3. The device isolation regions 6 can define side surfaces of the peripheral active regions pACT. The device isolation regions 6 can be formed of an insulating material.

[0034] The semiconductor body 3 can include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The semiconductor body 3 can include single crystalline silicon.

[0035] The second structure ST2 can further include core circuit transistors 12a, peripheral circuit transistors 12b, peripheral interconnect structures 21, and insulating structures 24 disposed on the semiconductor body 3.

[0036] The core circuit transistors 12a can include peripheral source / drain regions pSD formed in the peripheral active regions pACT, peripheral channel regions pCH between the peripheral source / drain regions pSD, and peripheral gates pGO and pGE on the peripheral channel regions pCH. The peripheral gates pGO and pGE can include peripheral gate dielectric layers pGO, and peripheral gate electrodes pGE on the peripheral gate dielectric layers pGO. The peripheral circuit transistors 12b can have a similar structure as the core circuit transistors 12a. In an example embodiment, the core circuit transistors 12a and the peripheral circuit transistors 12b can be planar transistors.

[0037] The core circuit transistors 12a can overlap the memory cell regions CA in a vertical direction, and the peripheral circuit transistors 12b can overlap the first peripheral circuit regions PERI1 in the vertical direction. As Figure 3As shown, according to the example embodiment, the first peripheral circuit region PERI1 can be provided in the first structure ST1 in which the memory cell region CA is provided, and one or more elements (e.g., channel structures, bit lines, gate electrodes, and contacts) of the first peripheral circuit region PERI1 can have the same or similar structure as that of the memory cell region CA. Thus, compared to a semiconductor device in which the first peripheral circuit region PERI1 is not provided in the first structure ST1, the area of the peripheral circuit regions PERI1 and PERI2 can be reduced by the area of the first peripheral circuit region PERI1. Thus, the size of the semiconductor device 1 can be reduced.

[0038] The peripheral interconnect structure 21 can include horizontal interconnects 18 extending in a horizontal direction, and vias 15 connected to the horizontal interconnects 18 and extending in a vertical direction. The horizontal interconnects 18 can form a plurality of layers. At least one of the horizontal interconnects 18 can be electrically connected to the peripheral active region pACT through the vias 15.

[0039] The insulating structure 24 can cover an upper surface of the semiconductor body 3, and can cover the core circuit transistors 12a, the peripheral circuit transistors 12b, and the peripheral interconnect structure 21.

[0040] The second structure ST2 can further include a via structure 27, lower interconnects 30, lower vias 33, a lower insulating layer 36, and a second bonding pad BP2. The via structure 27 can penetrate the semiconductor body 3, and can extend in a vertical direction. The via structure 27 can include a via 27a, and an insulating spacer 27b covering a side surface of the via 27a. The via 27a can be electrically connected to at least one of the core circuit transistors 12a and the peripheral circuit transistors 12b. The insulating spacer 27b can electrically insulate the via 27a from the semiconductor body 3.

[0041] The lower interconnects 30, the lower vias 33, the lower insulating layer 36, and the second bonding pad BP2 can be provided below the semiconductor body 3. At least one of the lower interconnects 30 can be electrically connected to the via 27a. At least one of the lower interconnects 30 can be electrically connected to the second bonding pad BP2 through the lower vias 33.

[0042] The lower insulating layer 36 can cover a lower surface of the semiconductor body 3. The lower insulating layer 36 can further cover the lower interconnects 30 and the lower vias 33.

[0043] The second structure ST2 can further include an interlayer insulating layer 39, a barrier insulating layer 42, a passivation layer 45, an upper interconnect 48, an upper via 51, an upper interconnect 54, and an upper via 57 provided on the insulating structure 24. The interlayer insulating layer 39 and the barrier insulating layer 42 can be alternately stacked. The passivation layer 45 can be provided on the uppermost interlayer insulating layer 39.

[0044] The upper interconnects 48 can extend in a horizontal direction in the interlayer insulating layer 39, and the upper vias 51 can extend in a vertical direction, and can connect the upper interconnects 48 to each other. The upper interconnects 54 can be provided on the passivation layer 45, and can be electrically connected to the upper interconnects 48 through the upper vias 57 extending in the vertical direction.

[0045] Figure 4 is a plan view illustrating a memory cell region according to an example embodiment. Figure 5A is a vertical sectional view of the memory cell region illustrated in Figure 4 is a vertical sectional view of the memory cell region illustrated in Figure 5B is a plan view illustrating Figure 5A is an enlarged view of the capacitor structure illustrated in Figure 6 is a perspective view illustrating a memory cell according to an example embodiment.

[0046] Referring to Figure 4 to Figure 6 , the memory cell region CA of the semiconductor device 1 can include the cell channel structures 110, the cell gate electrodes 142, the cell bit lines 160, and the capacitor structures 170 provided on the substrate 103.

[0047] The cell channel structures 110 can be provided on the substrate 103, and can extend horizontally in the X direction. The cell channel structures 110 can be spaced apart from each other in the Y direction and a vertical (e.g., Z) direction. In a plan view, the cell channel structures 110 can have a linear shape, a bar shape, or a column shape extending in the X direction. In an example, the cell channel structures 110 can include a semiconductor material (e.g., silicon, germanium, or silicon germanium).

[0048] Each of the cell channel structures 110 can include first and second impurity regions and a channel region. The first and second impurity regions can be provided at opposite ends of the cell channel structure 110 in the X direction, and the channel region can be provided between the first and second impurity regions. The first impurity region can be in contact with the cell bit line 160, and can be electrically connected to the cell bit line 160. The second impurity region can be in contact with the first electrode 171 of the capacitor structure 170, and can be electrically connected to the first electrode 171. The length of the first impurity region in the X direction and the length of the second impurity region in the X direction can be different from each other, or can be the same. The channel region can overlap the cell gate electrode 142 in the vertical direction. When the cell channel structure 110 is formed of a semiconductor material, each of the first and second impurity regions can include an impurity, and the impurity can have N-type conductivity or P-type conductivity.

[0049] The portion of the cell channel structure 110 overlapping the cell gate electrode 142 in the vertical direction and the cell gate electrode 142 can include a gate insulating layer 143. Figure 2AThe first impurity region can correspond to at least a part of a first source / drain region of the unit transistor CTR in the memory cell MC, and the second impurity region can correspond to at least a part of a second source / drain region of the unit transistor CTR in the memory cell MC. Figure 2A The first impurity region can correspond to at least a part of a first source / drain region of the unit transistor CTR in the memory cell MC, and the second impurity region can correspond to at least a part of a second source / drain region of the unit transistor CTR in the memory cell MC. Figure 2A The first impurity region can correspond to at least a part of a first source / drain region of the unit transistor CTR in the memory cell MC, and the second impurity region can correspond to at least a part of a second source / drain region of the unit transistor CTR in the memory cell MC. Figure 2A The first impurity region can correspond to at least a part of a first source / drain region of the unit transistor CTR in the memory cell MC, and the second impurity region can correspond to at least a part of a second source / drain region of the unit transistor CTR in the memory cell MC.

[0050] In another example, the unit channel structure 110 can include at least one of an oxide semiconductor (e.g., hafnium silicon oxide (HSO), hafnium zinc oxide (HZO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO)).

[0051] In another example, the unit channel structure 110 can include a two-dimensional (2D) material whose atoms can form a specific crystal structure and can form a channel of a transistor. The 2D material layer can include at least one of a transition metal dichalcogenide material layer (TMD material layer), a black phosphorus material layer, and a hexagonal boron nitride material layer (hBN material layer). For example, the 2D material layer can include at least one of BiOSe, CrI3, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D material, which can form a 2D material.

[0052] The unit gate electrode 142 can be provided on the substrate 103 and can extend horizontally in the Y direction. The unit gate electrodes 142 can be spaced apart from each other in the X direction and in the vertical direction. The unit gate electrodes 142 can overlap with the channel region of the unit channel structure 110 in the vertical direction. The unit gate electrodes 142 can extend in the Y direction and can have a linear shape, a bar shape, or a column shape in a plan view.

[0053] The unit gate electrode 142 can include a conductive material, and the conductive material can include a doped semiconductor material (e.g., doped silicon, doped germanium, or the like), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, or the like), a metal (e.g., tungsten, titanium, tantalum, cobalt, aluminum, ruthenium, or the like), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, or the like). At least one of the unit gate electrodes 142 can correspond to the reference Figure 2AThe depicted word line WL. In example embodiments, the cell gate electrode 142 can be disposed in a gate all-around structure around the cell channel structure 110.

[0054] In some example embodiments, the cell gate electrode 142 can be disposed on the upper and lower surfaces of each cell channel structure 110, and two cell gate electrodes 142 adjacent to each cell channel structure 110 can be configured as a word line WL. In some example embodiments, the memory cell transistor MCT can have a single gate structure. For example, one of the cell gate electrodes 142 can be disposed adjacent to each cell channel structure 110, and the cell gate electrodes 142 can be configured as a word line WL.

[0055] The memory cell region CA of the semiconductor device 1 can further include a cell gate dielectric layer 140, a gate capping layer 144, and an insulating layer 146. The cell gate dielectric layer 140 can be disposed in a gate all-around structure around the cell channel structure 110, and can cover the upper, lower, and side surfaces of the cell gate electrode 142. The gate capping layer 144 can be disposed between the cell gate electrode 142 and the cell bit line 160. A portion of the cell gate dielectric layer 140 can be disposed between the cell channel structure 110 and the gate capping layer 144. The gate capping layer 144 can be spaced apart from the cell bit line 160, and the insulating layer 146 can be disposed between the gate capping layer 144 and the cell bit line 160. The insulating layer 146 can be in contact with the cell bit line 160.

[0056] The cell gate dielectric layer 140 can include at least one of silicon oxide, silicon nitride, a low-κ material, and a high-κ material. The high-κ material can indicate a dielectric material having a dielectric constant higher than that of silicon oxide, and the low-κ material can indicate a dielectric material having a dielectric constant lower than that of silicon oxide. The high-κ material can be, for example, a metal oxide or a metal oxynitride. The high-κ material can be, for example, at least one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr2O3). The cell gate dielectric layer 140 can be formed as a single layer or multiple layers formed of the above-described materials.

[0057] The gate capping layer 144 can include at least one of an insulating material (e.g., silicon nitride, silicon oxynitride, and silicon oxycarbide).

[0058] The memory cell region CA of the semiconductor device 1 can further include a first buffer layer 120, a first liner 122, and a first gap fill insulating layer 126 disposed between the cell channel structures 110. The first buffer layer 120, the first liner 122, and the first gap fill insulating layer 126 can be in contact with the cell gate dielectric layer 140. For example, the first buffer layer 120 can extend in a horizontal direction on upper and lower surfaces of the cell channel structures 110 and can extend in a vertical direction between the cell channel structures 110. The first liner 122 can be conformally disposed on the first buffer layer 120. The first gap fill insulating layer 126 can fill spaces between the cell gate dielectric layers 140 adjacent to each other. The first gap fill insulating layer 126 can be in contact with the gate capping layer 144 and the cell bit line 160. The first buffer layer 120 and the first gap fill insulating layer 126 can include silicon oxide, and the first liner 122 can include silicon nitride.

[0059] The cell bit line 160 can extend in the X direction and the vertical direction on the substrate 103. The cell bit lines 160 can be spaced apart from each other in the X direction and the Y direction. The plurality of cell channel structures 110 stacked in the vertical direction can be electrically connected to the cell bit line 160. For example, the cell bit line 160 can be electrically connected to the first impurity region of the cell channel structure 110. The cell bit line 160 can include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound. For example, the cell bit line 160 can include doped polysilicon. The cell bit line 160 can correspond to the bit line BL described above. Figure 2A The bit line BL described above.

[0060] The memory cell region CA of the semiconductor device 1 can further include a contact structure 165 disposed on the cell bit line 160. The contact structure 165 can include a first conductive layer 163 and a second conductive layer 164. The first conductive layer 163 can be in contact with an upper surface of the cell bit line 160, and the second conductive layer 164 can be disposed on the first conductive layer 163.

[0061] The first conductive layer 163 can include a metal semiconductor compound. For example, the metal semiconductor compound can be configured as a layer that silicidizes a portion of the cell bit line 160. For example, the metal semiconductor compound can include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides, or can include a nitride such as TiSiN. The second conductive layer 164 can include a metal material (e.g., titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al)).

[0062] The memory cell region CA of the semiconductor device 1 can further include insulating structures 150. In a plan view, the insulating structures 150 can extend in the X direction and can be spaced apart from each other in the Y direction. The insulating structures 150 can be alternately arranged with the cell bit lines 160 in the Y direction. The insulating structures 150 can spatially isolate and electrically insulate the cell bit lines 160 from each other.

[0063] Each of the insulating structures 150 can include a first insulating pattern 152, a second insulating pattern 154, and a third insulating pattern 156. The first insulating pattern 152 can be in contact with the cell channel structure 110, the gate cap layer 144, and the cell bit line 160. The second insulating pattern 154 can be conformally formed along an inner wall of the first insulating pattern 152. The third insulating pattern 156 can fill an inner space of the second insulating pattern 154.

[0064] The capacitor structure 170 can be in contact with the cell channel structure 110 and can be electrically connected to the cell channel structure 110. The capacitor structure 170 can include a first electrode 171, a second electrode 172 on the first electrode 171, a plate electrode 175 on the second electrode 172, and a capacitor dielectric 173 between the first electrode 171 and the second electrode 172. The first electrode 171 can be in contact with the second impurity region of each of the cell channel structures 110. Each of the first electrodes 171 can have a cylindrical shape, but example embodiments are not limited thereto, and in example embodiments, the first electrode 171 can have a columnar shape.

[0065] The nodes of the first electrodes 171 can be separated from each other between the cell channel structures 110. For example, the first electrodes 171 can be spaced apart from each other. The first electrodes 171 can be referred to as "storage node electrodes." The first electrodes 171 can include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0066] The second electrode 172 can cover the first electrode 171, can extend in a vertical direction, and can cover an upper surface of the substrate 103. The capacitor dielectric 173 can extend between the first electrode 171 and the second electrode 172. The capacitor dielectric 173 can cover the upper surface of the substrate 103 and can electrically insulate the substrate 103 from the capacitor structure 170. In example embodiments, the substrate 103 can include an impurity region disposed on the upper surface of the substrate 103 and in contact with the second electrode 172. The capacitor structure 170 can not be electrically connected to the substrate 103 through the impurity region. A portion of the second electrode 172 and the capacitor dielectric 173, and the first electrode 171 can correspond to the data storage structure DS shown in FIG. 1B. The plate electrode 175 can correspond to the plate electrode PP. Figure 2A ​

[0067] The second electrode 172 can include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound. In an example embodiment, the first electrode 171 and the second electrode 172 can include titanium nitride. For example, the capacitor dielectric 173 can include at least one of a high-k material (e.g., zirconium oxide (ZrO2), aluminum oxide (Al2O3), and hafnium oxide (Hf2O3)).

[0068] The plate electrode 175 can cover the second electrode 172, and can extend in a vertical direction. The plate electrode 175 can include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound. In an example embodiment, the plate electrode 175 can include silicon germanium.

[0069] The contact plug 180 can be disposed on the plate electrode 175. The contact plug 180 can be electrically connected to the data storage structure DS through the plate electrode 175. The contact plug 180 can include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound.

[0070] The memory cell region CA of the semiconductor device 1 can further include a second buffer layer 130, a second liner 132, and a second gap fill insulating layer 136 disposed between the cell channel structures 110. The second buffer layer 130, the second liner 132, and the second gap fill insulating layer 136 can be in contact with the first electrode 171 of the capacitor structure 170. For example, the second buffer layer 130 can extend in a horizontal direction on upper and lower surfaces of the cell channel structures 110, and can extend in a vertical direction between the cell channel structures 110. The second liner 132 can be disposed conformally on the second buffer layer 130. The second gap fill insulating layer 136 can be disposed on the second liner 132, and can fill a space between the cell channel structures 110 adjacent thereto. The second buffer layer 130 and the second gap fill insulating layer 136 can include silicon oxide, and the second liner 132 can include silicon nitride.

[0071] Figure 7 FIG. 17 is a circuit diagram illustrating a peripheral circuit device in a first peripheral circuit region according to an example embodiment.

[0072] Reference Figure 7 In an example embodiment, the first peripheral circuit region PERI1 can include an antifuse array. The antifuse array can include antifuse memory cells AFC arranged along a peripheral bit line PBL, a program word line WLP, and a read word line WLR. Each antifuse memory cell AFC can include a selection transistor ST and an antifuse AF connected in series to each other.

[0073] The selection transistor ST can be connected between the bit line BL and the antifuse AF, and can be controlled by a read word line WLR. The read word line WLR can be connected to a selection gate of the selection transistor ST.

[0074] The source region of the antifuse AF can be connected to the drain region of the selection transistor ST, and the drain region of the antifuse AF can be electrically floating. The antifuse AF can be programmed by causing an insulating breakdown of the antifuse gate dielectric layer by applying a high voltage to the antifuse gate dielectric layer. The antifuse AF can be programmed in accordance with a voltage applied to a program word line WLP. The program word line WLP can be connected to an antifuse gate of the antifuse AF.

[0075] Figure 8 is a plan view showing a first peripheral circuit region according to an example embodiment. Figure 9 is a vertical cross-sectional view of the first peripheral circuit region shown in Figure 8 Figure 10A is a perspective view showing an antifuse memory cell in the first peripheral circuit region according to an example embodiment.

[0076] Reference is made to Figure 8 to Figure 10A , the first peripheral circuit region PERI1 can include a peripheral channel structure 210, a first peripheral gate electrode 242, a second peripheral gate electrode 342, and a peripheral bit line 260 disposed on the substrate 103.

[0077] The peripheral channel structure 210 can be disposed on the substrate 103, and can extend horizontally in the X direction. The peripheral channel structure 210 can be spaced apart from each other in the Y direction and the vertical direction. The peripheral channel structure 210 can have the same or similar structure as that of the cell channel structure 110 shown in Figure 4 、 Figure 5A and Figure 5B The peripheral channel structure 210 can be disposed at the same level as at least one of the cell channel structures 110, for example, with respect to the underlying substrate 103.

[0078] The first peripheral gate electrode 242 can be disposed on the substrate 103, and can extend horizontally in the Y direction. The first peripheral gate electrode 242 can be spaced apart from each other in the X direction and the vertical direction. The first peripheral gate electrode 242 can overlap with the channel regions of the peripheral channel structure 210 in the vertical direction.

[0079] ​The second peripheral gate electrode 342 can be disposed on the substrate 103 and can extend horizontally in the Y direction. The second peripheral gate electrode 342 can be spaced apart from each other in the X direction and the vertical direction. In an example embodiment, the first peripheral gate electrode 242 and the second peripheral gate electrode 342 can be disposed in a gate full-surrounding structure surrounding the peripheral channel structure 210. For example, a portion of each peripheral channel structure 210 can be surrounded by the first peripheral gate electrode 242 and the second peripheral gate electrode 342, and the first peripheral gate electrode 242 can be disposed closer to the peripheral bit line 260 than the second peripheral gate electrode 342.

[0080] At least one of the first peripheral gate electrode 242 can correspond to a reference Figure 7 described read word line WLR. At least one of the second peripheral gate electrode 342 can correspond to a reference Figure 7 described program word line WLP. A portion of the peripheral channel structure 210 vertically overlapping the first peripheral gate electrode 242 can correspond to a channel region, and the channel region and the first peripheral gate electrode 242 can form a reference Figure 7 described select transistor ST. A portion of the peripheral channel structure 210 vertically overlapping the second peripheral gate electrode 342 can correspond to a channel region, and the channel region and the second peripheral gate electrode 342 can be included in a reference Figure 7 described antifuse AF. The first peripheral gate electrode 242 and the second peripheral gate electrode 342 can be disposed at the same level as at least one of the cell gate electrodes 142, for example, with respect to the underlying substrate 103.

[0081] The first peripheral circuit region PERI1 can further include the first buffer layer 220, the first pad 222, and the first gap fill insulating layer 226 disposed between the peripheral channel structures 210. The first buffer layer 220, the first pad 222, and the first gap fill insulating layer 226 can have structures identical or similar to those of the reference Figure 4 、 Figure 5A and Figure 5B described first buffer layer 120, first pad 122, and first gap fill insulating layer 126, respectively.

[0082] The first peripheral circuit region PERI1 can further include the first peripheral gate dielectric layer 240, the first peripheral gate capping layer 244, and the first peripheral insulating layer 246. The first peripheral gate dielectric layer 240, the first peripheral gate capping layer 244, and the first peripheral insulating layer 246 can have structures identical or similar to those of the reference Figure 4 、 Figure 5A and Figure 5BThe structures of the unit gate dielectric layer 140, the gate cap layer 144, and the insulating layer 146 are the same or similar structures. For example, a first peripheral gate dielectric layer 240 can be disposed as a gate full-surround structure around the peripheral channel structure 210, and can cover the upper surface, the lower surface, and the side surface of the first peripheral gate electrode 242. A first peripheral gate cap layer 244 can be disposed between the first peripheral gate electrode 242 and the peripheral bit line 260. The first peripheral gate cap layer 244 can be spaced apart from the peripheral bit line 260, and a first peripheral insulating layer 246 in contact with the peripheral bit line 260 can be disposed between the first peripheral gate cap layer 244 and the peripheral bit line 260.

[0083] The peripheral bit line 260 can extend in the X direction and the vertical direction on the substrate 103. The peripheral bit lines 260 can be spaced apart from each other in the X direction and the Y direction. The plurality of peripheral channel structures 210 stacked in the vertical direction can be electrically connected to the peripheral bit line 260. The peripheral bit line 260 can correspond to the reference Figure 7 The peripheral bit line PBL described above.

[0084] The first peripheral circuit region PERI1 can further include a contact structure 265 disposed on the peripheral bit line 260. The contact structure 265 can include a first conductive layer 263 and a second conductive layer 264. The contact structure 265 can also be referred to as a "peripheral contact structure". As Figure 3 As shown in FIG. 1C, at least a portion of the contact structure 265 can be disposed at the same level as the contact structure 165 and the contact plug 180, for example, with respect to the underlying substrate 103.

[0085] The first peripheral circuit region PERI1 can further include an insulating structure 250. In a plan view, the insulating structure 250 can extend in the X direction, and can be spaced apart from each other in the Y direction. The insulating structure 250 can be alternately disposed with the peripheral bit line 260 in the Y direction. The insulating structure 250 can spatially isolate and electrically insulate the peripheral bit lines 260 from each other.

[0086] Each of the insulating structures 250 can include a first insulating pattern 252, a second insulating pattern 254, and a third insulating pattern 256. The first insulating pattern 252 can be in contact with the peripheral channel structure 210, the first peripheral gate cap layer 244, and the peripheral bit line 260. The second insulating pattern 254 can be conformally formed along the inner wall of the first insulating pattern 252. The third insulating pattern 256 can fill the inner space of the second insulating pattern 254.

[0087] The first peripheral circuit region PERI1 can further include a second buffer layer 330, a second spacer 332, and a second gap fill insulating layer 336 disposed between the peripheral channel structures 210. The second buffer layer 320, the second spacer 322, and the second gap fill insulating layer 336 can have the same or similar structures as those of the first buffer layer 220, the first spacer 222, and the first gap fill insulating layer 226, respectively.

[0088] The first peripheral circuit region PERI1 can further include a second peripheral gate dielectric layer 340, a second peripheral gate capping layer 344, and a second peripheral insulating layer 346. The second peripheral gate dielectric layer 340, the second peripheral gate capping layer 344, and the second peripheral insulating layer 346 can have the same or similar structures as those of the first peripheral gate dielectric layer 240, the first peripheral gate capping layer 244, and the first peripheral insulating layer 246, respectively. For example, the second peripheral gate dielectric layer 340 can be disposed as a gate all-around structure around the peripheral channel structures 210, and can cover upper, lower, and side surfaces of the second peripheral gate electrode 342. The second peripheral gate capping layer 344 can cover the side surfaces of the second peripheral gate electrode 342 that are not covered by the second peripheral gate dielectric layer 340. The second peripheral insulating layer 346 can be disposed between the peripheral channel structures 210 and the second peripheral gate capping layer 344, and can be in contact with the second peripheral gate dielectric layer 340.

[0089] The first peripheral circuit region PERI1 can further include an interlayer insulating layer 234. The interlayer insulating layer 234 can be disposed between the peripheral bit lines 260, and can extend in the Y direction. The interlayer insulating layer 234 can extend in the vertical direction, and can be in contact with the peripheral channel structures 210, the second gap fill insulating layer 336, and the second peripheral gate capping layer 344. In addition, an upper portion of the interlayer insulating layer 234 can extend in the horizontal direction, and can be in contact with the first spacer 222, the first peripheral gate dielectric layer 240, the first peripheral gate capping layer 244, the peripheral bit lines 260, the contact structures 265, and the second spacer 332.

[0090] A first end of the peripheral channel structure 210 of the first peripheral circuit region PERI1 can be in contact with the peripheral bit line 260, and can be electrically connected to the peripheral bit line 260. A second end of the peripheral channel structure 210 can be opposite the first end, and can be in contact with the interlayer insulating layer 234. The second end of the peripheral channel structure 210 can be electrically floating, and when a high voltage is applied to the second peripheral gate electrode 342, an insulating breakdown can occur in the second peripheral gate dielectric layer 340, and an anti-fuse AF can be programmed.

[0091] In an example embodiment, the first peripheral gate electrode 242 and the peripheral bit line 260 of the first peripheral circuit region PERI1 can be formed in the same process of forming the cell gate electrode 142 and the cell bit line 160, respectively. Thus, the process of manufacturing the semiconductor device can be simplified. The second peripheral gate electrode 342 can be formed in a process different from the process of forming the cell gate electrode 142 and the first peripheral gate electrode 242. For example, the process of forming the gate electrode on the peripheral channel structure 210 can be performed twice, and the first peripheral gate electrode 242 and the second peripheral gate electrode 342 can be formed by performing the process of forming the gate electrode twice.

[0092] In an example embodiment, Figure 5A The length Lc of the cell channel structure 110 in the X direction shown in FIG. 1 can be different from the length Lp1 of the peripheral channel structure 210 in the X direction shown in FIG. 2. For example, the length Lp1 of the peripheral channel structure 210 in the X direction can be greater than the length Lc of the cell channel structure 110 in the X direction. Figure 9

[0093] Figure 10B is a perspective view illustrating a antifuse memory cell in a first peripheral circuit region according to an example embodiment.

[0094] Referring to Figure 10B , the antifuse memory cell can include a select transistor ST including the first peripheral gate electrode 242 and an antifuse AF including the second peripheral gate electrode 342a. In an example embodiment, the threshold voltage of the select transistor ST can be different from the threshold voltage of the antifuse AF. As in the context of a transistor, the threshold voltage of the antifuse can refer to the minimum voltage required to conduct in the antifuse. For example, at least one of the gate length of the select transistor ST, the type and amount of material used in the gate electrode, the type and amount of material used in the gate dielectric layer, and the thickness of the gate dielectric layer can be different from those of the antifuse AF.

[0095] In an example embodiment, the gate length GLp1 of the first peripheral gate electrode 242 can be different from the gate length GLp2 of the second peripheral gate electrode 342a. Here, the "gate length" can indicate the length of the gate electrode 242 and 342a covering the peripheral channel structure 210, for example, along the direction between the source / drain regions at the opposite ends of the channel structure 210. In other words, the gate length GLp1 can indicate the length of the first peripheral gate electrode 242 in the X direction, and the gate length GLp2 can indicate the length of the second peripheral gate electrode 342a in the X direction. In an example embodiment, the gate length GLp1 of the first peripheral gate electrode 242 can be the same as the gate length GLc of the cell gate electrode 142 shown in FIG. 1. Figure 6 In an example embodiment, the gate length GLp1 of the first peripheral gate electrode 242 can be different from the gate length GLp2 of the second peripheral gate electrode 342a. Here, the "gate length" can indicate the length of the gate electrode 242 and 342a covering the peripheral channel structure 210, for example, along the direction between the source / drain regions at the opposite ends of the channel structure 210. In other words, the gate length GLp1 can indicate the length of the first peripheral gate electrode 242 in the X direction, and the gate length GLp2 can indicate the length of the second peripheral gate electrode 342a in the X direction. In an example embodiment, the gate length GLp1 of the first peripheral gate electrode 242 can be the same as the gate length GLc of the cell gate electrode 142 shown in FIG. 1.​

[0096] In an example embodiment, a thickness GTp1 of the first peripheral gate dielectric layer 240 (which can be a gate dielectric layer of the select transistor ST) can be different from a thickness GTp2 of the second peripheral gate dielectric layer 340 (which can be a gate dielectric layer of the antifuse AF). For example, the thickness GTp2 of the second peripheral gate dielectric layer 340 can be less than the thickness GTp1 of the first peripheral gate dielectric layer 240. Accordingly, an insulating breakdown voltage of the second peripheral gate dielectric layer 340 of the antifuse AF can be reduced or decreased. In an example embodiment, the thickness GTp1 of the first peripheral gate dielectric layer 240 can be the same as a thickness GTc of the cell gate dielectric layer 140 shown in FIG. 1A. Figure 6 In an example embodiment, a thickness GTp1 of the first peripheral gate dielectric layer 240 (which can be a gate dielectric layer of the select transistor ST) can be different from a thickness GTp2 of the second peripheral gate dielectric layer 340 (which can be a gate dielectric layer of the antifuse AF). For example, the thickness GTp2 of the second peripheral gate dielectric layer 340 can be less than the thickness GTp1 of the first peripheral gate dielectric layer 240. Accordingly, an insulating breakdown voltage of the second peripheral gate dielectric layer 340 of the antifuse AF can be reduced or decreased. In an example embodiment, the thickness GTp1 of the first peripheral gate dielectric layer 240 can be the same as a thickness GTc of the cell gate dielectric layer 140 shown in FIG. 1A.

[0097] In an example embodiment, the second peripheral gate electrode 342a can include a different material from the first peripheral gate electrode 242. The first peripheral gate electrode 242 can include the same material as a material of the cell gate electrode 142.

[0098] Figure 11 FIG. 1C is a plan view illustrating a first peripheral circuit region according to an example embodiment. Figure 12 FIG. 1D is a vertical cross-sectional view illustrating the first peripheral circuit region taken along line IV-IV’ shown in FIG. 1C. Figure 11 FIG. 1E is a vertical cross-sectional view illustrating the first peripheral circuit region shown in FIG. 1D. Figure 13 FIG. 1F is a perspective view illustrating an antifuse memory cell in the first peripheral circuit region according to an example embodiment.

[0099] Referring to Figure 11 to Figure 13 , the first peripheral circuit region PERI1 can include the first buffer layer 220, the first liner 222, the first gap fill insulating layer 226, the first peripheral gate dielectric layer 240, the first peripheral gate cap layer 244, the first peripheral insulating layer 246, the insulating structure 250, the peripheral bit line 260, and the contact structure 265, and these components can have the same or similar structures as the components described with reference to Figure 8 and Figure 9 FIGS. 1A to 1F.

[0100] The first peripheral circuit region PERI1 can include the peripheral channel structure 210, the first peripheral gate electrode 242, and the second peripheral gate electrode 442. The peripheral channel structure 210 can include the first peripheral channel structure 210a, the second peripheral channel structure 210b, and the epitaxial layer 470 connecting the first peripheral channel structure 210a to the second peripheral channel structure 210b.

[0101] The first peripheral gate electrode 242 and the second peripheral gate electrode 442 can have the same or similar structures as the cell gate electrode 142 and the antifuse gate electrode 342, respectively. Figure 8 and Figure 9The first and second peripheral gate electrodes 242 and 342 described above can have the same or similar structures. In an example embodiment, the first peripheral gate electrode 242 can vertically overlap the first peripheral channel structure 210a, and the second peripheral gate electrode 442 can vertically overlap the second peripheral channel structure 210b. The portion of the first peripheral channel structure 210a vertically overlapping the first peripheral gate electrode 242 can correspond to a channel region, and the channel region and the first peripheral gate electrode 242 can form a reference Figure 7 The select transistor ST described above can include the second peripheral channel structure 210b vertically overlapping the second peripheral gate electrode 442. The portion of the second peripheral channel structure 210b vertically overlapping the second peripheral gate electrode 442 can correspond to a channel region, and the channel region and the second peripheral gate electrode 442 can be included in a reference Figure 7 The antifuse AF described above can include the second peripheral channel structure 210b vertically overlapping the second peripheral gate electrode 442. The portion of the second peripheral channel structure 210b vertically overlapping the second peripheral gate electrode 442 can correspond to a channel region, and the channel region and the second peripheral gate electrode 442 can be included in a reference

[0102] The first peripheral circuit region PERI1 can further include a second buffer layer 430, a second spacer 432, and a second gap-fill insulating layer 436 disposed between the second peripheral channel structures 210b. The second buffer layer 430, the second spacer 432, and the second gap-fill insulating layer 436 can have the same or similar structures as those of the first buffer layer 220, the first spacer 222, and the first gap-fill insulating layer 226, respectively.

[0103] The first peripheral circuit region PERI1 can further include a second peripheral gate dielectric layer 440, a second peripheral gate capping layer 444, and a second peripheral insulating layer 446. The second peripheral gate dielectric layer 440, the second peripheral gate capping layer 444, and the second peripheral insulating layer 446 can have the same or similar structures as those of the first peripheral gate dielectric layer 240, the first peripheral gate capping layer 244, and the first peripheral insulating layer 246, respectively.

[0104] An epitaxial layer 470 can be disposed between the first peripheral channel structure 210a and the second peripheral channel structure 210b spaced apart from each other along the X direction. The epitaxial layer 470 can include a first epitaxial layer 471 and a second epitaxial layer 472. The first epitaxial layer 471 and the second epitaxial layer 472 can be respectively formed from the first peripheral channel structure 210a and the second peripheral channel structure 210b by a selective epitaxial growth (SEG) method. For example, the first epitaxial layer 471 and the second epitaxial layer 472 can respectively grow from end portions of the first peripheral channel structure 210a and the second peripheral channel structure 210b, and can be integrated and coupled to each other. The first epitaxial layer 471 can extend from the end portion of the first peripheral channel structure 210a toward the second peripheral channel structure 210b in the X direction, and the second epitaxial layer 472 can extend toward the first peripheral channel structure 210a in the X direction. Maximum vertical thicknesses of the first epitaxial layer 471 and the second epitaxial layer 472 can be respectively greater than maximum vertical thicknesses of the first peripheral channel structure 210a and the second peripheral channel structure 210b. In an example embodiment, the first epitaxial layer 471 and the second epitaxial layer 472 can include impurities. The first epitaxial layer 471 and the second epitaxial layer 472 can electrically connect the first peripheral channel structure 210a to the second peripheral channel structure 210b.

[0105] The first peripheral circuit region PERI1 can further include an interlayer insulating layer 434. The interlayer insulating layer 434 can extend in the Y direction. The interlayer insulating layer 234 can extend in a vertical direction, and can contact the second pad 432, the second gap fill insulating layer 436, the second peripheral gate cap layer 444, the first epitaxial layer 471, and the second epitaxial layer 472. Further, an upper portion of the interlayer insulating layer 434 can extend in a horizontal direction, and can contact the first pad 222, the first peripheral gate dielectric layer 240, the first peripheral gate cap layer 244, the peripheral bit line 260, and the contact structure 265.

[0106] A first end of the peripheral channel structure 210 of the first peripheral circuit region PERI1 can contact the peripheral bit line 260, and can be electrically connected to the peripheral bit line 260. A second end of the peripheral channel structure 210 can be opposite the first end, and can contact the interlayer insulating layer 434. The second end of the peripheral channel structure 210 can be electrically floating.

[0107] In an example embodiment, the first peripheral gate electrode 242, the second peripheral gate electrode 442, and the peripheral bit line 260 of the first peripheral circuit region PERI1 can be formed in the same process as forming the cell gate electrode 142 and the cell bit line 160 of the memory cell region CA. Unlike in the memory cell region CA, an epitaxial process for forming the first epitaxial layer 471 and the second epitaxial layer 472 can also be performed in the first peripheral circuit region PERI1.

[0108] In the example embodiment, Figure 5A The length Lc of the unit channel structure 110 in the X direction can be different from the length Lp2 of the peripheral channel structure 210 in the X direction as shown in FIG. 1B. Figure 12 The length Lp2 of the peripheral channel structure 210 in the X direction can be greater than the length Lc of the unit channel structure 110 in the X direction.

[0109] Figure 14A to Figure 18B are plan views and vertical cross-sectional views sequentially showing processes of a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A are plan views corresponding to Figure 4 , and Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B are vertical cross-sectional views taken along line II-II' in Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A .

[0110] Referring to Figure 14A and Figure 14B , a molded structure MD can be formed on the substrate 103. The molded structure MD can include alternating stacks of channel material layers 110p and sacrificial layers 112. An upper surface of the substrate 103 can be in contact with one of the sacrificial layers 112. The sacrificial layers 112 can include a material having etch selectivity to the channel material layers 110p.

[0111] In the example embodiment, the channel material layers 110p can include silicon, and the sacrificial layers 112 can include silicon germanium, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof. In the example embodiment, the channel material layers 110p can include silicon oxide, and the sacrificial layers 112 can include silicon nitride, silicon oxynitride, or a combination thereof.

[0112] An insulating pattern 114 can be provided in the molded structure MD. A first trench T1 extending in the X direction can be formed by anisotropic etching of the molded structure MD, and the first trench T1 can be filled with an insulating material to form the insulating pattern 114. The insulating pattern 114 can extend in the X direction, and can be spaced apart from each other in the X direction and the Y direction. The insulating pattern 114 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the insulating pattern 114 can include silicon oxide. In Figure 14AIn the embodiment, six insulating patterns 114 are shown, but the example embodiments are not limited thereto, and the number of the insulating patterns 114 and their arrangement can vary in the example embodiments.

[0113] Referring to Figure 15A and Figure 15B A second trench T2 can be formed. The second trench T2 can be formed by anisotropically etching the mold structure MD using the first mask layer M1 and the second mask layer M2 as etching masks. The second trench T2 can be disposed adjacent to the insulating pattern 114, and can extend in the Y direction. In the etching process, the upper surface of the substrate 103 can be partially etched.

[0114] Thereafter, the sacrificial layer 112 can be partially etched. For example, the sacrificial layer 112 can be partially etched in the horizontal direction by supplying an etchant into the second trench T2. The channel material layer 110p, which has etching selectivity with respect to the sacrificial layer 112, can not be etched. By etching the sacrificial layer 112, the upper surface and the lower surface of a portion of the channel material layer 110p can be exposed by the second trench T2. The term "exposed" can be used to describe a relationship between elements and / or certain intermediate processes in the fabrication of a complete semiconductor device, but does not necessarily require that a particular area, layer, structure, or other element be exposed in the context of a complete device.

[0115] Referring to Figure 16A and Figure 16B The channel material layer 110p exposed by the second trench T2 can be partially etched. For example, the portions of the channel material layer 110p exposed by the second trench T2 can be etched, and can be spaced apart from each other in the Y direction. By the etching process, the insulating pattern 114 can be exposed by the second trench T2.

[0116] Thereafter, the insulating pattern 114 can be partially etched. For example, by the etching process, the second trench T2 can extend in the X direction, and the length of the insulating pattern 114 in the X direction can be reduced. A portion of the side surface of the channel material layer 110p can be exposed by the second trench T2.

[0117] A first buffer layer 120, a first pad 122, and a first gap fill insulating layer 124p can be formed in the second trench T2. In a plan view, the first buffer layer 120 can conformally extend along the channel material layer 110p, and can be in contact with the insulating pattern 114. In a cross-sectional view, the first buffer layer 120 can cover the upper surface of the substrate 103, and the upper surface and the lower surface of the channel material layer 110p. The first pad 122 can be disposed on the first buffer layer 120, and can be conformally formed along the first buffer layer 120. The first gap fill insulating layer 124p can be formed on the first pad 122, and can fill the second trench T2.

[0118] The first buffer layer 120, the first liner 122, and the first gap fill insulating layer 124p can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first liner 122 can include a material having etching selectivity with respect to the first buffer layer 120 and the first gap fill insulating layer 124p. For example, the first liner 122 can include silicon nitride, and the first buffer layer 120 and the first gap fill insulating layer 124p can include silicon oxide.

[0119] A third trench T3 can be formed. The third trench T3 can be formed by anisotropically etching the mold structure MD using the first mask layer M1 and the third mask layer M3 as etching masks. The third trench T3 can extend in the Y direction, and can be alternately disposed with the second trench T2 in the X direction. In the etching process, the upper surface of the substrate 103 can be partially etched.

[0120] Thereafter, the sacrificial layer 112 can be partially etched. For example, the sacrificial layer 112 can be partially etched by supplying an etchant in the third trench T3. A portion of the upper surface and the lower surface of the channel material layer 110p can be exposed by the third trench T3.

[0121] Reference Figure 17A and Figure 17B The channel material layer 110p exposed by the third trench T3 can be partially etched. For example, a portion of the channel material layer 110p exposed by the third trench T3 can be etched, and a unit channel structure 110 spaced apart from each other in the Y direction can be formed. Through the etching process, the insulating pattern 114 can be exposed by the third trench T3.

[0122] Thereafter, the insulating pattern 114 can be removed, and a portion of the side surface of the unit channel structure 110 can be exposed by the third trench T3.

[0123] A second buffer layer 130, a second liner 132, a second gap fill insulating layer 134p, and an upper insulating layer 136 can be formed in the third trench T3. In a plan view, the second buffer layer 130 can conformingly extend along the unit channel structure 110, and can be in contact with the first buffer layer 120. In a cross-sectional view, the second buffer layer 130 can cover the upper surface of the substrate 103, and the upper surface and the lower surface of the unit channel structure 110. The second liner 132 can be disposed on the second buffer layer 130, and can be conformingly formed along the second buffer layer 130. The second gap fill insulating layer 134p can be formed on the second liner 132, and can fill the third trench T3. The upper insulating layer 136 can cover the upper surface of the second gap fill insulating layer 134p.

[0124] The second buffer layer 130, the second liner 132, and the second gap fill insulating layer 134p can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second liner 132 can include a material having etch selectivity with respect to the second buffer layer 130 and the second gap fill insulating layer 134p. For example, the second liner 132 can include silicon nitride, and the second buffer layer 130 and the second gap fill insulating layer 134p can include silicon oxide. The upper insulating layer 136 can include silicon nitride.

[0125] The first buffer layer 120, the first liner 122, and the first gap fill insulating layer 124p can be partially etched, and a dielectric material layer 140p and a cell gate electrode 142 can be formed. For example, a fourth trench T4 can be formed by partially etching the first buffer layer 120, the first liner 122, and the first gap fill insulating layer 124p. The fourth trench T4 can be formed in a space in which the second trench T2 has been disposed. The first gap fill insulating layer 124p can be etched such that a first gap fill insulating layer 124 can be formed.

[0126] First, upper and lower surfaces of the cell channel structure 110 can be exposed by the fourth trench T4 by partially etching the first buffer layer 120, the first liner 122, and the first gap fill insulating layer 124p. The dielectric material layer 140p can be conformally formed along inner walls of the fourth trench T4. For example, the substrate 103 and the dielectric material layer 140p can be conformally disposed along the cell channel structure 110 and the first gap fill insulating layer 124. Thereafter, the cell gate electrode 142 can be formed by forming a conductive material on the dielectric material layer 140p and etching back the conductive material. The cell gate electrode 142 can be disposed between the cell channel structure 110 and the first gap fill insulating layer 124.

[0127] Reference Figure 18A and Figure 18B The insulating structure 150 and the cell bit line 160 can be formed in the fourth trench T4. For example, the dielectric material layer 140p can be partially etched, and the cell channel structure 110 can be exposed by the fourth trench T4. The dielectric material layer 140p can be etched to form a cell gate dielectric layer 140. A conductive material can be formed to be in contact with the cell channel structure 110, and the cell bit line 160 can be formed by patterning the conductive material.

[0128] Before the conductive material is formed, a gate capping layer 144 covering side surfaces of the cell gate electrode 142 can be formed. The first gap fill insulating layer 126 and the insulating layer 146 can be formed by depositing an insulating material between the exposed cell channel structures 110. The first gap fill insulating layer 126 can be disposed in positions corresponding to the first gap fill insulating layer 124, and can fill gaps between the gate capping layers 144 adjacent to each other. The insulating layer 146 can be disposed between the cell gate dielectric layer 140 and the cell bit line 160.

[0129] The cell bit line 160 can be in contact with the cell channel structure 110, the first gap fill insulating layer 126, the gate capping layer 144, and the insulating layer 146. The cell bit line 160 can have a scallop shape in a cross-sectional view, but example embodiments thereof are not limited thereto.

[0130] In a plan view, the insulating structure 150 can be disposed between the cell bit lines 160. For example, the insulating structure 150 and the cell bit line 160 can extend in an X direction, and the insulating structure 150 can be alternately disposed with the cell bit line 160 in a Y direction. The insulating structure 150 can spatially isolate and electrically insulate the cell bit lines 160 from each other.

[0131] Each insulating structure 150 can include a first insulating pattern 152, a second insulating pattern 154, and a third insulating pattern 156. The first insulating pattern 152 can be in contact with the cell channel structure 110, the gate capping layer 144, and the cell bit line 160. The second insulating pattern 154 can be conformally formed along an inner wall of the first insulating pattern 152. The third insulating pattern 156 can fill an inner space of the second insulating pattern 154.

[0132] A contact structure 165 can be formed on the cell bit line 160. The contact structure 165 can include a first conductive layer 163 and a second conductive layer 164. The first conductive layer 163 can be in contact with an upper surface of the cell bit line 160, and the second conductive layer 164 can be disposed on the first conductive layer 163. The contact structure 165 can also be referred to as a "cell contact structure."

[0133] Before the contact structure 165 is formed, the upper insulating layer 136 can be removed, and the second gap fill insulating layer 134p can be exposed, and after the contact structure 165 is formed, by depositing an insulating material on the second gap fill insulating layer 134p, a second gap fill insulating layer 134p' can be formed. The second gap fill insulating layer 134p' can cover side surfaces of the contact structure 165.

[0134] Referring again to Figure 4 , Figure 5A and Figure 5B, a capacitor structure 170 and a contact plug 180 may be formed. The capacitor structure 170 may be electrically connected to each cell channel structure 110 and may be disposed between the cell bit lines 160. The capacitor structure 170 may be in contact with the cell channel structure 110 and may extend in a vertical direction. The capacitor structure 170 may include a first electrode 171 in contact with the cell channel structure 110, a second electrode 172 on the first electrode 171, a plate electrode 175 on the second electrode 172, and a capacitor dielectric 173 between the first electrode 171 and the second electrode 172. The contact plug 180 may be disposed on the plate electrode 175.

[0135] According to the aforementioned example embodiments, since the first peripheral circuit region is disposed at the same level or layer of the semiconductor structure as the memory cell region, the size of the semiconductor device can be reduced. Unless otherwise specified, spatially relative terms such as "upper," "upper surface," "below," "lower," "lower surface," "side surface," and the like may be represented by reference numerals and with reference to the accompanying drawings. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. For example, if the device in the drawings is flipped, elements described as being "below" or "beneath" other elements or features will be positioned "above" the other elements or features.

[0136] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device comprising: a memory cell region; and a peripheral circuit region adjacent to the memory cell region in a first horizontal direction, wherein the memory cell region includes: a cell channel structure extending in the first horizontal direction and stacked and spaced apart from each other in a vertical direction perpendicular to the first horizontal direction; a cell bit line extending in the vertical direction and in contact with the cell channel structure; and a cell gate electrode overlapping the cell channel structure in the vertical direction and extending in a second horizontal direction intersecting the first horizontal direction, wherein the peripheral circuit region includes: a peripheral channel structure extending in the first horizontal direction; a peripheral bit line extending in the vertical direction and in contact with the peripheral channel structure; and a first peripheral gate electrode and a second peripheral gate electrode overlapping the peripheral channel structure in the vertical direction and extending in the second horizontal direction, wherein the first peripheral gate electrode is closer to the peripheral bit line than the second peripheral gate electrode, and wherein at least one of the cell channel structures is located at the same level as the peripheral channel structure in the vertical direction. at least one of the cell gate electrodes is located at the same level as at least one of the first peripheral gate electrode and the second peripheral gate electrode in the vertical direction.

2. The semiconductor device of claim 1, wherein, the first peripheral gate electrode is located at the same level as the second peripheral gate electrode in the vertical direction.

3. The semiconductor device of claim 1, wherein, the peripheral channel structure includes a first end electrically connected to the peripheral bit line and a second end opposite the first end and electrically floating.

4. The semiconductor device of claim 1, wherein, 5. The semiconductor device of claim 1, further comprising: an interlayer insulating layer in contact with the peripheral channel structure, wherein the first end of the peripheral channel structure is in contact with the peripheral bit line and the second end of the peripheral channel structure is opposite the first end and in contact with the interlayer insulating layer.

6. The semiconductor device of claim 1, the peripheral channel structure includes a first portion and a second portion that respectively overlap the first peripheral gate electrode and the second peripheral gate electrode in the vertical direction, wherein, wherein the first peripheral gate electrode and the first portion of the peripheral channel structure provide a select transistor, and wherein the second peripheral gate electrode and the second portion of the peripheral channel structure provide an antifuse. the select transistor has a first threshold voltage and the antifuse has a second threshold voltage different from the first threshold voltage.

7. The semiconductor device of claim 6, wherein, in the first horizontal direction, a gate length of the first peripheral gate electrode is different from a gate length of the second peripheral gate electrode.

8. The semiconductor device of claim 7, wherein, 9. The semiconductor device of claim 7, further comprising: first and second peripheral gate dielectric layers, the first peripheral gate dielectric layer being between the peripheral channel structure and the first peripheral gate electrode, and the second peripheral gate dielectric layer being between the peripheral channel structure and the second peripheral gate electrode, wherein the second peripheral gate dielectric layer is thinner than the first peripheral gate dielectric layer. ​ 10. The semiconductor device of claim 7, wherein, The peripheral channel structure includes a first peripheral channel structure, a second peripheral channel structure spaced apart from the first peripheral channel structure in the first horizontal direction, and an epitaxial layer connecting the first peripheral channel structure to the second peripheral channel structure.

11. The semiconductor device of claim 10, wherein, The epitaxial layer includes a first epitaxial layer extending from an end of the first peripheral channel structure toward the second peripheral channel structure, and a second epitaxial layer extending from an end of the second peripheral channel structure toward the first peripheral channel structure.

12. The semiconductor device of claim 11, wherein, In the vertical direction, a maximum vertical thickness of the first epitaxial layer is greater than a maximum vertical thickness of at least one of the first peripheral channel structure or the second peripheral channel structure.

13. The semiconductor device of claim 1, wherein, The peripheral channel structure is longer than the cell channel structure in the first horizontal direction.

14. The semiconductor device of claim 1, wherein, In the first horizontal direction, a gate length of the first peripheral gate electrode is the same as a gate length of at least one of the cell gate electrodes.

15. A semiconductor device, comprising: a first structure including a memory cell region and a first peripheral circuit region; and a second structure overlapping the first structure in a vertical direction and including a core circuit region and a second peripheral circuit region, wherein the first peripheral circuit region includes: a peripheral channel structure extending in a first horizontal direction perpendicular to the vertical direction; a peripheral bit line extending in the vertical direction and in contact with the peripheral channel structure; and a first peripheral gate electrode and a second peripheral gate electrode overlapping the peripheral channel structure in the vertical direction and extending in a second horizontal direction intersecting the first horizontal direction, wherein the first peripheral gate electrode is closer to the peripheral bit line than the second peripheral gate electrode, and wherein the first peripheral circuit region overlaps the second peripheral circuit region in the vertical direction.

16. The semiconductor device of claim 15, wherein, The memory cell region overlaps the core circuit region in the vertical direction.

17. The semiconductor device of claim 15, wherein the memory cell region includes memory cells including cell transistors and capacitor structures, wherein the core circuit region includes core circuit transistors overlapping the memory cell region in the vertical direction, and wherein the second peripheral circuit region includes peripheral circuit transistors overlapping the first peripheral circuit region in the vertical direction.

18. The semiconductor device of claim 17, wherein the memory cell region includes contact plugs on the capacitor structures, wherein the first peripheral circuit region includes peripheral contact structures on the peripheral bit lines, and wherein at least a portion of the peripheral contact structures and the contact plugs have respective surfaces that are substantially coplanar.

19. The semiconductor device of claim 18, wherein, the memory cell region includes: cell channel structures extending in the first horizontal direction and stacked and spaced apart from each other in the vertical direction; cell bit lines extending in the vertical direction and in contact with the cell channel structures; and cell contact structures on the cell bit lines, wherein at least one of the cell channel structures and the peripheral channel structure have respective surfaces that are substantially coplanar.

20. A semiconductor device, comprising: a memory cell region; and a peripheral circuit region adjacent to the memory cell region in a first horizontal direction, wherein the memory cell region includes: cell channel structures extending in the first horizontal direction and stacked and spaced apart from each other in a vertical direction perpendicular to the first horizontal direction; cell bit lines extending in the vertical direction and in contact with the cell channel structures; capacitor structures extending in the vertical direction and in contact with the cell channel structures; cell gate electrodes overlapping the cell channel structures in the vertical direction and extending in a second horizontal direction intersecting the first horizontal direction; cell gate dielectric layers between the cell channel structures and the cell gate electrodes; and cell contact structures on the cell bit lines, wherein the peripheral circuit region includes: peripheral channel structures extending in the first horizontal direction; peripheral bit lines extending in the vertical direction and in contact with the peripheral channel structures; first and second peripheral gate electrodes overlapping the peripheral channel structures in the vertical direction and extending in the second horizontal direction, wherein the first peripheral gate electrode is closer to the peripheral bit lines than the second peripheral gate electrode; first peripheral gate dielectric layers between the peripheral channel structures and the first peripheral gate electrodes; and peripheral contact structures on the peripheral bit lines, wherein at least one of the cell channel structures and the peripheral channel structure have respective surfaces that are substantially coplanar, and wherein at least a portion of the peripheral contact structures and the cell contact structures have respective surfaces that are substantially coplanar.

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