Semiconductor element with bit line structure and preparation method thereof

Abstract

The invention provides a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a substrate and a bit line structure arranged on the substrate. The bit line structure includes an insulating spacer structure defining an air side liner. The semiconductor device also includes a sealing layer disposed over the insulating spacer structure to cover the air side liner. The sealing layer comprises a carbon-containing material.

Description

[0001] This application is a divisional application of Chinese Invention Patent Application No. 202411068871.7, filed on August 6, 2024, entitled “Semiconductor Element with Bitline Structure and Method of Fabricating the Same,” which claims priority to and the benefit of U.S. Utility Application No. 18 / 643,049, filed on April 23, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor element and a method of fabricating the same. In particular, the present disclosure relates to a bitline structure with an air spacer. BACKGROUND

[0003] In a semiconductor element, a storage node contact can be formed between adjacent bitline structures. In a conventional process, an air gap is typically formed to electrically insulate the adjacent bitline structures from their corresponding storage node contacts.

[0004] When the molding layer around the capacitor bottom electrode is partially removed by a wet etching process, the wet etchant can penetrate the bottom of the air gap and etch the adjacent spacer and storage node contact. This etching problem can degrade the performance of the semiconductor element and is a limiting factor that must be addressed to achieve further enhancement of the integration of the semiconductor element.

[0005] The above discussion of the background art is provided for the purpose of context only and is not admitted as prior art to the present disclosure. Any discussion of the background art is intended to be merely an example of the background art and should not be construed as an admission that the background art was prior art to the present disclosure. SUMMARY

[0006] One aspect of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate and a bitline structure disposed over the substrate. The bitline structure includes an insulating spacer structure defining an air spacer. The semiconductor element also includes a sealing layer disposed over the insulating spacer structure to cover the air spacer. The sealing layer includes a carbon-containing material.

[0007] Another aspect of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate, a bitline structure disposed over the substrate, and a landing pad disposed over the bitline structure and having a recessed region. The semiconductor element also includes a first sealing layer disposed in the recessed region. The first sealing layer includes a carbon-containing material.

[0008] Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a landing pad over a bit line structure and forming a recessed region in the landing pad. The method also includes removing a portion of the bit line structure and disposing a first sealing layer in the recessed region.

[0009] The sealing layer is resistant enough to, for example, a wet etching solution to prevent over-etching and penetration of the bottom of the air gap. For example, the sealing layer can sufficiently function as an etch stop layer in a subsequent etching process. Thus, the erosion problem can be solved. The performance and operational reliability of the semiconductor device can also be improved.

[0010] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter in the detailed description of the present disclosure. It should be appreciated that the concepts and technologies disclosed with respect to the particular embodiment discussed below can be extended or adapted to other embodiments that will be apparent to those of ordinary skill in the art upon reading the detailed description of the present disclosure. It is intended that the present disclosure cover adaptations and modifications of the concepts and technologies disclosed herein that are within the scope of the claims of the present disclosure. It should be understood that the present disclosure is not intended to limit the concepts and technologies disclosed herein to particular forms disclosed but rather, it is intended to cover all possible modifications and equivalent arrangements. BRIEF DESCRIPTION OF DRAWINGS

[0011] A more complete understanding of the present disclosure can be obtained by reference to the following detailed description when taken in conjunction with the accompanying drawings. The present disclosure should be understood to be in no way limited to the particular form disclosed but is intended to cover all modifications, equivalents, and alternatives falling within the scope of the claims.

[0012] Figure 1A A cross-sectional view of a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0013] Figure 1A An enlarged view of a portion of a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0014] Figure 2A A cross-sectional view of one or more stages of a method of fabricating a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0015] Figure 2B A cross-sectional view of one or more stages of a method of fabricating a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0016] Figure 2C A cross-sectional view of one or more stages of a method of fabricating a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0017] Figure 2D A cross-sectional view of one or more stages of a method of fabricating a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0018] Figure 2E According to some embodiments of the disclosure, cross-sectional schematic views of one or more stages of a method of fabricating a semiconductor device are shown.

[0019] Figure 2F According to some embodiments of the disclosure, cross-sectional schematic views of one or more stages of a method of fabricating a semiconductor device are shown.

[0020] Figure 2G According to some embodiments of the disclosure, cross-sectional schematic views of one or more stages of a method of fabricating a semiconductor device are shown.

[0021] Figure 2H According to some embodiments of the disclosure, cross-sectional schematic views of one or more stages of a method of fabricating a semiconductor device are shown.

[0022] Figure 2I According to some embodiments of the disclosure, cross-sectional schematic views of one or more stages of a method of fabricating a semiconductor device are shown.

[0023] Figure 2J According to some embodiments of the disclosure, cross-sectional schematic views of one or more stages of a method of fabricating a semiconductor device are shown.

[0024] Figure 2K According to some embodiments of the disclosure, cross-sectional schematic views of one or more stages of a method of fabricating a semiconductor device are shown.

[0025] Figure 3 According to some embodiments of the disclosure, a flowchart of a method of fabricating a semiconductor device is shown.

[0026] Wherein, the reference numerals are explained as follows:

[0027] 1a: semiconductor device

[0028] 10: substrate

[0029] 10a: active region

[0030] 10d1: interlayer

[0031] 10i: isolation region

[0032] 11: bit line structure

[0033] 11a: bit line overlay pattern

[0034] 11b: conductive pattern

[0035] 11c: conductive pattern

[0036] 11d: bit line contact

[0037] 11h1: recessed region

[0038] 11h2: recessed area

[0039] 11s1: spacer

[0040] 11s2: spacer

[0041] 11s3: spacer

[0042] 12: bit line structure

[0043] 12a: bit line overlay pattern

[0044] 12b: conductive pattern

[0045] 12c: conductive pattern

[0046] 12d: bit line contact

[0047] 12s1: spacer

[0048] 12s2: spacer

[0049] 12s3: spacer

[0050] 13: storage node contact

[0051] 14: metal silicide film

[0052] 15: landing pad

[0053] 15h1: recessed area

[0054] 15h2: recessed area

[0055] 16: encapsulation layer

[0056] 17: encapsulation layer

[0057] 18: interposer

[0058] 19: bottom electrode

[0059] 20: first molding layer

[0060] 21: first support layer

[0061] 22: second molding layer

[0062] 23: second support layer

[0063] 23h: contact hole

[0064] 30: method

[0065] 101: doped region

[0066] 102: doped region

[0067] S31: step

[0068] S32: step

[0069] S33: step

[0070] S34: step

[0071] S35: step

[0072] S36: step DETAILED DESCRIPTION

[0073] The embodiments of the present disclosure shown in the drawings are described using specific language and terminology. It is to be understood that the terminology is for the purpose of describing the embodiments and is not intended to be limiting. Any alterations and / or modifications of the described embodiments, and any further applications of the principles described herein, are contemplated with respect to the scope of the present disclosure. Reference signs can be repeated in all figures for elements performing substantially the same functions.

[0074] It is to be understood that the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers, or sections but do not to imply these elements, components, regions, layers, or sections should be limited to these terms. Rather, the terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the present disclosure.

[0075] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the concepts of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0076] Figure 1A A cross-sectional schematic view of a semiconductor element 1a is shown in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor element 1a can be disposed adjacent to a circuit. For example, the semiconductor element 1a can be disposed adjacent to a memory element such as a dynamic random access memory (DRAM) element or the like.

[0077] ReferringFigure 1A The semiconductor element 1a can include a substrate 10 and bit line structures 11 and 12. The bit line structures 11 and 12 can be disposed on the substrate 10.

[0078] The substrate 10 can include a semiconductor substrate. In some embodiments, the semiconductor material of the substrate 10 can include, for example, silicon (Si) (such as single-crystal silicon, polycrystalline silicon, and amorphous silicon), germanium (Ge), gallium (Ga), and indium (In). In some embodiments, the semiconductor material of the substrate 10 can include a compound semiconductor, including silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbide (SiGeC), gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials.

[0079] In some embodiments, the substrate 10 can include a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a multilayer substrate, or a gradient substrate. For example, an SOI substrate can include a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer can be disposed on a substrate, typically a silicon or glass substrate. In some embodiments, the substrate 10 can be a wafer, such as a silicon wafer. The substrate 10 can be doped (e.g., with P-type or N-type dopants) or undoped.

[0080] The substrate 10 can include active regions 10a and isolation regions 10i. The active regions 10a can be defined by the isolation regions 10i, as viewed from a top view. For example, the active regions 10a can be separated from each other by the isolation regions 10i.

[0081] The active regions 10a and the isolation regions 10i can be formed in the substrate 10. In some embodiments, the isolation regions 10i can include shallow trench isolation (STI) structures.

[0082] The wall oxide, liner, and gap fill dielectric can be formed in sequence as the isolation region 10i. The liner can be formed of stacked silicon oxide (SiO2) and silicon nitride (Si3N4). The gap fill dielectric can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), a low-k dielectric material (e.g., phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.), or a similar material, or a combination of the foregoing. In another embodiment, silicon nitride can be used as the gap fill dielectric in the isolation region 10i.

[0083] The substrate 10 can include a plurality of doped regions, such as doped regions 101 and 102. The doped regions 101 and 102 can be formed in the active region 10a. In some embodiments, the doped regions 101 and 102 can be disposed on or near a top surface of the active region 10a. The doped regions 101 and 102 can be separated from each other by the isolation region 10i. For example, the doped region 102 can be disposed between the doped regions 101 and separated from the doped regions 101 by the isolation region 10i.

[0084] In some embodiments, the doped regions 101 and 102 can be doped with an N-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). In some other embodiments, the doped regions 101 and 102 can be doped with a P-type dopant, such as boron (B) or indium (In). In some embodiments, the doped regions 101 and 102 can be doped with dopants or impurity ions having the same conductivity type. In some embodiments, the doped regions 101 and 102 can be doped with dopants or impurity ions having different conductivity types.

[0085] The bottom surfaces of the doped regions 101 and 102 can be located at a predetermined depth from the top surface of the active region 10a. The doped regions 101 and 102 can be adjacent to sidewalls of the isolation region 10i. The bottom surfaces of the doped regions 101 and 102 can be higher than a bottom surface of the isolation region 10i.

[0086] In some embodiments, the doped regions 101 and 102 can be referred to as source / drain regions. In some embodiments, the doped region 101 can include a bit line contact region and can be electrically connected to the bit line structure 11. The doped region 102 can include a storage node contact region and can be electrically connected to the memory element through the storage node contact 13. In some embodiments, the memory element can be a capacitor and can include a bottom electrode (e.g., the bottom electrode 19), a top electrode, and a dielectric layer therebetween. In other embodiments, the memory element can be a variable resistance pattern that is capable of switching between two resistance states by an electrical pulse applied to the memory element. For example, the memory element can include a phase change material that is capable of changing a crystal state according to an amount of electricity, such as a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0087] The interlayer 10d1 can be disposed on the substrate 10. The interlayer 10d1 can be disposed on a top surface of the active region 10a. The interlayer 10d1 can include a single insulating layer or multiple insulating layers. The interlayer 10d1 can include an isolation material or a dielectric material. The interlayer 10d1 can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride.

[0088] The recessed region 11h1 can be formed in the substrate 10. The bit line structure 11 can be disposed in the recessed region 11h1 and contact (e.g., directly contact) the doped region 101. Thus, the doped region 101 can include a bit line contact region.

[0089] The recessed region 11h1 can be formed between the isolation regions 10i. The recessed region 11h1 can be formed to expose the doped region 101 between the isolation regions 10i.

[0090] The recessed region 11h1 can be recessed into the substrate 10 from a top surface of the active region 10a and / or the interlayer 10d1. A width of the recessed region 11h1 can be greater than a distance between the isolation regions 10i.

[0091] A bottom surface of the recessed region 11h1 can be located at a higher position than a bottom surface of the doped region 101. For example, the recessed region 11h1 can not extend beyond the bottom surface of the doped region 101.

[0092] The recessed region 11h2 can be formed in the substrate 10 to expose the doped region 102. The doped region 102 can contact the storage node contact 13. Thus, the doped region 102 can include a storage node contact region.

[0093] The recessed region 11h2 may be recessed from the top surface of the active region 10a and / or the interposer 10d1. The recessed region 11h2 may be adjacent to the recessed region 11h1.

[0094] The storage node contact 13 may pass through the interposer 10d1 to contact (eg, directly contact) the doped region 102. A bottom surface of the storage node contact 13 may be located lower than a bottom surface of the recessed region 11h1.

[0095] The metal silicide film 14 may be formed on the storage node contact 13. The landing pad 15 may be connected to the storage node contact 13, and the metal silicide film 14 may be formed between the landing pad 15 and the storage node contact 13.

[0096] The metal silicide film 14 may include cobalt silicide, nickel silicide, manganese silicide, titanium silicide, or the like.

[0097] Landing pad 15 may be disposed between adjacent bit line structures, such as between bit line structures 11 and 12. Landing pad 15 may vertically overlap bit line structures 11 and 12. Landing pad 15 may be electrically connected to storage node contact 13.

[0098] Landing pad 15 and storage node contact 13 may each include a conductive material. Landing pad 15 and storage node contact 13 may each include a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and tungsten nitride), and a metal semiconductor compound (e.g., metal silicide).

[0099] The bit line structure 11 may include a bit line contact 11 d and stack patterns such as a conductive pattern 11 c , a conductive pattern 11 b , and a bit line capping pattern 11 a .

[0100] A bitline contact 11d may be disposed in the recessed region 11h1. A portion of the bitline contact 11d may contact (e.g., directly contact) the doped region 101. A bottom surface of the bitline contact 11d may be located lower than the top surface of the active region 10a or lower than the interposer 10d1. The bitline contact 11d may include doped polysilicon.

[0101] The conductive pattern 11 c may include any suitable material, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N, WN, WN2), the like, or combinations thereof.

[0102] The conductive pattern 11 b may include any suitable metal, such as tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co), the like, or combinations thereof.

[0103] The bit line capping pattern 11 a may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and / or silicon oxynitride.

[0104] The bit line structure 11 may include an insulating spacer structure. The insulating spacer structure may include spacers 11s1, 11s2, and 11s3 formed on both sidewalls of the bit line structure 11. The spacers 11s1, 11s2, and 11s3 may also be referred to as a first spacer, a second spacer, and a third spacer.

[0105] Spacer 11s1 may be disposed between spacer 11s2 and a sidewall of the bit line structure 11. For example, spacer 11s1 may directly contact a sidewall of the bit line structure 11. Spacer 11s2 may be disposed between spacer 11s1 and spacer 11s3. Spacer 11s3 may be the outermost spacer of the bit line structure 11.

[0106] The spacer 11s2 may include an oxygen-containing material, such as silicon oxide (SiO2). The spacer 11s2 may include or define an air spacer filled with air. In some embodiments, the spacer 11s2 may include a combination of an oxygen-containing material and an air spacer.

[0107] As used herein, a spacer may refer to any structure that provides electrical insulation between conductive structures, and an air liner or air gap may refer to an insulating structure that provides electrical insulation by air in the absence of other insulating materials.

[0108] The spacers 11s1 and 11s3 may each include a nitrogen-containing material such as silicon nitride (Si3N4). The spacers 11s1 and 11s3 may be connected to each other.

[0109] In some embodiments, the air liner can be defined by an oxygen-containing material (e.g., at the bottom of spacer 11s2) and a nitrogen-containing material (the material of spacers 11s1 and 11s3). For example, the oxygen-containing material can define the bottom of the air liner, and the nitrogen-containing material can define the sidewalls of the air liner.

[0110] In some embodiments, spacer 11s1 may have a first dielectric constant, spacer 11s2 may have a second dielectric constant, and spacer 11s3 may have a third dielectric constant.

[0111] The first dielectric constant may be equal to the third dielectric constant. The second dielectric constant may be lower than the first dielectric constant. The second dielectric constant may be lower than the third dielectric constant.

[0112] For example, the third dielectric constant can be about 7.5, and the second dielectric constant can be less than about 7.5. For example, the second dielectric constant can be about 3.9. For example, the second dielectric constant can range from about 1.0 to 3.9.

[0113] In some embodiments, spacers 11s2 may be disposed between the bit line structure 11 and the storage node contact 13. By using spacers with a low dielectric constant, such as spacers 11s2, parasitic capacitance issues between bit line structures and / or between the bit line structure and the storage node contact may be further reduced.

[0114] In some embodiments, a higher portion of the spacer 11s2 may contact a sealing layer 16. For example, the spacer 11s2 may be enclosed or covered by the sealing layer 16. The sealing layer 16 may include a different material than the spacers 11s1, 11s2, and 11s3.

[0115] The landing pad 15 may define a recessed region 15h1 and a recessed region 15h2. The recessed region 15h1 may be disposed on or above the insulating spacer structure of the bit line structure 11. The recessed region 15h2 may be disposed on or above the insulating spacer structure of the bit line structure 12.

[0116] The sealing layer 16 may be disposed in the recessed area 15h1 , along the contour of the recessed area 15h1 , or may not completely fill the recessed area 15h1 .

[0117] The sealing layer 17 may be arranged along the contour of the sealing layer 16. The sealing layer 17 may not fill the recessed area 15h1. The sealing layer 16 and the sealing layer 17 may also be referred to as a first sealing layer and a second sealing layer.

[0118] Sealing layer 16 and sealing layer 17 may comprise different materials. For example, sealing layer 16 may comprise a carbon-containing material such as silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), and silicon oxycarbonitride (SiOCN). Sealing layer 17 may each comprise a nitrogen-containing material such as silicon nitride (Si3N4).

[0119] The sealing layer 16 and the sealing layer 17 may define an air gap. The air gap defined by the sealing layer 16 and the sealing layer 17 may be closed or covered by the intermediate layer 18. The air gap may be filled with air.

[0120] The recessed area 15h1 may be exposed to air through the interposer 18. For example, Figure 2KDuring the etching process, the interlayer 18 can be penetrated, and a portion of the sealing layer 17 can also be etched. The sealing layer 16 in the recessed region 15h1 can be exposed to air through the sealing layer 17. For example, the sealing layer 16 in the recessed region 15h1 can be partially covered by the sealing layer 17, and partially exposed to air.

[0121] The sealing layer 16 can be exposed to air in the recessed region 15h1 and air in the spacer 11s2. The sealing layer 16 can separate the air in the recessed region 15h1 and the air in the spacer 11s2.

[0122] The interlayer 18 can be disposed on the landing pad 15. The interlayer 18 can include silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride. The interlayer 18 can be a single layer or multiple layers. The sealing layer 16 can contact the interlayer 18.

[0123] The bottom electrode (or lower electrode) 19 can be disposed on the landing pad 15. The bottom electrode 19 can overlap the bit line structure 11 and 12 in the vertical direction. The bottom electrode 19 can be electrically connected to the storage node contact 13.

[0124] The bottom electrode 19 can include a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and tantalum), a conductive metal nitride (e.g., titanium nitride, aluminum titanium nitride, silicon titanium nitride, tantalum nitride, aluminum tantalum nitride, silicon tantalum nitride, and tungsten nitride), a conductive metal oxide (e.g., iridium oxide), or other conductive materials.

[0125] In some embodiments, the sealing layer 16 can truncate the spacer 11s1 and contact (e.g., directly contact) the bit line overlay pattern 11a of the bit line structure 11.

[0126] The bit line structure 12 can be separated (or isolated) from the bit line structure 11 by the storage node contact 13. The bit line structure 12 can be disposed on the interlayer 10d1. The bit line structure 12 can be separated (or isolated) from the substrate 10 by the interlayer 10d1.

[0127] The bit line structure 12 can include a bit line contact 12d and a stack pattern (e.g., a conductive pattern 12c, a conductive pattern 12b, and a bit line overlay pattern 12a). The bit line structure 12 can include an insulating spacer structure. The insulating spacer structure can include spacers 12s1, 12s2, and 12s3 formed on two sidewalls of the bit line structure 12.

[0128] The spacer 12s2 can include an oxygen-containing material, such as silicon oxide (SiO2). The spacer 12s2 can include an air edge liner filled with air. In some embodiments, the spacer 12s2 can include a combination of an oxygen-containing material and an air edge liner.

[0129] In some embodiments, the higher portion of the spacer 12s2 can contact the sealing layer 16. For example, the spacer 12s2 can be enclosed or covered by the sealing layer 16.

[0130] Detailed descriptions of the bit line structure 12 can refer to the detailed descriptions of the bit line structure 11 described above, and are not repeated for brevity.

[0131] In conventional processes, air gaps (such as the air gap defined by the sealing layer 16 and the sealing layer 17) can be formed to electrically insulate the adjacent bit line structures from their respective storage nodes.

[0132] When the molding layer around the capacitor bottom electrode is partially removed by a wet etching process (such as the operation in Figure 2K , the wet etching solution can penetrate the bottom of the air gap and erode the adjacent spacer and storage node contact. This erosion problem can degrade the performance of the semiconductor element, and is a limiting factor that must be addressed to achieve further enhancement of the integration level of the semiconductor element.

[0133] The sealing layer (such as the sealing layer 16) is sufficiently resistant to, for example, a wet etching solution to prevent over-etching and penetration of the bottom of the air gap. For example, the sealing layer can sufficiently function as an etching stop layer in subsequent etching processes. Thus, the erosion problem can be addressed. The performance and operational reliability of the semiconductor element can also be improved.

[0134] Figure 1B is a magnified view of a portion of a semiconductor element according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 1a can include Figure 1B a magnified view of

[0135] The recessed region 15h1 can be exposed to air through the interlayer 18. For example, in the etching process of Figure 2K , the interlayer 18 can be etched through. A portion of the sealing layer 17 and a portion of the sealing layer 16 can also be etched. The surface of the sealing layer 16 in the recessed region 15h1 can be exposed through the sealing layer 17 and etched partially.

[0136] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , and Figure 2KAccording to some embodiments of the present disclosure, stages of a method for manufacturing a semiconductor device are shown. In order to better understand various aspects of the present disclosure, at least some of these figures have been simplified. In some embodiments, the following references can be made to Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F 、 Figure 2G 、 Figure 2H 、 Figure 2I 、 Figure 2J ,and Figure 2K The operations described are used to manufacture the semiconductor element 1 a in FIG. 1 .

[0137] like Figure 2K As shown, the isolation region 10i can be fabricated using an STI (shallow trench isolation) process. For example, after forming a liner layer (not shown) on the substrate 10, the liner layer and substrate 10 can be etched using an isolation mask (not shown) to define an isolation trench. The isolation trench can then be filled with a dielectric material to form the isolation region 10i.

[0138] The isolation trenches may be filled with dielectric material by chemical vapor deposition (CVD) and may be subjected to additional planarization processes such as chemical-mechanical polishing (CMP).

[0139] The doped region 101 and the two doped regions 102 may be formed in the active region 10 a and may be separated from each other by an isolation region 10 i.

[0140] One or more recessed regions may be formed in the substrate 10. For example, a recessed region 11h1 may be formed in the doped region 101. In some embodiments, the substrate 10 may be patterned to form the one or more recessed regions, exposing the doped region 101. In some embodiments, the substrate 10 may be patterned to form the one or more recessed regions, exposing a bit line contact region in the doped region 101, and the bit line contact region is configured to be electrically connected to the bit line structure.

[0141] In some embodiments, in a top view, the recessed areas may be arranged in a honeycomb form or a zigzag form. In some embodiments, each of the recessed areas may have a circular or elliptical shape.

[0142] An interposer 10d1 can be disposed on the substrate 10. The interposer 10d1 can be disposed on a top surface of the active region 10a. In some embodiments, the fabrication technique of the recessed region 11h1 can include an etching operation, such as an anisotropic etching operation. For example, the interposer 10d1 can define the doped region 101 or bitline contact regions in the doped region 101.

[0143] A plurality of bitline structures, such as the bitline structures 11 and 12, can be formed on the substrate 10. Each of the bitline structures can overlap a plurality of recessed regions. For example, the bitline structure 11 can overlap the recessed region 11h1.

[0144] The bitline structure 11 can include a bitline contact 11d for connecting the bitline contact regions in the doped region 101. The bitline structure 12 can include a bitline contact 12d disposed on the interposer 10d1. Each of the bitline structures can include a bitline contact, a conductive pattern, a conductive pattern, and a bitline cap pattern, which are sequentially stacked.

[0145] In some embodiments, the bitline structure 11 can be formed by disposing a material of the bitline contact 11d on the interposer 10d1 to fill the recessed region 11h1, and sequentially disposing materials of the conductive pattern 11c, the conductive pattern 11b, and the bitline cap pattern 11a. Then, the materials can be etched by a bitline mask pattern.

[0146] Insulating spacer structures can be formed on opposite sidewalls of the bitline structure 11. Insulating spacer structures can be formed on opposite sidewalls of the bitline structure 12.

[0147] A material of the spacer 11s1 can be formed on the opposite sidewalls of the bitline structure 11. A material of the spacer 12s1 can be formed on the opposite sidewalls of the bitline structure 12. In some embodiments, the spacers 11s1 and 12s1 can each include a nitrogen-containing material, such as silicon nitride (Si3N4). In some embodiments, the fabrication technique of the materials of the spacers 11s1 and 12s1 can include any suitable process, such as atomic layer deposition (ALD).

[0148] A material of the spacer 11s2 can be formed on the opposite sidewalls of the bitline structure 11. A material of the spacer 12s2 can be formed on the opposite sidewalls of the bitline structure 12. In some embodiments, the spacers 11s2 and 12s2 can each include an oxygen-containing material, such as silicon dioxide (SiO2). In some embodiments, the fabrication technique of the materials of the spacers 11s2 and 12s2 can include any suitable process, such as atomic layer deposition (ALD).

[0149] The material of spacers 11s3 can be formed on opposite sidewalls of the bitline structure 11. The material of spacers 12s3 can be formed on opposite sidewalls of the bitline structure 12. In some embodiments, spacers 11s3 and 12s3 can each comprise a nitrogen-containing material, such as silicon nitride (Si3N4). In some embodiments, the material of spacers 11s3 and 12s3 can be fabricated using any suitable process, such as atomic layer deposition (ALD).

[0150] A recessed region 11h2 may be formed in substrate 10 to expose doped region 102. The material of storage node contact 13 may be disposed in recessed region 11h2. The material of storage node contact 13 may be disposed adjacent to bit line structure 11. The material of storage node contact 13 may be recessed. This recessing process may be performed using a dry etching process, such as an etch-back process.

[0151] Next, a metal silicide film 14 may be formed on the exposed surface of the storage node contact 13. In some embodiments, the metal silicide film 14 may be formed by disposing a metal layer on the exposed surface of the storage node contact 13 and performing a heat treatment.

[0152] Next, landing pads 15 may be disposed on metal silicide film 14. Landing pads 15 may fill the space between bitline structures (such as bitline structures 11 and 12). In some embodiments, landing pads 15 may be formed by any suitable process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0153] like Figure 3 As shown, a portion of the bit line capping pattern 11a, a portion of the insulating spacer structure of the bit line structure 11, and a portion of the landing pad 15 can be removed by performing an etching process using a mask pattern. The etching process may expose the top surface of the insulating spacer structure and form a recessed region 15h1. Recessed region 15h2 can be formed in the same etching process. After the etching process, the mask pattern can be removed.

[0154] like Figure 2A As shown, a portion of the spacer 11s2 may be removed by an etching process using a chemical etchant (e.g., HF (hydrofluoric acid) vapor) to form a pair of air gaps on opposite sidewalls of the bit line structure 11. A portion of the spacer 11s2 may remain at the bottom of the air gap.

[0155] A portion of the spacer 12s2 can be removed by an etching process using a chemical etchant (e.g., HF (hydrofluoric acid) vapor), and a pair of air gaps can be formed on opposite sidewalls of the bit line structure 12. A portion of the spacer 12s2 can remain at the bottom of the air gaps.

[0156] As shown in FIG. 1C, a sealing layer 16 can be disposed on the landing pad 15 and in the recessed regions 15h1 and 15h2. Figure 2B

[0157] In some embodiments, the sealing layer 16 can include a carbon-containing material, such as silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), and silicon oxycarbonitride (SiOCN). In some embodiments, the fabrication technique of the sealing layer 16 can include any suitable process, such as low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), thermal growth, or chemical growth.

[0158] As shown in FIG. 1D, a sealing layer 17 can be disposed on the landing pad 15 and in the recessed regions 15h1 and 15h2. In some embodiments, the fabrication technique of the sealing layer 17 can include any suitable process, such as atomic layer deposition (ALD). The sealing layer 16 and the sealing layer 17 can define an air gap. Figure 2C

[0159] As shown in FIG. 1E, the sealing layers 16 and 17 can be removed by a planarization process, such as chemical mechanical polishing (CMP). The air gap can be exposed. The sealing layer 16 can be exposed. Figure 2D

[0160] As shown in FIG. 1F, an interlayer dielectric 18 can be disposed on the landing pad 15. The interlayer dielectric 18 can cover the recessed regions 15h1 and 15h2. The interlayer dielectric 18 can cover the air gap defined by the sealing layers 16 and 17. The fabrication technique of the interlayer dielectric 18 can include any suitable process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Figure 2E

[0161] Figure 2G ​​​​​As shown, for simplicity, layers under the landing pad 15 are not shown. A first molding layer 20 can be formed on the interposer 18. The first molding layer 20 can include silicon dioxide (Si02), undoped silica glass (USG), borosilica glass (BSG), phosphosilicate glass (PSG), borophosphosilica glass (BPSG), tetraethyl orthosilicate (TEOS), plasma enhanced tetraethyl orthosilicate (PE-TEOS), and fluoride silicate glass (FSG), etc. The first molding layer 20 can include a single layer or multiple layers. Fabrication techniques for the first molding layer 20 can include any suitable process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0162] A first support layer 21 can be formed on the first molding layer 20. The first support layer 21 can include silicon dioxide (Si02), silicon nitride (Si3N4), or silicon oxynitride. Fabrication techniques for the first support layer 21 can include any suitable process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0163] A second molding layer 22 can be formed on the first support layer 21. The second molding layer 22 can include the same material as the first molding layer 20.

[0164] A second support layer 23 can be formed on the second molding layer 22. The second support layer 23 can include the same material as the first support layer 21.

[0165] As shown, the interposer 18, the first molding layer 20, the first support layer 21, the second molding layer 22, and the second support layer 23 can be partially removed to form a contact hole 23h. The landing pad 15 can be exposed from the contact hole 23h. ​ As shown, a bottom electrode 19 can be disposed in each contact hole 23h. Fabrication techniques for the bottom electrode 19 can include any suitable process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0166] ​ As shown, the first molding layer 20, the first support layer 21, the second molding layer 22, and the second support layer 23 can be removed to expose the interposer 18.

[0167] As shown, the first molding layer 20, the first support layer 21, the second molding layer 22, and the second support layer 23 can be removed to expose the interposer 18. ​

[0168] ​​The first molding layer 20, the first support layer 21, the second molding layer 22, and the second support layer 23 can be removed by an etching process such as a wet etching process. Wet chemical etchants can include ammonium fluoride (NH4F), hydrofluoric acid (HF), hydrochloric acid (HC1), ammonium hydroxide (NH4OH), ammonium sulfide ((NH4)2S), and combinations of the foregoing.

[0169] The recessed regions 15h1 can be exposed to air through the interlayer 18. For example, in ​ the etching process, the interlayer 18 can be penetrated, and a portion of the sealing layer 17 can also be etched. The sealing layer 16 is sufficiently resistant to the wet etchant to prevent over-etching and penetration of the bottom of the recessed regions 15h1.

[0170] ​ A flowchart of a method 30 of fabricating a semiconductor device according to some embodiments of the present disclosure is shown.

[0171] In some embodiments, the method 30 can include a step S31 of forming a landing pad over the bitline structure. For example, as shown in ​ the landing pad 15 can be disposed over the bitline structure 11.

[0172] In some embodiments, the method 30 can include a step S32 of forming a recessed region in the landing pad. For example, as shown in ​ a portion of the bitline cover pattern 11a, a portion of the insulating spacer structure of the bitline structure 11, and a portion of the landing pad 15 can be removed by an etching process using a mask pattern. The recessed regions 15h1 can be formed.

[0173] In some embodiments, the method 30 can include a step S33 of removing a portion of the bitline structure. For example, as shown in ​ a portion of the spacer 11s2 can be removed by an etching process using a chemical etchant (e.g., hydrogen fluoride (HF) vapor) and form a pair of air gaps on opposite sidewalls of the bitline structure 11. A portion of the spacer 11s2 can remain at the bottom of the air gaps.

[0174] In some embodiments, the method 30 can include a step S34 of disposing a first sealing layer in the recessed region. For example, as shown in ​ the sealing layer 16 can be disposed over the landing pad 15 and in the recessed regions 15h1 and 15h2.

[0175] In some embodiments, the method 30 can include a step S35 of disposing a second sealing layer in the recessed region. For example, as shown in ​ the sealing layer 17 can be disposed over the landing pad 15 and in the recessed regions 15h1 and 15h2.

[0176] In some embodiments, the method 30 can include a step S36 of disposing an interlayer over the recessed region. For example, as shown in FIG. 1 IB, an interlayer 18 can be disposed over the landing pad 15. The interlayer 18 can cover the recessed regions 15hl and 15h2. ​

[0177] One aspect of the disclosure provides a semiconductor element. The semiconductor element includes a substrate and a bit line structure disposed over the substrate. The bit line structure includes an insulating spacer structure defining an air edge liner. The semiconductor element also includes a sealing layer disposed over the insulating spacer structure to cover the air edge liner. The sealing layer includes a carbon-containing material.

[0178] Another aspect of the disclosure provides a semiconductor element. The semiconductor element includes a substrate, a bit line structure disposed over the substrate, and a landing pad disposed over the bit line structure and having a recessed region. The semiconductor element also includes a first sealing layer disposed in the recessed region. The first sealing layer includes a carbon-containing material.

[0179] Another aspect of the disclosure provides a method of manufacturing a semiconductor element. The method includes forming a landing pad over a bit line structure and forming a recessed region in the landing pad. The method also includes removing a portion of the bit line structure and disposing a first sealing layer in the recessed region.

[0180] The sealing layer is resistant enough to, for example, a wet etching solution to prevent over-etching and penetration of the bottom of the air gap. For example, the sealing layer can sufficiently function as an etch stop layer in a subsequent etching process. Thus, the erosion problem can be solved. The performance and operational reliability of the semiconductor element can also be improved.

[0181] While the disclosure and the best mode thereof have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be implemented in different methodologies, and many of the individual steps can be implemented in a different order or omitted, and additional steps can be added.

[0182] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of the present application is intended to be illustrative, but not limiting, of the scope of the application, which is set forth in the following claims.​

Claims

1. A semiconductor device, comprising: a substrate; a bit line structure disposed over the substrate; a landing pad disposed over the bit line structure and having a recessed region; and a first encapsulation layer disposed in the recessed region, wherein the first encapsulation layer comprises a carbon-containing material.

2. The semiconductor device of claim 1, wherein the first encapsulation layer truncates an insulating spacer structure of the bit line structure.

3. The semiconductor device of claim 2, wherein the first encapsulation layer contacts the insulating spacer structure of the bit line structure.

4. The semiconductor device of claim 2, wherein the first encapsulation layer covers an air edge defined in the insulating spacer structure of the bit line structure.

5. The semiconductor device of claim 2, wherein the insulating spacer structure is disposed between the bit line structure and a storage node contact.

6. The semiconductor device of claim 1, further comprising: a second encapsulation layer disposed on the first encapsulation layer in the recessed region, wherein the first encapsulation layer and the second encapsulation layer have different materials.

7. The semiconductor device of claim 6, further comprising: an interlayer disposed in the recessed region, wherein the second encapsulation layer and the interlayer define an air gap.

8. The semiconductor device of claim 6, further comprising: an interlayer disposed in the recessed region, wherein the recessed region is exposed to air through the interlayer.

9. The semiconductor device of claim 8, wherein the first encapsulation layer contacts the interlayer.

10. The semiconductor device of claim 8, wherein the first encapsulation layer in the recessed region is partially covered by the second encapsulation layer.

11. The semiconductor device of claim 8, wherein the first encapsulation layer in the recessed region is partially etched.

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