Semiconductor device

Abstract

A semiconductor device includes: a bit line structure; a charge trapping structure on the bit line structure; word line structures alternately arranged with the charge trapping structures in the first direction, each of the word line structures including a first word line and a second word line spaced apart from each other in the first direction; an active pattern disposed on the bit line structure, disposed between the charge trapping structure and the word line structure, and electrically connected to the bit line structure; a contact pattern disposed on the active pattern and electrically connected to the active pattern; and an information storage structure on the contact pattern, and each of the charge trapping structures may include: at least one charge trapping layer between the active patterns; and a first insulating film between the at least one charge trapping layer and the active pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0053974 filed on April 23, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including vertical channel transistors. Background Art

[0004] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices also increases. In response to the trend of high integration density of semiconductor devices, fine patterned semiconductor devices are manufactured, and it may be necessary to realize patterns with fine widths or fine spacing. Summary of the Invention

[0005] An aspect of the present disclosure is to provide a semiconductor device including a vertical channel transistor configured to improve integration.

[0006] However, the objects of the present disclosure are not limited to the above objects, and various extensions can be made without departing from the spirit and scope of the present disclosure.

[0007] A semiconductor device according to example embodiments of the present disclosure may include: a bit line structure;

[0008] A charge trapping structure on the bit line structure; a word line structure arranged alternately with the charge trapping structure in a first direction, each of the word line structures including a first word line and a second word line spaced apart from each other in the first direction; an active pattern arranged on the bit line structure, disposed between the charge trapping structure and the word line structure, and electrically connected to the bit line structure; a contact pattern arranged on the active pattern and electrically connected to the active pattern; and an information storage structure on the contact pattern, and each of the charge trapping structures may include: at least one charge trapping layer disposed between the active patterns; and a first insulating film disposed between the at least one charge trapping layer and the active pattern.

[0009] A semiconductor device according to an example embodiment of the present disclosure can include a bit line structure extending in a first direction; first to third active patterns sequentially arranged along the first direction on the bit line structure and electrically connected to the bit line structure; a charge trapping structure disposed between the first and second active patterns; a word line structure disposed between the second and third active patterns and including a first word line opposite a side of the second active pattern and a second word line opposite a side of the third active pattern and spaced apart from the first word line in the first direction; a contact pattern disposed on the first to third active patterns and electrically connected to the first to third active patterns; and an information storage structure on the contact pattern, wherein the charge trapping structure can include a first insulating pattern having a first side surface in contact with the first active pattern and a second side surface opposite the first side surface and including a first insulating material; a second insulating pattern having a third side surface in contact with the second active pattern and a fourth side surface opposite the third side surface and including the first insulating material; and at least one charge trapping layer disposed between the first and second insulating patterns and including a material different from the first insulating material.

[0010] A semiconductor device according to an example embodiment of the present disclosure can include a first structure including a peripheral circuit region; and a second structure overlapping the first structure in a third direction and including a memory cell array region, wherein the memory cell array region can include a bit line structure; and a charge trapping structure disposed on the bit line structure; a word line structure arranged alternately with the charge trapping structure in a first direction perpendicular to the third direction, each of the word line structures including a first word line and a second word line spaced apart from each other in the first direction; an active pattern disposed between the charge trapping structure and the word line structure on the bit line structure and electrically connected to the bit line structure; a contact pattern disposed on the active pattern and electrically connected to the active pattern; and an information storage structure on the contact pattern, and each of the charge trapping structures can include a first charge trapping layer and a second charge trapping layer spaced apart from each other in the first direction; a first insulating film disposed between the first and second charge trapping layers and the active pattern; and a second insulating film disposed between the first and second charge trapping layers, and the first and second insulating films can include a first insulating material, and the first and second charge trapping layers include a second insulating material different from the first insulating material.

[0011] A semiconductor device according to an example embodiment of the present disclosure can provide a charge trapping structure including at least one charge trapping layer adjacent to an active pattern.

[0012] The at least one charge-trapping layer can function as a back gate capable of controlling the electric charges accumulated in the vertical channel region of the active pattern. For example, the vertical channel region within the active pattern can be a floating body disposed between the upper source / drain region and the lower source / drain region, and the at least one charge-trapping layer can suppress or prevent the performance of the transistor from being degraded due to the floating body effect. For example, the at least one charge-trapping layer can minimize or prevent the variation of the threshold voltage of the transistor by accumulating electric charges (i.e., holes) within the floating body in the vertical channel region.

[0013] The advantages and effects of the embodiments disclosed herein are not limited to the foregoing, and various extensions can be made without departing from the spirit and scope of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a schematic perspective view of a semiconductor device according to an example embodiment of the present disclosure;

[0016] Figure 2 is a plan view of a semiconductor device according to an example embodiment of the present disclosure;

[0017] Figure 3 is a sectional view taken along line I-I' of the semiconductor device shown in Figure 2

[0018] is a sectional view taken along line I-I' of the semiconductor device shown in

[0019] Figure 4A is a sectional view taken along line I-I' of the semiconductor device shown in Figure 3

[0020] Figure 4B is a sectional view taken along line I-I' of the semiconductor device shown in Figure 3

[0021] is a sectional view taken along line I-I' of the semiconductor device shown in Figure 4C Figure 3

[0022] Figure 5A is a diagram illustrating an operation of trapping electric charges in a charge-trapping layer of a charge-trapping structure of the semiconductor device shown in Figure 4A

[0023] Figure 5B is a diagram illustrating an operation of trapping electric charges in a charge-trapping layer of a charge-trapping structure of the semiconductor device shown in Figure 4C

[0024] ​​​​​​Figures 6A to 6I is a diagram illustrating an example embodiment of a method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0025] Hereinafter, the example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and the repeated description of the same components is omitted. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items. It will be understood that when an element is referred to as "on" another element, "attached" to another element, "connected" to another element, "coupled" with another element, "contacting" another element, etc., the element can be directly on the other element, directly attached to the other element, directly connected to the other element, directly coupled with the other element or directly contacting the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as, for example, "directly on" another element, "directly attached" to another element, "directly connected" to another element, "directly coupled" with another element, or "directly contacting" another element, there is no intermediate element. In the embodiments of the present invention, unless the context clearly indicates otherwise, the singular form of the component can include the plural form. In this specification, in order to make the embodiments of the present invention clear, the drawings are exaggerated. Please note that aspects described with respect to one embodiment may be incorporated in a different embodiment even though not specifically described in this regard. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0026] Figure 1 is a schematic perspective view of a semiconductor device according to an example embodiment of the present disclosure.

[0027] Reference Figure 1 The semiconductor device 100 may include a first structure ST1 and a second structure ST2 on the first structure ST1. The first structure ST1 may include a peripheral circuit region PERI. The second structure ST2 may include a memory cell array region CELL. The first structure ST1 may overlap the second structure ST2 in the vertical direction (Z direction).

[0028] The memory cell array region CELL may include a memory cell array. In an example, the memory cell array may include bit lines BL, word lines WL, and memory cells MC.

[0029] The memory cell MC may include a corresponding cell transistor CTR and an information storage element DS. One memory cell MC may be provided between one word line WL and one bit line BL. The memory cell array of the semiconductor device 100 may correspond to a dynamic random access memory.

[0030] A memory cell array of a dynamic random access memory (DRAM) device.

[0031] A cell transistor CTR can include a gate and a source / drain. The gate can be connected to a word line WL, the source can be connected to a bit line BL, and the drain can be connected to an information storage element DS. The information storage element DS can include a capacitor formed by a lower electrode and an upper electrode and a dielectric layer.

[0032] The word lines WL can extend in a second direction (Y direction) and can be spaced apart from each other in a first direction (X direction). The word lines WL can be disposed at the same level (in the Z direction) from each other, each of the word lines WL can be connected to a different memory cell MC. The bit lines BL can extend in the first direction (X direction) and can be spaced apart from each other in the second direction (Y direction).

[0033] The peripheral circuit region PERI can be electrically connected to the memory cell array region CELL. The peripheral circuit region PERI can include peripheral circuit elements. For example, the peripheral circuit region PERI can include a sub word line driver electrically connected to the word lines WL and a sense amplifier electrically connected to the bit lines BL.

[0034] The first structure ST1 can be bonded to the second structure ST2. For example, a first bonding pad BP1 can be included on a lower surface of the second structure ST2, and a second bonding pad BP2 can be included on an upper surface of the first structure ST1. The first bonding pad BP1 can be bonded to the second bonding pad BP2 and can electrically connect the first structure ST1 and the second structure ST2. For example, the first bonding pad BP1 and the second bonding pad BP2 can provide a path P electrically connecting the memory cell array region CELL and the peripheral circuit region PERI.

[0035] Figure 2 is a plan view of a semiconductor device according to example embodiments of the present disclosure. Figure 3 is a plan view of a semiconductor device according to example embodiments of the present disclosure. Figure 2 is a cross-sectional view taken along line I-I' of the semiconductor device shown in Figure 1 a memory cell array circuit diagram of Figure 2 and Figure 3 may be implemented with the semiconductor device described in

[0036] Referring to Figure 2 and Figure 3 , a memory cell array region CELL of a semiconductor device 100 according to example embodiments can include a bit line structure 110, a charge trapping structure 120, an active pattern 140, a word line structure 150, a contact pattern 170, and an information storage structure 180.

[0037] The bit line structure 110 can extend in a first direction (X direction). In an example, the bit line structure 110 can be electrically connected to the active pattern 140. The bit line structure 110 can be provided as a plurality, and the plurality of bit line structures 110 can be spaced apart from each other in a second direction (Y direction) and can extend in parallel. The bit line structure 110 can correspond to Figure 1 the bit line BL in the circuit diagram shown in FIG. 1B.

[0038] The bit line structure 110 can include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. For example, at least one of the bit line structure 110 can be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x , graphene, carbon nanotube, or a combination thereof. In an example, the bit line structure 110 can include a first conductive pattern 110a, a second conductive pattern 110b, and a third conductive pattern 110c, which are sequentially stacked in a vertical direction (Z direction). The first conductive pattern 110a can include, for example, a metal material such as titanium (Ti), tantalum (Ta), tungsten (W), and / or aluminum (Al); the second conductive pattern 110b can include, for example, a metal nitride such as titanium nitride (TiN) or a silicide material such as titanium silicide (TiSi); and the third conductive pattern 110c can include a semiconductor material such as polysilicon. The third conductive pattern 110c can be a layer doped with an impurity. However, according to an example embodiment, the materials of the layers included in the bit line structure 110, the number of layers, and the thickness thereof can vary.

[0039] The word line structure 150 can be disposed on the bit line structure 110. The word line structure 150 can be arranged in the first direction (X direction) alternately with the charge trapping structure 120. The word line structure 150 can be disposed on the bit line structure 110 between two adjacent charge trapping structures 120 and can extend between the active patterns 140.

[0040] Each of the word line structures 150 can include a gate dielectric layer 151, a word line 152, and a gate capping pattern 160.

[0041] The word lines 152 can be located between two adjacent charge trapping structures 120. The word lines 152 can be spaced apart from each other in a first direction (X direction) and can extend in a second direction (Y direction). The word lines 152 can include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. For example, the word lines 152 can be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x , graphene, carbon nanotube, or a combination thereof, but embodiments of the present disclosure are not limited thereto. The word lines 152 can include a single layer or multiple layers of the above-described materials. Each of the word lines 152 can correspond to one word line WL in the circuit diagram shown in FIG. 1B. Figure 1

[0042] The gate capping pattern 160 can extend in the second direction (Y direction) between the word lines 152. The gate capping pattern 160 can include first gate capping patterns 162 disposed on the word lines 152, and second gate capping patterns 164 extending in a vertical direction (Z direction) from spaces between the word lines 152 to spaces between the first gate capping patterns 162. The first gate capping patterns 162 can overlap the word lines 152 in the vertical direction (Z direction) and can be in contact with the word lines 152. Lower surfaces of the second gate capping patterns 164 can be disposed between the word lines 152 and can be in contact with an upper surface of the gate dielectric layer 151.

[0043] The gate capping pattern 160 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or a combination thereof. For example, the first gate capping patterns 162 can include silicon nitride, and the second gate capping patterns 164 can include silicon oxide. In some example embodiments, the first gate capping patterns 162 and the second gate capping patterns 164 can include the same material and can be integrally formed.

[0044] The gate dielectric layer 151 can be disposed between the active pattern 140 and the first gate capping patterns 162 and between the active pattern 140 and the word lines 152. The gate dielectric layer 151 can extend from a space between the active pattern 140 and the word lines 152 to a space between the insulating pattern 130 and the word lines 152. The gate dielectric layer 151 can have a U shape in a cross-sectional view. For example, the gate dielectric layer 151 can at least partially surround the word lines 152 and the gate capping pattern 160.

[0045] ​The gate dielectric layers 151 can be tunnel dielectric layers that do not include information storage layers. For example, each of the gate dielectric layers 151 can include silicon oxide and / or a high-k dielectric material. The high-k dielectric material can include a metal oxide or a metal oxynitride. For example, the high-k dielectric material can be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, although embodiments of the present disclosure are not limited thereto. Each of the gate dielectric layers 151 can be formed of a single layer or multiple layers of the above-described materials. In another example embodiment, the gate dielectric layers 151 can include information storage layers and dielectric layers. For example, the gate dielectric layers 151 can have a polarization characteristic depending on an electric field, and can include a ferroelectric layer that can have a residual polarization due to a dipole even in the absence of an external electric field. A polarization state within the ferroelectric layer can be used to record data. Thus, the gate dielectric layers 151 can include a ferroelectric layer referred to as an information storage layer. The ferroelectric layer that can be an information storage layer can include a Hf-based compound, a Zr-based compound, and / or a Hf-Zr-based compound. For example, the Hf-based compound can be a HfO-based ferroelectric material, the Zr-based compound can include a ZrO-based ferroelectric material, and the Hf-Zr-based compound can include a ferroelectric material based on HZO (hafnium zirconium oxide). The ferroelectric layer that can be an information storage layer can include a ferroelectric material doped with impurities such as C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and / or Sr. For example, the ferroelectric layer that can be an information storage layer can be a material in which HfO2, ZrO2, and / or HZO is doped with impurities such as C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and / or Sr. The information storage layer of the gate dielectric layers 151 is not limited to the above-described material types, and can include a material capable of storing information.

[0046] The semiconductor device 100 can further include an insulating pattern 130 disposed between the word line structure 150 and the bit line structure 110. The insulating pattern 130 can be in contact with an upper surface of the third conductive pattern 110c of the bit line structure 110, a side surface of the active pattern 140, and a lower surface of the gate dielectric layer 151 of the word line structure 150. In an example, a lower surface of the insulating pattern 130 can be disposed (in the Z direction) at the same level as a lower surface of the active pattern 140. The insulating pattern 130 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the insulating pattern 130 can include silicon oxide. Herein, the insulating pattern 130 can be referred to as a gate insulating pattern and can be included in the word line structure 150.

[0047] The charge trapping structure 120 can be disposed on the bit line structure 110. In an example, the charge trapping structure 120 can intersect the bit line structure 110. The charge trapping structure 120 can extend in a second direction (Y direction), and can be spaced apart from each other in a first direction (X direction). In an example, the charge trapping structure 120 can be arranged to alternate with the word line structure 150 in the first direction (X direction), and the active pattern 140 is interposed between the charge trapping structure 120 and the word line structure 150. The charge trapping structure 120 can be disposed between two adjacent word line structures 150.

[0048] Each charge trapping structure 120 can include at least one charge trapping layer 122 and a first insulating film 121 between the at least one charge trapping layer 122 and the active pattern 140. The first insulating film 121 and the at least one charge trapping layer 122 can extend along a vertical direction (Z direction). In an example, an upper surface of the charge trapping structure 120 can be disposed (in the Z direction) at the same level as an upper surface of the word line structure 150. In an example, a lower surface of the charge trapping structure 120 can be disposed at a lower level than a lower surface of the word line 152, and an upper surface of the charge trapping structure 120 can be disposed (in the Z direction) at a higher level than an upper surface of the word line 152. That is, the lower surface of the charge trapping structure 120 can be disposed at the same level as a lower surface of the insulating pattern 130, and the upper surface of the charge trapping structure 120 can be disposed (in the Z direction) at the same level as an upper surface of the gate capping pattern 160.

[0049] Electrons formed in a channel region 140a (see FIG. 2) of the active pattern 140 according to a voltage applied to the word line 152 and a voltage applied to the contact pattern 170 connected to the active pattern 140 can pass through the first insulating film 121 and be trapped in the at least one charge trapping layer 122. The first insulating film 121 can be referred to as a trap insulating layer. Figure 4A ) of the active pattern 140 according to a voltage applied to the word line 152 and a voltage applied to the contact pattern 170 connected to the active pattern 140 can pass through the first insulating film 121 and be trapped in the at least one charge trapping layer 122. The first insulating film 121 can be referred to as a trap insulating layer.

[0050] The first insulating film 121 can include a first insulating material, and the at least one charge trapping layer 122 can include a second insulating material different from the first insulating material. In an example, the first insulating film 121 can include an oxide, and the at least one charge trapping layer 122 can include a nitride. For example, the first insulating film 121 can include silicon oxide (e.g., SiO2), and the at least one charge trapping layer 122 can include silicon nitride (e.g., Si3N4).

[0051] Because the charge (e.g., holes) accumulated in the channel region 140a of the active pattern 140 of the cell transistor CTR can be controlled, the floating body effect can be suppressed or controlled, and the change in the threshold voltage of the cell transistor CTR can be prevented or reduced. The charge trapping structure 120 can improve the electrical characteristics of the cell transistor CTR.

[0052] The active pattern 140 can be disposed on the bit line structure 110 and can extend in the vertical direction (Z direction). In a plan view, the active pattern 140 can be disposed between the charge trapping structure 120 and the word line structure 150. The active patterns 140 can be spaced apart from each other in the first direction (X direction) and the second direction (Y direction). In an example, the upper surface of the active pattern 140 can be disposed (in the Z direction) at the same level as the upper surface of the charge trapping structure 120 and the upper surface of the word line structure 150. The lower surface of the active pattern 140 can be disposed (in the Z direction) at the same level as the lower surface of the charge trapping structure 120 and the lower surface of the insulating pattern 130.

[0053] The active pattern 140 can correspond to Figure 1 the channel region and the source / drain region of the cell transistor CTR shown in FIG. 1B. Herein, the active pattern 140 can be referred to as a "cell channel structure."

[0054] The active pattern 140 can include a single-crystal semiconductor material. The single-crystal semiconductor material can include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor, and can be, for example, a single-crystal semiconductor including silicon, silicon carbide, germanium, and / or silicon germanium. However, according to an example embodiment, the active pattern 140 can include a polycrystalline semiconductor material layer, an oxide semiconductor material layer such as indium gallium zinc oxide (IGZO), and / or a two-dimensional material layer such as MoS2.

[0055] The oxide semiconductor material layer can be indium gallium zinc oxide (IGZO). However, embodiments of the present disclosure are not limited thereto. For example, the oxide semiconductor material layer can include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and / or indium gallium silicon oxide (InGaSiO).

[0056] The two-dimensional material layer can include a transition metal dichalcogenide material layer (TMD material layer) that can have semiconductor properties, a black phosphorus material layer, and / or a hexagonal boron nitride material layer (hBN material layer). For example, the two-dimensional material layer can include BiOSe, CrI3, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P(black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and / or Janus 2D material that can form a two-dimensional material.

[0057] The semiconductor device 100 can include a vertical channel transistor formed by the active pattern 140, the bit line structure 110 electrically connected to the active pattern 140, and the word line 152 disposed on at least one side of the active pattern 140.

[0058] The contact pattern 170 can be disposed on the active pattern 140 and can be electrically connected to the active pattern 140. The contact pattern 170 can be electrically connected to the active pattern 140 and the information storage structure 180.

[0059] A lower surface of the contact pattern 170 is shown in contact with the active pattern 140 and the gate dielectric layer 151, but according to an example embodiment, the lower surface of the contact pattern 170 can also be in contact with the gate capping pattern 160.

[0060] The contact pattern 170 can include a conductive material, for example, doped single crystalline silicon, doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. In an example embodiment, the contact pattern 170 can include a first contact layer 170a, a second contact layer 170b, a third contact layer 170c, and a fourth contact layer 170d sequentially stacked. For example, the first contact layer 170a can include undoped polycrystalline silicon, the second contact layer 170b can include doped polycrystalline silicon, the third contact layer 170c can include a silicide material, and the fourth contact layer 170d can include metal. However, according to an example embodiment, the number of layers of the contact pattern 170 and the type of material can vary.

[0061] The semiconductor device 100 can further include a contact insulating pattern 175 disposed between the first to fourth contact layers 170a-d. Each contact insulating pattern 175 can extend vertically (in the Z direction) and can be in contact with the gate capping pattern 160 and / or the charge trapping structure 120. The contact insulating pattern 175 can spatially separate and electrically insulate the contact pattern 170.

[0062] The information storage structure 180 can include a first electrode 182 electrically connected to the contact pattern 170, a second electrode 186 on and at least partially covering the first electrode 182, and a dielectric layer 184 between the first electrode 182 and the second electrode 186. The information storage structure 180 can correspond to Figure 1 the information storage element DS in the circuit diagram shown in FIG. 1.

[0063] In an example embodiment, the information storage structure 180 can be a capacitor configured to store information in a DRAM. For example, the dielectric layer 184 of the information storage structure 180 can be a capacitor dielectric layer of a DRAM, and the dielectric layer 184 can include a high-k dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0064] According to an example embodiment, the information storage structure 180 can be a structure configured to store memory information different from a DRAM. For example, the dielectric layer 184 of the information storage structure 180 can be a capacitor dielectric layer of a ferroelectric memory (FeRAM). In this case, the dielectric layer 184 can be a ferroelectric layer that can record data using a polarization state. With respect to the ferroelectric layer, in another example embodiment, the dielectric layer 184 can include a lower dielectric layer including at least one of a high-k dielectric and silicon oxide, and a ferroelectric layer disposed on the lower dielectric layer.

[0065] The memory cell array region CELL of the semiconductor device 100 can further include a lower insulating layer 101 disposed below the bit line structure 110, an interconnection layer 103, a via 105, and a first bonding pad BP1. An upper surface of the lower insulating layer 101 can be in contact with a lower surface of the first conductive pattern 110a. The interconnection layer 103 can be buried in the lower insulating layer 101, and can be arranged in a plurality of layers. The via 105 can electrically connect the interconnection layer 103.

[0066] The first bonding pad BP1 can be disposed along a lower surface of the lower insulating layer 101. For example, a lower surface of the first bonding pad BP1 can be coplanar with the lower surface of the lower insulating layer 101. Each of the first bonding pads BP1 can be electrically connected to at least one of the interconnection layer 103 and the via 105. In addition, the bit line structure 110 can be electrically connected to at least one of the interconnection layer 103 and the via 105.

[0067] The peripheral circuit region PERI of the first structure ST1 can include a device isolation layer 6 disposed on an upper surface of the substrate 3 and a peripheral transistor TR. The peripheral transistor TR can include a peripheral source / drain region SD, a peripheral gate dielectric layer GO, and a peripheral gate electrode GE. The peripheral transistor TR can be a planar transistor. For example, the peripheral source / drain region SD can be disposed on the upper surface of the substrate 3, and a channel region of the peripheral transistor TR can be disposed between the peripheral source / drain regions SD. The channel region can be coplanar with an upper surface of the peripheral source / drain region SD, and can be in contact with a lower surface of the peripheral gate dielectric layer GO. The peripheral transistor TR can be a component of the sub word line driver and the sense amplifier described above.

[0068] The first structure ST1 can further include an insulating layer 9 disposed on the substrate 3, an interconnection layer 12, a via 15, and a second bonding pad BP2. The insulating layer 9 can be on and at least partially cover an upper surface of the substrate 3, and can be on and at least partially cover the peripheral transistor TR. The interconnection layer 12 can be buried within the insulating layer 9, and can be arranged in a plurality of layers. The via 15 can electrically connect the interconnection layer 12.

[0069] The second bonding pad BP2 can be disposed along an upper surface of the insulating layer 9. For example, an upper surface of the second bonding pad BP2 can be coplanar with the upper surface of the insulating layer 9. Each of the second bonding pads BP2 can be bonded to a corresponding first bonding pad BP1 thereof. Each of the second bonding pads BP2 can be electrically connected to at least one of the interconnection layer 12 and the via 15. In addition, the peripheral transistor TR can be electrically connected to at least one of the interconnection layer 12 and the via 15.

[0070] The semiconductor device 100 according to example embodiments of the disclosure can include a word line structure 150, a charge trapping structure 120 arranged alternately with the word line structure 150 in a first direction (X direction), and an active pattern 140 disposed between the word line structure 150 and the charge trapping structure 120. The charge trapping structure 120 can include a first insulating film 121 including a first insulating material and at least one charge trapping layer 122 adjacent to one side of the active pattern 140 between the first insulating film 121 and including a second insulating material different from the first insulating material. When a charge in the active pattern 140 passes through the first insulating film 121 and is trapped in the at least one charge trapping layer 122, the semiconductor device 100 can adjust a threshold voltage of the semiconductor device, thereby providing a semiconductor device including a vertical channel transistor that ensures versatility and scalability.

[0071] Figure 4A is a semiconductor device according to example embodiments Figure 3 is a magnified view of a region A of the semiconductor device.

[0072] Referring to Figure 4A , the semiconductor device 100 can include a charge trapping structure 120, a word line structure 150 spaced apart from the charge trapping structure 120 in a first direction (X direction), and an active pattern 140 disposed between the charge trapping structure 120 and the word line structure 150.

[0073] The active pattern 140 can be spaced apart from each other in the first direction (X direction) and the second direction (Y direction) on the third conductive pattern 110c of the bit line structure 110 and can extend in a vertical direction (Z direction). In an example, each active pattern 140 can include a first source / drain region 140b in contact with the bit line structure 110, a second source / drain region 140c electrically connected to the contact pattern 170, and a channel region 140a between the first source / drain region 140b and the second source / drain region 140c. In an example, the first source / drain region 140b and the second source / drain region 140c can have an N-type conductivity type.

[0074] The active pattern 140 can include a first active pattern 141, a second active pattern 142, and a third active pattern 143 spaced apart from each other in the first direction (X direction).

[0075] The charge trapping structure 120 can be disposed between two adjacent word line structures 150 and can extend between the active patterns 140. In an example, the charge trapping structure 120 can be disposed between a first active pattern 141 and a second active pattern 142. In an example, the charge trapping structure 120 can include at least one charge trapping layer 122 and a first insulating film 121 disposed between the first active pattern 141 and the second active pattern 142 and the at least one charge trapping layer 122.

[0076] The at least one charge trapping layer 122 can include a first charge trapping layer 122a and a second charge trapping layer 122b spaced apart from the first charge trapping layer 122a in a first direction (X direction). In an example, the first insulating film 121 can include a 1-1 insulating film 121a disposed between the first active pattern 141 and the first charge trapping layer 122a and a 1-2 insulating film 121b disposed between the second active pattern 142 and the second charge trapping layer 122b.

[0077] The 1-1 insulating film 121a can include a first side surface in contact with the first active pattern 141 and a second side surface opposite the first side surface and in contact with the first charge trapping layer 122a. The 1-2 insulating film 121b can include a third side surface in contact with the second active pattern 142 and a fourth side surface opposite the third side surface and in contact with the second charge trapping layer 122b.

[0078] The charge trapping structure 120 can further include a second insulating film 123 disposed between the first charge trapping layer 122a and the second charge trapping layer 122b. The second insulating film 123 can include an insulating material identical to that of the first insulating film 121. However, embodiments of the present disclosure are not limited thereto, and the second insulating film 123 can include an oxide, but can include a different oxide from the first insulating film 121.

[0079] A width of each of the first charge trapping layer 122a and the second charge trapping layer 122b in the first direction (X direction) can be less than a width of each of the 1-1 insulating film 121a and the 1-2 insulating film 121b in the first direction (X direction). For example, the width of each of the first charge trapping layer 122a and the second charge trapping layer 122b in the first direction (X direction) can be about 1 nm to about 3 nm. The width of each of the 1-1 insulating film 121a and the 1-2 insulating film 121b in the first direction (X direction) can be about 4 nm to about 5 nm.

[0080] The width of the second insulating film 123 in the first direction (X direction) can be greater than the width of each of the first insulating films 121 in the first direction (X direction) and the width of each of the at least one charge trapping layer 122 in the first direction (X direction). For example, the width of the second insulating film 123 in the first direction (X direction) can be about 5 nm to about 10 nm.

[0081] The charge trapping structure 120 can include a 1-1 insulating film 121a, a first charge trapping layer 122a, a second insulating film 123, a second charge trapping layer 122b, and a 1-2 insulating film 121b arranged sequentially in the first direction (X direction).

[0082] Herein, the 1-1 insulating film 121a can be referred to as a first insulating pattern, the 1-2 insulating film 121b can be referred to as a second insulating pattern, and the second insulating film 123 can be referred to as a third insulating pattern.

[0083] The word line 152 can be disposed on the third conductive pattern 110c between two adjacent charge trapping structures 120 and can extend between the second active pattern 142 and the third active pattern 143. In an example, the insulating pattern 130 can be in contact with side surfaces of the second active pattern 142 and the third active pattern 143 that are in contact with the word line structure 150.

[0084] The word line structure 150 can include a gate dielectric layer 151, a word line 152, and a gate capping pattern 160. The word line 152 can include a first word line 152a and a second word line 152b disposed between the second active pattern 142 and the third active pattern 143 but spaced apart from each other in the first direction (X direction). The first word line 152a can be disposed adjacent to the second active pattern 142, and the second word line 152b can be disposed adjacent to the third active pattern 143. The first word line 152a and the second word line 152b can extend in the vertical direction (Z direction). The first gate capping pattern 162 can be disposed on the first word line 152a and the second word line 152b to contact upper surfaces of the first word line 152a and the second word line 152b. The second gate capping pattern 164 can extend on the gate dielectric layer 151 from a space between the first word line 152a and the second word line 152b to a space between the first gate capping patterns 162. The gate dielectric layer 151 can at least partially surround the first gate capping pattern 162 and the first word line 152a and the second word line 152b.

[0085] The first contact layer 170a can be provided on the first active pattern 141, the second active pattern 142, and the third active pattern 143, and thus can be electrically connected to the first active pattern 141, the second active pattern 142, and the third active pattern 143. The first contact layer 170a can overlap the first active pattern 141 to the third active pattern 143 in a vertical direction (Z direction), and can overlap (in the Z direction) a portion of the word line structure 150 adjacent to the first active pattern 141 to the third active pattern 143 and a portion of the charge trapping structure 120 adjacent to the first active pattern 141 to the third active pattern 143.

[0086] The second word line 152b of the word line structure 150 provided on the left side and the first word line 152a of the word line structure 150 provided on the right side based on the charge trapping structure 120 provided between the first active pattern 141 and the second active pattern 142 can be in the form of one charge trapping structure 120 provided between the first active pattern 141 and the second active pattern 142.

[0087] Figure 4B is a semiconductor device according to another example embodiment. Figure 3 is an enlarged view of a region A of the semiconductor device.

[0088] Referring to Figure 4B In the semiconductor device 100a, the remaining components other than the charge trapping structure 120a can be the same as or correspond to those shown in Figure 4A

[0089] The semiconductor device 100a can include a charge trapping structure 120a, a word line structure 150 spaced apart from the charge trapping structure 120a in a first direction (X direction), and an active pattern 140 provided between the charge trapping structure 120a and the word line structure 150.

[0090] ​The charge trapping structure 120a can include a charge trapping layer 122' and a first insulating film 121 disposed between the first active pattern 141 and the second active pattern 142 and the charge trapping layer 122'. The 1-1 insulating film 121a can include a first side surface in contact with the first active pattern 141 and a second side surface opposite the first side surface, and the 1-2 insulating film 121b can include a third side surface in contact with the second active pattern 142 and a fourth side surface opposite the third side surface. The charge trapping layer 122' can be in contact with the second side surface of the 1-1 insulating film 121a and the fourth side surface of the 1-2 insulating film 121b. The first insulating film 121 can include a first insulating material, and the charge trapping layer 122' can include a second insulating material different from the first insulating material. In an example, a width of the charge trapping layer 122' in the first direction (X direction) can be greater than a width of each of the first insulating films 121 in the first direction (X direction). For example, the width of the charge trapping layer 122' in the first direction (X direction) can be about 7 nm to about 16 nm, and the width of each of the 1-1 insulating film 121a and the 1-2 insulating film 121b in the first direction (X direction) can be about 4 nm to about 5 nm.

[0091] The charge trapping structure 120a can include the 1-1 insulating film 121a, the charge trapping layer 122', and the 1-2 insulating film 121b arranged sequentially in the first direction (X direction).

[0092] Figure 4C is a semiconductor device according to another example embodiment. Figure 3 An enlarged view of a region A of the semiconductor device.

[0093] Referring to Figure 4C In the semiconductor device 100b, the remaining components other than the charge trapping structure 120b can be the same as or correspond to those shown in Figure 4A

[0094] The semiconductor device 100b can include the charge trapping structure 120b, a word line structure 150 spaced apart from the charge trapping structure 120b in the first direction (X direction), and an active pattern 140 disposed between the charge trapping structure 120b and the word line structure 150.

[0095] The charge trapping structure 120b can have a structure further including a penetration or extension through Figure 4A ​The charge trapping structure 120b may include a first charge trapping layer 122a and a second charge trapping layer 122b, a first insulating film 121 disposed between the first active pattern 141 and the second active pattern 142 and the first charge trapping layer 122a and the second charge trapping layer 122b, a conductive film 125 disposed between the first charge trapping layer 122a and the second charge trapping layer 122b, and a second insulating film 123 located in a space between the first charge trapping layer 122a and the second charge trapping layer 122b and the conductive film 125 and at least partially filling the space. In an example, the second insulating film 123 may include a 2-1 insulating film 123a disposed between the first charge trapping layer 122a and the conductive film 125, and a 2-2 insulating film 123b disposed between the second charge trapping layer 122b and the conductive film 125.

[0096] The conductive film 125 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. For example, the conductive film 125 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiAlC, TaAlC, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x , graphene, carbon nanotubes, or a combination thereof, but the embodiments of the present disclosure are not limited thereto. The conductive film 125 may be formed of a single layer or multiple layers of the above materials.

[0097] The charge trapping structure 120b may include a 1-1 insulating film 121a, a first charge trapping layer 122a, a 2-1 insulating film 123a, a conductive film 125, a 2-2 insulating film 123b, a second charge trapping layer 122b, and a 1-2 insulating film 121b sequentially arranged in the first direction (X direction).

[0098] Figure 5A It is shown in Figure 4A Schematic diagram of an operation of trapping charges in a charge trapping layer of a charge trapping structure of a semiconductor device. Figure 5B It is shown in Figure 4C A diagram illustrating an operation of trapping charges in a charge trapping layer of a charge trapping structure of a semiconductor device.

[0099] Reference Figure 5A and Figure 5BThe operation of trapping the electric charges TRC in the charge trapping layer 122 of the charge trapping structure 120 can be a previous operation (e.g., a read and / or a write) of the semiconductor device 100. For example, the operation of trapping the electric charges TRC in the charge trapping layer 122 of the charge trapping structure 120 can be an operation that is first performed before program execution when power is supplied to a system of the semiconductor device 100. In another example, the operation of trapping the electric charges in the charge trapping layer 122 of the charge trapping structure 120 can be performed in a last process in a manufacturing process of the semiconductor device 100.

[0100] Referring to Figure 5A A positive first programming voltage (+Vpa) can be applied to the word line 152 to perform the operation of trapping the electric charges TRC in the charge trapping layer 122 of the charge trapping structure 120, and a positive second programming voltage (+Vpb) can be applied to the first contact layer 170a (and / or the contact pattern 170). The first programming voltage (+Vpa) can have a voltage that is greater than a voltage of a cell transistor (e.g., a threshold voltage of the cell transistor CTR in the memory cell 110). Figure 1 The first programming voltage (+Vpa) can have a value that allows the electrons in the channel region 140a of the active pattern 140 to pass through the first insulating films 121a and 121b and be trapped in the charge trapping layers 122a and 122b.

[0101] When the first programming voltage (+Vpa) is applied to the second word line 152b disposed at the left side of the first active pattern 141, and the second programming voltage (+Vpb) is applied to the first contact layer 170a (in the Z direction) overlapping the first active pattern 141, the electrons of the channel region 140a of the first active pattern 141 can pass through the 1-1 insulating film 121a in contact with the first active pattern 141, and can be trapped in the first charge trapping layer 122a.

[0102] When the first programming voltage (+Vpa) is applied to the first word line 152a disposed at the right side of the second active pattern 142, and the second programming voltage (+Vpb) is applied to the first contact layer 170a (in the Z direction) overlapping the second active pattern 142, the electrons of the channel region 140a of the second active pattern 142 can pass through the 1-2 insulating film 121b in contact with the second active pattern 142, and can be trapped in the second charge trapping layer 122b.

[0103] In an example embodiment, the operation of trapping the electric charges TRC in the first charge trapping layer 122a and the operation of trapping the electric charges TRC in the second charge trapping layer 122b can be performed simultaneously, or can be performed independently or separately.

[0104] In another example embodiment, when the operation of trapping the electric charges TRC in the first charge trapping layer 122a and the operation of trapping the electric charges TRC in the second charge trapping layer 122b are performed independently, the first programming voltage (+Vpa) can be applied to the second word line 152b disposed at the left side of the first active pattern 141, and the second programming voltage (+Vpb) can be applied to the first contact layer 170a (in the Z direction) overlapping the first active pattern 141. Figure 4BWhen the operation of trapping the charge TRC in the charge trapping layer 122' of the charge trapping structure 120a is performed, the first programming voltage (+Vpa) can be applied to the second word line 152b disposed at the left side of the first active pattern 141 and the first word line 152a disposed at the right side of the second active pattern 142, and the second programming voltage (+Vpb) can be applied to the first contact layer 170a (in the Z direction) overlapping the first active pattern 141 and the second active pattern 142. In this case, the electron of the channel region 140a of the first active pattern 141 can pass through the 1-1 insulating film 121a in contact with the first active pattern 141, and the electron of the channel region 140a of the second active pattern 142 can pass through the 1-2 insulating film 121b in contact with the second active pattern 142, so that the electron can be trapped in the charge trapping layer 122'.

[0105] Referring to Figure 4A , Figure 4B and Figure 5A , at least one charge trapping layer 122 or 122' can function as a back gate configured to control the charge accumulated in the vertical channel region 140a of the active pattern 140. For example, the vertical channel region 140a in the active pattern can be a floating body disposed between the upper source / drain region (second source / drain region) 140c and the lower source / drain region (first source / drain region) 140b, and at least one charge trapping layer 122 functioning as a back gate can inhibit or prevent the performance of the transistor from being degraded due to the floating body effect. For example, at least one charge trapping layer 122 can reduce, minimize, or prevent the variation of the threshold voltage of the transistor by accumulating the charge (e.g., hole) within the floating body of the vertical channel region 140a.

[0106] Referring to Figure 5B , to perform the operation of trapping the charge TRC in the charge trapping layer 122 of the charge trapping structure 120b, the positive third programming voltage (+Vpc) can be applied to the conductive film 125, and the negative fourth programming voltage (-Vn) can be applied to the first contact layer 170a (and / or the contact pattern 170).

[0107] When the fourth programming voltage (-Vn) is applied to the first contact layer 170a (in the Z direction) overlapping the first active pattern 141 and the second active pattern 142, and the third programming voltage (+Vpc) is applied to the conductive film 125, the electron of the channel region 140a of the first active pattern 141 can pass through the 1-1 insulating film 121a in contact with the first active pattern 141 and can be trapped in the first charge trapping layer 122a, and the electron of the channel region 140a of the second active pattern 142 can pass through the 1-2 insulating film 121b in contact with the second active pattern 142 and can be trapped in the second charge trapping layer 122b.

[0108] In the example embodiment, although Figure 1 is not shown in the circuit diagram, but can be formed between Figure 1 two word lines WL in the circuit diagram of , and the conductive film 125 can correspond to the back gate line (not shown).

[0109] Figures 6A to 6I is a diagram showing an example embodiment of a method of manufacturing a semiconductor device.

[0110] Referring to Figure 6A , a mask layer M can be formed on the semiconductor substrate 10. In the example embodiment, the semiconductor substrate 10 can be a silicon-on-insulator (SOI) substrate. The semiconductor substrate 10 can include a lower semiconductor layer 11, an insulating layer 13, and an upper semiconductor layer 14. For example, the lower semiconductor layer 11 and the upper semiconductor layer 14 can include single-crystal silicon. In some example embodiments, the semiconductor substrate 10 can be a bulk silicon substrate.

[0111] Referring to Figure 6B , a first trench T1 can be formed in the semiconductor substrate 10. The first trench T1 can penetrate or extend vertically (in the Z direction) through the mask layer M, the upper semiconductor layer 14, and the insulating layer 13, and can at least partially expose an upper surface of the lower semiconductor layer 11. The first trench T1 can extend in a second direction (Y direction) and be spaced apart from each other in a first direction (X direction).

[0112] Referring to Figure 6C , a first material layer 121P, a second material layer 122P, and a third material layer 123P can be sequentially formed conformally along inner walls of the first trench T1. In an example, the first material layer 121P can be in contact with the mask layer M, side surfaces of the upper semiconductor layer 14, the insulating layer 13, and the upper surface of the lower semiconductor layer 11. The second material layer 122P and the third material layer 123P can be sequentially formed on the first material layer 121P according to a surface profile of the first material layer 121P.

[0113] The first material layer 121P can include a first insulating material. The second material layer 122P can include a second insulating material different from the first insulating material. The third material layer 123P can include a third insulating material different from the second insulating material. In an example, the first material layer 121P and the third material layer 123P can include an oxide, and the second material layer 122P can include a nitride. For example, the first material layer 121P and the third material layer 123P can include silicon oxide, and the second material layer 122P can include silicon nitride.

[0114] The first material layer 121P, the second material layer 122P, and the third material layer 123P can be sequentially deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The first material layer 121P and the third material layer 123P can be deposited to be thicker (in the X direction) than the second material layer 122P disposed between the first material layer 121P and the third material layer 123P. In an example, the third material layer 123P can be deposited to be thicker (in the X direction) than the first material layer 121P.

[0115] Referring to Figure 6D A second trench T2 can be formed in the upper semiconductor layer 14. The second trench T2 can be formed by anisotropically etching the upper semiconductor layer 14 to expose an upper surface of the insulating layer 13. The second trench T2 can extend in a second direction (Y direction) and be spaced apart from each other in a first direction (X direction). The upper semiconductor layer 14 patterned by the etching process can be referred to as an active pattern 140.

[0116] After the etching process, an additional patterning process can be performed on the active pattern 140 along the first direction (X direction). As Figure 2 illustrated, the patterned active pattern 140 can be spaced apart from each other in the second direction (Y direction) along the charge trapping structure 120.

[0117] An insulating pattern 130 can be formed between the active pattern 140. The insulating pattern 130 can be in contact with a lower region of a side surface of the active pattern 140. The insulating pattern 130 can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an example embodiment, the insulating pattern 130 can include silicon oxide.

[0118] Referring to Figure 6E A preliminary dielectric layer 151P can be conformally formed along inner walls of the second trench T2. The preliminary dielectric layer 151P can be on and at least partially cover side surfaces and an upper surface of the mask layer M, an upper surface of the first material layer 121P, an upper surface of the second material layer 122P, an upper surface of the third material layer 123P, an upper surface of the insulating pattern 130, and side surfaces of the active pattern 140.

[0119] A preliminary word line 152P and a preliminary gate capping pattern 164P located between the preliminary word line 152P can be formed on the preliminary dielectric layer 151P within the second trench T2. The preliminary word line 152P can be formed by depositing a conductive material on the preliminary dielectric layer 151P and anisotropically etching the deposited conductive material. As Figure 2 illustrated, the preliminary word line 152 can extend in the second direction (Y direction) along the charge trapping structure 120 and can be spaced apart from each other in the first direction (X direction).

[0120] A preliminary gate capping pattern 164P can be formed between the preliminary word lines 152P on the preliminary dielectric layer 151P within the second trench T2.

[0121] Referring to Figure 6F A planarization process can be performed to remove the mask layer M, and a portion of the preliminary word lines 152P and a portion of the preliminary gate capping pattern 164P can be etched by an etch-back process. Through the etch process, the preliminary word lines 152P can be formed into the word lines 152, and the preliminary gate capping pattern 164P can be formed into the second gate capping pattern 164. The first gate capping pattern 162 and the second gate capping pattern 164 can be formed to be at least partially surrounded by the upper portions of the word lines 152. When the etch-back process is performed on the preliminary word lines 152P and the preliminary gate capping pattern 164P and the first gate capping pattern 162 is formed, the word line structure 150 is formed.

[0122] Referring to Figure 6G A contact pattern 170 can be formed on the active pattern 140. The contact pattern 170 can include a first contact layer 170a, a second contact layer 170b, a third contact layer 170c, and a fourth contact layer 170d, which are sequentially stacked. The contact pattern 170 can be electrically connected to the active pattern 140.

[0123] A contact insulating pattern 175 can be formed between the contact patterns 170. The contact insulating pattern 175 can be formed by sequentially depositing the first to fourth contact layers 170a to 170d, and then at least partially filling the contact patterns with an insulating material after a patterning process. The contact insulating pattern 175 can electrically isolate the contact patterns 170 from each other.

[0124] An information storage structure 180 including a first electrode 182, a dielectric layer 184, and a second electrode 186 can be formed on the contact pattern 170. The first electrode 182 can be in contact with the fourth contact layer 170d of the contact pattern 170.

[0125] Referring to Figure 6H The resulting structure of Figure 6G can be inverted so that the information storage structure 180 faces downward (-Z direction) of the lower semiconductor layer 11, and a grinding process can be performed. The lower semiconductor layer 11 and the insulating layer 13 can be removed by the grinding process, and the insulating pattern 130 and the active pattern 140 can be exposed. In other embodiments, the information storage structure 180 can be formed on the active pattern 140 without first inverting the resulting structure of Figure 6GThe lower semiconductor layer 11 and the insulating layer 13 can be removed by a grinding process with the resultant structure of the lower semiconductor layer 11 and the insulating layer 13. The first to third material layers 121P, 122P, and 123P can be partially etched to form a surface coplanar with the active pattern 140. As the first to third material layers 121P, 122P, and 123P are partially etched, a charge trapping structure 120 including the first insulating film 121, the charge trapping layer 122, and the second insulating film 123 can be formed.

[0126] Referring to Figure 6I , the bit line structure 110 and the lower insulating layer 101 can be formed on the active pattern 140 to manufacture Figure 1 the memory cell array region CELL of the semiconductor device 100. The bit line structure 110 can include the third conductive pattern 110c, the second conductive pattern 110b, and the first conductive pattern 110a sequentially stacked on the active pattern 140.

[0127] The lower insulating layer 101 can be formed on the bit line structure 110, the interconnection layer 103 and the through-connection 105 can be formed in the lower insulating layer 101, and the first bonding pad BP1 can be formed on an upper surface (in the -Z direction) of the lower insulating layer 101.

[0128] Next, referring to Figure 2 , the memory cell array region CELL (or the second structure ST2 in Figure 1 ) can be in contact with the peripheral circuit region PERI (or the first structure ST1 in Figure 1 ).

[0129] The peripheral circuit region PERI can be formed before the memory cell array region CELL is formed. The peripheral circuit region PERI can be formed before a manufacturing process of the memory cell array region CELL, or the peripheral circuit region PERI can be formed after the manufacturing process of the memory cell array region CELL.

[0130] Referring to Figure 3 , on the substrate 3, the peripheral transistor TR on the substrate 3, the interconnection layer 12, the through-connection 15, the insulating layer 9 on the peripheral transistor TR, the interconnection layer 12, and the through-connection 15 and at least partially covering the peripheral transistor TR, the interconnection layer 12, and the through-connection 15, and the second bonding pad BP2 can be formed to manufacture the peripheral circuit region PERI.

[0131] The memory cell array region CELL and the peripheral circuit region PERI can be bonded and connected by applying pressure to the first bonding pad BP1 and the second bonding pad BP2. The memory cell array region CELL and the peripheral circuit region PERI can be bonded and connected by applying pressure to the first bonding pad BP1 and the second bonding pad BP2. Figure 6IThe resulting structure is inverted such that the first bonding pad BP1 of the memory cell array region CELL faces downward. In an example, the peripheral circuit region PERI and the memory cell array region CELL can be directly bonded without additional adhesive material or adhesive.

[0132] While example embodiments have been shown and described above, it will be clear to those of ordinary skill in the art that modifications and changes can be made without departing from the spirit and scope of the disclosure as defined in the appended claims.

Claims

1. A semiconductor device comprising: a bit line structure; a charge trapping structure over the bit line structure; a word line structure arranged alternately with the charge trapping structure in a first direction, each of the word line structures including a first word line and a second word line spaced apart from each other in the first direction; an active pattern arranged on the bit line structure, arranged between the charge trapping structure and the word line structure, and electrically connected to the bit line structure; a contact pattern arranged on and electrically connected to the active pattern; and an information storage structure over the contact pattern, wherein each of the charge trapping structures includes: at least one charge trapping layer between the active patterns; and a first insulating film between the at least one charge trapping layer and the active pattern. the first insulating film includes a first insulating material, and 2. The semiconductor device according to claim 1, wherein wherein the at least one charge trapping layer includes a second insulating material different from the first insulating material. the first insulating material includes an oxide, and 3. The semiconductor device according to claim 2, wherein wherein the second insulating material includes a nitride. the at least one charge trapping layer includes a first charge trapping layer and a second charge trapping layer spaced apart from each other in the first direction.

4. The semiconductor device according to claim 1, wherein a width of each of the first insulating films in the first direction is greater than a width of the first charge trapping layer and greater than a width of the second charge trapping layer.

5. The semiconductor device according to claim 4, wherein each of the charge trapping structures further includes a second insulating film between the first charge trapping layer and the second charge trapping layer.

6. The semiconductor device according to claim 4, wherein a width of the second insulating film in the first direction is greater than a respective width of each of the first insulating films in the first direction.

7. The semiconductor device according to claim 6, wherein each of the charge trapping structures further includes a conductive film between the first charge trapping layer and the second charge trapping layer.

8. The semiconductor device according to claim 4, wherein each of the charge trapping structures further includes a second insulating film between the first charge trapping layer and the conductive film and between the second charge trapping layer and the conductive film, respectively.

9. The semiconductor device according to claim 8, wherein the at least one charge trapping layer is in contact with the first insulating film.

10. The semiconductor device according to claim 1, wherein a width of the at least one charge trapping layer in the first direction is greater than a width of each of the first insulating films in the first direction, respectively.

11. The semiconductor device according to claim 10, wherein each of the word line structures includes:

12. The semiconductor device according to claim 1, wherein a gate insulating pattern between the bit line structure and the first word line and the second word line; a first gate capping pattern on an upper surface of the first word line and an upper surface of the second word line; and a second gate capping pattern arranged on the gate insulating pattern, arranged between the first word line and the second word line, and arranged between the first gate capping pattern, wherein an upper surface of the charge trapping structure is coplanar with an upper surface of the first gate capping pattern and an upper surface of the second gate capping pattern.

13. The semiconductor device according to claim 1, further comprising a contact insulating pattern between the contact pattern, the contact insulating pattern overlaps the charge trapping structure in a second direction crossing the first direction. wherein 14. A semiconductor device comprising: ​ a bit line structure extending in a first direction; a first active pattern to a third active pattern sequentially arranged along the first direction on the bit line structure and electrically connected to the bit line structure; a charge trapping structure between the first active pattern and the second active pattern; a word line structure between the second active pattern and the third active pattern, the word line structure including a first word line opposite to a side of the second active pattern and a second word line opposite to a side of the third active pattern and spaced apart from the first word line in the first direction; a contact pattern arranged on the first active pattern to the third active pattern and electrically connected to the first active pattern to the third active pattern; and an information storage structure on the contact pattern, wherein the charge trapping structure includes: a first insulating pattern having a first side surface in contact with the first active pattern and a second side surface opposite to the first side surface and including a first insulating material; a second insulating pattern having a third side surface in contact with the second active pattern and a fourth side surface opposite to the third side surface and including the first insulating material; and at least one charge trapping layer between the first insulating pattern and the second insulating pattern, the at least one charge trapping layer including a material different from the first insulating material. the at least one charge trapping layer includes a first charge trapping layer in contact with the second side surface of the first insulating pattern and a second charge trapping layer in contact with the fourth side surface of the second insulating pattern, and 15. The semiconductor device according to claim 14, wherein wherein the charge trapping structure further includes a third insulating pattern including the first insulating material between the first charge trapping layer and the second charge trapping layer. the charge trapping structure further includes a conductive film extending through the third insulating pattern in a second direction intersecting the first direction.

16. The semiconductor device according to claim 15, wherein a lower surface of the charge trapping structure is in contact with an upper surface of the bit line structure.

17. The semiconductor device according to claim 14, wherein the at least one charge trapping layer is in contact with the second side surface of the first insulating pattern and the fourth side surface of the second insulating pattern, and 18. The semiconductor device according to claim 14, wherein wherein respective widths of the first insulating pattern and the second insulating pattern in the first direction are less than a width of the at least one charge trapping layer in the first direction. the at least one charge trapping layer has a lower surface at a level lower than a level of lower surfaces of the first word line and the second word line and an upper surface at a level higher than a level of upper surfaces of the first word line and the second word line, wherein an upper surface of the bit line structure provides a reference plane.

19. The semiconductor device according to claim 14, wherein 20. A semiconductor device comprising: a first structure including a peripheral circuit region; and a second structure overlapping the first structure in a third direction and including a memory cell array region, wherein the memory cell array region includes: a bit line structure; a charge trapping structure on the bit line structure; ​ a word line structure arranged alternately with the charge trapping structure in a first direction perpendicular to the third direction, each of the word line structure including first and second word lines spaced apart from each other in the first direction; an active pattern on the bit line structure between the charge trapping structure and the word line structure, the active pattern electrically connected to the bit line structure; a contact pattern on the active pattern, the contact pattern electrically connected to the active pattern; and an information storage structure on the contact pattern, wherein each of the charge trapping structure includes: first and second charge trapping layers spaced apart from each other in the first direction; a first insulating film between the first and second charge trapping layers and the active pattern; and a second insulating film between the first and second charge trapping layers, and wherein the first and second insulating films include a first insulating material, and the first and second charge trapping layers include a second insulating material different from the first insulating material.

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