Magnetic memory device including magnetic tunnel junction structure

Abstract

A magnetic memory device including a magnetic tunnel junction structure is provided. The magnetic memory device includes: a plurality of bit lines; a plurality of source lines arranged at different vertical heights from the plurality of bit lines; and a plurality of memory cells connected between the bit line and the source line and each including a memory device and a select transistor, in which the plurality of memory cells includes a first memory cell including a first memory device and a second memory cell including a second memory device. Each of the first and second memory devices includes a magnetic tunnel junction including a pinned layer, a tunnel barrier layer, and a free layer. Each of the second memory devices includes a first dummy device, a second dummy device, and an active device between the first dummy device and the second dummy device.

Description

TECHNICAL FIELD

[0001] The present inventive concepts relate to magnetic memory devices, and more particularly to magnetic memory devices including magnetic tunnel junction (MTJ) structures. BACKGROUND

[0002] Electronic devices utilizing the magnetoresistance properties of MTJs have been researched. For example, as MTJ cells of high-integration magnetic random access memory (MRAM) devices become miniaturized, fast read / write operations and low operating voltages of semiconductor devices embedded in electronic products become more desirable. In accordance with these requirements, a great deal of research has been conducted on magnetic memory devices utilizing the magnetoresistance properties of MTJs. For example, highly-integrated magnetic memory devices are being developed to provide high-speed read operations and write operations as nonvolatile memory devices. SUMMARY

[0003] According to an embodiment of the present inventive concepts, a magnetic memory device includes a plurality of bit lines, a plurality of source lines arranged at different vertical heights from the plurality of bit lines, and a plurality of memory cells connected between the bit lines and the source lines and each including a memory device and a selection transistor, wherein the plurality of memory cells includes first memory cells including first memory devices and second memory cells including second memory devices, each of the first and second memory devices includes a magnetic tunnel junction including a pinned layer, a tunnel barrier layer, and a free layer, in some of the second memory devices, the magnetic tunnel junction has an irreversible resistance state due to insulating breakdown of the tunnel barrier layer, each of the second memory devices includes a first dummy device, a second dummy device, and an active device between the first dummy device and the second dummy device, and a pitch between the first dummy device and the active device in a first horizontal direction is substantially equal to a pitch between the second dummy device and the active device.

[0004] According to an embodiment of the present inventive concept, a magnetic memory device includes a substrate having a first region and a second region; a plurality of first memory elements and a plurality of second memory elements each constituting a memory cell and spaced apart from each other in a first horizontal direction in the first region; an inter-wiring insulating layer located in the second region and having at least a portion located at substantially the same vertical height as the first memory elements and the second memory elements; a capping layer pattern covering sidewalls of the plurality of first memory elements and sidewalls of the plurality of second memory elements; and a buried layer pattern covering the capping layer pattern and filling a portion of each of spaces between the plurality of first memory elements and spaces between the plurality of second memory elements in the first region, wherein each of the plurality of first memory elements and the plurality of second memory elements includes a magnetic tunnel junction including a pinned layer, a tunnel barrier layer, and a free layer, in some of the plurality of second memory elements, the magnetic tunnel junction has an irreversible resistance state due to insulating breakdown of the tunnel barrier layer, each of the second memory elements includes a first dummy element, a second dummy element, and an active element located between the first dummy element and the second dummy element, a pitch between the first dummy element and the active element in the first horizontal direction is substantially equal to a pitch between the second dummy element and the active element, and a pitch between the active element and the first dummy element in the first horizontal direction is substantially equal to a pitch between the plurality of first memory elements in the first horizontal direction.

[0005] According to an embodiment of the present inventive concept, a magnetic memory device includes a substrate having a cell array region and a peripheral circuit region; a separation insulating layer in the cell array region and the peripheral circuit region; a plurality of first memory elements and a plurality of second memory elements on the separation insulating layer in the cell array region, wherein the plurality of first memory elements and the plurality of second memory elements constitute a plurality of memory cells and are spaced apart from each other in a horizontal direction; an inter-wiring insulating layer in the peripheral circuit region and having at least a portion at substantially the same vertical height as the plurality of first memory elements and the plurality of second memory elements; a cap layer pattern covering sidewalls of the plurality of first memory elements and sidewalls of the plurality of second memory elements; and a buried layer pattern covering the cap layer pattern and filling a portion of each of spaces between the plurality of first memory elements and spaces between the plurality of second memory elements in the cell array region, wherein each of the plurality of first memory elements and the plurality of second memory elements includes a magnetic tunnel junction including a pinned layer, a tunnel barrier layer, and a free layer, the magnetic tunnel junction in some of the plurality of second memory elements has an irreversible resistance state due to insulating breakdown of the tunnel barrier layer, each of the plurality of second memory elements includes a first dummy device, a second dummy device, and an active device between the first dummy device and the second dummy device, a pitch between the first dummy device and the active device in a first horizontal direction is substantially equal to a pitch between the second dummy device and the active device, a pitch between the active device and the first dummy device in the first horizontal direction is substantially equal to a pitch between the plurality of first memory elements in the first horizontal direction, a maximum length of the active device in the first horizontal direction is less than a maximum length of the first memory element in the first horizontal direction, and a maximum length of the first dummy device in the first horizontal direction is less than a maximum length of the first memory element in the first horizontal direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] The above and other aspects of the present inventive concept will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which: FIG. 1A is a configuration diagram illustrating a magnetic memory device having a variable resistance device according to an embodiment of the present inventive concept; FIG. 1B is a circuit diagram illustrating a cell array of a variable resistance device according to an embodiment of the present inventive concept; FIG. 2 is a configuration diagram of each memory cell provided in the memory cell array of FIG. 1A FIG. 3A and FIG. 3B is a conceptual diagram illustrating data stored in a magnetization direction in a magnetic tunnel junction (MTJ) structure of a memory cell of FIG. 2 FIG. 4 is a conceptual diagram illustrating a magnetization direction of a write operation in the MTJ structure of a memory cell of FIG. 2 FIG. 5A , FIG. 5B , FIG. 6 , FIG. 7A and FIG. 7B are conceptual diagrams of the MTJ structure of a memory cell according to an embodiment of the inventive concept; FIG. 2 FIG. 8A is a cross-sectional view illustrating a magnetic memory device according to an embodiment of the inventive concept; FIG. 8B , FIG. 8C and FIG. 8D are enlarged views of the region A of FIG. 8A FIG. 9 is a block diagram of an information processing system including a magnetic memory device according to an embodiment of the inventive concept; FIG. 10 is a block diagram of an electronic system including a magnetic memory device according to an embodiment of the inventive concept; FIG. 11 is a block diagram of a memory card including a magnetic memory device according to an embodiment of the inventive concept; FIG. 12 is a block diagram of an electronic device including a magnetic memory device according to an embodiment of the inventive concept; and FIG. 13 is a block diagram of a server system including a magnetic memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0007] Embodiments of the inventive concept can be modified in various ways and can take various other forms, and embodiments of the inventive concept will be shown in the drawings and described herein in detail. However, the present disclosure and drawings are not intended to limit the embodiments to certain forms disclosed herein. The embodiments described below are merely illustrative and various modifications can be made from the embodiments.

[0008] ​​​​​The use of all examples or illustrative terms is merely intended to illustrate the technical spirit and the scope is not limited to the examples or illustrative terms unless limited by the claims.

[0009] Unless otherwise described below, in the present specification, a vertical direction is defined as a Z direction, and a first direction and a second direction can each be defined as a horizontal direction substantially perpendicular to the Z direction. The first direction can be referred to as X, and the second direction can be referred to as Y. A vertical level can refer to a height level in the vertical direction Z. A horizontal width can refer to a length in the horizontal direction X and / or Y, and a vertical length can refer to a length in the vertical direction Z.

[0010] FIG. 1A is a configuration diagram illustrating a magnetic memory device having a variable resistance device according to an embodiment of the present inventive concept.

[0011] Referring to FIG. 1A The magnetic memory device 100 can include a memory cell array 10, an address decoder circuit 15, and a data input / output circuit 16.

[0012] The memory cell array 10 includes a plurality of memory cells MC arranged in rows and columns. The plurality of memory cells MC can include a magnetic memory cell including a variable resistance device. For example, the magnetic memory device 100 can include a magnetic random access memory (MRAM) including an upper electrode of a magnetic material, a lower electrode of a magnetic material, and a dielectric disposed between the upper electrode and the lower electrode.

[0013] In the magnetic memory device 100, each memory cell MC can include a selection transistor and a variable resistance implemented as a magnetic tunnel junction (MTJ). The memory cell array 10 includes a plurality of word lines WL, a plurality of bit lines BL and OBL, and a plurality of source lines SL connected to the memory cells MC. Each word line WL is connected to a gate of the selection transistor of the memory cells MC located in a row, and each of the bit line BL and the source line SL is connected to the variable resistance and a source of the selection transistor of the memory cells MC located in a column.

[0014] The memory cell array 10 includes a normal memory cell array 12 and a one-time programmable (OTP) memory cell array 14.

[0015] The normal memory cell array 12 includes a plurality of normal memory cells 20, and each of the plurality of normal memory cells 20 includes a first select transistor and a first variable resistance device. The normal memory cell array 12 includes the first select transistor connected to each of a plurality of word lines WL in one-to-one correspondence with rows, and the first variable resistance device connected to each of a plurality of bit lines BL in one-to-one correspondence with columns.

[0016] The OTP memory cell array 14 includes a plurality of OTP memory cells 30, and the OTP memory cell 30 includes a second select transistor and a second variable resistance device. The OTP memory cell 30 can have the same structure as the normal memory cell 20. The OTP memory cell array 14 can include the second select transistor connected to each of a plurality of word lines WL, the second variable resistance device connected to an OTP bit line OBL corresponding to a column, and the second variable resistance device can be short-circuited. For example, the second variable resistance device of the OTP memory cell 30 can have an irreversible resistance state by applying a breakdown voltage (BV) to electrically break down a tunnel barrier layer in a one-time programming operation.

[0017] As a peripheral circuit of the memory cell array 10, the magnetic memory device 100 can include an address decoder circuit 15 and a data input / output circuit 16.

[0018] The address decoder circuit 15 can be connected to the memory cell array 10 through the word lines WL and the source lines SL. The address decoder circuit 15 can decode a row address to select the word lines WL and the source lines SL, and decode a column address to select the bit lines BL.

[0019] The data input / output circuit 16 can be connected to the memory cell array 10 through the bit lines BL and the OBLs. The data input / output circuit 16 can include a column selection circuit, a write driver circuit, and a sense amplifier circuit. In the column selection circuit, one of the bit lines BL is selected in response to a column selection signal provided from the address decoder circuit 15, and a predetermined read / write voltage is applied to the bit line BL selected by the column selection circuit by using a read / write operation through the write driver circuit. The sense amplifier circuit determines data of the normal memory cell 20 in the normal memory cell array 12.

[0020] FIG. 1B is a circuit diagram showing a cell array of a variable resistance device according to an embodiment of the inventive concept.

[0021] Referring to FIG. 1B The magnetic memory device 100 can include a magnetoresistive memory cell array 10. The magnetoresistive memory cell array 10 can also be referred to as a memory cell array in which a plurality of memory cells are arranged in a matrix form. FIG. 1AThe OTP memory cell array described in FIG. 1. The magnetoresistive memory cell array 10 can be connected to a write driver 18a, a selection circuit 17, a source line voltage generator 18b, and a sense amplifier 18c. The magnetoresistive memory cell array 10 can include a plurality of magnetoresistive memory cells 30. The magnetoresistive memory cell 30 can be referred to as a memory cell in FIG. 1B The OTP memory cell described in FIG. 1. The magnetoresistive memory cell array 10 can include a plurality of word lines WL1 to WLm and a plurality of bit lines BL1 to BLn. The magnetoresistive memory cell array 10 can have the magnetoresistive memory cell 30 between each of the word lines WL1 to WLm and each of the bit lines BL1 to BLn. For example, each of the magnetoresistive memory cells 30 can be adjacent to a cross point between the plurality of word lines WL1 to WLm and the plurality of bit lines BL1 to BLn.

[0022] The magnetoresistive memory cell array 10 can include cell transistors MN11 to MNmn and magnetic tunnel junction layers MTJ11 to MTJmn, a gate of the cell transistor MN11 to MNmn is connected to the word line WL1 to WLm, the magnetic tunnel junction layer MTJ11 to MTJmn is connected between each of the cell transistors MN11 to MNmn and each of the bit lines BL1 to BLn and constitutes a variable resistance layer.

[0023] A respective source of the cell transistor MN11 to MNmn can be connected to a source line SL. The selection circuit 17 can selectively connect the bit lines BL1 to BLn to the sense amplifier 18c in response to a column selection signal CSL_s1 to CSL_sn. The sense amplifier 18c can generate an output data DOUT by amplifying a difference between an output voltage signal of the selection circuit 17 and a reference voltage VREF.

[0024] The write driver 18a is connected to the bit lines BL1 to BLn, generates a program current based on a write data, and supplies the program current to the bit lines BL1 to BLn. To magnetize the magnetic tunnel junction layers MTJ11 to MTJmn in the magnetoresistive memory cell array 10, a voltage higher than a voltage to be applied to the bit lines BL1 to BLn can be applied to the source line SL. The source line voltage generator 18b can generate a source line drive voltage VSL and supply the source line drive voltage VSL to the source line of the magnetoresistive memory cell array 10.

[0025] FIG. 2 is a configuration diagram of each memory cell provided in the memory cell array 10 of FIG. 1A

[0026] Referring to FIG. 2 , a normal memory cell 20 among the memory cells MC (see FIG. 1A ) provided in the memory cell array 10 (see FIG. 1A ) is illustrated.​

[0027] A normal memory cell 20 includes a select transistor 21 and an MTJ structure 22. A gate of the select transistor 21 can be connected to a word line WL, and a drain electrode of the select transistor 21 (which is one electrode of the select transistor 21) can be connected to a bit line BL through the MTJ structure 22. A source electrode of the select transistor 21 (which is another electrode of the select transistor 21) can be connected to a source line SL.

[0028] The MTJ structure 22 can include a pinned layer 23, a free layer 25, and a tunnel barrier layer 24 disposed between the pinned layer 23 and the free layer 25. A magnetization direction of the pinned layer 23 can be fixed, and a magnetization direction of the free layer 25 can be parallel (P) or anti-parallel (AP) to the magnetization direction of the pinned layer 23 according to data stored by a write operation. To fix the magnetization direction of the pinned layer 23, an anti-ferromagnetic layer can be additionally provided.

[0029] The pinned layer 23 can include a ferromagnetic material. For example, the pinned layer 23 can include at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO, MnOFeO, FeOFeO, NiOFeO, CuOFeO, MgOFeO, EuO, and / or YFeO.

[0030] The tunnel barrier layer 24 can include a non-magnetic material. For example, the tunnel barrier layer 24 can include at least one of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc oxide (MgZnO), titanium nitride (TiN), and / or vanadium nitride (VN).

[0031] For example, the free layer 25 can include a ferromagnetic material including at least one of cobalt (Co), iron (Fe), and / or nickel (Ni). For example, the free layer 25 can include at least one of FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO, MnOFeO, FeOFeO, NiOFeO, CuOFeO, MgOFeO, EuO, and / or YFeO.

[0032] In embodiments of the inventive concept, the normal memory cell 20 can be defined as a data 0 (zero) logic state when the free layer 25 and the pinned layer 23 of the MTJ structure 22 are in a parallel (P) state, i.e., when the MTJ structure 22 has a low resistance. In addition, the normal memory cell 20 can be defined as a data 1 (one) logic state when the free layer 25 and the pinned layer 23 of the MTJ structure 22 are in an anti-parallel (AP) state, i.e., when the MTJ structure 22 has a high resistance. In embodiments of the inventive concept, the normal memory cell 20 can be defined as a data 0 logic state in the anti-parallel (AP) state of the MTJ structure 22, and can be defined as a data 1 logic state in the parallel (P) state.

[0033] FIG. 3A and FIG. 3B is a conceptual diagram illustrating data stored in a magnetization direction in the MTJ structure of the memory cell of FIG. 2

[0034] Referring to FIG. 3A and FIG. 3B , the resistance value of the MTJ structure 22 can vary according to the magnetization direction of the free layer 25.

[0035] When the read current IR flows through the MTJ structure 22, a data voltage depending on the resistance value of the MTJ structure 22 can be output. Because the intensity of the read current IR is much smaller than that of the write current, the magnetization direction of the free layer 25 is not changed by the read current IR.

[0036] As shown in FIG. 3A , in the MTJ structure 22, the magnetization direction of the free layer 25 and the magnetization direction of the pinned layer 23 can be arranged to be parallel to each other. The MTJ structure 22 in this state can have a low resistance value, and can output data 0 through a read operation.

[0037] As shown in FIG. 3B , in the MTJ structure 22, the magnetization direction of the free layer 25 and the magnetization direction of the pinned layer 23 can be arranged to be anti-parallel to each other. The MTJ structure 22 in this state can have a high resistance value, and can output data 1 through a read operation.

[0038] FIG. 4 is a conceptual diagram illustrating a magnetization direction through a write operation in the MTJ structure of the memory cell of FIG. 2

[0039] Referring to FIG. 4 , the magnetization direction of the free layer 25 can be determined according to the directions of the write currents IW1 and IW2 flowing through the MTJ structure 22.

[0040] ​​When a first write current IW1 is applied from the free layer 25 toward the pinned layer 23 as shown in (a), free electrons having the same spin direction as the pinned layer 23 can exert a torque on the free layer 25. Thus, the free layer 25 can be magnetized to be parallel to the pinned layer 23. Accordingly, data 0 having a low resistance value can be stored in the MTJ structure 22 as shown in (b).

[0041] In the MTJ structure 22 in the data 0 state, when a second write current IW2 is applied from the pinned layer 23 toward the free layer 25 as shown in (c), free electrons having an opposite spin direction from the pinned layer 23 return to the free layer 25 and can exert a torque on the free layer 25. Thus, the free layer 25 can be magnetized to be anti-parallel to the pinned layer 23. Accordingly, data 1 having a high resistance value can be stored in the MTJ structure 22 as shown in (d).

[0042] For example, by spin transfer torque (STT), the magnetization direction of the free layer 25 in the MTJ structure 22 can change to be parallel or anti-parallel to the pinned layer 23, and thus, data 0 or data 1 can be stored.

[0043] FIG. 5A to FIG. 7B is a conceptual diagram of a storage cell of an MTJ structure according to an embodiment of the inventive concept. FIG. 2 is a conceptual diagram of a storage cell of an MTJ structure according to an embodiment of the inventive concept.

[0044] Referring to FIG. 5A , the MTJ structure 22 can include a pinned layer 51, a tunnel barrier layer 52, a free layer 53, and an anti-ferromagnetic layer 54.

[0045] The anti-ferromagnetic layer 54 can include an anti-ferromagnetic material. For example, the anti-ferromagnetic layer 54 can include at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF, FeCl, FeO, CoCl, CoO, NiCl, NiO, and / or Cr.

[0046] The free layer 53 and the pinned layer 51 of the MTJ structure 22 can each include ferromagnetic, and thus, a stray field can be generated at the edge of the ferromagnetic. The stray field can reduce the magnetic resistance or increase the magnetic resistance of the free layer 53. For example, the stray field can affect the switching characteristics, forming an asymmetric switching. Thus, a structure to reduce or control the stray field that can be generated from the ferromagnetic in the MTJ structure 22 can be desirable.

[0047] Referring to FIG. 5B , the MTJ structure 22 can include a pinned layer 61, a tunnel barrier layer 62, and a free layer 63, and the pinned layer 61 can include a synthetic anti-ferromagnetic.

[0048] The pinned layer 61 can include a first ferromagnetic layer 61 1, a coupling layer 61 2, and a second ferromagnetic layer 61 3. For example, each of the first ferromagnetic layer 61 1 and the second ferromagnetic layer 61 3 can include at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO, MnOFeO, FeOFeO, NiOFeO, CuOFeO, MgOFeO, EuO, and / or YFeO. For example, the coupling layer 61 2 can include ruthenium (Ru).

[0049] The magnetization direction of the first ferromagnetic layer 61 1 and the magnetization direction of the second ferromagnetic layer 61 3 can be different directions from each other, and each magnetization direction can be fixed.

[0050] Referring to FIG. 6 , the magnetization direction of the MTJ structure 22 can be substantially perpendicular to the tunnel barrier layer 72, and thus the direction of current flow and the easy axis of magnetization can be substantially parallel to each other.

[0051] A structure in which the magnetization directions are substantially perpendicular is called a perpendicular MTJ structure. The perpendicular MTJ structure 22 further includes a pinned layer 71, a tunnel barrier layer 72, and a free layer 73. When the magnetization direction of the free layer 73 and the magnetization direction of the pinned layer 71 are parallel to each other, the resistance value can decrease, and when the magnetization direction of the free layer 73 and the magnetization direction of the pinned layer 71 are anti-parallel to each other, the resistance value can increase. Thus, data can be stored in the perpendicular MTJ structure 22 according to the resistance value.

[0052] To implement the perpendicular MTJ structure 22, the free layer 73 and the pinned layer 71 can include a material having a high magnetic anisotropy energy. For example, each of the free layer 73 and the pinned layer 71 can include an ordered alloy, and include at least one of iron (Fe), cobalt (Co), nickel (Ni), palladium (Pa), and / or platinum (Pt). Each of the free layer 73 and the pinned layer 71 can include at least one of a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, and / or a Co-Ni-Pt alloy.

[0053] FIG. 7A A double MTJ structure 22 is shown in which the tunnel barrier layers 82 and 84 are located on opposite sides of the free layer 83 from the pinned layers 81 and 85, respectively.

[0054] A double MTJ structure 22 that forms a horizontal magnetic force can include a first pinned layer 81, a first tunnel barrier layer 82, a free layer 83, a second tunnel barrier layer 84, and a second pinned layer 85. The first pinned layer 81 and the second pinned layer 85 can be similar to the pinned layer 51 (seeFIG. 5A ). The first tunnel barrier layer 82 and the second tunnel barrier layer 84 can be similar to the tunnel barrier layer 52 (see FIG. 5A ), and the free layer 83 can be similar to the free layer 53 (see FIG. 5A ).

[0055] When the magnetization direction of the first pinned layer 81 and the magnetization direction of the second pinned layer 85 are fixed in opposite directions from each other, the magnetic forces caused by the first pinned layer 81 and the second pinned layer 85 can substantially cancel out. The dual MTJ structure 22 can perform a read operation by using less current compared to a typical MTJ device. The dual MTJ structure 22 can provide a higher resistance during a read operation due to the second tunnel barrier layer 84, and thus a clear resistance value can be obtained.

[0056] FIG. 7B A perpendicular dual MTJ structure 22 is shown with tunnel barrier layers 92 and 94 located on either side (e.g., opposite sides) of a pinned layer 91 and 95, respectively, of a free layer 93.

[0057] A perpendicular magnetic force forming perpendicular dual MTJ structure 22 can include a first pinned layer 91, a first tunnel barrier layer 92, a free layer 93, a second tunnel barrier layer 94, and a second pinned layer 95. The first pinned layer 91 and the second pinned layer 95 can be similar to the pinned layer 71 (see FIG. 6 ). The first tunnel barrier layer 92 and the second tunnel barrier layer 94 can be similar to the tunnel barrier layer 72 (see FIG. 6 ), and the free layer 93 can be similar to the free layer 73 (see FIG. 6 ).

[0058] When the magnetization direction of the first pinned layer 91 and the magnetization direction of the second pinned layer 95 are fixed in opposite directions from each other, the magnetic forces caused by the first pinned layer 91 and the second pinned layer 95 can substantially cancel out. The perpendicular dual MTJ structure 22 can perform a read operation by using less current compared to a typical MTJ device. The perpendicular dual MTJ structure 22 can provide a higher resistance during a read operation due to the second tunnel barrier layer 94, and thus a clear resistance value can be obtained.

[0059] FIG. 8A is a cross-sectional view showing a magnetic memory device according to an embodiment of the inventive concept.

[0060] Reference is made to FIG. 7B together with FIGS. 1 to FIG. 8AThe magnetic memory device 100 can include a substrate W divided into a first region and a second region. The first region can be a cell array region in which magnetic resistance storage cells are formed. The second region can be a peripheral circuit region disposed adjacent to the first region and in which core / peripheral circuits are formed. In the first region and the second region, the substrate W can include an active region 100a defined by a device isolation layer 102. In the cell array region, the magnetic memory device 100 can include a plurality of bit lines BL, a plurality of source lines SL corresponding to the bit lines BL, and a plurality of storage cells connected between the bit lines and the source lines and including a storage device and a first transistor 116. The storage cells can include first storage cells including first storage devices 161 (see FIG. 8D ), and second storage cells including second storage devices.

[0061] The second storage device can include a first dummy device 161b, a second dummy device, and an active device 161a located between the first dummy device 161b and the second dummy device. A pitch SP in a first horizontal direction X between the first dummy device 161b and the active device 161a can be equal to a pitch SP between the second dummy device and the active device 161a. However, for ease of explanation, FIG. 8A The magnetic memory device 100 including the active device 161a and the dummy device 161b among the magnetic resistance storage cells is illustrated. The first storage cells can constitute a normal storage cell array to be programmed a plurality of times, and the second storage cells can constitute a one-time programmable (OTP) storage cell array to be programmed once.

[0062] The first transistor 116 can be disposed in the active region 100a of the first region. The first transistor can correspond to FIG. 2 the selection transistor 21 in FIG. 1. For example, two first transistors 116 including two first gate electrodes 108 can be formed in the active region 100a. For example, a first source region 112 can be formed in a central portion of the active region 100a. The first source region 112 can be a common source region shared by the two first transistors 116 formed in the active region 100a. The number of the first transistors 116 illustrated in the common source region is not limited to that illustrated in the drawing. The number of selection transistors (i.e., the first transistors 116) per unit storage cell can be greater in the second storage cells than in the first storage cells. For example, a first drain region 114 can be formed in two edges of the active region 100a.

[0063] The source line 132 can be formed on the first source region 112 of the active region 100a. For example, the source line 132 can contact an upper surface of the first source region 112. For example, the source line 132 can include at least one metal such as tungsten, titanium, and tantalum, or a metal nitride such as tungsten nitride, titanium nitride, and tantalum nitride.

[0064] Although FIG. 8A Although an example in which the first transistor 116 has a buried gate structure and the first gate electrode 108 is formed in a trench extending into the substrate W is illustrated, in an embodiment of the present inventive concept, the first transistor 116 can include at least one of a finFET (fin-type field effect transistor) device, a gate all-around type FET device, or a planar transistor device.

[0065] The second transistor 118 constituting the core / peripheral circuit can be formed on the substrate W in the second region. In an embodiment of the present inventive concept, the second transistor 118 can include a planar transistor. For example, the second transistor 118 can include a second gate insulating layer pattern 120, a second gate electrode 122, and a second source / drain region 126 formed on the substrate W in the second region. A second hard mask pattern 124 can cover the second gate electrode 122. The second gate insulating layer pattern 120, the second gate electrode 122, and the second hard mask pattern 124 can be collectively referred to as a second gate structure.

[0066] A first interlayer insulating layer 140 can be formed on the substrate W in the first region and the second region. The first interlayer insulating layer 140 can be formed to cover the source line 132, the first transistor 116, and the second transistor 118 with a sufficient thickness. In an embodiment of the present inventive concept, the first interlayer insulating layer 140 can include a first lower interlayer insulating layer 140a and a second lower interlayer insulating layer 140b. The source line 132 can be formed to pass through the first lower interlayer insulating layer 140a.

[0067] In the first region, a contact plug 134 can be formed to pass through the first interlayer insulating layer 140 and can contact the first drain region 114. The contact plug 134 can be formed to pass through the first lower interlayer insulating layer 140a and the second lower interlayer insulating layer 140b and can contact the first drain region 114.

[0068] A first wiring line 142 can be disposed on the contact plug 134. A first inter-wiring insulating layer 144 can be located between the first wiring lines 142. The first inter-wiring insulating layer 144 can at least partially surround the first wiring lines 142. For example, the first inter-wiring insulating layer 144 can include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. For example, the first inter-wiring insulating layer 144 can include a tetraethyl orthosilicate (TEOS) film, an ultra low K (ULK) film, or an extremely low k (ELK) film. In an embodiment of the inventive concept, the ULK film or the ELK film can have a dielectric constant of about 2 to about 3.5. In an embodiment of the inventive concept, the first inter-wiring insulating layer 144 can include a SiOC film, a SiOF film, a SiCH film, a SiCOH film, or a combination thereof.

[0069] A metal wiring can be disposed on the first wiring lines 142. The metal wiring can include wiring lines electrically connected to the selection transistors and wiring contacts. According to an embodiment of the inventive concept, first wiring contacts 146 can be provided as the wiring contacts. The first wiring contacts 146 can be electrically connected to the respective first wiring lines 142. In an embodiment of the inventive concept, the first wiring contacts 146 can contact the respective first wiring lines 142, but the inventive concept is not limited thereto. For example, at least one wiring contact and at least one wiring line are located between each of the respective first wiring lines 142 and the first wiring contacts 146, so each of the first wiring lines 142 can be electrically connected to a respective one of the first wiring contacts 146 through the at least one wiring contact and the at least one wiring line. The first wiring contacts 146 located in the second region can be spaced apart from each other. For example, when each of the first wiring contacts 146 in the first region is electrically connected to the active device 161a, each of the first wiring contacts 146 can be connected to and integrated as a single body with each other. The first wiring contacts 146 can not be electrically connected to the dummy device 161b. Thus, the dummy device 161b can be connected to the bit line, but can not be connected to the source line. The active device 161a can be connected to the source line through the metal wiring.

[0070] A second inter-wiring insulating layer 148 can be located between the first wiring contacts 146. The second inter-wiring insulating layer 148 can at least partially surround the first wiring contacts 146. The second inter-wiring insulating layer 148 can include, for example, silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In an embodiment of the inventive concept, the second inter-wiring insulating layer 148 can include a TEOS film, a ULK film, or an ELK film.

[0071] The separation insulating layer 150 may cover the first wiring contact 146 and the second inter-wiring insulating layer 148. The separation insulating layer 150 may be disposed on the first wiring contact 146 and the second inter-wiring insulating layer 148. The separation insulating layer 150 may include an insulating material having a dielectric constant higher than that of silicon oxide but lower than that of silicon nitride. In an embodiment of the present inventive concept, the separation insulating layer 150 may include an insulating material other than oxide. For example, the separation insulating layer 150 may include SiCN. The separation insulating layer 150 may cover the first wiring contact 146 and the second inter-wiring insulating layer 148 with a substantially constant thickness.

[0072] In the first region, the lower electrode contact 152 may be provided on the corresponding first wiring contact 146. In the case of the OTP memory cell 30 (see FIG. 1A ), the lower electrode contact 152 may not be provided on every lower surface of all magnetic tunnel junctions 168. According to an embodiment of the present inventive concept, the lower electrode contact 152 may be provided on the lower surface of the active device 161a, but not on the lower surface of the dummy device 161b. The lower electrode contact 152 may be formed to penetrate the separating insulating layer 150 and may contact the corresponding first wiring contact 146. For example, when direct contact between the first wiring contact 146 and the active device 161a and the dummy device 161b is difficult, the lower electrode contact 152 may be provided. In an embodiment of the present inventive concept, when the first wiring contact 146 and the active device 161a are in direct contact with each other, the lower electrode contact 152 may not be provided. In an embodiment of the present inventive concept, the first wiring contact 146 contacting the lower electrode contact 152 provided on the lower surface of the active device 161a may be a first wiring contact 146 formed by integrating a plurality of first wiring contacts 146. Although the drawing shows that three first wiring contacts 146 are formed into one body, the number of first wiring contacts 146 formed into one body is not limited to that shown in the drawing.

[0073] In the first region, the contact spacer layer 154 may cover the sidewalls of the lower electrode contacts 152 on the separation insulating layer 150. The upper surface of the portion of the contact spacer layer 154 located between adjacent lower electrode contacts 152 may be located at a lower height in the vertical direction than the upper surface of the portion of the contact spacer layer 154 covering the sidewalls of the lower electrode contacts 152. For example, the contact spacer layer 154 may conformally cover the upper surface of the separation insulating layer 150 and the sidewalls of the lower electrode contacts 152. For example, the contact spacer layer 154 may include silicon oxide. For example, the contact spacer layer 154 may include a TEOS film.

[0074] In the first region, an active device 161a constituting an OTP storage unit can be provided on the lower electrode contact 152. The active device 161a can have an isolated island shape. Although one active device 161a is shown in the drawing, a plurality of active devices 161a can be provided. The plurality of active devices 161a can be spaced apart from each other in the horizontal direction. For example, the active device 161a can be spaced apart from a dummy device 161b in the horizontal direction. A lower surface of the active device 161a can contact an upper surface of a portion of the lower electrode contact 152 and an upper surface of a portion of the separation layer 154 covering a side wall of the lower electrode contact 152. The active device 161a can have a structure in which a lower electrode 160, a magnetic tunnel junction 168, and an upper electrode 170 are stacked. For example, a lower surface of the lower electrode 160 can contact an upper surface of a portion of the lower electrode contact 152 and an upper surface of a portion of the separation layer 154 covering a side wall of the lower electrode contact 152.

[0075] The magnetic tunnel junction 168 can constitute a variable resistance layer, and can include a pinned layer pattern 162, a tunnel barrier layer pattern 164, and a free layer pattern 166. The active device 161a can have a tapered shape in which a horizontal width decreases away from the substrate W in the vertical direction (Z direction). For example, each of the lower electrode 160 provided in the active device 161a and the dummy device 161b, the magnetic tunnel junction 168 including the pinned layer pattern 162, the tunnel barrier layer pattern 164, and the free layer pattern 166, and the upper electrode 170 can have a tapered shape in which a horizontal width decreases away from the substrate W in the vertical direction (Z direction).

[0076] The lower electrode 160 and the upper electrode 170 can include a metal or a metal nitride. For example, the pinned layer pattern 162 can include iron manganese (FeMn), iridium manganese (IrMn), platinum manganese (PtMn), manganese oxide (MnO), manganese sulfide (MnS), manganese tellurium (MnTe), and manganese fluoride (MnF2), iron fluoride (FeF2), iron chloride (FeCl2), iron oxide (FeO), cobalt chloride (CoCl2), cobalt oxide (CoO), nickel chloride (NiCl2), nickel oxide (NiO), and chromium (Cr).

[0077] A buried layer pattern 174 can be formed on the cap layer pattern 172 to fill a portion of a space between the lower electrode 160 and the upper electrode 170. The buried layer pattern 174 can include, for example, silicon oxide. For example, the buried layer pattern 174 can include silicon oxide formed using a high-density plasma (HDP) process. An uppermost end of the buried layer pattern 174 can be located at a lower height in the vertical direction than an uppermost end of the upper electrode 170, and a lowermost end of the buried layer pattern 174 can be located at a higher height in the vertical direction than an upper surface of the separation insulating layer 150.

[0078] In the first region, a first insulating stopper layer 182 of the insulating stop structure 180 can be formed on the cap layer pattern 172 and the buried layer pattern 174. The first insulating stopper layer 182 can fill the remaining portion of the space between the active device 161a and the dummy device 161b on the cap layer pattern 172. For example, the lower portion of the space between the active device 161a and the dummy device 161b on the cap layer pattern 172 can be filled with the buried layer pattern 174, and the upper portion can be filled with the first insulating stopper layer 182. The first insulating stopper layer 182 can fill the upper portion of the space between the active device 161a and the dummy device 161b on the cap layer pattern 172, and cover the uppermost surface of the cap layer pattern 172. The first insulating stopper layer 182 can additionally cover the sidewall of the cap layer pattern 172, which covers the sidewall of the active device 161a or the dummy device 161b located at the outermost position among the active device 161a and the dummy device 161b.

[0079] The first insulating stopper layer 182 can include an insulating material having a dielectric constant higher than that of silicon oxide but a dielectric constant lower than that of silicon nitride. In an embodiment of the inventive concept, the first insulating stopper layer 182 can include an insulating material other than an oxide.

[0080] The bit line 192B extending while being disposed on the upper surface of the active device 161a and the upper surface of the dummy device 161b can be formed on the cap layer pattern 172, the buried layer pattern 174, the active device 161a, and the dummy device 161b. For example, the bit line 192B can contact the upper surface of the active device 161a and the upper surface of the dummy device 161b. The bit line 192B can be disposed on the upper electrode 170 of the active device 161a. For example, the bit line 192B can contact the upper electrode 170 of the active device 161a. The bit line 192B can have a structure in which a barrier metal layer and a metal layer are stacked on each other. The barrier metal layer can include, for example, titanium, titanium nitride, tantalum, and tantalum nitride. The metal layer can include copper, tungsten, and aluminum. The bit line 192B can extend in a second horizontal direction (Y direction). A plurality of bit lines 192B can be disposed to be parallel to each other in a first horizontal direction (X direction).

[0081] In the second region, a third inter-wiring insulating layer 178 can be formed on the separation insulating layer 150. For example, at least a portion of the third inter-wiring insulating layer 178 can be located at substantially the same vertical level as the buried layer pattern 174. For example, the buried layer pattern 174 can be located at substantially the same vertical level as a portion of the third inter-wiring insulating layer 178. For example, an uppermost end of the third inter-wiring insulating layer 178 can be located at a higher vertical level than an uppermost end of the buried layer pattern 174, and a lowermost end of the third inter-wiring insulating layer 178 can be located at a lower vertical level than a lowermost end of the buried layer pattern 174. In embodiments of the present inventive concept, an uppermost end of the third inter-wiring insulating layer 178 can be located at substantially the same vertical level as an uppermost end of the first insulating stopper layer 182, and a lowermost end of the third inter-wiring insulating layer 178 can be located at substantially the same vertical level as an uppermost surface of the separation insulating layer 150. For example, at least a portion of the third inter-wiring insulating layer 178 can be located at substantially the same vertical level as the active device 161a and the dummy device 161b. The active device 161a and the dummy device 161b can be located at substantially the same vertical level as a portion of the third inter-wiring insulating layer 178.

[0082] The third inter-wiring insulating layer 178 can include an insulating material having a dielectric constant lower than a dielectric constant of the buried layer pattern 174. For example, the third inter-wiring insulating layer 178 can include an insulating material having a dielectric constant lower than a dielectric constant of silicon oxide. In embodiments of the present inventive concept, the third inter-wiring insulating layer 178 can include a ULK film or an ELK film.

[0083] The second wiring line 192L and the second wiring contact 192C can be formed through the second insulating stopper layer 184, the third inter-wiring insulating layer 178, and the separation insulating layer 150 of the insulating stop structure 180, and can be connected to the first wiring contact 146. For example, the second wiring line 192L can be formed through the second insulating stopper layer 184 and through an upper portion of the third inter-wiring insulating layer 178. The second wiring contact 192C can be connected to the second wiring line 192L, and can be formed through a lower portion of the third inter-wiring insulating layer 178. Further, the second wiring contact 192C can be formed through the separation insulating layer 150, and can contact the first wiring contact 146. The second wiring line 192L and the second wiring contact 192C can include the same material as the bit line 192B. The second wiring line 192L and the second wiring contact 192C can have a structure in which a barrier metal layer and a metal layer are stacked on each other. For example, the second wiring line 192L and the second wiring contact 192C can be integrally connected to each other such that they form a single body. In an embodiment of the inventive concept, an upper surface of the first insulating stopper layer 182, an upper surface of the bit line 192B, an upper surface of the second wiring line 192L, an upper surface of the second insulating stopper layer 184, and an uppermost surface of the third inter-wiring insulating layer 178 can be located at substantially the same vertical height, i.e., a third vertical height, thereby being substantially coplanar with each other.

[0084] A third insulating stopper layer 186 of the insulating stop structure 180 can be disposed on the first insulating stopper layer 182, the bit line 192B, the second wiring line 192L, the second insulating stopper layer 184, and the third inter-wiring insulating layer 178. A fourth inter-wiring insulating layer 194 can be disposed on the third insulating stopper layer 186. A third wiring line 198 and a third wiring contact 196 can be disposed in the fourth inter-wiring insulating layer 194, and the third wiring line 198 can be electrically connected to the bit line 192B through the third wiring contact 196 contacting the bit line 192B.

[0085] FIG. 8B to FIG. 8D is according to an embodiment of the inventive concept FIG. 8A is an enlarged view of the area A.

[0086] will be described with reference to FIG. 1A to FIG. 8A FIG. 8B ​The active device 161a and the dummy device 161b can have a tapered shape whose horizontal width decreases as a distance from the substrate W in a vertical direction (Z direction) increases, and can have a maximum length among lengths in the horizontal direction at a bottom surface of the active device 161a and the dummy device 161b. According to an embodiment of the inventive concept, the active device 161a can have a maximum length WT_161a among lengths in a first horizontal direction (X direction), and the dummy device 161b can have a maximum length WT_161b among lengths in the first horizontal direction (X direction).

[0087] The horizontal width of the cap pattern 172 and the buried layer pattern 174 adjacent to the maximum length WT_161a of the active device 161a and the maximum length WT_161b of the dummy device 161b can be a pitch SP. The pitch SP can be a pitch between the active device 161a and the dummy device 161b.

[0088] Referring to FIG. 8D , the first memory device 161 can also have a tapered shape whose horizontal width decreases as a distance from the substrate W in a vertical direction (Z direction) increases, and can have a maximum length in the horizontal direction. According to an embodiment of the inventive concept, the first memory device 161 can have a maximum length WT_161 among lengths in a first horizontal direction X. The width of the cap pattern 174 and the buried layer pattern 174 located between the plurality of first memory devices 161 in the horizontal direction is defined as a pitch SP, similar to FIG. 8B The pitch (i.e., the pitch SP) between the active device 161a and the dummy device 161b in the first horizontal direction X can be substantially constant. FIG. 8D The pitch SP in FIG. 8B may also be substantially constant. The pitch between the active device 161a and the dummy device 161b in the first horizontal direction X can be substantially equal to the pitch between the first memory devices 161 in the first horizontal direction X. For example, FIG. 8D The pitch SP in and the pitch SP in

[0089] may have the same width. FIG. 8D FIG. 8B The maximum length WT_161a of the active device 161a can be smaller than a maximum length WT_161 among lengths of the first memory device 161 in the first horizontal direction X. The maximum length WT_161b among lengths of the dummy device 161b in the first horizontal direction X can be greater than the maximum length WT_161 among lengths of the first memory device 161 in the first horizontal direction X. For example, in FIG. 8DIn the embodiment, the spacing SP can be maintained the same, and as the maximum length WT_161a of the active device 161a decreases, the maximum length WT_161b of the dummy device 161b can increase. The maximum length WT_161b of the dummy device 161b can be greater than the maximum length WT_161a of the active device 161a. The maximum length WT_161a of the active device 161a in the first horizontal direction X can be approximately 10 nm to approximately 20 nm.

[0090] Reference FIG. 8C , the maximum length WT_161a of the active device 161a can be less than FIG. 8D The maximum length WT_161 among the lengths of the first storage device 161 in the first horizontal direction X can be less than the maximum length WT_161 among the lengths of the first storage device 161 in the first horizontal direction X. Since the maximum length WT_161a of the active device 161a and the maximum length WT_161b of the dummy device 161b are both less than FIG. 8D The buried layer pattern 174 may be moved in the first horizontal direction X to have a maximum length WT_161 among the lengths of the first memory device 161 in the first horizontal direction X and may be located between the active device 161a and the first dummy device 161b. FIG. 8C and FIG. 8D , the spacing SP can be maintained the same.

[0091] Reference FIG. 8D Each lower electrode contact 152 may be disposed on a lower surface of the first memory device 161 . Each lower electrode contact 152 may be connected to the first wiring contact 146 .

[0092] FIG. 9 is a block diagram of an information processing system including a magnetic memory device according to an embodiment of the inventive concept.

[0093] Reference FIG. 9 The information processing system 700 includes an input device 710, an output device 720, a processor 730, and a memory device 740. In an embodiment of the present invention, the memory device 740 may include a cell array including non-volatile memory cells and a peripheral circuit for operations such as read / write operations. In an embodiment of the present invention, the memory device 740 may include a non-volatile memory device and a memory controller.

[0094] The memory 742 provided in the memory device 740 may include a memory device 740 according to FIG. 1 to FIG. FIG. 8DA magnetic tunnel junction (MTJ) 168 or a magnetic memory device 100 including the MTJ of the described embodiments.

[0095] The processor 730 can be connected to the input device 710, the output device 720, and the memory device 740 through an interface, and can control the overall operation of the information processing system 700.

[0096] FIG. 10 is a block diagram of an electronic system including a magnetic memory device according to an embodiment of the inventive concept.

[0097] Referring to FIG. 10 , the electronic system 800 includes a nonvolatile memory system 810, a MODEM 820, a central processing device 830, a RAM 840, and a user interface 850 electrically connected to a bus 802.

[0098] The nonvolatile memory system 810 can include a memory 812 and a memory controller 814. The nonvolatile memory system 810 stores data processed by the central processing device 830 or data input from the outside.

[0099] The nonvolatile memory system 810 can include a nonvolatile memory such as MRAM, PRAM, RRAM, and FRAM. At least one of the memory 812 and the RAM 840 can include a MTJ 168 or a magnetic memory device 100 including the MTJ according to the embodiments described with reference to FIGS. 1 to FIG. 8D

[0100] The electronic system 800 can be used, for example, in a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state drive (SSD), or a home appliance. However, the inventive concept is not limited thereto.

[0101] FIG. 11 is a block diagram of a memory card including a magnetic memory device according to an embodiment of the inventive concept.

[0102] Referring to FIG. 11 , the memory card 900 includes a memory 910 and a memory controller 920.

[0103] The memory 910 can store data. In an embodiment of the inventive concept, the memory 910 has a nonvolatile property of retaining stored data even if power interruption or termination occurs. The memory 910 can include a MTJ 168 or a magnetic memory device 100 including the MTJ according to the embodiments described with reference to FIGS. 1 to FIG. 8D

[0104] ​​The memory controller 920 can read data stored in the memory 910 or store data in the memory 910 in response to a read / write request from the host 930.

[0105] FIG. 12 is a block diagram of an electronic device including a magnetic memory device according to an embodiment of the inventive concept.

[0106] Referring to FIG. 12 , the electronic device 1000 includes a host 1010 and a storage device 1020.

[0107] The host 1010 can include a user device, for example, a personal computer, a portable computer, a tablet PC, a smart phone, a digital camera, and a digital video camera. The host 1010 stores data in the storage device 1020 or reads data from the storage device 1020 through an input / output request.

[0108] The host 1010 can be connected to the storage device 1020 through various interfaces such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect (PCI), a high-speed PCI (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer small interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0109] The storage device 1020 can be a data storage device for performing a write operation or a read operation according to an input / output request from the host 1010, and can include a magnetic memory device 1022. The magnetic memory device 1022 includes a memory cell array 1024 and an OTP control circuit 1028, and the memory cell array 1024 includes a normal memory cell array 1025 and an OTP memory cell array 1026.

[0110] A normal memory cell including a first selection transistor and a first variable resistance device is arranged in the normal memory cell array 1025, and a bit line of the normal memory cell is provided to a sense amplifier. An OTP memory cell including a second selection transistor and a shorted second variable resistance device is arranged in the OTP memory cell array 1026, and an OTP bit line of the OTP memory cell is provided to the sense amplifier.

[0111] The OTP control circuit 1028, instead of the shorted second variable resistance device of the OTP memory cell, generates a reference resistance and provides the reference resistance to the OTP bit line. The sense amplifier detects and amplifies a current flowing in the bit line of the normal memory cell and the OTP bit line of the OTP memory cell to which the reference resistance is connected, thereby improving a sense margin of the normal memory cell.

[0112] FIG. 13 is a block diagram of a server system including a magnetic memory device according to an embodiment of the inventive concept.

[0113] Referring to FIG. 13 , the server system 1100 includes a server 1110 and at least one storage device 1120 storing data for operating the server 1110.

[0114] The server 1110 includes an application communication module 1111, a data processing module 1112, an upgrade module 1113, a scheduling module 1114, a local resource module 1115, and a repair information module 1116. The application communication module 1111 is implemented to communicate with the server 1110 and a computing system connected to a network or to communicate between the server 1110 and the storage device 1120. The application communication module 1111 transmits data or information provided through a user interface to the data processing module 1112.

[0115] The data processing module 1112 is connected to the local resource module 1115. The local resource module 1115 provides a list of repair shops / dealers / technical information based on data or information connected to the server 1110. The upgrade module 1113 is interfaced with the data processing module 1112. The upgrade module 1113 upgrades firmware, reset codes, diagnostic system upgrades, or other information of electronic products based on data or information transmitted from the storage device 1120.

[0116] The scheduling module 1114 allows a user to make a real-time selection based on data or information input to the server 1110. The repair information module 1116 is interfaced with the data processing module 1112. The repair information module 1116 is used to provide repair-related information, such as audio, video, or document files, to a user. The data processing module 1112 encapsulates the relevant information based on information transmitted from the storage device 1120. The information is transmitted to the storage device 1120 or displayed to the user. The storage device 1120 can include a magnetic memory device 1122 as a data storage device.

[0117] The magnetic memory device 1122 includes a memory cell array 1124 and an OTP control circuit 1128, and the memory cell array 1124 includes a normal memory cell array 1125 and an OTP memory cell array 1126.

[0118] A normal memory cell including a first selection transistor and a first variable resistance device is arranged in the normal memory cell array 1125, and a bit line of the normal memory cell is provided to a sense amplifier. An OTP memory cell including a second selection transistor and a shorted second variable resistance device is arranged in the OTP memory cell array 1126, and an OTP bit line of the OTP memory cell is provided to the sense amplifier.

[0119] A shorted second variable resistance device of the OTP control circuit 1128, rather than the OTP storage cell, generates a reference resistance and provides the reference resistance to the OTP bit line. The sense amplifier detects and amplifies the current flowing in the OTP bit line of the OTP storage cell to which the bit line of the normal storage cell and the reference resistance are connected, thereby improving the readout margin of the normal storage cell.

[0120] The embodiments of the inventive concept described above are merely illustrative and various modifications and other embodiments can be made by those skilled in the art without departing from the spirit and scope of the inventive concept.

[0121] As is traditional in the field of the inventive concept, the embodiments are described in terms of functional blocks, units and / or modules, and are shown in the attached drawings as functional blocks, units and / or modules. Those skilled in the art will appreciate that these blocks, units and / or modules can be implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other technologies. In the case of the blocks, units and / or modules being implemented by microprocessors or similar, they can be programmed using software (e.g., microcode) to perform various functions described herein, and can optionally be driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented by a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit and / or module of the embodiments can be physically separated or can be combined in a single element, as can be desired in various embodiments. Moreover, the blocks, units and / or modules can be physically implemented as two or more blocks, units and / or modules which are physically separate and distinct from one another, or can be physically implemented as a single block, unit and / or module.

[0122] While the inventive concept has been described with reference to the embodiments thereof, it is to be understood that the inventive concept is not limited to the embodiments and constructions described above and illustrated herein, but instead is capable of numerous modifications and changes as will occur to those skilled in the art.

Claims

1. A magnetic memory device, the magnetic memory device comprising: a plurality of bit lines; a plurality of source lines arranged at different vertical levels from the plurality of bit lines; and a plurality of memory cells connected between the bit lines and the source lines and each including a memory element and a select transistor, wherein the plurality of memory cells includes first memory cells including first memory elements and second memory cells including second memory elements, each of the first memory elements and the second memory elements includes a magnetic tunnel junction including a pinned layer, a tunnel barrier layer, and a free layer, in some of the second memory elements, the magnetic tunnel junction has an irreversible resistance state due to insulating breakdown of the tunnel barrier layer, each of the second memory elements includes a first dummy element, a second dummy element, and an active element between the first dummy element and the second dummy element, and a pitch between the first dummy element and the active element in a first horizontal direction is substantially equal to a pitch between the second dummy element and the active element. a pitch between the active element and the second dummy element in the first horizontal direction is substantially equal to a pitch between the first memory elements in the first horizontal direction.

2. The magnetic memory device of claim 1, wherein, a maximum length of the active element in the first horizontal direction is less than a maximum length among lengths of the first memory elements in the first horizontal direction.

3. The magnetic memory device of claim 1, wherein, a maximum length of the first dummy element in the first horizontal direction is less than the maximum length among the lengths of the first memory elements in the first horizontal direction.

4. The magnetic memory device of claim 3, wherein, a maximum length of the first dummy element in the first horizontal direction is greater than the maximum length among the lengths of the first memory elements in the first horizontal direction.

5. The magnetic memory device of claim 3, wherein, a maximum length of the active element in the first horizontal direction ranges from 10 nm to 20 nm.

6. The magnetic memory device of claim 3, wherein, 7. The magnetic memory device of claim 1, further comprising word lines extending in the first horizontal direction, the source lines are electrically connected to the bit lines, respectively. wherein the first dummy element is not connected to the source lines, and 8. The magnetic memory device of claim 1, wherein, the active element is connected to the source lines through a metal wiring. the first memory cells constitute a normal memory cell array to be programmed multiple times, and 9. The magnetic memory device of claim 1, wherein, the second memory cells constitute a one-time programmable memory cell array to be programmed once. a number of select transistors per unit memory cell is greater in the second memory cells than in the first memory cells.

10. The magnetic memory device of claim 9, wherein, 11. A magnetic memory device, the magnetic memory device comprising: a substrate having a first region and a second region; a plurality of first memory elements and a plurality of second memory elements each constituting a memory cell and spaced apart from each other in a first horizontal direction in the first region; a first dummy element, a second dummy element, and an active element between the first dummy element and the second dummy element, and a pitch between the first dummy element and the active element in a first horizontal direction is substantially equal to a pitch between the second dummy element and the active element. an inter-wiring insulating layer located in the second region and having at least a portion located at substantially the same vertical height as the first memory device and the second memory device; a cap layer pattern covering side walls of the plurality of first memory devices and side walls of the plurality of second memory devices; and a buried layer pattern covering the cap layer pattern and filling a portion of each of spaces between the plurality of first memory devices and spaces between the plurality of second memory devices in the first region, wherein each of the plurality of first memory devices and the plurality of second memory devices includes a magnetic tunnel junction including a pinned layer, a tunnel barrier layer, and a free layer, in some of the plurality of second memory devices, the magnetic tunnel junction has an irreversible resistance state due to insulating breakdown of the tunnel barrier layer, each of the second memory devices includes a first dummy device, a second dummy device, and an active device located between the first dummy device and the second dummy device, a pitch between the first dummy device and the active device in the first horizontal direction is substantially equal to a pitch between the second dummy device and the active device, and a pitch between the active device and the first dummy device in the first horizontal direction is substantially equal to a pitch between the plurality of first memory devices in the first horizontal direction.

12. The magnetic memory device of claim 11, wherein, a maximum length of the active device in the first horizontal direction is less than a maximum length among lengths of the first memory devices in the first horizontal direction.

13. The magnetic memory device of claim 12, wherein, a maximum length of the first dummy device in the first horizontal direction is less than a maximum length among lengths of the first memory devices in the first horizontal direction.

14. The magnetic memory device of claim 12, wherein, a maximum length of the first dummy device in the first horizontal direction is greater than a maximum length among lengths of the first memory devices in the first horizontal direction.

15. The magnetic memory device of claim 11, further comprising a word line extending in the first horizontal direction, wherein the memory cell further comprises a select transistor, the memory cell is connected between a bit line and a source line, and the source line is located at a different vertical height than the bit line.

16. The magnetic memory device of claim 11, wherein, at least one of the magnetic tunnel junction or select transistor constituting the first dummy device or the second dummy device is not connected to a metal wiring.

17. The magnetic memory device of claim 16, wherein, the metal wiring includes: a plurality of wiring lines electrically connected to the select transistor; and a plurality of wiring contacts located on the plurality of wiring lines, the active device is electrically connected to at least three of the plurality of wiring contacts, and each of the plurality of first memory devices is electrically connected to one of the plurality of wiring contacts.

18. The magnetic memory device of claim 11, wherein, the first region includes a cell array region and the second region includes a peripheral circuit region.

19. A magnetic memory device, comprising: a substrate having a cell array region and a peripheral circuit region; a separation insulating layer located in the cell array region and the peripheral circuit region; a plurality of first memory devices and a plurality of second memory devices located on the separation insulating layer in the cell array region, wherein the plurality of first memory devices and the plurality of second memory devices constitute a plurality of memory cells and are spaced apart from each other in a horizontal direction; an inter-wiring insulating layer located in the peripheral circuit region and having at least a portion located at substantially the same vertical height as the plurality of first memory devices and the plurality of second memory devices; a cap layer pattern covering sidewalls of the plurality of first memory devices and sidewalls of the plurality of second memory devices; and a buried layer pattern covering the cap layer pattern and filling a portion of each of spaces between the plurality of first memory devices and spaces between the plurality of second memory devices in the cell array region, wherein each of the plurality of first memory devices and the plurality of second memory devices includes a magnetic tunnel junction including a pinned layer, a tunnel barrier layer, and a free layer, in some of the plurality of second memory devices, the magnetic tunnel junction has an irreversible resistance state due to insulating breakdown of the tunnel barrier layer, each of the plurality of second memory devices includes a first dummy device, a second dummy device, and an active device located between the first dummy device and the second dummy device, a pitch between the first dummy device and the active device in a first horizontal direction is substantially equal to a pitch between the second dummy device and the active device, a pitch between the active device and the first dummy device in the first horizontal direction is substantially equal to a pitch between the plurality of first memory devices in the first horizontal direction, a maximum length of the active device in the first horizontal direction is less than a maximum length of the first memory device in the first horizontal direction, and a maximum length of the first dummy device in the first horizontal direction is less than a maximum length of the first memory device in the first horizontal direction.

20. The magnetic memory device of claim 19, wherein, at least one of the magnetic tunnel junction or a select transistor constituting the first dummy device or the second dummy device is not connected to a metal wiring, the metal wiring includes a plurality of wiring lines electrically connected to the select transistor and a plurality of wiring contacts located on the plurality of wiring lines, the active device is electrically connected to at least three of the plurality of wiring contacts, and each of the plurality of first memory devices is electrically connected to one of the plurality of wiring contacts.

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