Bidirectional silicon controlled rectifier chip, preparation method thereof and semiconductor device

Abstract

The invention discloses a bidirectional silicon controlled rectifier chip, a preparation method thereof and a semiconductor device, and the preparation method comprises the steps: selecting an N-type gas-doped material sheet as a substrate, carrying out the N-type epitaxial layer growth processing of the substrate based on a chemical vapor deposition method, and obtaining a substrate structure comprising an N-type epitaxial layer; performing multi-step diffusion doping processing on the substrate structure to form a mutually isolated multi-well structure which comprises a P-type well, a deep P-type well and a first N-type well; performing ion implantation processing on the deep P-type well in the multi-well structure to obtain a doping optimization structure; and insulating layer deposition processing is carried out on the doping optimization structure, and then a conductive layer is covered to obtain the bidirectional silicon controlled rectifier chip. According to the invention, the performance uniformity and reliability of the bidirectional silicon controlled rectifier chip are remarkably improved, and the technical problem that the consistency of the off-state repetitive peak voltage (VDRM) and the gate trigger current (IGT) is insufficient due to the poor resistivity uniformity of the gas-doped material sheet in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a TRIAC chip, a preparation method thereof, and a semiconductor device. BACKGROUND

[0002] TRIAC (Triode for Alternating Current) is a semiconductor device applied to AC control, and its key performance parameters include VDRM (Voltage Drain Repeat Peak) and IGT (Gate Trigger Current). VDRM determines the maximum voltage that the device can withstand in the off state, and IGT affects the sensitivity and control accuracy of the device triggering conduction. In the prior art, the existing TRIAC chip forms a multi-well structure such as a P-type well and an N-type well through diffusion doping or ion implantation process to build the functional area of the device. These processes achieve the required electrical characteristics by controlling the doping concentration and distribution. However, due to the limitation of the intrinsic characteristics of the gas-doped material sheet, its resistivity uniformity is poor, which can be about 30%, which directly affects the stability and consistency of VDRM and IGT, making it difficult to meet the demand of high reliability application for the uniformity of device performance.

[0003] In the preparation process of the existing TRIAC chip, the VDRM and the resistivity of the substrate material present an open parabolic relationship, that is, under certain process conditions, there is an optimal resistivity that makes the VDRM reach the maximum value. However, the material resistivity not only affects the VDRM, but also has a significant impact on the IGT. The non-uniformity of the resistivity will cause large deviations in the VDRM and IGT values of different chips, thereby affecting the triggering characteristics and voltage withstand capability of the device. This non-uniformity is caused by the preparation process of the gas-doped material sheet, and the doping process is difficult to control accurately, resulting in uneven resistivity distribution within the wafer and between wafers.

[0004] Therefore, how to effectively improve the uniformity of the resistivity of the substrate material in the preparation process to improve the consistency of the VDRM and IGT of the TRIAC chip has become a technical problem to be solved. SUMMARY

[0005] The present application aims to provide a TRIAC chip, a preparation method thereof, and a semiconductor device, to solve the technical problem of poor resistivity uniformity of the substrate material in the prior art affecting the consistency of VDRM and IGT. To achieve this goal, the following technical solutions are adopted: A preparation method of a TRIAC chip, comprising: selecting an N-type gas-doped material sheet as a substrate, and performing N-type epitaxial layer growth treatment on the substrate based on a chemical vapor deposition method to obtain a substrate structure comprising an N-type epitaxial layer; The substrate structure is subjected to a multi-step diffusion doping process to form a plurality of isolated well structures, wherein the plurality of well structures comprises a P-type well, a deep P-type well and a first N-type well; The deep P-type well in the plurality of well structures is subjected to an ion implantation process to obtain a doping optimization structure; After the deposition of an insulating layer on the doping optimization structure and the covering of a conductive layer, the thyristor chip is obtained.

[0006] Further, the resistivity of the N-type gas-doped material sheet ranges from 120 to 180 Ω·cm.

[0007] Further, the resistivity of the N-type epitaxial layer ranges from 150 to 153 Ω·cm.

[0008] Further, the step of selecting the N-type gas-doped material sheet as the substrate comprises: Ammonia, hydrogen peroxide and deionized water are configured in a ratio of 1:1:5 to obtain a first mixed solution, and hydrofluoric acid and deionized water are configured in a ratio of 1:10 to obtain a second mixed solution; The N-type gas-doped material sheet is placed in the first mixed solution for cleaning treatment at 70-80 degrees Celsius, and the cleaning time is 5-10 minutes to obtain a cleaned substrate; The cleaned substrate is placed in the second mixed solution for secondary cleaning treatment, and the cleaning time is 5-10 minutes to obtain the substrate.

[0009] Further, the step of growing an N-type epitaxial layer on the substrate based on the chemical vapor deposition method to obtain a substrate structure comprising an N-type epitaxial layer comprises: The substrate is subjected to high-temperature preheating treatment under high-temperature conditions, and hydrogen gas is introduced as a carrier gas for 5-10 minutes to obtain a heat-stable substrate; Trichlorosilane is used as a silicon source, phosphine is used as an N-type doping source, and hydrogen gas is used as a carrier gas to deposit an initial N-type epitaxial layer on the heat-stable substrate by the chemical vapor deposition method to obtain a preliminary epitaxial structure; The flow rate of phosphine is adjusted to optimize the doping of the preliminary epitaxial structure to obtain a uniformly doped epitaxial layer; The uniformly doped epitaxial layer is subjected to annealing treatment in an inert gas atmosphere to obtain a substrate structure comprising an N-type epitaxial layer.

[0010] Further, the step of subjecting the substrate structure to a multi-step diffusion doping process to form a plurality of isolated well structures, wherein the plurality of well structures comprises a P-type well, a deep P-type well and a first N-type well comprises: The substrate structure is subjected to a low-temperature oxidation process based on a hydrofluoric acid solution to form a silicon oxide layer; etching the silicon oxide layer to define a plurality of P-type well regions, to obtain a substrate structure with a P-type well mask; performing boron diffusion treatment on the substrate structure with the P-type well mask, to obtain a substrate structure with P-type wells; performing second oxidation and photolithography treatment on the surface of the substrate structure with P-type wells, to obtain a substrate structure with a first N-type well mask; performing phosphorus diffusion treatment on the substrate structure with the first N-type well mask, to obtain a substrate structure with P-type wells and first N-type wells; performing deep boron diffusion and annealing treatment on the substrate structure with P-type wells and first N-type wells, to obtain a plurality of well structures isolated from each other.

[0011] Further, the deep P-type well includes a first deep P-type well and a second deep P-type well, and the step of performing ion implantation treatment on the deep P-type well in the plurality of well structures to obtain a doping optimization structure includes: performing photolithography treatment on the first deep P-type well and the second deep P-type well, to obtain a deep P-type well surface with a preset pattern; according to the deep P-type well surface, performing first phosphorus ion implantation treatment on the first deep P-type well, with an energy of 100-150 keV, a dose of 10 14 ~10 15 cm -2 , and a doping concentration of 10 17 ~10 18 cm -3 , to implant a second N-type well structure on the upper part of the first deep P-type well; according to the deep P-type well surface, performing second phosphorus ion implantation treatment on the second deep P-type well, with a dose of 10 15 ~10 16 cm -2 , and a doping concentration of 10 19 ~10 20 cm -3 , to implant a third N-type well structure on the upper part of the second deep P-type well; performing high-temperature annealing treatment on the second N-type well structure and the third N-type well structure, to obtain the doping optimization structure.

[0012] Further, the step of performing insulation layer deposition treatment on the doping optimization structure and then covering a conductive layer to obtain the bidirectional thyristor chip includes: performing low-temperature chemical vapor deposition treatment on the doping optimization structure to deposit a silicon oxide insulation layer with a thickness of 1-2 μm, to obtain an insulation layer structure covering the doping optimization structure; Coating and patterning the insulating layer structure to form a lead hole pattern corresponding to the upper part of the second N-type well and the third N-type well, to obtain a photoresist mask structure with a lead hole pattern; Performing a reactive ion etching process on the photoresist mask structure to form a lead hole on the insulating layer structure, to expose the connection area of the second N-type well and the third N-type well, to obtain an insulating layer structure with a lead hole; Performing a sputtering deposition process on the insulating layer structure with a lead hole to deposit an aluminum-silicon alloy conductive layer, to form a metal layer structure covering the lead hole and the insulating layer, to obtain the triac chip.

[0013] The application also discloses a triac chip prepared by the triac chip preparation method of any one of the above. An N-type gas-doped material substrate; An N-type epitaxial layer arranged on the N-type gas-doped material substrate; A multi-well structure including a shallow P-type well, a middle P-type well, a deep P-type well and a first N-type well, each well of the multi-well structure being separated by the N-type epitaxial layer; wherein the deep P-type well includes a first deep P-type well and a second deep P-type well, the first deep P-type well being implanted with a second N-type well on the upper part, and the second deep P-type well being implanted with a third N-type well on the upper part; An insulating layer covering the multi-well structure and being provided with lead holes respectively exposing the first N-type well, the middle P-type well, the second N-type well and the third N-type well; A conductive layer covering the insulating layer and the lead holes and being electrically connected with the first N-type well, the middle P-type well, the second N-type well and the third N-type well.

[0014] The application also discloses a semiconductor device including the triac chip and an external circuit electrically connected with the triac chip, the external circuit being used for controlling the turn-on and turn-off of the triac chip.

[0015] Compared with the prior art, the application has the following beneficial effects: The bidirectional thyristor chip and the preparation method thereof of the present application, by selecting an N-type gas-doped material wafer as a substrate, combining the growth of an N-type epitaxial layer, multi-step diffusion doping to form a multi-well structure, ion implantation optimization of a deep P-type well, and deposition processes of an insulating layer and a conductive layer, significantly improve the performance uniformity and reliability of the bidirectional thyristor chip, solving the technical problem of insufficient consistency of the off-state repetitive peak voltage (VDRM) and gate trigger current (IGT) caused by poor resistivity uniformity of the gas-doped material wafer in the prior art. By growing an N-type epitaxial layer on the N-type gas-doped material substrate, the present application effectively improves the uniformity of the substrate resistivity, providing a stable base for subsequent doping processes; the multi-well structure including a shallow P-type well, a middle P-type well, a deep P-type well, and a first N-type well formed by the multi-step diffusion doping process further optimizes the accurate control and distribution uniformity of the doping concentration; for the ion implantation process of the deep P-type well, by implanting a second N-type well and a third N-type well on the first deep P-type well and the second deep P-type well respectively, the electrical properties of the well structure are accurately adjusted, significantly improving the stability of VDRM and the trigger consistency of IGT; finally, through the deposition of the insulating layer and the conductive layer and the design of the lead hole, the reliable electrical connection of the multi-well structure and the conductive layer is realized, further enhancing the overall performance of the device.

[0016] Compared with the prior art, the present application improves the uniformity of VDRM and IGT of the chip without significantly increasing the production cost, significantly reduces the performance deviation within and between wafers, thereby improving the performance of the bidirectional thyristor chip in high-reliability application scenarios, and meeting the demand for high-power and high-precision alternating current control. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the conditions that can be implemented by the present application, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0019] Figure 1 The overall steps of the bidirectional thyristor chip preparation method are shown in the figure; Figure 2It is a schematic diagram of a bidirectional thyristor chip structure. Figure 3 It is a schematic diagram of a cross-sectional structure in an embodiment of a bidirectional thyristor chip.

[0020] In the figure, the reference numerals are: 1, N-type gas-doped material substrate; 2, N-type epitaxial layer; 31, shallow P-type well; 32, middle P-type well; 33, first deep P-type well; 34, second deep P-type well; 41, first N-type well; 42, second N-type well; 43, third N-type well. DETAILED DESCRIPTION

[0021] In order to make the purposes, features and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described below are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0022] In the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0023] The technical solutions of the present application will be further described below in conjunction with the drawings and through specific embodiments.

[0024] Reference Figure 1 The present application provides a bidirectional thyristor chip preparation method, comprising: S1: selecting an N-type gas-doped material wafer as a substrate, performing N-type epitaxial layer growth treatment on the substrate based on a chemical vapor deposition method, to obtain a substrate structure comprising an N-type epitaxial layer; In step S1, an N-type gas-doped material wafer is selected as a substrate, and an N-type epitaxial layer is grown on the substrate based on a chemical vapor deposition (CVD) method to obtain a substrate structure including the N-type epitaxial layer. In a specific implementation, a silicon-based N-type gas-doped material wafer can be selected as the substrate. This material is doped with N-type impurities (such as phosphorus or arsenic) through a gas doping process to form a semiconductor substrate with a certain resistivity. However, the resistivity uniformity of the gas-doped material wafer can be poor (about 30%), which can lead to inconsistent performance of the chip. Therefore, an N-type epitaxial layer is grown on the substrate by a chemical vapor deposition method. This process introduces a gas containing N-type dopant atoms (such as phosphine) into the reaction chamber at high temperature, so that the gas is deposited on the surface of the substrate and forms an N-type epitaxial layer with uniform crystal structure. The thickness of the epitaxial layer can be controlled to be 5-20 microns, depending on the design requirements of the chip. The growth of the epitaxial layer improves the flatness and crystal quality of the substrate surface, and improves the uniformity of the resistivity, which helps to reduce the resistivity deviation within and between wafers.

[0025] S2: performing multi-step diffusion doping treatment on the substrate structure to form a plurality of isolated well structures, wherein the plurality of well structures include a P-type well, a deep P-type well, and a first N-type well; In step S2, the substrate structure is subjected to multi-step diffusion doping treatment to form a plurality of isolated well structures. The multi-step diffusion doping can be completed by a thermal diffusion process. First, photoresist is coated on the surface of the substrate structure, and a specific mask pattern is formed by photolithography to define the position and shape of the doped region. Then, a P-type dopant (such as boron) is introduced into the N-type epitaxial layer by a high-temperature diffusion furnace to form a P-type well and a deep P-type well. The P-type well can be relatively shallow and used to build a functional area of the device, while the deep P-type well is relatively deep to enhance the voltage bearing capacity of the device. Subsequently, an N-type dopant (such as phosphorus) is introduced by a similar mask and diffusion process to form a first N-type well. These well structures are separated from each other by the isolation effect of the epitaxial layer, so that the electrical properties are independent. The key of the multi-step diffusion is to accurately control the concentration and diffusion depth of the dopant. Complex but ordered doped regions can be formed in the substrate structure, which together constitute the PNPN structure of the bidirectional thyristor chip, thereby realizing the bidirectional conduction function. At the same time, the multi-step diffusion process improves the uniformity of the doping distribution by controlling the doping process in steps, and reduces the performance deviation caused by uneven doping.

[0026] It is worth noting that the P-type well can also be divided into shallow P-type well and middle P-type well, the depth of the P-type well can be controlled by adjusting the concentration of the dopant and the diffusion time, and the middle P-type well is used to build the trigger area of the device. In another embodiment, a shallow P-type well is arranged between the middle P-type well and the deep P-type well, which can be used to isolate the electrical characteristics between the deep P-type well and the P-type well, prevent the formation of parasitic PNP or NPN bipolar transistors, adjust the local potential distribution, and reduce the cross talk between devices.

[0027] S3: ion implantation treatment is performed on the deep P-type well in the multi-well structure to obtain a doped optimization structure; In step S3, ion implantation treatment is performed on the deep P-type well in the multi-well structure to obtain a doped optimization structure, and the electrical characteristics of the deep P-type well are optimized to improve the trigger sensitivity and voltage bearing capacity of the chip. In specific implementation, the ion implantation process implants N-type dopants (such as phosphorus or arsenic) with high energy into the upper region of the deep P-type well by ion implantation equipment with accurate dose and energy, to form a local N-type doped region, such as a second N-type well or a third N-type well, thereby optimizing the electrical characteristics of the deep P-type well. For example, by implanting a third N-type well on the upper part of the deep P-type well, the gate trigger current (IGT) can be reduced, the trigger sensitivity can be improved, and the voltage isolation capability of the deep P-type well can be enhanced, further improving the stability of VDRM. After ion implantation, annealing treatment can be required to repair lattice damage and activate the dopant. This annealing process is carried out at a temperature of 900-1100°C to activate the dopant atoms effectively, thereby forming a doped optimization structure with optimized electrical performance.

[0028] S4: After the deposition of the insulating layer on the doped optimization structure and covering the conductive layer, the bidirectional thyristor chip is obtained.

[0029] In step S4, after the deposition of the insulating layer on the doped optimization structure, a conductive layer is covered to obtain a triac chip. The encapsulation and electrical connection of the chip are completed. In specific implementation, the deposition of the insulating layer can adopt a chemical vapor deposition method or a plasma enhanced chemical vapor deposition method (PECVD). A layer of insulating material such as silicon dioxide (SiO2) or silicon nitride (Si3N4) is deposited on the surface of the doped optimization structure, and the thickness is generally between 0.5 and 2 microns. The insulating layer not only plays an electrical isolation role, but also protects the doped structure below from the influence of the external environment. Then, through a photoetching and etching process, lead holes are formed on the insulating layer. These lead holes expose specific areas (such as the first N-type well, the P-type well, etc.) in the multi-well structure, so as to be electrically connected with the conductive layer. The deposition of the conductive layer can adopt a physical vapor deposition method (PVD) or a sputtering process. Metal materials (such as aluminum or copper) are covered in the insulating layer and the lead holes to form an electrical connection with the multi-well structure. The thickness of the conductive layer can be 1-3 microns, so as to have good conductivity and reliability, so that the electrodes of the chip can effectively transmit current and be connected with external circuits, thereby realizing the AC control function of the triac.

[0030] In summary, the present application improves the uniformity of the substrate by selecting an N-type gas-doped material sheet and growing an N-type epitaxial layer. The ordered multi-well structure is formed by multi-step diffusion doping. The electrical properties of the deep P-type well are optimized by ion implantation. The encapsulation and connection of the chip are completed by the deposition of the insulating layer and the conductive layer. The high-performance preparation of the triac chip is realized. The consistency of VDRM and IGT is significantly improved, and the demand for high-reliability applications is met.

[0031] In one embodiment, the resistivity of the N-type gas-doped material sheet ranges from 120 to 180 Ω·cm. The resistivity of the N-type epitaxial layer ranges from 150 to 153 Ω·cm.

[0032] In the above embodiment, the N-type gas-doped material sheet is selected as the substrate, and the resistivity range is 120-180 Ω·cm. In actual implementation, a silicon-based material can be selected as the substrate, and an N-type gas-doped material sheet is prepared through a gas-phase doping process (for example, a gas containing phosphorus or arsenic is introduced into a silicon melt) to achieve the specified resistivity range. The resistivity range of 120-180 Ω·cm indicates that the substrate has a relatively high resistivity, which helps to improve the off-state repetitive peak voltage (VDRM) of the bidirectional thyristor chip. For example, by precisely adjusting the amount of phosphine (PH3) or arsine (AsH3) introduced and combining a high-temperature annealing process, the doping atoms are uniformly distributed in the silicon crystal, so that the resistivity is controlled within the range of 120-180 Ω·cm. Based on the chemical vapor deposition (CVD) method, an N-type epitaxial layer is grown on the N-type gas-doped material sheet, and the resistivity range of the N-type epitaxial layer is 150-153 Ω·cm. The epitaxial growth improves the crystal quality and electrical uniformity of the substrate. In actual implementation, the chemical vapor deposition is performed in a special epitaxial growth device, such as a reduced pressure chemical vapor deposition (RPCVD) system. The substrate is placed in a high-temperature reaction chamber (the temperature can be 1000-1200°C), and a silicon source gas (such as silicon tetrachloride SiCl4 or silane SiH4) and an N-type doping gas (such as phosphine PH3) are introduced. The silicon atoms and doping atoms are orderly deposited and grown into a single-crystal N-type epitaxial layer on the substrate surface. To achieve a resistivity of 150-153 Ω·cm, the concentration and flow rate of the doping gas can be adjusted, for example, the flow rate of phosphine is controlled within a specific range by a mass flow controller (MFC), and the pressure and temperature in the reaction chamber are monitored to ensure uniform doping of the doping atoms. The resistivity range of 150-153 Ω·cm is more narrow than the resistivity range of 120-180 Ω·cm of the substrate, indicating that the epitaxial layer has a higher resistivity uniformity. Uniform resistivity distribution can reduce the performance deviation between chips, such as the fluctuation of VDRM and gate trigger current (IGT).

[0033] In one embodiment, the step of selecting an N-type gas-doped material sheet as a substrate includes: The ammonia, hydrogen peroxide, and deionized water are configured in a ratio of 1:1:5 to obtain a first mixed solution, and the hydrofluoric acid and deionized water are configured in a ratio of 1:10 to obtain a second mixed solution. The N-type gas-doped material sheet is placed in the first mixed solution for cleaning treatment at 70-80 degrees Celsius, and the cleaning time is 5-10 minutes to obtain a cleaned substrate. The cleaned substrate is placed in the second mixed solution for secondary cleaning treatment, and the cleaning time is 5-10 minutes to obtain the substrate.

[0034] In the above embodiment, the ammonia water, hydrogen peroxide and deionized water are mixed in a ratio of 1:1:5 to remove organic contaminants, particles and part of metal impurities on the surface of the substrate. In actual implementation, the ammonia water (NH4OH) provides an alkaline environment, can react with organic matter and decompose it, the hydrogen peroxide (H2O2) can oxidize the particle contaminants and make them loose as a strong oxidizing agent, and the deionized water plays a dilution role to make the chemical activity of the solution moderate to avoid causing excessive corrosion to the surface of the substrate. The ratio of 1:1:5 is optimized to ensure the cleaning effect and avoid the roughening of the silicon surface caused by the high concentration of the solution. In actual operation, high-purity ammonia water (the concentration can be 28-30%) and hydrogen peroxide (the concentration can be 30-35%) are used to prepare the first mixed solution. The N-type gas-doped material sheet is placed in the first mixed solution for cleaning at a temperature of 70-80 degrees Celsius, and the cleaning time is 5-10 minutes. The cleaning effect is optimized by controlling the temperature and time. In actual implementation, the first mixed solution can be heated to 70-80 degrees Celsius by using a constant-temperature water bath or a special cleaning equipment (such as a wet cleaning tank) to improve the chemical reaction rate of the solution, for example, the oxidation ability of hydrogen peroxide and the dissolution ability of ammonia water, so as to effectively remove the organic matter and particles on the surface of the substrate. During the cleaning process, the N-type gas-doped material sheet can be fixed by a wafer clamp and completely immersed in the first mixed solution. In order to make the cleaning uniform, slight stirring or ultrasonic assisted cleaning technology can be used to promote the full contact of the solution with the surface of the substrate. The cleaning time is controlled in the range of 5-10 minutes. This time range is optimized. Too short time may lead to incomplete cleaning, and too long time may increase the surface roughness or cause unnecessary chemical corrosion. After cleaning, the substrate is rinsed with deionized water to remove the residual solution and avoid the influence of alkaline residues on subsequent processes. Through this step, a preliminarily cleaned substrate can be obtained, and the organic contaminants and particles on the surface of the substrate are significantly reduced. Hydrofluoric acid (HF) is mixed with deionized water in a ratio of 1:10 to obtain a solution for secondary cleaning. This solution can be called dilute hydrofluoric acid (DHF) solution, which mainly removes the natural oxide layer (SiO2) and other inorganic impurities on the surface of the N-type gas-doped material sheet. In actual implementation, high-purity electronic-grade hydrofluoric acid (the concentration is 49% or higher) can be selected and mixed with high-purity deionized water in a ratio of 1:10. For example, 10 mL of hydrofluoric acid is mixed with 100 mL of deionized water to obtain the diluted hydrofluoric acid solution. The ratio of 1:10 makes the concentration of hydrofluoric acid low enough to avoid excessive corrosion to the silicon substrate, while effectively dissolving the surface oxide layer. The preparation process also needs to be carried out in a clean room environment, and the solution is stored in a corrosion-resistant container (such as a polytetrafluoroethylene container) to prevent the container material from dissolving impurities.The cleaned substrate is placed in a second mixed solution for secondary cleaning, and the cleaning time is 5-10 minutes, and the substrate surface quality is optimized. In actual implementation, the substrate after preliminary cleaning can be immersed in a diluted hydrofluoric acid solution. Hydrofluoric acid reacts with the natural oxide layer on the silicon surface to generate water-soluble hexafluorosilicic acid (H2SiF6), thereby effectively removing the oxide layer. At the same time, the diluted hydrofluoric acid can also remove part of the metal ions and inorganic impurities, further improving the cleanliness of the substrate surface. The cleaning time is controlled within 5-10 minutes, which can completely remove the oxide layer while avoiding excessive surface hydrophobicity or microscopic corrosion caused by prolonged immersion. During the cleaning process, the uniformity of cleaning can be ensured by slightly shaking the wafer clamp or circulating the solution. After cleaning, the substrate is rinsed with a large amount of deionized water to remove residual hydrofluoric acid, and the surface moisture is removed by nitrogen blowing or spin-drying technology to obtain a clean N-type gas-doped material wafer substrate.

[0035] In an embodiment, the step of growing an N-type epitaxial layer on the substrate by chemical vapor deposition includes: The substrate is placed in a high-temperature condition for high-temperature preheating treatment, and hydrogen gas is introduced as a carrier gas for 5-10 minutes to obtain a thermally stable substrate; Trichlorosilane is used as a silicon source, phosphine is used as an N-type doping source, and hydrogen gas is used as a carrier gas to deposit an initial N-type epitaxial layer on the thermally stable substrate by chemical vapor deposition to obtain a preliminary epitaxial structure; The flow rate of phosphine is adjusted to optimize the doping of the preliminary epitaxial structure to obtain a uniformly doped epitaxial layer; The uniformly doped epitaxial layer is annealed in an inert gas atmosphere to obtain a substrate structure including an N-type epitaxial layer.

[0036] In this embodiment, the substrate is placed in a high temperature condition for high temperature pre-treatment, and the residual trace impurities and defects on the surface of the substrate are removed by high temperature annealing, and at the same time, the surface of the substrate reaches a thermodynamic stable state. Specifically, the cleaned N-type gas-doped material substrate can be placed in a chemical vapor deposition device (such as a horizontal or vertical CVD reaction chamber), and the temperature of the reaction chamber can be raised to 1000-1200°C to remove the trace oxides and organic residues on the surface of the substrate, and at the same time, promote the rearrangement of surface atoms and enhance the flatness of the crystal surface. During the preheating process, high-purity hydrogen gas is introduced as a carrier gas, and the hydrogen flow is controlled at 10-50 standard liters per minute (SLM) to form a reducing atmosphere in the reaction chamber to prevent oxidation of the substrate surface. At the same time, hydrogen can also carry away volatile impurities. The preheating time is controlled at 5-10 minutes, and the substrate surface reaches a thermal stable state, and the lattice structure is more regular. Trichlorosilane (SiHCl3) is used as the silicon source, phosphine (PH3) is used as the N-type doping source, and hydrogen is used as the carrier gas to deposit an initial N-type epitaxial layer on the thermal stable substrate by chemical vapor deposition. A layer of monocrystalline silicon film is deposited on the surface of the substrate by gas phase reaction, and N-type doping is introduced to form conductive properties. Specifically, the CVD reaction chamber is maintained at a high temperature state (usually 1000-1150°C) to promote the thermal decomposition of trichlorosilane. Trichlorosilane decomposes to form silicon atoms at high temperature. These silicon atoms deposit on the substrate surface and grow monocrystalline according to the crystal structure of the substrate to form an epitaxial layer. At the same time, phosphine as an N-type doping source releases phosphorus atoms by thermal decomposition, which are doped into the silicon lattice during growth to form N-type conductive properties. Hydrogen is used as a carrier gas with a flow rate of 20-100 SLM to transport trichlorosilane and phosphine to the reaction chamber and maintain stable pressure in the reaction chamber (usually 100-760 Torr). The flow rate of trichlorosilane is controlled at 0.5-5 g / min, and the flow rate of phosphine is adjusted according to the required doping concentration, which can be 10-100 SCCM. The deposition time is determined according to the target epitaxial layer thickness, usually several minutes to several tens of minutes, to obtain an initial N-type epitaxial layer.The flow rate of phosphine is adjusted for doping optimization of the preliminary epitaxial structure. By controlling the input amount of the doping source, the distribution of phosphorus atoms in the epitaxial layer is optimized to improve the uniformity of the doping concentration and the stability of the electrical properties. In specific implementation, after the initial epitaxial layer deposition is completed, the high temperature and hydrogen carrier atmosphere of the reaction chamber are maintained unchanged, and the flow rate of phosphine is gradually adjusted by a mass flow controller (MFC), for example, gradually reduced or increased from the initial 50 SCCM to the target value (such as 20-80 SCCM). This adjustment process is based on feedback control of real-time monitoring data (such as in-situ resistivity measurement or doping concentration analysis) to make the doping concentration uniformly distributed in the entire epitaxial layer. While adjusting the flow rate of phosphine, the flow rate of trichlorosilane and the deposition rate can be appropriately optimized to balance the growth rate and doping efficiency, for example, to reduce the growth rate to improve the diffusion uniformity of the doping atoms. This optimization process usually lasts for several minutes until the doping concentration of the epitaxial layer reaches the design requirement (for example, 10. 15 ~10 17 The uniformly doped epitaxial layer is annealed in an inert gas atmosphere to repair crystal defects in the epitaxial layer, activate the doping atoms, and further optimize the crystal structure. In specific implementation, the deposited substrate structure is placed in an annealing furnace or CVD reaction chamber, and an inert gas (such as high-purity nitrogen or argon, with a flow rate of 5-20 SLM) is introduced to avoid oxidation or other chemical reactions. The annealing temperature is usually controlled at 900-1100 degrees Celsius, and the annealing time is 10-30 minutes. This temperature and time range can effectively activate the doped phosphorus atoms to occupy the substitution sites in the silicon lattice, while repairing the point defects or dislocations that may be introduced during growth. After annealing, the substrate is slowly cooled (for example, at a rate of 5-10 degrees Celsius per minute) to room temperature to avoid crystal damage caused by thermal stress, and a substrate structure with a high-quality N-type epitaxial layer is obtained.

[0037] In an embodiment, the multi-step diffusion doping process of the substrate structure to form a multi-well structure isolated from each other includes the steps of forming a P-type well, a deep P-type well, and a first N-type well. The substrate structure is subjected to low-temperature oxidation treatment based on a hydrofluoric acid solution to form a silicon oxide layer. The silicon oxide layer is etched to define a plurality of P-type well regions, obtaining a substrate structure with a P-type well mask. The substrate structure with a P-type well mask is subjected to boron diffusion treatment to obtain a substrate structure containing a P-type well. The surface of the substrate structure containing a P-type well is subjected to a second oxidation and photolithography process to obtain a substrate structure with a first N-type well mask. The substrate structure with a first N-type well mask is subjected to phosphorus diffusion treatment to obtain a substrate structure containing a P-type well and a first N-type well. The substrate structure containing P-type well and first N-type well is subjected to deep boron diffusion and annealing treatment to obtain a multi-well structure isolated from each other.

[0038] In the embodiment, the substrate structure is subjected to low-temperature oxidation treatment based on hydrofluoric acid solution. The silicon substrate of the N-type epitaxial layer is soaked in diluted hydrofluoric acid (HF) solution for 1-2 minutes to remove the surface natural oxide layer and organic impurities. A silicon oxide layer with a thickness of 50-200 nanometers is grown on the substrate surface through a low-temperature thermal oxidation process. The low-temperature oxidation can effectively reduce the damage of thermal stress to the crystal structure of the substrate, and the generated silicon oxide layer has good compactness and uniformity. The oxidation process is carried out in an oxygen or water vapor atmosphere for 30-60 minutes to ensure that the silicon oxide layer has a moderate thickness and effectively blocks the diffusion of doping atoms. The silicon oxide layer is subjected to etching treatment to define a plurality of P-type well regions. A layer of photoresist is coated on the surface of the silicon oxide layer. The photoresist pattern covering the P-type well region is formed by exposing and developing the photoresist using a pre-designed mask through a photoetching machine. Then, the silicon oxide regions not protected by the photoresist are removed by wet etching (for example, using a buffered hydrofluoric acid solution) or dry etching (for example, reactive ion etching, RIE), so as to expose the silicon surface of the P-type well region on the substrate surface. After etching, the photoresist is removed to obtain a substrate structure with a P-type well mask. At this time, the silicon oxide layer acts as a mask to expose only the P-type well region, while the other regions are still covered by the silicon oxide layer. The substrate structure with the P-type well mask is subjected to boron diffusion treatment to obtain a substrate structure containing a P-type well. Boron atoms are introduced into the exposed P-type well region through high-temperature diffusion to form a well structure with P-type conductivity characteristics. In specific implementation, the substrate is placed in a diffusion furnace, the temperature is raised to 900-1100 degrees Celsius, and a gaseous doping source containing boron (such as borane B2H6 or boron trichloride BCl3) is introduced. The doping source decomposes at high temperature to release boron atoms which diffuse into the substrate through the exposed silicon surface to form a P-type well. The diffusion time is 30-120 minutes, and the specific time and temperature are determined according to the required P-type well depth (usually 1-5 microns) and doping concentration (10 16 ~10 18The silicon oxide mask effectively prevents boron atoms from entering the non-P-type well region, ensuring the selectivity of the doped region. After diffusion is completed, the electrical properties of the P-type well are preserved by rapid cooling, and a substrate structure containing a P-type well is obtained. The surface of the substrate structure containing the P-type well is subjected to a second oxidation and photolithography process. First, the substrate surface is subjected to a second low-temperature oxidation (temperature 800-900 degrees Celsius) to regrow a layer of silicon oxide on the surface of the P-type well and other regions. Subsequently, the photolithography and etching processes are repeated to define the first N-type well region using a new mask. By coating, exposing, developing, and etching the photoresist, the silicon oxide layer in the N-type well region is removed, exposing the silicon surface, while the other regions are still protected by the silicon oxide layer, resulting in a substrate structure with a first N-type well mask. The substrate structure with the first N-type well mask is subjected to phosphorus diffusion treatment to obtain a substrate structure containing a P-type well and a first N-type well. The N-type well is formed by the diffusion of phosphorus atoms in the exposed area. In specific implementation, the substrate is placed in a diffusion furnace with a temperature control of 900-1050 degrees Celsius, and a gaseous doping source containing phosphorus (such as phosphine PH3 or phosphorus pentachloride PCl5) is introduced. Phosphorus atoms diffuse into the substrate through the exposed silicon surface to form the first N-type well. The diffusion time is 30-90 minutes. The silicon oxide mask ensures that phosphorus atoms only enter the N-type well region. After diffusion is completed, the substrate structure contains both P-type wells and first N-type wells, and the two well structures are preliminarily isolated in space by the silicon oxide mask. The substrate structure containing the P-type well and the first N-type well is subjected to deep boron diffusion and annealing treatment to obtain a multi-well structure that is mutually isolated. This step forms a deep P-type well through deep boron diffusion and optimizes the crystal quality and electrical properties of the well structure through annealing. In specific implementation, the substrate is placed in a diffusion furnace and a high-concentration boron source (such as borane) is introduced for deep boron diffusion. The time is 60-180 minutes to form a deep P-type well with a doping concentration of 10 17 ~10 19 atoms per cubic centimeter. The deep P-type well enhances the electrical isolation performance of the well structure. Subsequently, annealing treatment is performed in an inert gas (such as nitrogen or argon, flow rate 5-20 SLM) atmosphere at a temperature of 900-1000 degrees Celsius for 10-30 minutes to activate the doping atoms, repair lattice defects, and optimize the interface properties of the P-type well, deep P-type well, and first N-type well. After annealing, slow cooling (5-10 degrees Celsius per minute) is used to avoid thermal stress. Finally, a multi-well structure containing P-type wells, deep P-type wells, and first N-type wells that are mutually isolated is obtained. In another embodiment, it is worth noting that the P-type well also includes a shallow P-type well and a medium P-type well. The preparation method is similar to that of the shallow P-type well and the medium P-type well. The shallow P-type well and the medium P-type well can be formed by adjusting the boron diffusion conditions, such as reducing the diffusion temperature and time to obtain a shallower doping depth and concentration to form a shallow P-type well; and appropriately increasing the diffusion temperature and time to obtain a medium P-type well.

[0039] In an embodiment, the deep P-type well comprises a first deep P-type well and a second deep P-type well, characterized in that the step of ion implantation treatment on the deep P-type well in the multi-well structure to obtain a doping optimization structure comprises: photolithography treatment on the first deep P-type well and the second deep P-type well to obtain a deep P-type well surface with a preset pattern; first phosphorus ion implantation treatment on the first deep P-type well according to the deep P-type well surface, with an energy of 100-150 keV, a dose of 10 14 ~10 15 cm -2 , and a doping concentration of 10 17 ~10 18 cm -3 , to implant a second N-type well structure on the upper part of the first deep P-type well; second phosphorus ion implantation treatment on the second deep P-type well according to the deep P-type well surface, with a dose of 10 15 ~10 16 cm -2 , and a doping concentration of 10 19 ~10 20 cm -3 , to implant a third N-type well structure on the upper part of the second deep P-type well; high-temperature annealing treatment on the second N-type well structure and the third N-type well structure to obtain the doping optimization structure.

[0040] In this embodiment, photolithography treatment is performed on the first deep P-type well and the second deep P-type well to form a deep P-type well surface with a preset pattern. A photoresist is coated on the wafer surface, and a mask plate and a light source (usually ultraviolet light or deep ultraviolet light) are used to transfer the designed pattern to the photoresist. After exposure and development, the photoresist is removed in specific areas, exposing the deep P-type well surface area that needs to be ion implanted. The pattern design of these areas accurately corresponds to the doping area of subsequent ion implantation, thereby ensuring the accuracy of the doping position. After the photolithography treatment is completed, the wafer surface forms a deep P-type well surface with a preset pattern, providing a basis for the subsequent ion implantation process. According to the pattern of the deep P-type well surface formed by photolithography treatment, first phosphorus ion implantation treatment is performed on the first deep P-type well to form a second N-type well structure on the upper part of the first deep P-type well. Specifically, the energy range of the first phosphorus ion implantation treatment is set to 100-150 keV, the dose range is 10 14 ~10 15 cm -2 , and the doping concentration reaches 10 17 ~10 18 cm -3As a N-type dopant, the implantation energy of phosphorus ions determines the penetration depth of ions in the silicon substrate, while the dose and doping concentration directly affect the electrical properties of the N-type well. The energy range of 100-150 keV enables phosphorus ions to be implanted into the upper region of the first deep P-type well, forming a relatively shallow N-type doping layer, which is the second N-type well structure. Since the first deep P-type well is P-type doped, the implantation of phosphorus ions will form an N-type region on its upper part, thereby realizing the construction of P-N junction. The processing for the second deep P-type well is also based on the surface pattern formed by lithography, but the process parameters are different to form the third N-type well structure. Specifically, the second phosphorus ion implantation is performed on the second deep P-type well, with a dose range of 10 15 ~10 16 cm -2 , and a doping concentration of 10 19 ~10 20 cm -3 . Compared with the processing of the first deep P-type well, the phosphorus ion implantation of the second deep P-type well uses a higher dose and doping concentration, and the third N-type well requires a higher carrier concentration to achieve the characteristics of low resistivity and high conductivity. The third N-type well is used to form a highly doped contact region or source / drain region to optimize the current transmission capability of the device. A higher doping concentration, i.e. more phosphorus atoms, is implanted into the upper region of the second deep P-type well, thereby forming a highly doped N-type region, i.e. the third N-type well structure. This region forms a highly doped P-N junction with the underlying P-type well. After completing the ion implantation of the first deep P-type well and the second deep P-type well, the wafer surface forms the preliminary structure of the second N-type well and the third N-type well. A high-temperature annealing process is performed on the second N-type well structure and the third N-type well structure in an inert gas (such as nitrogen) environment, with a temperature range of 900-1100°C, depending on the process design and equipment type. The annealing process diffuses the implanted phosphorus atoms in the lattice at high temperature and occupies the appropriate lattice positions, thereby activating the dopant and restoring the integrity of the lattice, and can repair the lattice defects generated during ion implantation, reducing the influence of defect states on carrier mobility. During the annealing process, the phosphorus atoms in the second N-type well and the third N-type well will further diffuse, making the doping distribution more uniform, and at the same time making the doping concentration and depth meet the design requirements. After high-temperature annealing, the second N-type well on the upper part of the first deep P-type well and the third N-type well structure on the upper part of the second deep P-type well are stabilized, forming a doping structure with optimized electrical properties.

[0041] In an embodiment, after the step of depositing an insulating layer on the doping optimization structure and covering a conductive layer, the step of obtaining the thyristor chip comprises: The doped optimization structure is subjected to a low-temperature chemical vapor deposition treatment to deposit a silicon oxide insulating layer with a thickness of 1-2 μm, thereby obtaining an insulating layer structure covering the doped optimization structure; The insulating layer structure is subjected to a coating and patterning treatment to form a lead hole pattern corresponding to the upper portions of the second N-type well and the third N-type well, thereby obtaining a photoresist mask structure with the lead hole pattern; The photoresist mask structure is subjected to a reactive ion etching treatment to form a lead hole on the insulating layer structure, thereby exposing the connecting region of the second N-type well and the third N-type well, and obtaining an insulating layer structure with the lead hole; The insulating layer structure with the lead hole is subjected to a sputtering deposition treatment to deposit an aluminum-silicon alloy conductive layer, thereby forming a metal layer structure covering the lead hole and the insulating layer, and obtaining the bidirectional thyristor chip.

[0042] In this embodiment, a low-temperature chemical vapor deposition process is performed on the doped optimization structure to deposit a layer of silicon oxide insulating layer. This process is carried out in a vacuum environment by introducing reaction gases such as silane (SiH4) and oxygen (O2) into the reaction chamber, and a chemical reaction occurs at a lower temperature (usually between 400-600°C) to generate silicon oxide (SiO) and deposit it on the surface of the doped optimization structure. A layer of photoresist is coated on the surface of the insulating layer structure, and a spin coating technique is used to ensure uniform thickness of the photoresist. The designed lead hole pattern is transferred to the photoresist using a mask plate through a photolithography device. The pattern on the mask plate corresponds exactly to the connection area of the second N-type well and the third N-type well, which are usually the key electrode areas that need to be connected to the external circuit in the device. Under the irradiation of ultraviolet or deep ultraviolet light, the photoresist undergoes a chemical change in the exposed area. After development, the photoresist in the unexposed area (or exposed area, depending on the type of photoresist) is removed, forming a photoresist mask structure with a lead hole pattern on the surface of the insulating layer. The photoresist mask structure with the lead hole pattern is subjected to a reactive ion etching process to form lead holes on the insulating layer structure, exposing the connection area of the second N-type well and the third N-type well. Fluorine-containing gas (such as CF4 or SF6) can be used as the etching gas to react with silicon oxide in a plasma environment, while ion bombardment enhances the anisotropy of etching. The photoresist mask protects the areas that do not need to be etched, while the exposed silicon oxide in the lead hole pattern area is gradually removed until the surface of the second N-type well and the third N-type well is exposed. The insulating layer structure with lead holes is subjected to a sputter deposition process, in which high-energy ion bombardment of an aluminum-silicon alloy target in a high-vacuum environment causes target atoms to detach and deposit on the wafer surface, forming a uniform metal layer. During sputtering, aluminum-silicon alloy atoms not only fill the lead holes and form ohmic contacts with the exposed second N-type well and third N-type well, but also cover the entire surface of the insulating layer, forming a continuous metal layer structure. The direct contact between the metal in the lead hole and the doped area ensures low-resistance transmission of electrical signals. To ensure the quality of the metal layer, sputter deposition is carried out in a clean environment, and the deposition rate and thickness are controlled to avoid stress problems caused by excessive thickness of the metal layer or insufficient conductivity caused by excessive thinness. After completing the sputter deposition, a metal patterning process (such as photolithography and etching) is performed to form the final electrode and interconnection structure, thus obtaining a complete bidirectional thyristor chip.

[0043] It is worth noting that all the equipment described in this application can be realized by existing technology, the algorithms described are based on mature algorithms of existing technology, and the chemicals and conditions used in the preparation process are within the safe range and will not harm the operators or the environment.

[0044] Reference Figure 2 and Figure 3The application further discloses a bidirectional thyristor chip prepared by the bidirectional thyristor chip preparation method. An N-type gas-doped material substrate 1; An N-type epitaxial layer 2 arranged on the N-type gas-doped material substrate 1; A multi-well structure including a shallow P-type well 31, a middle P-type well 32, a deep P-type well and a first N-type well 41, each well of the multi-well structure being separated by the N-type epitaxial layer 2; wherein the deep P-type well includes a first deep P-type well 33 and a second deep P-type well 34, the first deep P-type well 33 being implanted with a second N-type well 42 at an upper portion, and the second deep P-type well 34 being implanted with a third N-type well 43 at an upper portion; An insulating layer covering the multi-well structure and being provided with lead holes respectively exposing the first N-type well 41, the middle P-type well 32, the second N-type well 42 and the third N-type well 43; A conductive layer covering the insulating layer and the lead holes and being electrically connected with the first N-type well 41, the middle P-type well 32, the second N-type well 42 and the third N-type well 43.

[0045] In this embodiment, N-type gas-doped material wafer is used as the substrate, with a resistivity controlled between 120-180Ω·cm. The N-type gas-doped material wafer is prepared by gas-phase doping technology, introducing N-type dopants such as phosphorus or arsenic to ensure uniform doping concentration and low defect density. Compared with other substrate materials, it provides sufficient voltage resistance to avoid device breakdown under high voltage. The N-type epitaxial layer 2 grown on the N-type gas-doped material substrate 1 is a core component of the high-performance bidirectional photosensitive thyristor chip, with a precisely controlled resistivity of 150±3Ω·cm, ensuring sufficient conductivity to support device operation while avoiding excessively low resistivity that would lower the breakdown voltage. Through chemical vapor deposition (CVD) technology, the epitaxial layer is grown in a high-temperature environment, with precise control of dopant (such as phosphine) flow, growth temperature, and deposition time to ensure a resistivity deviation within ±3Ω·cm. This resistivity control allows the peak off-state breakdown voltage (VDRM) of the chip to be uniformly controlled within ±25V in both forward and reverse directions, significantly improving device consistency and reliability. The multi-well structure includes a shallow P-type well 31, a middle P-type well 32, a deep P-type well (divided into a first deep P-type well 33 and a second deep P-type well 34), a first N-type well 41, a second N-type well 42, and a third N-type well 43. These wells are isolated from each other by the N-type epitaxial layer 2, effectively preventing electrical interference between doped regions. The shallow P-type well 31 and the middle P-type well 32 are formed by ion implantation of P-type dopants such as boron, providing different doping depths and concentrations to optimize device trigger sensitivity and conduction characteristics. The deep P-type well is formed through a deeper ion implantation and diffusion process, with higher doping concentration and depth, enhancing the device's voltage resistance and electrical isolation performance. The second N-type well 42 and the third N-type well 43 are implanted in the upper part of the first deep P-type well 33 and the second deep P-type well 34, respectively, with the high doping concentration of the third N-type well 43 significantly reducing the contact resistance and improving the ohmic contact performance with the conductive layer. The complex design of this multi-well structure optimizes the gate trigger current (IGT) of the bidirectional photosensitive thyristor chip to within ±5uA, demonstrating extremely high trigger sensitivity and consistency. The insulating layer, which can be silicon dioxide (SiO2) deposited by low-pressure chemical vapor deposition (LPCVD) process, effectively isolates the multi-well structure from the conductive layer, preventing electrical short circuits and leakage. The lead holes formed on the insulating layer through photolithography and reactive ion etching (RIE) process expose the connection areas of the first N-type well 41, the middle P-type well 32, the second N-type well 42, and the third N-type well 43. The precise formation of the lead holes ensures reliable electrical connection between the conductive layer and the doped regions, while avoiding damage to the doped regions during the etching process. The conductive layer, which is an aluminum-silicon alloy formed by sputtering deposition process, fills the lead holes and covers the surface of the insulating layer, forming ohmic contact with the underlying doped regions.The aluminum-silicon alloy can effectively reduce the contact resistance and ensure efficient transmission of electrical signals due to its low resistivity and good compatibility with silicon. The electrical connection mode of the embodiment realizes efficient operation of the chip through precise butt joint of the conductive layer and the multi-well structure. The first N-type well 41, the middle P-type well 32, the second N-type well 42 and the third N-type well 43 are respectively electrically connected with the conductive layer through the lead hole, forming the main electrode and gate structure of the bidirectional thyristor. This connection mode ensures that the current can be efficiently conducted through the doped area when the chip works in forward and reverse directions, and the gate trigger signal can quickly respond to the light control or electric control signal. The high doping property of the third N-type well 43 significantly reduces the resistance of the gate trigger, so that the IGT control is within the range of ± 5uA, showing extremely high sensitivity. In addition, the uniform deposition of the conductive layer and the precise alignment of the lead hole ensure the VDRM consistency of the chip under forward and reverse voltages, which is controlled within ± 25V. This electrical connection mode not only optimizes the electrical performance of the chip, but also improves the fault tolerance and production efficiency of the manufacturing process.

[0046] The application further discloses a semiconductor device, which comprises the bidirectional thyristor chip and an external circuit electrically connected with the bidirectional thyristor chip, and the external circuit is used for controlling the turn-on and turn-off of the bidirectional thyristor chip.

[0047] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of manufacturing a bidirectional thyristor chip, characterized by, The application relates to a bidirectional thyristor chip and a preparation method thereof. The application comprises the following steps: An N-type gas-doped material sheet is selected as a substrate, and an N-type epitaxial layer is grown on the substrate based on a chemical vapor deposition method, so that a substrate structure comprising an N-type epitaxial layer is obtained; A multi-step diffusion doping process is performed on the substrate structure, so that a plurality of isolated multi-well structures are formed, wherein the multi-well structures comprise a P-type well, a deep P-type well and a first N-type well; An ion implantation process is performed on the deep P-type well in the multi-well structure, so that a doping optimization structure is obtained; 2. The method of claim 1, wherein the step of forming the gate electrode is performed by a method comprising: forming a first gate electrode on the first semiconductor substrate; and forming a second gate electrode on the second semiconductor substrate. After an insulating layer deposition process is performed on the doping optimization structure and a conductive layer is covered, the bidirectional thyristor chip is obtained.

3. The method of claim 1, wherein the step of forming the gate electrode is performed by a method comprising: forming a first gate electrode on the first semiconductor substrate; and forming a second gate electrode on the second semiconductor substrate. The resistivity of the N-type gas-doped material sheet ranges from 120 to 180 ohm*cm.

4. The method of claim 1, wherein the step of forming the gate electrode is performed by a method comprising: forming a first gate electrode on the first semiconductor substrate; and forming a second gate electrode on the second semiconductor substrate. The resistivity of the N-type epitaxial layer ranges from 150 to 153 ohm*cm. The step of selecting the N-type gas-doped material sheet as the substrate comprises the following steps: Ammonia, hydrogen peroxide and deionized water are configured in a ratio of 1:1:5 to obtain a first mixed solution, and hydrofluoric acid and deionized water are configured in a ratio of 1:10 to obtain a second mixed solution; The N-type gas-doped material sheet is cleaned in the first mixed solution at 70-80 DEG C for 5-10 minutes to obtain a cleaned substrate; 5. The method of claim 1, wherein the step of forming the gate electrode is performed by a method comprising: forming a first gate electrode on the first semiconductor substrate; and forming a second gate electrode on the second semiconductor substrate. The cleaned substrate is cleaned in the second mixed solution for 5-10 minutes to obtain the substrate. The step of growing the N-type epitaxial layer on the substrate based on the chemical vapor deposition method to obtain the substrate structure comprising the N-type epitaxial layer comprises the following steps: The substrate is subjected to high-temperature preheating treatment under high-temperature conditions, and hydrogen is introduced as a carrier gas for 5-10 minutes to obtain a heat-stable substrate; Trichlorosilane is used as a silicon source, phosphine is used as an N-type doping source, and hydrogen is used as a carrier gas to deposit an initial N-type epitaxial layer on the heat-stable substrate by the chemical vapor deposition method, so that a preliminary epitaxial structure is obtained; The flow of phosphine is adjusted to perform doping optimization treatment on the preliminary epitaxial structure, so that a uniformly doped epitaxial layer is obtained; 6. The method of claim 1, wherein the step of forming the gate electrode is performed by a method comprising: forming a first gate electrode on the first semiconductor substrate; forming a second gate electrode on the second semiconductor substrate; and forming a third gate electrode on the third semiconductor substrate. The uniformly doped epitaxial layer is subjected to annealing treatment in an inert gas atmosphere, so that the substrate structure comprising the N-type epitaxial layer is obtained. The step of performing a multi-step diffusion doping process on the substrate structure to form a plurality of isolated multi-well structures, wherein the multi-well structures comprise a P-type well, a deep P-type well and a first N-type well, comprises the following steps: The substrate structure is subjected to low-temperature oxidation treatment based on a hydrofluoric acid solution to form a silicon oxide layer; The silicon oxide layer is subjected to etching treatment to define a plurality of P-type well regions, so that a substrate structure with a P-type well mask is obtained; The substrate structure with the P-type well mask is subjected to boron diffusion treatment, so that a substrate structure containing a P-type well is obtained; The surface of the substrate structure containing the P-type well is subjected to second oxidation and photolithography treatment, so that a substrate structure with a first N-type well mask is obtained; The substrate structure with the first N-type well mask is subjected to phosphorus diffusion treatment, so that a substrate structure containing a P-type well and a first N-type well is obtained; The substrate structure containing the P-type well and the first N-type well is subjected to deep boron diffusion and annealing treatment, so that a plurality of isolated multi-well structures are obtained.

7. The method of claim 1, wherein the deep P-well includes a first deep P-well and a second deep P-well, and wherein the first deep P-well is formed by implanting a first dose of P-type ions at a first energy, and the second deep P-well is formed by implanting a second dose of P-type ions at a second energy. The step of performing ion implantation treatment on the deep P-type well in the multi-well structure to obtain a doping optimization structure comprises: performing photoetching treatment on the first deep P-type well and the second deep P-type well to obtain a deep P-type well surface with a preset pattern; According to the deep P-type well surface, the first deep P-type well is subjected to a first phosphorus ion implantation treatment with an energy of 100-150 keV, a dose of 10 14 ~10 15 cm -2 , and a doping concentration of 10 17 ~10 18 cm -3 , so as to implant a second N-type well structure on the upper portion of the first deep P-type well. According to the deep P-type well surface, a second phosphorus ion implantation treatment is performed on the second deep P-type well, with a dose of 10 15 ~10 16 cm -2 , a doping concentration of 10 19 ~10 20 cm -3 , so as to implant a third N-type well structure on the upper portion of the second deep P-type well. performing high-temperature annealing treatment on the second N-type well structure and the third N-type well structure to obtain the doping optimization structure.

8. The method according to claim 7, wherein the step of forming the gate electrode is performed by a method comprising the steps of: forming a first gate electrode on the first semiconductor substrate; and forming a second gate electrode on the second semiconductor substrate. The step of performing deposition treatment on the doping optimization structure to obtain the bidirectional thyristor chip comprises: performing low-temperature chemical vapor deposition treatment on the doping optimization structure to deposit a silicon oxide insulating layer with a thickness of 1-2 μm to obtain an insulating layer structure covering the doping optimization structure; performing coating and patterning treatment on the insulating layer structure to form a lead hole pattern corresponding to the upper portions of the second N-type well and the third N-type well to obtain a photoresist mask structure with a lead hole pattern; performing reactive ion etching treatment on the photoresist mask structure to form a lead hole on the insulating layer structure to expose the connection region of the second N-type well and the third N-type well to obtain an insulating layer structure with a lead hole; performing sputtering deposition treatment on the insulating layer structure with a lead hole to deposit an aluminum-silicon alloy conductive layer to form a metal layer structure covering the lead hole and the insulating layer to obtain the bidirectional thyristor chip.

9. A triac chip, characterized by The bidirectional thyristor chip is prepared by the method of any one of claims 1-8, comprising: an N-type gas-doped material substrate; an N-type epitaxial layer disposed on the N-type gas-doped material substrate; a multi-well structure comprising a shallow P-type well, a middle P-type well, a deep P-type well, and a first N-type well, each well of the multi-well structure being separated by the N-type epitaxial layer; wherein the deep P-type well comprises a first deep P-type well and a second deep P-type well, the upper portion of the first deep P-type well being implanted with a second N-type well, and the upper portion of the second deep P-type well being implanted with a third N-type well; an insulating layer covering the multi-well structure and provided with lead holes respectively exposing the first N-type well, the middle P-type well, the second N-type well, and the third N-type well; a conductive layer covering the insulating layer and the lead holes and electrically connected with the first N-type well, the middle P-type well, the second N-type well, and the third N-type well.

10. A semiconductor device comprising the bidirectional thyristor chip of claim 9 and an external circuit electrically connected with the bidirectional thyristor chip, the external circuit being used to control the turn-on and turn-off of the bidirectional thyristor chip.

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