Gallium nitride-based epitaxial structure and method of manufacture

Abstract

The application relates to the technical field of semiconductor devices, and provides a gallium nitride-based epitaxial structure and a preparation method.The gallium nitride-based epitaxial structure comprises a Si substrate with a pyramid-shaped nanostructure on the surface, a graphene layer, a high-temperature AlN starting layer, a stepped Al x Ga 1‑ x N buffer layer, an N-type GaN active layer, a stepped Al y GaN barrier layer, an electron blocking layer, a P-type GaN contact layer and a passivation layer.Through the synergistic effect of the structured Si substrate and the graphene layer, the design of the stepped buffer layer and the barrier layer, the lattice mismatch stress is effectively relieved, the dislocation density is reduced, the carrier mobility and the device breakdown voltage are improved, the high-temperature working stability is enhanced, and the application to high-frequency and high-power semiconductor devices is suitable.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gallium nitride-based epitaxial structure and its fabrication method. Background Technology

[0002] Epitaxial structures refer to thin film materials with specific crystal structures and properties deposited on substrate materials through epitaxial growth. Gallium nitride-based epitaxial structures are typically multilayer material systems based on GaN, grown on substrates such as sapphire (Al2O3), silicon carbide (SiC), or silicon (Si). Their complex structures offer multiple functions, including stress modulation and optimization of electrical and optical performance. Lattice mismatch refers to the difference in lattice constants between the epitaxial layer material and the substrate material. This difference leads to stress concentration, resulting in defects (such as dislocations and cracks), affecting the performance and reliability of semiconductor devices. To address the lattice mismatch problem, existing epitaxial structures often employ thick buffer layers, relying on the natural stress relief provided by the thick buffer layer. While this initially reduces interfacial stress, the greater the thickness, the more significant the accumulation of residual thermal stress in the overall structure. Especially during high-temperature growth and cooling, the thick buffer layer cannot release stress in time, easily leading to cracks, warping, or even delamination, affecting the performance and reliability of semiconductor devices.

[0003] A search revealed that invention patent CN119767735A discloses an epitaxial structure for a gallium nitride semiconductor chip. This structure includes a Si substrate, an AlN nucleation layer, a stepped-gradient AlGaN buffer layer, a C-doped GaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, an AlGaN barrier layer, and a Si passivation layer. The stepped-gradient AlGaN buffer layer comprises four sub-buffer layers, with the Al composition gradually increasing in each layer to alleviate lattice mismatch. However, this technical solution still has significant drawbacks: while the incremental Al composition design of the stepped-gradient buffer layer can achieve partial stress relief, the thickness distribution of the four sub-buffer layers does not consider the dynamic stress release requirements, and the fixed rate of Al composition gradient change leads to stress concentration zones easily forming inside the buffer layer during high-temperature growth and cooling cycles. Dislocation accumulation is particularly likely at the sub-buffer layer interfaces, failing to completely solve the residual thermal stress problem caused by the thick buffer layer and affecting the long-term operational stability of the device. Summary of the Invention

[0004] To address the aforementioned problems, this invention aims to provide a gallium nitride-based epitaxial structure and its fabrication method, which can solve the technical problems in the prior art where thick buffer layers cannot release stress in a timely manner, are prone to cracking, warping, or even peeling, thereby affecting the performance and reliability of semiconductor devices.

[0005] The technical solution of the present invention is as follows:

[0006] On one hand, the present invention provides a gallium nitride-based epitaxial structure, comprising:

[0007] A Si substrate with a structured surface, wherein the surface of the Si substrate is provided with multiple pyramid-shaped nanostructures;

[0008] A graphene layer is disposed on the Si substrate;

[0009] A high-temperature AlN initiation layer is disposed on the graphene layer;

[0010] Stepped Al x Ga 1-x An N-buffer layer is disposed on the high-temperature AlN initiation layer;

[0011] An N-type GaN active layer is disposed on the stepped Al... x Ga 1-x On the N-buffer layer;

[0012] Stepped Al y A GaN barrier layer is disposed on the N-type GaN active layer;

[0013] An electron blocking layer is disposed in the stepped Al y On the GaN barrier layer;

[0014] A p-type GaN contact layer is disposed on the electron blocking layer; and

[0015] A passivation layer is disposed on the P-type GaN contact layer.

[0016] Preferably, the stepped Al x Ga 1-x The N buffer layer includes a first-level Al layer arranged sequentially from bottom to top. 0.73 Ga 0.27 N-buffer layer, second-level Al 0.47 Ga 0.53 N-buffer layer, third-level Al 0.34 Ga 0.66 N-buffer layer, fourth-level Al 0.21 Ga 0.79 N buffer layer and fifth-level Al 0.12 Ga 0.88 N buffer layers, first level Al 0.73 Ga 0.27 N-buffer layer, second-level Al 0.47 Ga 0.53 N-buffer layer, third-level Al 0.34 Ga 0.66 N-buffer layer, fourth-level Al 0.21 Ga 0.79 N buffer layer and fifth-level Al0.12 Ga 0.88 The aluminum composition of the N-buffer layer is set in a gradient decreasing manner.

[0017] Preferably, the first-level Al 0.73 Ga 0.27 The thickness of the N buffer layer is 60~80 nm, and the second-stage Al... 0.47 Ga 0.53 The thickness of the N buffer layer is 90~110 nm, and the third-level Al 0.34 Ga 0.66 The thickness of the N buffer layer is 110~130nm, and the fourth-level Al 0.21 Ga 0.79 The thickness of the N buffer layer is 190~210 nm, and the fifth-level Al 0.12 Ga 0.88 The thickness of the N buffer layer is 370~390 nm.

[0018] Preferably, the stepped Al y The GaN barrier layer includes a first-level Al layer arranged sequentially from bottom to top. 0.4 GaN barrier layer, second-stage AlGaN graded barrier layer and third-stage Al 0.2 In the GaN barrier layer, the Al molar fraction in the second-stage AlGaN graded barrier layer gradually decreases from 40% to 20%.

[0019] Preferably, the first-level Al 0.4 The thickness of the GaN barrier layer is 20~40 nm, the thickness of the second-stage AlGaN graded barrier layer is 190~210 nm, and the thickness of the third-stage Al... 0.2 The thickness of the GaN barrier layer is 20~40 nm.

[0020] Preferably, the N-type GaN active layer has five pairs of InGaN well layers and GaN barrier layers stacked alternately, forming an indium composition gradient sub-well structure, wherein the band change of the indium composition gradient sub-well is an asymmetric trapezoidal shape.

[0021] Preferably, the indium component gradient sub-well is located near the stepped Al x Ga 1-x The bandgap thickness on the N-buffer layer side is 0.4–0.6 nm, and the bandgap thickness in the middle of the indium-component gradient sub-well is 1.0–1.2 nm. The indium-component gradient sub-well is located near the stepped Al... y The band gradient thickness on the GaN barrier layer side is 1.2~1.4 nm.

[0022] On the other hand, a method for preparing the above-mentioned gallium nitride-based epitaxial structure is also provided, comprising the following steps:

[0023] S1. Construct a simulation model of the gallium nitride-based epitaxial structure. The simulation model describes the potential distribution, charge conservation, and carrier current density within the semiconductor device using the Poisson equation, the continuity equation of electrons and holes, and the drift-diffusion current equation of electrons and holes.

[0024] S2. Using the simulation model, determine the breakdown voltage of the gallium nitride-based epitaxial structure under various structural parameters. The breakdown voltage is the maximum voltage value that the structure can withstand under reverse bias.

[0025] S3. Determine the optimal structural parameters of the gallium nitride-based epitaxial structure based on the breakdown voltage under various structural parameters, wherein the step of determining the optimal structural parameters of the gallium nitride-based epitaxial structure includes determination by using the honey badger optimization algorithm;

[0026] The structural parameters include: the thickness of each layer in the gallium nitride-based epitaxial structure, the size parameters of the pyramid-shaped nanostructure on the Si substrate, and the stepped Al... x Ga 1-x The doping concentration in the N buffer layer and the stepped Al y Doping concentration in the GaN barrier layer.

[0027] The honey badger optimization algorithm includes initializing honey badger individuals using Sine chaotic mapping, where each honey badger individual represents a set of structural parameters, and the initialization generates the initial position of the honey badger individual through Sine chaotic mapping.

[0028] S4. According to the optimal structural parameters, surface structuring treatment is performed on the Si substrate to prepare multiple pyramid-shaped nanostructures.

[0029] S5. A graphene layer is deposited on the Si substrate by chemical vapor deposition;

[0030] S6. Raise the growth temperature to 1000-1200℃ and deposit a high-temperature AlN initiation layer on the graphene layer by chemical vapor deposition.

[0031] S7. A stepped Al2 structure is formed by chemical vapor deposition on the high-temperature AlN initiation layer. x Ga 1-x N-buffer layer;

[0032] S8, via chemical vapor deposition on the stepped Al x Ga 1-x An N-type GaN active layer is deposited on the N-buffer layer;

[0033] S9. Deposit stepped Al on the N-type GaN active layer by chemical vapor deposition. y GaN barrier layer;

[0034] S10, via chemical vapor deposition on the stepped Al y An electron blocking layer is deposited on the GaN barrier layer;

[0035] S11. A P-type GaN contact layer is deposited on the electron blocking layer by chemical vapor deposition;

[0036] S12, and perform surface passivation treatment on the P-type GaN contact layer to deposit a passivation layer.

[0037] Compared with the shortcomings of the prior art, the beneficial effects of the present invention are as follows:

[0038] (1) This invention designs a stepped Al x Ga 1-x The N-buffer layer employs a stepped aluminum composition control to achieve a layer-by-layer transition of stress and lattice mismatch, timely release of stress, and improvement of the performance and reliability of semiconductor devices.

[0039] (2) This invention introduces a non-planar growth interface by setting multiple pyramid-shaped nanostructures on the surface of a silicon substrate, which effectively disperses stress and suppresses vertical dislocation penetration, reducing cracks and warping caused by stress accumulation. At the same time, the three-dimensional microstructure provides multi-directional growth sites, promotes self-organized nucleation of the epitaxial layer and improves crystal quality, laying the foundation for high-quality growth of subsequent graphene layers and epitaxial materials.

[0040] (3) By using a graphene layer as an intermediate layer, the present invention reduces the interface energy level, optimizes the GaN lattice mismatch and stress release, and its virtual substrate characteristics provide a flexible buffer platform for GaN epitaxial growth, suppressing dislocation propagation and crack generation, and improving the crystal quality and structural integrity of the epitaxial layer.

[0041] (4) By employing a high-temperature AlN initiation layer, this invention suppresses the chemical reaction of silicon at high temperatures, significantly reduces the dislocation density, and provides a high-quality initial template with higher lattice matching, thus paving the way for subsequent step-type AlN initiation. x Ga 1-x The N-buffer layer provides a stable lattice transition platform, effectively reducing interface dislocation density and stress concentration, and improving the overall crystal quality and reliability of the epitaxial structure. Attached Figure Description

[0042] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0043] Figure 1 This is a schematic diagram of a gallium nitride-based epitaxial structure provided in an embodiment of the present invention.

[0044] Figure 2 This is a stepped Al provided in an embodiment of the present invention. x Ga 1-x A schematic diagram of the N-buffer layer.

[0045] Figure 3 This is a stepped Al provided in an embodiment of the present invention. y Schematic diagram of the GaN barrier layer.

[0046] Figure 4 This is a schematic diagram of the band structure of an indium-component gradient sub-well provided in an embodiment of the present invention.

[0047] Figure 5 This is a schematic flowchart of a preparation method provided in an embodiment of the present invention.

[0048] Figure labeling: 1-Si substrate; 2-Graphene layer; 3-High-temperature AlN initiation layer; 4-Stepped Al x Ga 1-x N buffer layer; 41-first level Al 0.73 Ga 0.27 N buffer layer; 42-Secondary Al 0.47 Ga 0.53 N buffer layer; 43-Third level Al 0.34 Ga 0.66 N buffer layer; 44-Fourth level Al 0.21 Ga 0.79 N buffer layer; 45-fifth level Al 0.12 Ga 0.88 N-buffer layer; 5-N type GaN active layer; 6-stepped Al y GaN barrier layer; 61-First-stage Al 0.4 GaN barrier layer; 62-Second-stage AlGaN gradient barrier layer; 63-Third-stage Al 0.2 GaN barrier layer; 7-electron blocking layer; 8-P-type GaN contact layer; 9-passivation layer. Detailed Implementation

[0049] The present invention will be further described below with reference to the accompanying drawings and embodiments, but this is not intended to limit the scope of the invention; it is merely illustrative. It should be noted that, unless otherwise specified, the embodiments and technical features described in this application can be combined with each other. Unless otherwise indicated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Unless otherwise specified, the experimental methods used in the following embodiments are conventional methods. Unless otherwise specified, the materials, reagents, etc., used in the following embodiments are commercially available.

[0050] Reference manual attached Figure 1 The diagram shows a schematic diagram of a gallium nitride-based epitaxial structure provided in an embodiment of the present invention.

[0051] The present invention provides a gallium nitride-based epitaxial structure comprising: a Si substrate 1, a graphene layer 2, a high-temperature AlN initiation layer 3, and a stepped Al... x Ga 1-x 4. N-type buffer layer, 5. N-type GaN active layer, 6. Stepped Al y GaN barrier layer 6, electron blocking layer 7, P-type GaN contact layer 8, and passivation layer 9.

[0052] The Si substrate 1 forms the basis of the epitaxial structure. The Si substrate 1 employs a structured surface, with multiple pyramid-shaped nanostructures formed on its surface. This micro-nano patterning design effectively expands stress relief channels, reduces in-plane stress accumulation, suppresses crack formation, and promotes directional growth of epitaxial nucleation, thus contributing to superior crystal quality.

[0053] Optionally, the recommended height of the pyramid-shaped nanostructure is 100 nm to 300 nm, the recommended apex angle is 60° to 90°, and the recommended spacing is 200 nm to 500 nm.

[0054] It is worth noting that the pyramid-shaped surface, when stress is applied, can form multiple stress-relieving channels through its sharp apex and sloping sides. These channels help disperse the stress generated during epitaxial layer growth to the surrounding area, rather than concentrating it in a single location. Without a microstructured surface, the stress generated during epitaxial growth may concentrate in a small area, leading to dislocation formation. The nanostructured surface reduces stress concentration areas by increasing stress-relieving channels, thereby reducing dislocation density. X-ray diffraction (XRD) tests show that after using a pyramid-shaped nanostructure with a height of 200 nm and a apex angle of 75°, the dislocation density decreased from 1 × 10⁻⁶. 9 cm -2 Reduced to 5×10 8 cm -2The reduction is approximately 30% to 50% (compared to planar Si substrate samples), with the specific value depending on the height, spacing, and apex angle of the pyramids.

[0055] Graphene layer 2 is disposed on Si substrate 1. As an interface control layer, graphene layer 2 can form a high-quality intermediate transition interface between Si and AlN to reduce the interface energy level. At the same time, it provides a "decoupled" virtual lattice template for subsequent epitaxial layers, improving GaN lattice mismatch and stress release.

[0056] A high-temperature AlN initiation layer 3 is disposed on the graphene layer 2. The high-temperature AlN initiation layer 3 is used to prevent silicon erosion, and because its lattice constant is close to that of GaN, it serves as a bridge layer for lattice transition, facilitating subsequent step-like AlN formation. x Ga 1-x N-buffer layer 4 provides a lattice transition layer.

[0057] Stepped Al x Ga 1-x N buffer layer 4 is disposed on the high-temperature AlN initiation layer 3. Stepped Al x Ga 1-x The N buffer layer 4 adopts a gradient design of aluminum composition, and releases stress step by step through a multi-layer gradual change to achieve a smooth transition from AlN to GaN lattice. This not only significantly reduces the through dislocation density, but also improves the lattice matching degree between the buffer layer and the active layer and the overall thermodynamic stability.

[0058] The N-type GaN active layer 5 is set in a stepped Al... x Ga 1-x N buffer layer 4.

[0059] Stepped Al y GaN barrier layer 6 is disposed on N-type GaN active layer 5.

[0060] Electron blocking layer 7 is set in a stepped Al y GaN barrier layer 6.

[0061] N-type GaN active layer 5, stepped Al y The heterostructure system formed by the GaN barrier layer 6 and the electron blocking layer 7 constructs an ideal two-dimensional electron gas channel (2DEG) with high electron mobility and high current carrying capacity. The stepped barrier layer structure further optimizes the interface electric field distribution, improving the stability and thermal reliability of the 2DEG.

[0062] A p-type GaN contact layer 8 is disposed on the electron blocking layer 7. The p-type GaN contact layer 8 is used to form an ohmic contact electrode structure.

[0063] Passivation layer 9 is disposed on p-type GaN contact layer 8. Passivation layer not only prevents environmental oxidation and improves device lifetime, but also suppresses the interference of surface states on electron transport behavior, thereby improving device consistency and long-term reliability.

[0064] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0065] (1) In the embodiments of the present invention, a stepped Al is designed. x Ga 1-x The N-buffer layer gradually changes the aluminum composition in the buffer layer, progressively transitioning stress and lattice mismatch, releasing stress in a timely manner, and improving the performance and reliability of semiconductor devices.

[0066] (2) In this embodiment of the invention, multiple pyramid-shaped nanostructures are provided on the surface of the silicon substrate. By introducing a non-planar growth interface, stress is effectively dispersed and vertical dislocation penetration is suppressed, reducing cracks or warping caused by stress accumulation. At the same time, the three-dimensional microstructure can also provide polycrystalline growth sites, promote the self-organization and nucleation of the epitaxial layer and improve the crystal quality, thus laying a solid foundation for the high-quality growth of the subsequent graphene layer and epitaxial material.

[0067] (3) In this embodiment of the invention, the graphene layer is used as an intermediate layer, which can reduce the interface energy level, improve the GaN lattice mismatch and stress release. The virtual substrate characteristics of the graphene layer provide a flexible buffer platform for GaN epitaxial growth, which helps to suppress dislocation propagation and crack generation, thereby improving the crystal quality and structural integrity of the epitaxial layer.

[0068] (4) In this embodiment of the invention, a high-temperature AlN initiation layer is used, which can suppress the chemical reaction of silicon at high temperatures, significantly reduce the dislocation density, and provide a high-quality initial template with a lattice closer to GaN, thus facilitating subsequent step-type AlN initiation. x Ga 1-x The N-buffer layer provides a stable lattice transition platform, effectively reducing interface dislocation density and stress concentration, thereby improving the overall crystal quality and reliability of the epitaxial structure.

[0069] Reference manual attached Figure 2 This illustrates a stepped Al provided by an embodiment of the present invention. x Ga 1-x A schematic diagram of the N-buffer layer.

[0070] In one possible implementation, stepped Al x Ga 1-x N buffer layer 4 includes the first level Al 0.73 Ga 0.27 N-buffer layer 41, second-level Al 0.47 Ga 0.53 N-buffer layer 42, third level Al0.34 Ga 0.66 N buffer layer 43, fourth level Al 0.21 Ga 0.79 N buffer layer 44 and fifth level Al 0.12 Ga 0.88 N buffer layer 45.

[0071] Optionally, the first level AI 0.73 Ga 0.27 The thickness of the N buffer layer 41 is 70 nm, and the second-stage Al 0.47 Ga 0.53 The thickness of the N buffer layer 42 is 100 nm, and the third-level Al 0.34 Ga 0.66 The thickness of the N buffer layer 43 is 120 nm, and the fourth-level Al 0.21 Ga 0.79 The thickness of the N buffer layer 44 is 200 nm, and the fifth-level Al 0.12 Ga 0.88 The thickness of the N buffer layer 45 is 380 nm.

[0072] In this embodiment of the invention, different aluminum contents and thicknesses are sequentially set, from Al 0.73 Ga 0.27 N gradually transitions to Al 0.12 Ga 0.88 Nitrogen (N) enables gradual control of lattice constant and stress, effectively mitigating stress concentration issues caused by lattice mismatch and thermal expansion differences between GaN and Si. By progressively decreasing the x-value, the lattice parameters gradually approach those of GaN, helping to suppress the generation of through dislocations and the accumulation of interface defects. The progressively increasing thickness design also reflects a balance between stress release and nucleation stability, ensuring that each buffer layer functions as both a bridge between the transition lattice and a buffer for absorbing and transmitting stress, thereby significantly improving the overall crystal quality and structural integrity of the epitaxial structure.

[0073] Reference manual attached Figure 3 This illustrates a stepped Al provided by an embodiment of the present invention. y Schematic diagram of the GaN barrier layer.

[0074] In one possible implementation, stepped Al y GaN barrier layer 6 includes the first-level Al 0.4 GaN barrier layer 61, second-stage AlGaN gradient barrier layer 62, and third-stage Al 0.2 In the GaN barrier layer 63, the Al molar fraction in the second-stage AlGaN graded barrier layer 62 gradually decreases from 40% to 20%.

[0075] It should be noted that the first layer uses Al with an aluminum content of 40%. 40 The aluminum ratio in GaN is designed to provide sufficient variation during the transition of the lattice constant for better docking with subsequent graded layers. The high aluminum content gives this layer a high polarization field, effectively increasing carrier density and thus improving electron mobility. The second-level layer uses a graded aluminum molar fraction, gradually decreasing from 40% to 20%. This gradient design is crucial for achieving a smooth transition of the lattice constant. Gradually reducing the aluminum content effectively reduces lattice stress caused by differences in aluminum content and makes the structure more uniform. The third-level layer has an aluminum content of 20%, close to the aluminum molar fraction of GaN, further achieving lattice matching with the GaN layer. By reducing the aluminum content, Al... 0.2 The GaN layer can form a better lattice connection with the GaN active layer, avoiding the effects of thermal expansion mismatch.

[0076] Optionally, the first level AI 0.4 The GaN barrier layer 61 has a thickness of 30 nm, the second-stage AlGaN graded barrier layer 62 has a thickness of 200 nm, and the third-stage Al... 0.2 The thickness of the GaN barrier layer 63 is 30 nm.

[0077] It should be noted that the thickness of the first-stage barrier layer is 30 nm. This relatively thin layer is designed primarily to provide an initial polarization electric field in the epitaxial structure while avoiding excessive stress accumulation. The thickness of the second-stage barrier layer is 200 nm, a significant increase compared to the first stage. The main function of this layer is to slowly adjust the lattice constant and release stress by gradually varying the aluminum molar fraction (from 40% to 20%). The thickness of the third-stage barrier layer is again reduced to 30 nm. This thinner layer is designed to achieve better matching with the GaN layer and maintain a smaller polarization effect, thereby improving carrier injection efficiency and electron mobility.

[0078] In this embodiment of the invention, through a stepped Al y GaN barrier layer 6 can form a high-quality two-dimensional electron gas (2DEG) in AlGaN / GaN heterojunction, the first-stage Al 0.4 The GaN barrier layer 61 provides a strong polarization field to enhance carrier density, while the graded layer smooths band changes, reduces interface potential abrupt changes and carrier scattering, and simultaneously releases lattice stress caused by differences in aluminum content. The third Al layer... 0.2 The GaN barrier layer 63 helps to construct a stable top electron control region. The stepped barrier formed by the three layers not only improves electron mobility and device stability, but also enhances tolerance to thermal stress and structural defects, which is beneficial for realizing high-performance, high-reliability power or RF devices.

[0079] Reference manual attached Figure 4 The diagram illustrates the band structure of an indium-component gradient sub-well according to an embodiment of the present invention.

[0080] In one possible implementation, an indium-component gradient sub-well structure is formed in the N-type GaN active layer 5, consisting of five pairs of alternately stacked InGaN well layers and GaN barrier layers.

[0081] Optionally, the band structure of the indium-component gradient sub-well exhibits an asymmetric trapezoidal shape.

[0082] Optionally, the indium component is located near the stepped Al x Ga 1-x The band gradient thickness on all four sides of the N-buffer layer is 0.5 nm, and the band thickness in the middle of the indium-component gradient sub-well is maintained at 1.1 nm. The indium-component gradient sub-well is close to the stepped Al. y The band gradient thickness on the 6th side of the GaN barrier layer is 1.3 nm.

[0083] In this embodiment of the invention, the asymmetric bandgap design results in a steeper potential barrier (gradual thickness 0.5 nm) near the buffer layer, which helps to limit carrier leakage to the substrate. Meanwhile, the gentler transition (gradual thickness 1.3 nm) near the barrier layer helps to improve carrier injection efficiency and recombination probability, while maintaining a stable bandwidth (1.1 nm) in the middle provides a stable excited-state region. This trapezoidal distribution optimizes the bandgap and quantum confinement effects, enhances the overlap of electron and hole wave functions, and thus significantly improves the luminous intensity and response performance of the epitaxial structure in light-emitting devices (such as LEDs) or high-speed electronic devices, while suppressing undesirable effects such as thermal escape and nonradiative recombination.

[0084] Reference manual attached Figure 5 The diagram shows a flow chart of a preparation method provided by an embodiment of the present invention.

[0085] This invention provides a preparation method for preparing the above-mentioned gallium nitride-based epitaxial structure. The preparation method includes:

[0086] S1: Construct a simulation model of gallium nitride-based epitaxial structure.

[0087] Specifically, the simulation model of gallium nitride-based epitaxial structure is described by the Poisson equation, the continuity equations for electrons and holes, and the drift-diffusion current equations for electrons and holes.

[0088] The Poisson equation is used to calculate the potential distribution within a semiconductor device, and its expression is:

[0089]

[0090] in, ε This represents the dielectric constant of a semiconductor. This represents gradient operation. Represents electric potential, q Represents the fundamental charge of an electron. p Represents hole density. n Represents electron density, N D Indicates the donor concentration of ionized donors. N A This indicates the concentration of ionized acceptors.

[0091] The continuity equations for electrons and holes describe the conservation of charge, as follows:

[0092]

[0093] in, J n This represents the current density of electrons. J p This represents the current density of holes. R n Indicates the recombination rate of electrons. R p This represents the recombination rate of holes. G n Indicates the rate of electron generation. G p This represents the hole generation rate. This represents the partial derivative operation. t Indicates time.

[0094] The drift-diffusion current equations for electrons and holes are as follows:

[0095]

[0096] in, μ n Indicates electron mobility. μ p This represents the hole mobility. D n The diffusion coefficient of electrons is represented by... D p This represents the diffusion coefficient of holes.

[0097] S2: Determine the breakdown voltage of gallium nitride-based epitaxial structures under various structural parameters through simulation models.

[0098] The breakdown voltage refers to the maximum voltage that a gallium nitride-based epitaxial structure can withstand under reverse bias. If this value is exceeded, the material will undergo avalanche breakdown or tunneling breakdown, resulting in the insulation layer becoming conductive and the current increasing dramatically.

[0099] S3: Determine the optimal structural parameters of the gallium nitride-based epitaxial structure based on the breakdown voltage under various structural parameters.

[0100] Optionally, structural parameters include: the thickness of each layer, the size parameters of the pyramid-shaped nanostructure on the Si substrate, and the stepped Al... x Ga 1-x Doping concentration in the N-buffer layer, step-like Al y Doping concentration in the GaN barrier layer.

[0101] In one possible implementation, S3 specifically involves determining the optimal structural parameters of the gallium nitride-based epitaxial structure using the honey badger optimization algorithm based on the breakdown voltage under various structural parameters.

[0102] The Honey Badger Algorithm (HBA) is a swarm intelligence optimization algorithm that simulates the foraging behavior of honey badgers in the wild, possessing strong global exploration and local exploitation capabilities. This invention employs a novel Honey Badger Algorithm to determine the optimal structural parameters of gallium nitride-based epitaxial structures.

[0103] Specifically, the breakdown voltage can be used as the fitness function of the honey badger optimization algorithm.

[0104] Honey badger individuals are initialized using a Sine chaotic map. Each honey badger individual represents a feasible set of structural parameters, and each honey badger individual consists of multiple dimensional components, each component representing a structural parameter.

[0105]

[0106] in, x i Indicates the first i The initial location of each individual honey badger. lb i Indicates the first i A lower bound for a feasible solution. ub i Indicates the first i An upper bound for a feasible solution. y i Indicates the first i The chaos number corresponding to each individual honey badger y i-1 Indicates the first i -1 chaos number corresponding to individual honey badgers μ This represents the chaos parameter, which is typically set to 0.99.

[0107] It should be noted that the structural parameters represented by each component specifically refer to the thickness of each layer mentioned above, the size parameters of the pyramid-shaped nanostructure on the Si substrate, and the stepped Al... xGa 1-x Doping concentration in the N-buffer layer, step-like Al y Doping concentration in the GaN barrier layer.

[0108] In this embodiment of the invention, the initial position of honey badger individuals is generated using Sine chaotic mapping, which has stronger population diversity and ergodicity. It can effectively avoid the initial solution distribution being concentrated or repeated, improve the early global exploration capability, lay a broader search foundation for subsequent searches, and help to escape local optima.

[0109] An elite selection strategy was adopted, retaining the top half of the honey badger individuals with the highest fitness values ​​and discarding the other half to filter the initial population.

[0110] In this embodiment of the invention, half of the honey badger individuals with the highest fitness values ​​are retained, which is equivalent to introducing a "survival of the fittest" mechanism in evolution, ensuring that excellent genes are inherited, while reducing the interference of inferior solutions with the search direction, and significantly improving the stability and convergence efficiency of the search.

[0111] During the mining phase, random numbers are introduced. r 1. Select in parallel between searching around the globally optimal individual or the current individual, and update the individual's position:

[0112] when hour:

[0113] ;

[0114] when hour:

[0115] .

[0116] in, Indicates the first t At the +1st iteration, the... i The location of an individual honey badger ω t Indicates the first t Nonlinear weighting factor in the next iteration Indicates the first t During the nth iteration i The location of an individual honey badger x best This indicates the location of the globally optimal individual. F This indicates the search direction control parameter. β This represents an individual honey badger's ability to obtain food, and is generally taken as a fixed value of 6. I i Indicates the first i The strength factor of an individual honey badger α Represents density factor, r 1、r 2. r 3 and r 4 represents a random number between 0 and 1.

[0117] In this embodiment of the invention, random numbers are used. r 1. By choosing between searching around the globally optimal individual or the current individual in parallel, the search path becomes both directional and perturbative, balancing global exploration and local development, and effectively enhancing the ability to escape local optima.

[0118]

[0119] in, t Indicates the current iteration number. T This indicates the maximum number of iterations.

[0120] In this embodiment of the invention, the weights gradually decrease as the iterations proceed, maintaining a strong exploratory nature in the early stages and focusing on fine-grained local searches in the later stages. This reflects a time-adaptive search strategy, preventing premature convergence while ensuring the accuracy of later searches.

[0121]

[0122] in, r 5 represents a random number between 0 and 1. S Indicates the intensity of concentration.

[0123] In this embodiment of the invention, the search intensity is adaptively adjusted according to the distance between an individual and the global optimal solution. When the individual is far from the optimal solution, the exploration force is enhanced, and when the individual is close, the search amplitude is reduced, preventing individuals from clustering in the optimal region too early and improving the synergistic efficiency of global search and local convergence.

[0124]

[0125] in, C represents the density constant, and exp represents the exponential function with the natural constant as the base.

[0126] In this embodiment of the invention, the "focusing degree" of the search area is controlled. Initially, a large-scale search is allowed, and later the honey badger is encouraged to concentrate near the optimal solution, gradually focusing the search space and improving the accuracy of the final solution, which meets the optimization requirement of approaching the global optimum layer by layer.

[0127]

[0128] in, r 6 represents a random number between 0 and 1.

[0129] In this embodiment of the invention, directional perturbation is introduced to avoid the search direction becoming fixed, enhance the diversity of search paths, help prevent getting stuck in symmetric solutions or infinite loop paths, and further improve the robustness and adaptability of the algorithm.

[0130] During the honey-collecting phase, update individual location:

[0131]

[0132] in, r 7 represents a random number between 0 and 1.

[0133] In this embodiment of the invention, by moving the current individual toward the global optimal solution and controlling the movement amplitude with an appropriate perturbation factor, an efficient local fine search is achieved, ensuring that the optimal structural parameters are found quickly near the global optimum, and the optimization results are more accurate.

[0134] Update the fitness values ​​of each individual honey badger and the global best individual.

[0135] Determine if the current iteration count has reached the maximum iteration count. If yes, output the set of structural parameters represented by the honey badger individual with the highest fitness. Otherwise, return to continue iterating.

[0136] In this embodiment of the invention, a honey badger optimization algorithm based on breakdown voltage is used to intelligently optimize the multilayer parameters (such as composition ratio, layer thickness, buffer layer structure, etc.) of gallium nitride-based epitaxial structures. This enables efficient searching of the optimal combination of structural parameters that maximizes the breakdown voltage within a complex, high-dimensional design space. The greatest advantage of this approach is that it avoids the inefficient methods of relying on experience or trial and error in traditional designs, achieving global optimization and adaptive tuning of structural performance. This significantly improves the electrical performance and reliability of the epitaxial structure, while shortening the development cycle and reducing manufacturing costs.

[0137] S4: According to the optimal structural parameters, surface structuring treatment was performed on Si substrate 1 to prepare multiple pyramid-shaped nanostructures on the surface of Si substrate 1.

[0138] Optionally, multiple pyramid-shaped nanostructures are fabricated using photolithography. Specifically, a layer of photoresist is first uniformly coated on the surface of a Si substrate. Using an ultraviolet (UV) exposure device, light is passed through the photoresist through a mask to define a pyramid-shaped pattern. During exposure, the photosensitive material undergoes a chemical reaction in the exposed areas, forming soluble regions. After exposure, the unexposed areas of photoresist are removed using a developer to form the desired pyramid-shaped pattern. The unprotected silicon surface portions are then removed using dry etching (e.g., plasma etching) or wet etching (e.g., solutions such as hydrofluoric acid) to form the pyramid-shaped structure.

[0139] S5: Graphene layer 2 is deposited on Si substrate 1 by chemical vapor deposition.

[0140] S6: Increase the growth temperature to the high-temperature region and deposit a high-temperature AlN initiation layer 3 on the graphene layer 2 through chemical vapor deposition.

[0141] S7: Stepped Al formations were deposited on the high-temperature AlN initiation layer 3 via chemical vapor deposition. x Ga 1-x N buffer layer 4.

[0142] S8: Through chemical vapor deposition, in a stepped Al x Ga 1-x An N-type GaN active layer 5 is formed by depositing on the N buffer layer 4.

[0143] S9: Stepped Al deposited on the N-type GaN active layer 5 via chemical vapor deposition. y GaN barrier layer 6.

[0144] S10: Deposited via chemical vapor deposition on a stepped Al... y An electron blocking layer 7 is deposited on the GaN barrier layer 6.

[0145] S11: A P-type GaN contact layer 8 is deposited on the electron blocking layer 7 by chemical vapor deposition.

[0146] S12: Perform surface passivation treatment on the P-type GaN contact layer 8 and deposit passivation layer 9.

[0147] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A gallium nitride based epitaxial structure, characterized by, Comprise: a Si substrate with a structured surface, the surface of the Si substrate is provided with a plurality of pyramid-shaped nanostructures; a graphene layer disposed on the Si substrate; a high-temperature AlN starting layer disposed on the graphene layer; staircase Al x Ga 1-x N buffer layer disposed on the high-temperature AlN initiation layer; the staircase Al x Ga 1-x N buffer layer comprises a first-stage Al 0.73 Ga 0.27 N buffer layer, a second-stage Al 0.47 Ga 0.53 N buffer layer, a third-stage Al 0.34 Ga 0.66 N buffer layer, a fourth-stage Al 0.21 Ga 0.79 N buffer layer, and a fifth-stage Al 0.12 Ga 0.88 N buffer layer, the first-stage Al 0.73 Ga 0.27 N buffer layer, the second-stage Al 0.47 Ga 0.53 N buffer layer, the third-stage Al 0.34 Ga 0.66 N buffer layer, the fourth-stage Al 0.21 Ga 0.79 N buffer layer, and the fifth-stage Al 0.12 Ga 0.88 N buffer layer; an aluminum component of the staircase Al An N-type GaN active layer is disposed on the stepped Al x Ga 1-x N buffer layer; five pairs of InGaN potential well layers and GaN potential barrier layers are alternately stacked in the N-type GaN active layer to form an indium composition gradient quantum well structure, and the energy band of the indium composition gradient quantum well changes in an asymmetric trapezoidal shape. staircase Al y a GaN barrier layer disposed on the N-type GaN active layer; the staircase Al y The GaN barrier layer comprises a first-stage Al 0.4 The GaN barrier layer, a second-stage AlGaN graded barrier layer and a third-stage Al 0.2 The GaN barrier layer, the mole fraction of Al in the second-stage AlGaN graded barrier layer is graded from 40% to 20%. an electron blocking layer disposed on the stepped Al y GaN barrier layer; a P-type GaN contact layer disposed on the electron blocking layer; and a passivation layer disposed on the P-type GaN contact layer. Comprise the following steps:

2. The gallium nitride based epitaxial structure of claim 1 wherein, the first-stage Al 0.73 Ga 0.27 N buffer layer has a thickness of 60-80 nm, the second-stage Al 0.47 Ga 0.53 N buffer layer has a thickness of 90-110 nm, the third-stage Al 0.34 Ga 0.66 N buffer layer has a thickness of 110-130 nm, the fourth-stage Al 0.21 Ga 0.79 N buffer layer has a thickness of 190-210 nm, the fifth-stage Al 0.12 Ga 0.88 N buffer layer has a thickness of 370-390 nm.

3. The gallium nitride based epitaxial structure of claim 1 wherein, The first-stage Al 0.4 The thickness of the GaN barrier layer is 20-40 nm, the thickness of the second-stage AlGaN graded barrier layer is 190-210 nm, and the thickness of the third-stage Al 0.2 The thickness of the GaN barrier layer is 20-40 nm.

4. The gallium nitride based epitaxial structure of claim 1 wherein, The indium composition gradient quantum well near the stepped Al x Ga 1-x The band gap gradient thickness near the GaN buffer layer side is 0.4-0.6 nm, the band gap maintaining thickness in the middle of the indium composition gradient quantum well is 1.0-1.2 nm, and the band gap gradient thickness near the stepped Al y GaN barrier layer side is 1.2-1.4 nm.

5. A method of producing a gallium nitride based epitaxial structure as claimed in any one of claims 1 to 4, characterised by, S1, constructing the simulation model of the gallium nitride-based epitaxial structure, the simulation model describes the potential distribution, charge conservation and carrier current density in the semiconductor device through Poisson equation, continuity equation of electrons and holes and drift-diffusion current equation of electrons and holes; S2, determining the breakdown voltage of the gallium nitride-based epitaxial structure under various structure parameters through the simulation model, the breakdown voltage is the maximum voltage value that the structure can withstand under reverse bias; S3, determining the optimal structure parameters of the gallium nitride-based epitaxial structure according to the breakdown voltage under various structure parameters, wherein the step of determining the optimal structure parameters of the gallium nitride-based epitaxial structure comprises determining by the meerkat optimization algorithm; S4, according to the optimal structure parameters, surface structuring treatment is carried out on the Si substrate to prepare a plurality of pyramid-shaped nanostructures; S5, depositing a graphene layer on the Si substrate by chemical vapor deposition; S6, increasing the growth temperature to 1000-1200℃, depositing a high-temperature AlN starting layer on the graphene layer by chemical vapor deposition; S11, depositing a P-type GaN contact layer on the electron blocking layer by chemical vapor deposition; S7, depositing a stepwise AlN buffer layer on the high-temperature AlN starting layer by chemical vapor deposition x Ga 1-x N buffer layer; S8, via chemical vapor deposition on the stepped Al x Ga 1-x An N-type GaN active layer is deposited on the N-buffer layer; S9, depositing a step AlGaN barrier layer by chemical vapor deposition on the N-type GaN active layer y GaN barrier layer; S10, depositing an electron blocking layer on the stepped Al y GaN barrier layer by chemical vapor deposition; S12, and surface passivation treatment is carried out on the P-type GaN contact layer to deposit a passivation layer. The meerkat optimization algorithm comprises initializing meerkat individuals by Sine chaotic mapping, each meerkat individual represents a set of structure parameters, and the initialization generates the initial position of the meerkat individual by Sine chaotic mapping.

6. The method of claim 5, wherein the method further comprises: The structural parameters include: the thickness of each layer in the gallium nitride-based epitaxial structure, the size parameters of the pyramid-shaped nanostructure on the Si substrate, and the stepped Al... x Ga 1-x The doping concentration in the N buffer layer and the stepped Al y Doping concentration in the GaN barrier layer.

7. The method of claim 5, wherein the method further comprises the step of: ​ ​

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