Multilayer epitaxial wafer and preparation process thereof

Abstract

The invention provides a multilayer epitaxial wafer and a preparation process thereof. The crystal orientation is lt; 100 gt; a plurality of epitaxial layers are stacked on the N-type conductive substrate in sequence, the thicknesses of the epitaxial layers are reduced in sequence, and the resistivity of the epitaxial layers is increased in sequence; and the epitaxial total film thickness is 9.5-10.5 [mu] m. The limitation of a traditional single-layer or double-layer epitaxial wafer is broken through, and stable preparation of a four-layer epitaxial structure is realized by adopting a processing technology of epitaxially growing a high-resistance N-type phosphorus-doped multi-layer epitaxial layer on a low-resistance N-type arsenic-doped silicon substrate; the epitaxial wafer is monitored layer by layer, so that the film thickness and the resistivity of each layer can be accurately controlled; a layer-by-layer film thickness decreasing processing method is adopted, so that interference between epitaxial middle layers can be effectively reduced, and the consistency and yield of product quality are improved; product performance is improved, and requirements of high-end electronic devices are met.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor silicon wafer preparation, and particularly relates to a multilayer epitaxial wafer and a preparation process thereof, in particular to a semiconductor epitaxial wafer with a four-layer epitaxial structure and an accurate control preparation method thereof. BACKGROUND

[0002] An epitaxial wafer is an important semiconductor material and is widely used in the manufacturing process of electronic devices; with the rapid development of the semiconductor industry, the epitaxial wafer market also presents great potential and opportunities. Epitaxy is to grow a new single crystal layer with a required conductivity type, resistivity, thickness and lattice structure along the original crystal direction on a single crystal substrate. In a broad sense, epitaxy is also a kind of CVD process, and the substrate on which the epitaxial layer is grown is called an epitaxial wafer, which is a material for manufacturing semiconductor devices by depositing a thin film on a substrate wafer.

[0003] At present, the common epitaxial wafers on the market are mainly single-layer or double-layer products. However, with the improvement of the performance requirements of electronic devices, the traditional single-layer or double-layer epitaxial wafers cannot meet the requirements, and it is urgent to develop multilayer epitaxial wafers to improve the product performance and market competitiveness. The main technical difficulties of multilayer epitaxy are the accurate control of the thickness and resistivity of each layer and the control of the interface quality between layers. SUMMARY

[0004] The application provides a multilayer epitaxial wafer and a preparation process thereof, which solves the technical problem that the existing preparation process can only prepare single-layer or double-layer epitaxial wafers and cannot accurately control the thickness and resistivity of each layer.

[0005] To solve at least one of the above technical problems, the technical solution adopted by the application is:

[0006] A multilayer epitaxial wafer, which is stacked with multiple epitaxial layers on a N-type conductive substrate with a crystal direction of <100> in sequence, the thickness of each epitaxial layer decreases in sequence and the resistivity thereof increases in sequence; and the total film thickness of the epitaxy is 9.5-10.5 μm.

[0007] Further, the epitaxial layer is four layers, the dopant is phosphorus, and the parameters of each layer are as follows:

[0008] The film thickness of the first epitaxial layer is 3.8-4.2 μm, and the resistivity is 0.092-0.108 Ω.cm;

[0009] The film thickness of the second epitaxial layer is 2.85-3.15 μm, and the resistivity is 0.184-0.216 Ω.cm;

[0010] The film thickness of the third epitaxial layer is 1.9-2.1 μm, and the resistivity is 0.276-0.324 Ω.cm;

[0011] The fourth epitaxial layer has a film thickness of 0.95-1.05 μm and a resistivity of 1.84-2.16 Ω·cm.

[0012] Further, the substrate is an N-type silicon wafer with a diameter of 200±0.2 mm, a thickness of 705-745 μm, and an R-type chamfer of 22°; the substrate is doped with arsenic, and has a resistivity of 0.0017-0.0025 Ω·cm.

[0013] Further, the back sealing structure of the substrate includes a POLY layer close to the silicon wafer and an LTO layer on the POLY layer, and the thickness of the POLY layer is greater than that of the LTO layer.

[0014] Preferably, the total thickness of the back sealing structure is

[0015] A preparation process of the multi-layer epitaxial wafer as described above, comprising the steps of:

[0016] A monitoring wafer of the same specification as the formal substrate is prepared, and layer-by-layer epitaxial growth monitoring is performed on the monitoring wafer to obtain multi-layer epitaxial process parameters meeting the standard requirements.

[0017] Based on the obtained multi-layer epitaxial process parameters of the monitoring wafer, multi-layer epitaxial growth is sequentially performed on the formal substrate to obtain a finished multi-layer epitaxial wafer.

[0018] The finished multi-layer epitaxial wafer is subjected to parameter detection, and if qualified, it is packaged and shipped; if unqualified, the multi-layer epitaxial process parameters of the monitoring wafer are re-obtained.

[0019] Further, the monitoring wafer is prepared, specifically comprising:

[0020] A silicon wafer of the same specification as the formal substrate is obtained, which is an N-type conductive substrate doped with arsenic, has a <100> crystal orientation, and has a resistivity of 0.0017-0.0025 Ω·cm; and has a diameter of 200±0.2 mm, a thickness of 705-745 μm, and an R-type chamfer of 22°.

[0021] The silicon wafer is subjected to back sealing treatment, and the thickness of the back sealing structure is

[0022] Further, the back sealing structure includes a POLY layer and an LTO layer sequentially grown on the back surface of the silicon wafer, and the thickness of the POLY layer is greater than that of the LTO layer.

[0023] Further, the layer-by-layer epitaxial growth monitoring on the monitoring wafer specifically comprises:

[0024] The epitaxial layer is grown by using a processing mode of decreasing film thickness layer by layer, and the resistivity increases layer by layer;

[0025] The film thickness and resistivity of each layer are tested after the growth of each layer;

[0026] When the measured film thickness and resistivity of each layer meet the target film thickness and target resistivity, the growth of the next layer can be performed until the epitaxial layer growth is completed.

[0027] When the film thickness and / or resistivity of any layer does not meet the requirements, the epitaxial growth is restarted.

[0028] Further, the epitaxial layer is four layers, and the dopant is phosphorus. The parameters of each layer of the epitaxial layer are as follows:

[0029] When the first epitaxial layer is grown, the flow rate of SiH4 is 300 sccm, the flow rate of PH3 is 2.0 sccm, the growth time is 8-10 min, and the growth temperature is 1100°C. The obtained film thickness is 3.8-4.2 μm, and the resistivity is 0.092-0.108 Ω·cm.

[0030] When the second epitaxial layer is grown, the flow rate of SiH4 is 250 sccm, the flow rate of PH3 is 1.0 sccm, the growth time is 6-8 min, and the growth temperature is 1080°C. The obtained film thickness is 2.85-3.15 μm, and the resistivity is 0.184-0.216 Ω·cm.

[0031] When the third epitaxial layer is grown, the flow rate of SiH4 is 200 sccm, the flow rate of PH3 is 0.67 sccm, the growth time is 4-6 min, and the growth temperature is 1070°C. The obtained film thickness is 1.9-2.1 μm, and the resistivity is 0.276-0.324 Ω·cm.

[0032] When the fourth epitaxial layer is grown, the flow rate of SiH4 is 150 sccm, the flow rate of PH3 is 0.1 sccm, the growth time is 2-3 min, and the growth temperature is 1060°C. The obtained film thickness is 0.95-1.05 μm, and the resistivity is 1.84-2.16 Ω·cm.

[0033] The multi-layer epitaxial wafer provided in the present application adopts a design scheme of decreasing film thickness layer by layer, reduces the interference between layers, and improves the consistency of products. The processing technology mode of epitaxially growing a high-resistance N-type phosphorus (P) doped multi-layer epitaxial layer on a low-resistance N-type arsenic (As) doped silicon substrate is adopted to break the limitation of traditional single-layer or double-layer epitaxial wafers, and a stable four-layer epitaxial structure is realized.

[0034] The application provides a preparation process of a multilayer epitaxial wafer, which can accurately control the thickness and resistivity of each layer by monitoring the epitaxial wafer layer by layer, and can effectively reduce the interference between layers in the epitaxy, improve the consistency and yield of product quality, improve the product performance, and meet the demand of high-end electronic devices. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram of a multilayer epitaxial wafer in the application;

[0036] Figure 2 is a preparation process flow chart of the multilayer epitaxial wafer in the application;

[0037] Figure 3 is a process flow chart of step S1 in the application.

[0038] In the drawings:

[0039] 10, silicon substrate 20, back sealing structure 21, POLY layer

[0040] 22, LTO layer 30, epitaxial layer 31, first epitaxial layer

[0041] 32, second epitaxial layer 33, third epitaxial layer 34, fourth epitaxial layer DETAILED DESCRIPTION

[0042] The application will be described in detail below in combination with the drawings and specific embodiments.

[0043] The application provides a multilayer epitaxial wafer, as shown in the drawings, which comprises a silicon substrate 10 as a substrate, a back sealing structure 20 on the back surface thereof, and a multilayer epitaxial layer 30 grown on the front surface thereof. Figure 1 The specific structure is as follows:

[0044] The silicon substrate 10 is used as a substrate, and is an N-type conductive silicon wafer, the crystal direction of which is <100>, and the V groove opening is <100>. The diameter is 200±0.2mm, the thickness is 705-745μm, and the R-type chamfer is 22°. The doping agent of the substrate is arsenic (As), and the resistivity range of the substrate is 0.0017-0.0025Ω·cm, so as to avoid the occurrence of subsequent epitaxial particle defects.

[0045] This is because if the resistivity of arsenic-doped N-type silicon substrate is greater than 0.0025 Ω·cm, local point defects are easily generated in the subsequent epitaxial growth process, resulting in poor surface particles of the epitaxial layer; and also cause the gettering effect of the back sealing structure to be insufficient, which cannot balance the arsenic effect and the epitaxial quality. In the embodiment, the epitaxial layer dopant is phosphorus (P) and the substrate dopant is arsenic (As), which is an N+N type homoepitaxial wafer. If the resistivity is less than 0.0017 Ω·cm, self-doping effect will occur, that is, arsenic atoms in the substrate diffuse to the epitaxial layer, affecting the resistivity control of the epitaxial layer.

[0046] Therefore, the substrate resistivity is in the range of 0.0017-0.0025 Ω·cm, which not only reduces the lattice stress caused by uneven arsenic doping, reduces the defect density, and improves the quality of the epitaxial layer; but also ensures the conductivity of the substrate, reduces the influence of self-doping on the resistivity of the epitaxial layer, and does not affect the gettering effect of the back sealing.

[0047] The back sealing structure 20 is used for gettering and preventing self-doping phenomenon. It includes a POLY layer 21 close to the silicon substrate 10 and an LTO layer 22 located on the POLY layer 21. A chemical vapor deposition method is used to deposit a POLY layer 21 on the back of the silicon substrate 10, and the metal impurities in the substrate are adsorbed through the grain boundaries of the polysilicon, that is, gettering is achieved, and the thermal stress is also buffered. Then, an LTO layer 22 is deposited on the surface of the POLY layer as a sealing layer to prevent the arsenic (As) dopant in the substrate from volatilizing during the high-temperature process of epitaxial growth, and to isolate the external pollution.

[0048] When the back sealing substrate is performed, a POLY layer 21 must be deposited and grown first, and then an LTO layer 22 is deposited and grown. The order cannot be reversed, otherwise the LTO layer 22 will hinder the gettering effect of the POLY layer 21. The lattice matching of the POLY layer 21 and the silicon substrate is good, and direct contact can reduce interface defects; the LTO layer 22 acts as a dielectric layer and needs to be covered on the POLY layer 21 to effectively block impurity diffusion. During high-temperature epitaxy, the POLY layer 21 first absorbs the substrate impurities, and the LTO layer 22 then isolates the external environment, forming a double protection.

[0049] When the back sealing structure 20 is grown, the film thickness is measured by using QS200 after each layer is grown, and the total thickness of the two films is and the thickness of the POLY layer 21 is greater than the thickness of the LTO layer 22. Preferably, the thickness of the POLY layer 21 is the thickness of the LTO layer 22 is

[0050] The epitaxial layer 30 is formed by sequentially stacking four epitaxial layers on the front surface of the N-type conductive substrate, each epitaxial layer having a thickness decreasing and a resistivity increasing in turn, and the total film thickness of the epitaxial layer being 9.5-10.5 μm. Specifically, the four epitaxial layers are all doped with phosphorus, and include a first epitaxial layer 31, a second epitaxial layer 22, a third epitaxial layer 23 and a fourth epitaxial layer in turn from the substrate.

[0051] Further, the growth of each epitaxial layer needs to be monitored in terms of the film thickness and the resistivity of the epitaxial layer, respectively, and the process parameters are monitored by using the exclusive processing path. The monitoring path is: epitaxial film growth-epitaxial film thickness measurement-epitaxial resistivity test-4PP four-probe calculation. That is, by layer-by-layer monitoring, the film thickness and the resistivity of each layer are accurately controlled to ensure the consistency and yield of the product.

[0052] According to the adjusted parameters, the four epitaxial layers are grown in turn, and the film thickness of each layer is decreased and the resistivity is increased in turn. The film thickness and the resistivity of each layer are tested immediately after the growth of each layer. The QS200 is used to measure the epitaxial film thickness, and the 4PP (four-probe) is used to measure the resistivity. The film thickness and the resistivity data of each epitaxial layer are recorded, and the parameters of each layer are ensured to meet the design requirements, otherwise the process conditions need to be adjusted. That is, when the film thickness and the resistivity of each layer meet the target requirements, the growth of the next layer can be performed. If either the film thickness or the resistivity of any layer does not meet the requirements, the epitaxial growth is restarted.

[0053] The parameters of each epitaxial layer to be obtained are as follows:

[0054] The film thickness of the first epitaxial layer 31 is 3.8-4.2 μm, and the resistivity is 0.092-0.108 Ω·cm;

[0055] The film thickness of the second epitaxial layer 32 is 2.85-3.15 μm, and the resistivity is 0.184-0.216 Ω·cm;

[0056] The film thickness of the third epitaxial layer 33 is 1.9-2.1 μm, and the resistivity is 0.276-0.324 Ω·cm;

[0057] The film thickness of the fourth epitaxial layer 34 is 0.95-1.05 μm, and the resistivity is 1.84-2.16 Ω·cm.

[0058] After the growth of each epitaxial layer, the film thickness and the resistivity are monitored in real time to ensure consistency with the target values. After the epitaxial growth is completed, the total thickness of the epitaxial layer 30 is tested to ensure that the total film thickness of the epitaxial layer is controlled within 9.5-10.5 μm.

[0059] The thickness of the epitaxial film affects the resistivity range, so the processing method of gradually decreasing the film thickness layer by layer is adopted to reduce the influence of film thickness on resistivity as much as possible. QS200 is used to measure the thickness of the epitaxial film, and 4PP is used to measure the resistivity, so as to obtain accurate film thickness and resistivity products.

[0060] The application breaks the limitation of traditional single-layer or double-layer epitaxial wafer, adopts four-layer epitaxial structure to meet the performance requirements of high-end electronic devices; through layer-by-layer monitoring of the monitoring wafer, accurate control of the film thickness and resistivity of each layer is realized to ensure the consistency and yield of the product; the processing method of gradually decreasing the film thickness layer by layer can effectively reduce the interference between layers and improve the electrical performance of the product; the back sealing structure of POLY layer+LTO layer is adopted to effectively absorb impurities and prevent self-doping phenomenon, thereby improving the product quality; finally, through comprehensive detection of geometric parameters and surface particles, it is ensured that the product meets the requirements of high-end applications.

[0061] A preparation process of a multi-layer epitaxial wafer as described above, comprising the steps of:

[0062] S1, preparing a monitoring wafer with the same specifications as the formal substrate, and performing layer-by-layer epitaxial growth monitoring on the monitoring wafer to obtain multi-layer epitaxial process parameters meeting the standard requirements.

[0063] The epitaxial wafer prepared by the application is prepared by a process mode of epitaxially growing a high-resistance N-type phosphorus (P) doped multi-layer epitaxial layer on a low-resistance N-type arsenic (As) doped silicon substrate, to prepare a power device with high withstand voltage and low on-resistance. Therefore, a suitable conductive substrate is selected to prepare a monitoring wafer; wherein the step process is as shown in Figure 3 .

[0064] S11, obtaining a silicon wafer with the same specifications as the formal substrate.

[0065] The silicon wafer 10 as the formal substrate is an N-type conductive silicon wafer doped with arsenic, with a <100> crystal orientation and a <100> V-groove opening. The diameter is 200±0.2mm, the thickness is 705-745μm, and the R-type chamfer is 22°. The dopant of the substrate is arsenic (As), and considering that high-resistance arsenic can cause local point defects, the resistivity range is selected to be 0.0017-0.0025Ω·cm; the product with a lower resistivity range avoids the occurrence of subsequent epitaxial particle defects.

[0066] The substrate resistivity is in the range of 0.0017-0.0025Ω·cm, which not only reduces the lattice stress caused by uneven arsenic doping, reduces the defect density, and improves the quality of the epitaxial layer; but also ensures the conductivity of the substrate, reduces the influence of self-doping on the resistivity of the epitaxial layer, and does not affect the impurity absorption effect of the back sealing.

[0067] S12, back sealing treatment is performed on the silicon substrate, and the thickness of the back sealing structure is

[0068] A POLY layer 21 is first deposited on the back of the silicon substrate 10 by chemical vapor deposition, and the metal impurities in the substrate are adsorbed through the grain boundaries of the polysilicon, that is, impurity gettering is achieved, and the thermal stress is buffered. Then, an LTO layer 22 is deposited on the surface of the POLY layer as a sealing layer to prevent the arsenic (As) dopant in the substrate from volatilizing during the high-temperature epitaxial growth process, and to isolate the external pollution.

[0069] The back sealing structure 20 is mainly used for impurity gettering and preventing self-doping. The POLY layer 21 has good lattice matching with the silicon substrate, and direct contact can reduce interface defects. The LTO layer 22 is a dielectric layer, which needs to be covered on the POLY layer 21 to effectively block impurity diffusion. During high-temperature epitaxy, the POLY layer 21 first absorbs the substrate impurities, and the LTO layer 22 then isolates the external environment, forming a double protection.

[0070] During the growth of the back sealing structure 20, the film thickness is measured by using QS200 after the growth of each layer, and the total thickness of the two films is , and the thickness of the POLY layer 21 is greater than the thickness of the LTO layer 22. Preferably, the thickness of the POLY layer 21 is , and the thickness of the LTO layer 22 is

[0071] S13, layer-by-layer epitaxial growth monitoring is performed on the monitoring wafer.

[0072] The growth is performed in a layer-by-layer film thickness decreasing manner, and the resistivity increases layer by layer. After the growth of each layer of film, the film thickness and resistivity are tested.

[0073] Specifically, four epitaxial layers with phosphorus as the dopant are sequentially stacked on the front surface of the N-type conductive substrate, and the substrate sequentially includes a first epitaxial layer 31, a second epitaxial layer 22, a third epitaxial layer 23, and a fourth epitaxial layer. The thickness of each epitaxial layer decreases and the resistivity increases in turn, and the total epitaxial film thickness is 9.5-10.5 μm.

[0074] Further, the growth process of each epitaxial layer needs to be monitored for epitaxial film thickness and epitaxial resistivity, respectively, using a dedicated processing path: epitaxial film growth-epitaxial film thickness measurement-epitaxial resistivity test-4PP four-probe calculation, to monitor the process parameters. QS200 is used to measure the epitaxial film thickness, and 4PP (four-probe) is used to measure the resistivity. The film thickness and resistivity data of each epitaxial layer are recorded to ensure that the parameters of each layer meet the design requirements, otherwise the process conditions need to be adjusted. Through layer-by-layer monitoring, the film thickness and resistivity of each layer are accurately controlled to ensure the consistency and yield of the product.

[0075] S14, judging whether the thickness and resistivity of each layer meet the target requirements.

[0076] If the measured thickness and resistivity of each layer meet the target requirements, the growth of the next layer can be performed.

[0077] If the thickness and / or resistivity of any layer do not meet the requirements, the corresponding process conditions are adjusted and the epitaxial growth is restarted until the epitaxial layer growth is completed.

[0078] The dopant phosphorus (P) is easier to achieve resistivity gradient control than the dopant arsenic (As) in the epitaxial growth, and the parameters of each layer of the epitaxial layer obtained are as follows:

[0079] The thickness of the first epitaxial layer 31 is 3.8-4.2 μm, and the resistivity is 0.092-0.108 Ω.cm. During growth, the flow rate of SiH4 is 300 sccm, the flow rate of PH3 is 2.0 sccm, a high-doping and high-growth-rate process is used, the growth time is controlled to be 8-10 min, and the growth temperature is 1100 °C.

[0080] The thickness of the second epitaxial layer 32 is 2.85-3.15 μm, and the resistivity is 0.184-0.216 Ω.cm. During growth, the flow rate of SiH4 is 250 sccm, the flow rate of PH3 is 1.0 sccm, a process with reduced growth rate and reduced doping concentration is used relative to the first epitaxial layer, the growth time is controlled to be 6-8 min, the growth temperature is 1080 °C, and the growth temperature is slightly reduced to reduce interlayer diffusion.

[0081] The thickness of the third epitaxial layer 33 is 1.9-2.1 μm, and the resistivity is 0.276-0.324 Ω.cm. During growth, the flow rate of SiH4 is 200 sccm, the flow rate of PH3 is 0.67 sccm, the growth rate is further reduced and the doping concentration is further reduced, the growth time is controlled to be 4-6 min, and the growth temperature is 1070 °C to optimize the interface quality.

[0082] The thickness of the fourth epitaxial layer 34 is 0.95-1.05 μm, and the resistivity is 1.84-2.16 Ω.cm. Since the layer film is the thinnest, during growth, the flow rate of SiH4 is 150 sccm, the flow rate of PH3 is 0.1 sccm, the doping concentration is reduced to increase the resistivity, the growth time is controlled to be 2-3 min, and the growth temperature is 1060 °C; the thermal budget is reduced to prevent degradation of the lower layer.

[0083] This interlayer transition control method using gradual doping can avoid lattice adaptation caused by interface mutation; and a short pause of 1-2 min is made before the growth of each layer to adjust the gas flow rate and temperature to ensure process stability.

[0084] In-situ monitoring mode is adopted, the film thickness growth rate is monitored in real time by laser interferometer, and the growth temperature is monitored by infrared temperature measurement to ensure temperature uniformity.

[0085] S2, based on the obtained process parameters of the multi-layer epitaxy of the monitoring wafer, sequentially performing multi-layer epitaxy growth on the formal substrate to obtain a finished epitaxial wafer with multiple layers.

[0086] Based on the epitaxial processing parameters of the monitoring wafer, the epitaxial film is grown on the front surface of the formal substrate. During the epitaxial film growth of the formal product, in addition to monitoring the epitaxial film thickness and resistivity according to the monitoring method of the monitoring wafer, the total film thickness of the product epitaxial layer 30 is also measured after the fourth epitaxial layer is completed. The film thickness and resistivity testing instruments are still QS200 and 4PP (four probes), and finally the finished epitaxial wafer is obtained.

[0087] S3, detecting parameters of the finished epitaxial wafer, if qualified, packaging and shipping; if not qualified, reacquiring the multi-layer epitaxy process parameters of the monitoring wafer.

[0088] Finally, the parameters of the finished epitaxial wafer are detected, including testing the geometric parameters and surface particles of the finished epitaxial wafer. Before detection, particles need to be removed by RCA cleaning (SC1 / SC2) or megasonic cleaning.

[0089] Among them, the geometric parameters are measured by ADE equipment, and the main control items include total thickness variation TTV, overall bow BOW, warp WARP and thickness irregularity STIR. And the finished epitaxial wafer must meet the requirements of the four standards, TTV < 5 μm, BOW < 50 μm, WARP < 50 μm, and STIR < 0.5 μm.

[0090] At the same time, SP2 equipment is used for full wafer scanning to measure the surface particle data, and the main control items include LLS 0.12 μm, LLS 0.16 μm, and LLS 0.2 μm. The standard requirements are: LLS 0.12 μm < 40 pieces / wafer, LLS 0.16 μm < 30 pieces / wafer, and LLS 0.2 μm < 20 pieces / wafer.

[0091] The surface particles of the epitaxial wafer will directly affect the yield of subsequent photolithography, etching and other processes. If a 0.12 μm particle may cause short circuit or open circuit of the device.

[0092] If the particle exceeds the standard, it will be reworked or scrapped. First, remove the particles by RCA cleaning (SC1 / SC2) or megasonic rework cleaning, and then re-detect. After detection, it is packaged and shipped.

[0093] If repeated cleaning still exceeds the standard, such as LLS 0.12 μm>50, then directly judge as a waste piece. Again, re-epitaxy processing is performed on the monitoring piece to obtain new multi-layer epitaxy process parameters of the monitoring piece; and then surface particle and geometric parameter monitoring is performed.

[0094] At the time of packaging delivery, the qualified products are packaged with the reference surface facing downward, 25-50 pieces per box, without adhesive tape, with a desiccant placed in the packaging box and a label attached.

[0095] The multi-layer epitaxial wafer designed in the application adopts a design of gradually decreasing layer thickness, reduces layer interference, and improves product consistency; breaks the limitation of traditional single-layer or double-layer epitaxial wafers, adopts a processing technology mode of epitaxially growing a high-resistance N-type phosphorus (P) doped multi-layer epitaxial layer on a low-resistance N-type arsenic (As) doped silicon substrate, and realizes stable preparation of a four-layer epitaxial structure.

[0096] The preparation process of the multi-layer epitaxial wafer proposed in the application can accurately control the thickness and resistivity of each layer by monitoring the epitaxial wafer layer by layer; and the processing method of gradually decreasing layer thickness can effectively reduce the interference between layers in epitaxy, improve the consistency and yield of product quality, and improve product performance to meet the needs of high-end electronic devices.

[0097] The above detailed description of the embodiments of the application is only a preferred embodiment of the application, and cannot be considered as limiting the scope of the application. Any equivalent changes and improvements made within the scope of the application should still belong to the patent coverage range of the application.

Claims

1. A multilayer epitaxial wafer, characterized in that: The N-type conductive substrate with <100> crystal direction is sequentially stacked with multi-layer epitaxial layers, the thickness of each epitaxial layer is sequentially reduced and the resistivity is sequentially increased, and the total film thickness of the epitaxial layers is 9.5-10.5 μm.

2. The multi-layer epitaxial wafer of claim 1, wherein, The epitaxial layers are four layers, the dopant is phosphorus, and the parameters of each layer are respectively: The film thickness of the first epitaxial layer is 3.8-4.2 μm, and the resistivity is 0.092-0.108 Ω·cm; The film thickness of the second epitaxial layer is 2.85-3.15 μm, and the resistivity is 0.184-0.216 Ω·cm; The film thickness of the third epitaxial layer is 1.9-2.1 μm, and the resistivity is 0.276-0.324 Ω·cm; The film thickness of the fourth epitaxial layer is 0.95-1.05 μm, and the resistivity is 1.84-2.16 Ω·cm.

3. The multi-layer epitaxial wafer of claim 1, wherein, The substrate is an N-type silicon wafer with a diameter of 200±0.2 mm and a thickness of 705-745 μm, and has an R-type chamfer of 22°; the substrate is doped with arsenic, and the resistivity ranges from 0.0017 to 0.0025 Ω·cm.

4. The multi-layer epitaxial wafer according to any one of claims 1 to 3, wherein The multi-layer thin film packaging structure adopted on the back of the substrate includes a POLY layer close to the silicon wafer and an LTO layer above the POLY layer, and the thickness of the POLY layer is greater than that of the LTO layer; Preferably, the total thickness of the backseal structure is 5. A process for the production of a multilayer epitaxial wafer according to any one of claims 1 to 4, characterized in that the steps It comprises: Prepare a monitoring wafer of the same specification as the formal substrate, and perform layer-by-layer epitaxial growth monitoring on the monitoring wafer to obtain multi-layer epitaxial process parameters meeting the standard requirements; Based on the obtained multi-layer epitaxial process parameters of the monitoring wafer, sequentially perform multi-layer epitaxial growth on the formal substrate to obtain a finished epitaxial wafer with multiple layers; Perform parameter detection on the finished epitaxial wafer, and if it is qualified, package and ship it; if it is not qualified, reacquire the multi-layer epitaxial process parameters of the monitoring wafer.

6. The manufacturing process of claim 5, wherein, Preparing the monitoring wafer specifically includes: Obtain a silicon wafer of the same specification as the formal substrate, which is an N-type conductive substrate doped with arsenic, has a <100> crystal direction, and has a resistivity of 0.0017-0.0025 Ω·cm; the diameter is 200±0.2 mm, the thickness is 705-745 μm, and it has an R-type chamfer of 22°; the silicon substrate is back-etched and the back-etch structure has a thickness of 7. The manufacturing process of claim 6, wherein, The back sealing structure includes a POLY layer and an LTO layer sequentially grown on the back of the silicon wafer, and the thickness of the POLY layer is greater than that of the LTO layer.

8. The production process according to any one of claims 5 to 7, characterized in that, Performing layer-by-layer epitaxial growth monitoring on the monitoring wafer specifically includes: Use a layer-by-layer film thickness decreasing processing method for growth, and the resistivity increases layer by layer; And after each layer of film growth, test its film thickness and resistivity; When the measured film thickness and resistivity of each layer meet the target film thickness and target resistivity, the growth of the next layer can be performed, until the epitaxial layer growth is completed; When the film thickness and / or resistivity of any layer does not meet the requirements, start epitaxial growth again.

9. The manufacturing process of claim 8, wherein, The epitaxial layers are four layers, the dopant is phosphorus, and the parameters of each layer are respectively: During the growth of the first epitaxial layer, the SiH4 flow rate is 300 sccm, the PH3 flow rate is 2.0 sccm, the growth time is 8-10 min, and the growth temperature is 1100°C; the obtained film thickness is 3.8-4.2 μm, and the resistivity is 0.092-0.108 Ω·cm; The second epitaxial layer is grown with a SiH4 flow rate of 250 sccm, a PH3 flow rate of 1.0 sccm, a growth time of 6-8 min, and a growth temperature of 1080°C; the obtained film thickness is 2.85-3.15 μm, and the resistivity is 0.184-0.216 Ω·cm; The third epitaxial layer is grown with a SiH4 flow rate of 200 sccm, a PH3 flow rate of 0.67 sccm, a growth time of 4-6 min, and a growth temperature of 1070°C; The obtained film thickness is 1.9-2.1 μm, and the resistivity is 0.276-0.324 Ω·cm; The fourth epitaxial layer is grown with a SiH4 flow rate of 150 sccm, a PH3 flow rate of 0.1 sccm, a growth time of 2-3 min, and a growth temperature of 1060°C; the obtained film thickness is 0.95-1.05 μm, and the resistivity is 1.84-2.16 Ω·cm.

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