Semiconductor device

Abstract

A semiconductor device includes: a substrate including an active region; a gate structure crossing the active region of the substrate and extending in a first horizontal direction; and a bit line structure extending across the gate structure in a second horizontal direction intersecting the first horizontal direction. The gate structure includes a first gate electrode layer disposed on the substrate, an intermediate conductive layer disposed on the first gate electrode layer, and a second gate electrode layer disposed on the intermediate conductive layer. The intermediate conductive layer includes a grain portion having a crystal orientation substantially perpendicular to an upper surface of the first gate electrode layer.

Description

TECHNICAL FIELD

[0001] The present inventive concept relates to a buried gate electrode of a semiconductor device, and more particularly, to a buried gate electrode having an intermediate conductive layer. BACKGROUND

[0002] The integration of semiconductor devices can be increased to meet increasing demands for high performance, speed, and / or multi-functionality of semiconductor devices. The integration of semiconductor devices can be increased by fabricating a fine-patterned semiconductor device in which a pattern has a fine width and / or a fine pitch. SUMMARY

[0003] Example embodiments provide a semiconductor device including a gate electrode layer in which degradation due to surface roughness and growth distribution can be reduced.

[0004] According to an example embodiment, a semiconductor device includes a substrate including an active region, a gate trench disposed in the substrate and extending across the active region in a first horizontal direction, and a gate structure disposed in the gate trench. The gate structure includes a buried gate electrode disposed in the gate trench, a gate cap layer disposed in the gate trench on the buried gate electrode, and a gate dielectric layer disposed between the buried gate electrode and the gate trench and between the gate cap layer and the gate trench. The buried gate electrode includes a first gate electrode layer, a second gate electrode layer disposed on the first gate electrode layer, and an intermediate conductive layer disposed between the first gate electrode layer and the second gate electrode layer.

[0005] According to an example embodiment, a semiconductor device includes a substrate including an active region, a gate structure crossing the active region of the substrate and extending in a first horizontal direction, and a bit line structure extending across the gate structure in a second horizontal direction intersecting the first horizontal direction. The gate structure includes a first gate electrode layer disposed on the substrate, an intermediate conductive layer disposed on the first gate electrode layer, and a second gate electrode layer disposed on the intermediate conductive layer. The intermediate conductive layer includes a grain portion having a crystal orientation substantially perpendicular to an upper surface of the first gate electrode layer.

[0006] According to an example embodiment, a semiconductor device includes a substrate including an active region; a gate trench disposed in the substrate and extending across the active region in a first horizontal direction; a gate structure disposed in the gate trench; a bit line structure extending across the gate structure in a second horizontal direction that intersects the first horizontal direction; a contact plug disposed on a side surface of the bit line structure; a landing pad disposed on the contact plug; and a capacitor structure electrically connected to the landing pad. The gate structure includes a buried gate electrode disposed in the gate trench; a gate cap layer disposed in the gate trench on the buried gate electrode; and a gate dielectric layer disposed between the buried gate electrode and the gate trench and between the gate cap layer and the gate trench. The buried gate electrode includes a first gate electrode layer; a second gate electrode layer on an upper surface of the first gate electrode layer; a third gate electrode layer on an upper surface of the second gate electrode layer; and an intermediate conductive layer between the upper surface of the first gate electrode layer and a lower surface of the second gate electrode layer. Side surfaces of the first gate electrode layer, side surfaces of the second gate electrode layer, side surfaces of the third gate electrode layer, and side surfaces of the intermediate conductive layer are in contact with the gate dielectric layer. The first gate electrode layer includes a first TiN including a grain portion having a crystal orientation substantially parallel to an upper surface of the substrate. The intermediate conductive layer includes a second TiN different from the first TiN and including a grain portion having a crystal orientation substantially perpendicular to the upper surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the present inventive concepts will become more fully understood from the following detailed description, in conjunction with the accompanying drawings, wherein:

[0008] FIG. 1 is a top view illustrating a semiconductor device according to an example embodiment;

[0009] FIG. 2A is a vertical cross-sectional view taken along line I-I' and II-II' of the illustrated semiconductor device; FIG. 1

[0010] FIG. 2B is a vertical cross-sectional view taken along line III-III' of the illustrated semiconductor device; FIG. 1

[0011] FIG. 2C is a vertical cross-sectional view taken along line IV-IV' of the illustrated semiconductor device; FIG. 1 ​​​

[0012] FIG. 3A is FIG. 2B enlarged view of a portion of the semiconductor device illustrated;

[0013] FIG. 3B is FIG. 2C enlarged view of a portion of the semiconductor device illustrated;

[0014] FIG. 4 is an enlarged view of a portion of the semiconductor device according to an example embodiment;

[0015] FIG. 5 is an enlarged view of a portion of the semiconductor device according to an example embodiment;

[0016] FIG. 6 is an enlarged view of a portion of the semiconductor device according to an example embodiment;

[0017] FIG. 7 is a vertical cross-sectional view taken along FIG. 1 line IV-IV' of the semiconductor device illustrated;

[0018] FIG. 8 is FIG. 7 enlarged view of a portion of the semiconductor device illustrated;

[0019] FIG. 9A to FIG. 9C , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13C , FIG. 14A to FIG. 14C and FIG. 15A to FIG. 15C are vertical cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment according to a process sequence. DETAILED DESCRIPTION

[0020] In the following detailed description, reference is made to the accompanying drawings, which are depicted by way of illustration, and not by way of limitation, of embodiments that can be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that various embodiments of the disclosure can be practiced without departing from the spirit or scope of the disclosure. It should be noted that the various embodiments can be implemented in other manners not specifically set forth herein without departing from the spirit or scope of the disclosure. For example, specific structural and functional details are described to provide a thorough understanding of at least one embodiment of the disclosure. However, it should be noted that the disclosure can be practiced without specifically relying on the details set forth herein. Moreover, well-known structures have not been shown or described in detail to avoid unnecessarily obscuring the disclosure. Those skilled in the art will appreciate that, in some embodiments, the functions described can be implemented in hardware, software, or combinations thereof. In one embodiment, the various processes described can be implemented as a set of instructions contained on a computer-readable medium, which can be read and executed by one or more processors to perform the functions described herein. In another embodiment, the various processes described can be implemented as a combination of software and hardware. In yet another embodiment, aspects of the disclosure can be provided as a service or software as a service (SaaS). As used herein, the term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing, or carrying instruction(s) and / or data.

[0021] Hereinafter, terms such as "upper", "middle", "intermediate", "lower", "first", "second", "third", and the like can be used to describe components of the specification. These terms can be used to describe various components, but the components are not limited by these terms. For example, a "first component" can be referred to as a "second component".

[0022] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0023] FIG. 1 is a plan view illustrating a semiconductor device according to an example embodiment.

[0024] FIG. 2A shows a vertical cross-sectional view taken along FIG. 1 lines I-I' and II-II' of the illustrated semiconductor device. FIG. 2B is a vertical cross-sectional view taken along FIG. 1 line III-III' of the illustrated semiconductor device. FIG. 2C is a vertical cross-sectional view taken along FIG. 1 line IV-IV' of the illustrated semiconductor device.

[0025] FIG. 3A is an enlarged view of a portion of the illustrated semiconductor device. FIG. 2B FIG. 3A may correspond to a region "A" in

[0026] FIG. 2B FIG. 3B is an enlarged view of a portion of the illustrated semiconductor device. FIG. 2C

[0027] may correspond to a region "B" in FIG. 3B FIG. 2C

[0028] Referring to FIG. 1 , FIG. 2A to FIG. 2C and FIG. 3A to FIG. 3B , the semiconductor device 100 according to an example embodiment can include a substrate 3, a gate structure GS, a buffer layer 21, a bit line structure BLS, a spacer structure SP, a contact plug 60, a landing pad 69, and a capacitor structure 80.

[0029] The substrate 3 can include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The substrate 3 can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a substrate including an epitaxial layer.

[0030] ​​​​The substrate 3 can include an active region 6a, a device isolation layer 6s, a first impurity region 9a, and a second impurity region 9b. The device isolation layer 6s can be an insulating layer extending downward from the upper surface of the substrate 3. The device isolation layer 6s can define the active region 6a. For example, the active region 6a can correspond to a portion of the upper surface of the substrate 3 surrounded by the device isolation layer 6s. In a plan view, the active region 6a can have a bar shape having a short axis and a long axis, and can extend in a tilted direction with respect to the X direction and the Y direction (see FIG. 1B). FIG. 1

[0031] The active region 6a can include the first impurity region 9a and the second impurity region 9b extending to a predetermined depth in the substrate 3 from the upper surface of the substrate 3. The first impurity region 9a and the second impurity region 9b can be spaced apart from each other. The first impurity region 9a and the second impurity region 9b can function as source / drain regions of a transistor. For example, for the active region 6a, two gate structures GS can cross the active region 6a, a drain region can be formed between the two gate structures GS, and a source region can be formed in a region opposite to the drain region with respect to the two gate structures GS. For example, the first impurity region 9a can correspond to the drain region, and the second impurity region 9b can correspond to the source region. The source region and the drain region formed by the first impurity region 9a and the second impurity region 9b can be formed by doping or ion implantation. For example, the source region and the drain region formed by the first impurity region 9a and the second impurity region 9b can be formed by doping or ion implantation of substantially the same impurity. The source region and the drain region can be interchangeably referred to depending on the circuit configuration of the transistor formed. The first impurity region 9a and the second impurity region 9b can include an impurity of a conductivity type opposite to that of the substrate 3. For example, the active region 6a can contain a p-type impurity, and the first impurity region 9a and the second impurity region 9b can contain an n-type impurity.

[0032] The device isolation layer 6s can extend downward from the upper surface of the substrate 3 and can define the active region 6a. The device isolation layer 6s can surround the active region 6a. The device isolation layer 6s can space different active regions apart from each other. The device isolation layer 6s can include silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof. The device isolation layer 6s can be formed of a single layer or a plurality of layers.

[0033] In a plan view, the gate structure GS can extend in the X direction and can be spaced apart from each other in the Y direction. Additionally, the gate structure GS can cross the active region 6a. For example, two gate structures GS can intersect in the active region 6a. The transistor including the gate structure GS, and the first impurity region 9a and the second impurity region 9b, respectively, can form a buried channel array transistor (BCAT), but is not limited thereto. ​

[0034] In the cross-sectional view, the gate structure GS can be buried in the substrate 3. For example, the gate structure GS can be disposed inside the gate trench T formed in the substrate 3. Accordingly, the gate structure GS can be referred to as a buried gate structure.

[0035] The gate structure GS can include a gate dielectric layer 13, a buried gate electrode, an upper pattern 18, and a gate capping layer 19. The gate dielectric layer 13 can be disposed inside the gate trench T. The buried gate electrode can include a plurality of lower patterns (e.g., 14, 15, and 16). The plurality of lower patterns (e.g., 14, 15, and 16) of the buried gate electrode can be sequentially stacked on the gate dielectric layer 13. The upper pattern 18 can be disposed on the buried gate electrode. The gate capping layer 19 can be disposed on the upper pattern 18.

[0036] The gate dielectric layer 13 can be conformally formed on the inner wall of the gate trench T. The gate dielectric layer 13 can include silicon oxide or a material having a high dielectric constant. In an example embodiment, the gate dielectric layer 13 can be a layer formed by oxidation of the active region 6a, or can be a layer formed by deposition.

[0037] The buried gate electrode can include a plurality of lower patterns (e.g., 14, 15, and 16). The plurality of lower patterns can include a first gate electrode layer 14, an intermediate layer 15, and a second gate electrode layer 16. The lower patterns can fill at least a portion of a lower region of the gate trench T, and can be sequentially stacked in a vertical direction (e.g., a Z direction) from a lower surface of the gate dielectric layer 13. The lower patterns can be collectively referred to as a gate electrode.

[0038] The first gate electrode layer 14 can be disposed in a lower portion of the gate trench T. The first gate electrode layer 14 can contact a lower surface and a lower region of a sidewall of the gate dielectric layer 13 in the lower portion of the gate trench T. The first gate electrode layer 14 can be formed of a conductive material, and can include, for example, at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), or aluminum (Al). In an embodiment, the first gate electrode layer 14 can include a first titanium nitride (TiN). Further, the first gate electrode layer 14 can be referred to as a first buried gate electrode layer.

[0039] An intermediate layer 15 can be disposed on the first gate electrode layer 14. The intermediate layer 15 can contact sidewalls of the gate dielectric layer 13 on the first gate electrode layer 14. The intermediate layer 15 can be formed of a conductive material and can include at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), or aluminum (Al). Accordingly, the intermediate layer 15 can be referred to as an intermediate conductive layer. In an embodiment, the intermediate layer 15 can include a second titanium nitride (TiN), which can be different from the first TiN in an embodiment. A thickness d1 of the intermediate layer 15 can be less than a thickness of the first gate electrode layer 14 and a thickness of the second gate electrode layer 16 and greater than a thickness of the gate dielectric layer 13. In an example, the thickness d1 of the intermediate layer 15 can range from about to about In an example, the thickness d1 of the intermediate layer 15 can range from about to about

[0040] A second gate electrode layer 16 can be disposed on the intermediate layer 15. The second gate electrode layer 16 can contact sidewalls of the gate dielectric layer 13 on the intermediate layer 15. The second gate electrode layer 16 can be formed of a conductive material and can include at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), or aluminum (Al). In an embodiment, the second gate electrode layer 16 can include at least one of tungsten (W) or molybdenum (Mo). Further, the second gate electrode layer 16 can be referred to as a second buried gate electrode layer.

[0041] In this document, reference is made to a grain having a crystal orientation. It should be understood that the structure of a metal can be composed of individual crystalline regions called grains. The crystal orientation of a material can be understood in terms of a horizontal width and a vertical height of a grain. For example, in a material having a horizontal crystal orientation, the horizontal width of a grain of the material can be greater than the vertical height. Similarly, in a material having a vertical crystal orientation, the horizontal width of a grain of the material can be less than the vertical height.

[0042] Each of the first gate electrode layer 14, the intermediate layer 15, and the second gate electrode layer 16 can include a crystal grain G1, Gm, and G2. In this case, each of the crystal grains G1, Gm, and G2 can include a crystal grain portion G1p, Gmp, and G2p corresponding to a crystal region each having the same crystal orientation. For example, the first gate electrode layer 14 includes the first crystal grain G1 having at least one first crystal grain portion G1p, the second gate electrode layer 16 includes the second crystal grain G2 having at least one second crystal grain portion G2p, and the intermediate layer 15 can include the third crystal grain Gm having at least one third crystal grain portion Gmp.

[0043] For example, the first gate electrode layer 14 can include a first metal crystal grain having a first metal crystal grain portion, and the second gate electrode layer 16 can include a second metal crystal grain having a second metal crystal grain portion, where the first metal crystal grain portion has a crystal grain orientation substantially parallel to the upper surface of the substrate, and the second metal crystal grain portion has a crystal grain orientation substantially perpendicular to the upper surface of the intermediate layer 15. Substantially parallel or substantially perpendicular can refer to the orientation of the crystal grains, for example, in a material where the crystal orientation is substantially parallel to the upper surface of the substrate, greater than 50% or more of the crystal grains can have a horizontal width greater than a vertical height, greater than 60% or more of the crystal grains can have a horizontal width greater than a vertical height, or greater than 80% or more of the crystal grains can have a horizontal width greater than a vertical height.

[0044] The crystal orientation of the first crystal grain portion G1p can be horizontal. Thus, a maximum horizontal width G1h of the first crystal grain portion G1p can be greater than a maximum vertical width G1v (or "maximum vertical thickness"). The maximum horizontal width G1h can be defined as a maximum value of a width of the first crystal grain portion G1p along one horizontal direction (e.g., the X direction and / or the Y direction), and the maximum vertical width G1v can be defined as a maximum value of a width of the first crystal grain portion G1p along a vertical direction (e.g., the Z direction).

[0045] Reference FIG. 3AIn addition to the first grain portion G1p, the first grain G1 can include a grain portion having a crystal orientation that is not horizontal. In this case, the crystal orientation of the grain portion can include a vertical direction, but is not limited thereto. In an embodiment, a first ratio occupied by the first grain portion G1p in the first grain G1 can be higher than a second ratio occupied by the grain portion having a crystal orientation that is not horizontal in the first grain G1. In this case, the first ratio and the second ratio can be measured as a ratio of numbers. For example, the ratio can be a ratio of counts of grains in a certain area, or a ratio of areas occupied by grains in a cross-sectional sample. In an embodiment, the first ratio can be 50% or more, for example, from about 50% to about 90%, or from about 60% to about 80%. Embodiments are not limited to the example grain ratio, and other ratios can be used.

[0046] The crystal orientation of the second grain portion G2p can be substantially perpendicular to the upper surface of the intermediate layer 15. In an embodiment, the crystal orientation of the second grain portion G2p can be a vertical direction (e.g., the Z direction). Accordingly, a maximum vertical width G2v of the second grain portion G2p can be greater than a maximum horizontal width G2h. The maximum vertical width G2v can be defined as a maximum value of a width of the second grain portion G2p along a vertical direction (e.g., the Z direction), and the maximum horizontal width G2h can be defined as a maximum value of a width of the second grain portion G2p in one horizontal direction (e.g., the X direction and / or the Y direction). In another perspective, the second grain portion G2p can be understood to have a vertical grain structure. In an example, the maximum vertical width G2v of the second grain portion G2p can be greater than the maximum horizontal width G1h of the first grain portion G1p. In a case where the second electrode layer 16 is formed by a bottom-up growth method, it can be understood that the crystal orientation of the second grain G2 including the second grain portion G2p can be substantially vertical. In an embodiment, a volume ratio occupied by the second grain portion G2p in the second grain G2 can be 80% or more, for example, from about 80% to about 95%, or from about 90% to about 95%. These volume ratios can be associated with a columnar grain structure. For example, the second grain portion G2p can be understood to have a columnar grain structure.

[0047] The crystal orientation of the third grain portion Gmp can be substantially perpendicular to the upper surface of the first gate electrode layer 14. In an embodiment, the crystal orientation of the third grain portion Gmp can be a vertical direction (e.g., Z direction). Likewise, the maximum vertical width Gmv of the third grain portion Gmp can be equal to or greater than the maximum horizontal width Gmh. The maximum vertical width Gmv can be defined as a maximum value of the width of the third grain portion Gmp along the vertical direction (e.g., Z direction), and the maximum horizontal width Gmh can be defined as a maximum value of the width of the third grain portion Gmp along the horizontal direction (e.g., X direction and / or Y direction). In a case where the intermediate layer 15 is formed by a limited deposition on the upper surface of the first gate electrode layer 14, it can be understood that the crystal orientation of the third grain Gm including the third grain portion Gmp can be substantially vertical. In an embodiment, the volume ratio of the third grain portion Gmp to the third grain Gm can be 90% or greater, for example, from about 90% to about 99%, or from about 95% to about 99%.

[0048] According to an example embodiment, by providing the intermediate layer 15 having the third grain portion Gmp on the upper surface of the first gate electrode layer 14, it can be possible to provide a substrate (e.g., the upper surface of the intermediate layer 15) having a more favorable and uniform surface state for the upward growth of the second gate electrode layer 16. In detail, since the upper surface of the intermediate layer 15 can be flatter than the upper surface of the first gate electrode layer 14, and the third grain portion Gmp of the intermediate layer 15 has a substantially vertical crystal orientation, the second gate electrode layer 16 can be uniformly grown upward on the upper surface of the intermediate layer 15, so that the growth dispersion is small and the surface roughness characteristics can be improved.

[0049] The size of each grain of the first gate electrode layer 14, the intermediate layer 15, and the second gate electrode layer 16 can be determined depending on the type of material. For example, when the first gate electrode layer 14 is selected from the group consisting of titanium (Ti) or titanium nitride (TiN), and when the second gate electrode layer 16 is selected from the group consisting of tungsten (W), tungsten nitride (WN), molybdenum (Mo), or molybdenum nitride (MoN), the size of each second grain G2 can be greater than the size of each first grain G1. For example, the size of the second grain portion G2p can be greater than the size of the first grain portion G21. In this case, the size of the grain portion can mean the volume of the grain portion. Since the material included in each of the first gate electrode layer 14 and the second gate electrode layer 16 is an example, the size relationship between the first grain G1 and the second grain G2 can be different.

[0050] The first gate electrode layer 14 can include at least one first void G1_0 between the first grain portions G1p, and the second gate electrode layer 16 can include at least one second void G2_0 between the second grain portions G2p. In an embodiment, a size of the first void G1_0 can be greater than a size of the second void G2_0. Additionally, a number of the first void G1_0 can be greater than a number of the second void G2_0. In another aspect, a film quality of the second gate electrode layer 16 can be denser than a film quality of the first gate electrode layer 14.

[0051] The upper pattern 18 can be disposed between the second gate electrode layer 16 and a gate cover layer 19. The upper pattern 18 can be a semiconductor pattern including polysilicon doped with a p-type impurity or an n-type impurity. The upper pattern 18 can be referred to as a third gate electrode layer or a polysilicon layer.

[0052] The gate cover layer 19 can be disposed on an upper portion of the gate structure GS. The gate cover layer 19 can fill at least a portion of the gate trench T. A portion of an upper surface of the gate cover layer 19 can be coplanar with an upper surface of the device isolation layer 6s, and a portion of the upper surface of the gate cover layer 19 can have a curved surface that is concave upward. The gate cover layer 19 can include silicon nitride.

[0053] The buffer layer 21 can be disposed on the active region 6a, the device isolation layer 6s, and the gate structure GS. The buffer layer 21 can include silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof. The buffer layer 21 can consist of a single layer or multiple layers.

[0054] The bit line structure BLS extends in the Y direction and can be spaced apart from each other in the X direction. The bit line structure BLS can have a bar shape extending in the Y direction. The bit line structure BLS can include a bit line BL and a bit line cover layer 28 on the bit line BL. The bit line BL can include a first conductive layer 25a, a second conductive layer 25b, and a third conductive layer 25c. The first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c can be sequentially stacked on the buffer layer 21. The first conductive layer 25a can include polysilicon. The second conductive layer 25b can include a metal semiconductor compound. For example, the metal semiconductor compound can be a layer in which a portion of the first conductive layer 25a is silicided. For example, the metal semiconductor compound can include a cobalt silicide (CoSi), a titanium silicide (TiSi), a nickel silicide (NiSi), a tungsten silicide (WSi), or other metal silicide, or can include a nitride such as TiSiN. The third conductive layer 25c can include a metal material such as titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al). The bit line BL can be disposed below the first conductive layer 25a. The bit line BL can also include a plug portion 25p extending downward and in contact with the second impurity region 9b. The plug portion 25p can be located within a contact hole H formed on the upper surface of the substrate 3. In a top view, the plug portion 25p can contact a central portion of the active region 6a. The plug portion 25p can electrically connect the active region 6a to the bit line structure BLS. The plug portion 25p can include the same material as the first conductive layer 25a.

[0055] The bit line cover layer 28 can include a first insulating layer 28a, a second insulating layer 28b, and a third insulating layer 28c disposed on the bit line BL. A side surface of the first insulating layer 28a can be coplanar with the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c. The first insulating layer 28a, the second insulating layer 28b, and the third insulating layer 28c can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and for example, can include silicon nitride.

[0056] The spacer structure SP can be disposed on both sides of the bit line structure BLS, respectively, and can extend in the Y direction along the side surfaces of the bit line structure BLS. The spacer structure SP can include a first spacer SP1, a second spacer SP2, a third spacer SP3, and a fourth spacer SP4 disposed on the side surfaces of the bit line structure BLS. The first spacer SP1 can be conformally disposed along the side surfaces of the bit line structure BLS and the contact hole H. The second spacer SP2 is disposed on the first spacer SP1 and can fill the contact hole H. The third spacer SP3 can cover the side surfaces of the first spacer SP1, and the fourth spacer SP4 can cover the side surfaces of the third spacer SP3. The third spacer SP3 and the fourth spacer SP4 can cover the upper surface of the second spacer SP2. The first spacer SP1, the second spacer SP2, the third spacer SP3, and the fourth spacer SP4 can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an example embodiment, the first spacer SP1 and the fourth spacer SP4 can include silicon nitride, and the second spacer SP2 can include silicon oxide, while the third spacer SP3 can include an air gap. The spacer structure SP of the present inventive concept is illustrative, and the materials and the number of layers are not limited thereto and can vary in various ways.

[0057] The contact plug 60 is disposed between the bit line structures BLS and can contact the spacer structure SP. The contact plug 60 can be disposed between the bit line structures BLS and between the gate structures GS.

[0058] The lower end of the contact plug 60 can be located at a lower level than the upper surface of the substrate 3. The upper surface of the contact plug 60 can be located at a lower level than the upper end of the bit line structure BLS. The contact plug 60 can extend into the substrate 3 and can contact the second impurity region 9b of the active region 6a. The contact plug 60 can be electrically connected to the second impurity region 9b. The contact plug 60 can be formed of a conductive material, and can include at least one of, for example, polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or aluminum (Al). In an example embodiment, the contact plug 60 can include doped polysilicon, and can include an n-type impurity such as phosphorus (P), arsenic (As), and antimony (Sb).

[0059] The fence structure 63 can be disposed between the bit line structures BLS and can overlap the gate structures GS in the vertical direction. The fence structure 63 can be arranged alternately with the contact plugs 60 along the Y direction. The fence structure 63 can spatially separate the contact plugs 60 from each other and electrically insulate the contact plugs 60 from each other. A lower surface of the fence structure 63 can be in contact with the gate cap layer 19 of the gate structure GS. In an example embodiment, the lower surface of the fence structure 63 can have a curved surface that is convex downward toward the gate cap layer 19, and an upper surface of the gate cap layer 19 can have a curved surface that is concave upward. The lower surface of the fence structure 63 can be located at a lower level than the upper surface of the substrate 3. The fence structure 63 can include an insulating material, such as silicon nitride.

[0060] The semiconductor device 100 can further include a metal semiconductor compound layer 66 disposed on an upper surface of the contact plug 60. The metal semiconductor compound layer 66 can contact a side surface of the spacer structure SP and a side surface of the fence structure 63.

[0061] The landing pad 69 can be disposed on the metal semiconductor compound layer 66 and can include a barrier layer 69a that covers the bit line structures BLS, the spacer structure SP, and the fence structure 63, and a metal layer 69b located on the barrier layer 69a. The landing pad 69 can be electrically connected to the second impurity region 9b of the active region 6a through the contact plug 60. The metal semiconductor compound layer 66 can include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicide. The barrier layer 69a can include at least one of a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The metal layer 69b can include at least one of a conductive material, such as titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al).

[0062] The semiconductor device 100 can further include an upper insulating spacer 50 that covers the bit line structures BLS, the spacer structure SP, and the fence structure 63. The upper insulating spacer 50 can be disposed between the bit line structures BLS and the barrier layer 69a, between the spacer structure SP and the barrier layer 69a, and between the fence structure 63 and the barrier layer 69a.

[0063] The semiconductor device 100 can further include an insulating pattern 72 disposed between the landing pads 69. An upper surface of the insulating pattern 72 can be coplanar with upper surfaces of the landing pads 69, and the insulating pattern 72 can extend downward and partially contact the bit line structures BLS. The insulating pattern 72 can spatially separate the landing pads 69 from each other and electrically insulate them from each other.

[0064] The semiconductor device 100 can also include an etch stop layer 75 covering an upper surface of the landing pad 69 and an upper surface of the insulating pattern 72. A capacitor structure 80 can be disposed on the landing pad 69 and the insulating pattern 72. The capacitor structure 80 can include a lower electrode 82, a capacitor dielectric layer 84, and an upper electrode 86. The lower electrode 82 can penetrate the etch stop layer 75 and contact an upper surface of the landing pad 69. The capacitor dielectric layer 84 can cover the lower electrode 82 and the etch stop layer 75, and the upper electrode 86 can cover the capacitor dielectric layer 84. The capacitor structure 80 can be electrically connected to the landing pad 69 and the contact plug 60. The lower electrode 82 and the upper electrode 86 can include at least one of a doped semiconductor, a metal nitride, a metal, or a metal oxide. The lower electrode 82 and the upper electrode 86 can include, for example, at least one of polysilicon, titanium nitride (TiN), tungsten (W), titanium (Ti), ruthenium (Ru), or tungsten nitride (WN). The capacitor dielectric layer 84 can include, for example, at least one of a high dielectric constant material such as zirconium oxide (Zr02), aluminum oxide (AI2O3), or hafnium oxide (Hf203).

[0065] FIG. 4 is a partial enlarged view illustrating a semiconductor device according to an example embodiment.

[0066] Referring to FIG. 4 , the semiconductor device 100a can be the same as or similar to the semiconductor device described with reference to FIG. 1 , FIG. 2A to FIG. 2C and FIG. 3A to FIG. 3B . As shown in FIG. 4 , a thickness of the intermediate layer 15 can be less than a thickness of the gate dielectric layer 13.

[0067] Referring to FIG. 5 , a vertical thickness of the intermediate layer 15 along the Z direction can be less than a horizontal thickness of the gate dielectric layer 13 along the Y direction. Thus, the thickness of the intermediate layer 15 can be less than the thicknesses of the first gate electrode layer 14 and the second gate electrode layer 16 as well as the gate dielectric layer 13. In an example, the thickness d1 of the intermediate layer 15 can range from about 1 nm to about 10 nm. In an example, the thickness d1 of the intermediate layer 15 can range from about 2 nm to about 5 nm.

[0068] FIG. 5 is a partial enlarged view illustrating a semiconductor device according to an example embodiment.

[0069] Referring to FIG. 1 , the semiconductor device 100b can be the same as or similar to the semiconductor device described with reference to FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3B , FIG. 4 and FIG. 5 ​​The semiconductor device described is the same or similar. As FIG. 6 As shown, the upper surface 14US of the first gate electrode layer 14 can be in a downward convex shape in a direction toward the upper surface of the substrate.

[0070] Referring to FIG. 6 , the upper surface 14US of the first gate electrode layer 14 can be in a downward convex shape in a direction toward the upper surface of the substrate or the lower region of the trench T. Therefore, the lower surface 15LS of the intermediate layer 15 that is in contact with the upper surface 14US of the first gate electrode layer 14 can also be in a downward convex shape in a direction toward the lower region of the trench T.

[0071] The upper surface 14US of the first gate electrode layer 14 can have a gentler curve than the lower surface 14LS of the first gate electrode layer 14. The lower surface 14LS of the first gate electrode layer 14 can be defined as a surface that is in a downward convex shape in the lower region of the trench T. In another perspective, the curvature of the upper surface 14US of the first gate electrode layer 14 can be less than the curvature of the lower surface 14LS of the first gate electrode layer 14.

[0072] FIG. 1 is a partial enlarged view illustrating a semiconductor device according to an example embodiment.

[0073] Referring to FIG. 2A to FIG. 2C , the semiconductor device 100c can be the same or similar to the semiconductor device described with reference to FIG. 3A to FIG. 3B , FIG. 4 , FIG. 5 , FIG. 6 and FIG. 6 . As shown, the intermediate layer 15 can be in a downward convex shape in a direction toward the center of the first gate electrode layer 14. FIG. 7

[0074] Referring to FIG. 7 , the upper surface 15US and the lower surface 15LS of the intermediate layer 15 can be in a downward convex shape in a direction toward the center of the first gate electrode layer 14. Therefore, the lower surface 16LS of the second gate electrode layer 16 that is in contact with the upper surface 15US of the intermediate layer 15 can also be in a downward convex shape.

[0075] The upper surface 15US and the lower surface 15LS of the intermediate layer 15 can have a gentler curve than the lower surface 14LS of the first gate electrode layer 14. In another perspective, the curvature of each of the upper surface 15US and the lower surface 15LS of the intermediate layer 15 can be less than the curvature of the lower surface 14LS of the first gate electrode layer 14.

[0076] FIG. 1 is a vertical cross-sectional view illustrating a semiconductor device according to an example embodiment. FIG. 8 is an enlarged view of a portion of the vertical cross-sectional view of​FIG. 7 A vertical sectional view taken along the line IV-IV' of the illustrated semiconductor device.

[0077] FIG. 8 is FIG. 7 An enlarged view of a portion of the illustrated semiconductor device. FIG. 7 may correspond to FIG. 8 Region "C" in FIG. 6.

[0078] Referring to FIG. 1 to FIG. 6 and FIG. 7 , the semiconductor device 200 can be the same as or similar to the semiconductor device described with reference to FIG. 8 . In FIG. 1 to FIG. 6 and FIG. 7 , it can be shown that at least some (6a_1) of the active regions 6a can protrude upward in the vertical direction from the upper surface of the first gate electrode layer 14. Therefore, the description of the portions that are the same as those described with reference to FIG. 8 may be omitted or simplified.

[0079] Referring to FIG. 9A to FIG. 9C and FIG. 10A to FIG. 10C , the active regions 6a can include first active regions 6a_1 and second active regions 6a_2 whose upper surfaces are located at different levels from the upper surface of the substrate 3.

[0080] The upper surface 6a_1US of the first active regions 6a_1 can be disposed at a higher level with respect to the upper surface of the substrate 3 than the upper surface of the second active regions 6a_2. In another aspect, the upper regions of the first active regions 6a_1 can be positioned to protrude upward in the vertical direction (e.g., the Z direction) from the upper surface 14US of the first gate electrode layer 14. The portion of the first active regions 6a_1 that protrudes from the upper surface 14US of the first gate electrode layer 14 can be referred to as a protrusion. The first gate electrode layer 14 can have portions 14a and 14b spaced apart in the X direction, and the protrusion is disposed therebetween.

[0081] The intermediate layer 15 can include a horizontal portion 15h located on the upper surface 14US of the first gate electrode layer 14, and an extension portion 15e extending from the horizontal portion 15h to cover the protrusion of the first active regions 6a_1 (or the gate dielectric layer 13 located on the protrusion). The intermediate layer 15 can be conformally formed on the upper surface 14US and the protrusion.

[0082] According to example embodiments, the plurality of portions 14a and 14b spaced apart in the X direction by the protrusions may be reconnected to each other via the intermediate layer 15. Specifically, by providing the intermediate layer 15 on the first gate electrode layer 14 and the active region 6a, the first gate electrode layer 14 may be isolated from the active region 6a. For example, by providing the intermediate layer 15 on the first gate electrode layer 14 and the active region 6a, the first gate electrode layer 14 may be prevented from being physically or electrically disconnected from the active region 6a.

[0083] According to example embodiments, the protrusion of the active region 6a_1 may be covered by the intermediate layer 15 , and the second gate electrode layer 16 may be substantially uniformly grown on the first gate electrode layer 14 from bottom to top without physical or electrical interruption due to the protrusion.

[0084] According to example embodiments, an upper surface of a portion of the second gate electrode layer 16 disposed on the extension portion 15 e may have an upwardly convex shape (not shown).

[0085] FIG. 11A to FIG. 11C 、 FIG. 12A to FIG. 12C 、 FIG. 13A to FIG. 13C 、 FIG. 14A to FIG. 14C 、 FIG. 15A to FIG. 15C 、 FIG. 9A to FIG. 9C and FIG. 10A are vertical cross-sectional views illustrating a method of fabricating a semiconductor device according to example embodiments, according to process sequence diagrams.

[0086] refer to FIG. 10B , a device isolation layer 6s and a plurality of gate trenches T1 and T2 may be formed in the substrate 3 .

[0087] The device isolation layer 6s can be formed by forming a trench on the upper surface of the substrate 3, filling the trench with an insulating material, and performing a planarization process to etch the substrate 3 and the insulating material. The device isolation layer 6s can define an active region 6a. For example, the active region 6a can correspond to a portion of the upper surface of the substrate 3 surrounded by the device isolation layer 6s. In a top view, the active region 6a can be in the shape of a strip having a short axis and a long axis and can be spaced apart from each other. The device isolation layer 6s can be composed of a single layer or multiple layers.

[0088] In example embodiments, the first and second impurity regions 9a and 9b may be formed by implanting impurities into the substrate 3 before forming the device isolation layer 6s. However, depending on embodiments, the first and second impurity regions 9a and 9b may be formed after forming the device isolation layer 6s or in another process step.

[0089] Thereafter, the substrate 3 can be anisotropically etched to form gate trenches T1 and T2. The gate trenches T1 and T2 extend in the X direction, and can cross the active region 6a and the device isolation layer 6s.

[0090] In an example embodiment, the gate trenches T1 and T2 can have different depths. For example, the lower end portion of the gate trench T2 can be disposed at a lower level than the lower end portion of the gate trench T1. In an example embodiment, the gate trenches T1 and T2 can be sequentially formed. For example, the gate trench T2 can be formed after the gate trench T1 is formed, and the gate trench T1 can be formed after the gate trench T2 is formed. The gate trenches T1 and T2 can be alternately formed along the Y direction. Without being limited, the depths of the gate trenches T1 and T2 can be substantially the same (not shown). The gate trenches T1 and T2 can be collectively referred to as gate trenches T.

[0091] Referring to FIG. 10C , FIG. 11A and FIG. 11B , a gate dielectric layer 13 can be formed on the structure in which the gate trenches T are formed. For example, the gate dielectric layer 13 can be conformally formed on the structure in which the gate trenches T are formed. A first gate electrode layer 14 can be formed by forming a conductive material on the gate dielectric layer 13, and sequentially performing a planarization process and an etch-back process. The gate trenches T thus formed can be collectively referred to as gate trenches T. In an embodiment, the first gate electrode layer 14 can be formed by chemical vapor deposition (CVD), but is not limited thereto.

[0092] Referring to FIG. 11C , FIG. 12A and FIG. 12B , an intermediate layer 15 can be formed on the gate dielectric layer 13.

[0093] The intermediate layer 15 can be formed by depositing a conductive material on the gate dielectric layer 13. The intermediate layer 15 can be formed by physical vapor deposition (PVD), but is not limited thereto.

[0094] The intermediate layer 15 can be defined to include a lower portion 15L, a middle portion 15S, and an upper portion 15U. The lower portion 15L can be disposed on the upper surface of the first gate electrode layer 14. The middle portion 15S can be disposed on the gate dielectric layer 13. The upper portion 15U can be disposed on the impurity regions 9a and 9b. An end portion of the upper portion 15U can be formed to protrude beyond the surface of the middle portion 15S. The upper surface of the lower portion 15L can be in a convex shape upward, and thus, both end portions of the lower portion 15L can be formed to have a smaller thickness than the middle portion. The middle portion 15S of the intermediate layer 15 can extend downward from the upper portion 15U, and can contact the lower portion 15L at the side surfaces of the impurity regions 9a and 9b. The middle portion 15S can be formed to have a thickness that becomes smaller as it extends downward. The thickness of the middle portion 15S can be smaller than the thickness of each of the lower portion 15L and the upper portion 15U.

[0095] Referring to FIG. 12C , FIG. 13A and FIG. 13B , the middle portion 15S and the upper portion 15U of the intermediate layer 15 can be removed. For example, the middle portion 15S and the upper portion 15U of the intermediate layer 15 can be removed using a wet etching process.

[0096] The lower portion 15L can be preserved by a wet etching process using a difference in etch selectivity between the gate dielectric layer 13, the middle portion 15S, and the upper portion 15U.

[0097] Referring to FIG. 13C , FIG. 14A and FIG. 14B , a second gate electrode layer 16 can be disposed in the gate trench T. The second gate electrode layer 16 can be formed by selectively depositing a conductive material on the upper surface of the intermediate conductive layer 15 and growing it upward from the bottom. In an embodiment, the second gate electrode layer 16 can be formed by, for example, area-selective atomic layer deposition (AS-ALD), but is not limited thereto.

[0098] Referring to FIG. 14C , FIG. 15A and FIG. 15B , a polysilicon layer forming an upper pattern 18 can be disposed in the gate trench T. The polysilicon layer forming the upper pattern 18 can be formed by forming polysilicon on the second gate electrode layer 16 to fill the gate trench T and then sequentially performing a planarization process and an etch-back process on the polysilicon.

[0099] Referring to FIG. 15C , ​ and ​The gate structure GS can be formed by forming a gate cap layer 19 in the gate trench T. The gate cap layer 19 can be formed by forming an insulating material on the polysilicon layer forming the upper pattern 18. The gate cap layer 19 can be disposed to fill at least a portion of the gate trench T1. A planarization process can be performed to planarize the gate cap layer 19.

[0100] As set forth herein, according to example embodiments, a semiconductor device including gate electrode layers in which at least one of physical breakage, surface roughness, or growth profile deterioration can be improved can be provided.

[0101] In detail, according to example embodiments, deterioration of a semiconductor device including gate electrode layers can be suppressed or prevented by disposing an intermediate layer including a conductive material between two vertically stacked gate electrode layers.

[0102] While example embodiments have been illustrated and described herein, it will be clear to those of ordinary skill in the art that modifications and variations can be made without departing from the scope of the disclosure, as defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate including an active region; a gate trench disposed in the substrate and extending across the active region in a first horizontal direction; and a gate structure disposed in the gate trench, wherein the gate structure includes: a buried gate electrode disposed in the gate trench; a gate cap layer disposed on the buried gate electrode and the gate trench; and a gate dielectric layer disposed between the buried gate electrode and the gate trench and between the gate cap layer and the gate trench, the buried gate electrode includes: a first gate electrode layer; a second gate electrode layer disposed on the first gate electrode layer; and an intermediate conductive layer disposed between the first gate electrode layer and the second gate electrode layer. the gate structure further includes a third gate electrode layer disposed between the second gate electrode layer and the gate cap layer, 2. The semiconductor device of claim 1, wherein, wherein side surfaces of the first gate electrode layer, side surfaces of the second gate electrode layer, side surfaces of the intermediate conductive layer, and side surfaces of the third gate electrode layer are in contact with the gate dielectric layer. the third gate electrode layer includes polysilicon.

3. The semiconductor device of claim 2, wherein, 4. The semiconductor device according to claim 1, wherein the first gate electrode layer includes a first TiN, the intermediate conductive layer includes a second TiN different from the first TiN, and the second gate electrode layer includes at least one of W or Mo.

5. The semiconductor device according to claim 4, wherein the first TiN includes a grain portion having a crystal orientation that is horizontal, and the second TiN includes a grain portion having a crystal orientation that is perpendicular to an upper surface of the first gate electrode layer.

6. The semiconductor device according to claim 1, wherein the first gate electrode layer includes first grains, the second gate electrode layer includes second grains, and a size of each of the second grains is greater than a size of each of the first grains.

7. The semiconductor device according to claim 1, wherein the first gate electrode layer includes a first grain portion, the second gate electrode layer includes a second grain portion, a maximum horizontal width of the first grain portion is equal to or greater than a maximum vertical thickness of the first grain portion, and a maximum vertical thickness of the second grain portion is greater than a maximum horizontal width of the second grain portion. the maximum vertical thickness of the second grain portion is greater than the maximum horizontal width of the first grain portion.

8. The semiconductor device of claim 7, wherein, the intermediate conductive layer includes a third grain portion, 9. The semiconductor device of claim 1, wherein, wherein a maximum vertical thickness of the third grain portion is equal to or greater than a maximum horizontal width of the third grain portion. a thickness of the intermediate conductive layer is less than a thickness of the first gate electrode layer and less than a thickness of the second gate electrode layer.

10. The semiconductor device of claim 1, wherein, a thickness of the intermediate conductive layer is less than a thickness of the gate dielectric layer.

11. The semiconductor device of claim 1, wherein, a thickness of the intermediate conductive layer is greater than or equal to 5 angstroms and less than or equal to 30 angstroms.

12. The semiconductor device of claim 1, wherein, the first gate electrode layer is in a shape in which an upper surface of the first gate electrode layer is convex downward.

13. The semiconductor device of claim 1, wherein, the intermediate conductive layer is in a convex shape in a direction toward the first gate electrode layer.

14. The semiconductor device of claim 1, wherein, ​ 15. A semiconductor device comprising: a substrate including an active region; a gate structure extending across the active region of the substrate in a first horizontal direction; and a bit line structure extending across the gate structure in a second horizontal direction intersecting the first horizontal direction, wherein the gate structure includes: a first gate electrode layer disposed on the substrate; an intermediate conductive layer disposed on the first gate electrode layer; and a second gate electrode layer disposed on the intermediate conductive layer, and the intermediate conductive layer includes a grain portion having a crystal orientation substantially perpendicular to an upper surface of the first gate electrode layer. at least some of the active region have protrusions protruding in a vertical direction from the upper surface of the first gate electrode layer, and 16. The semiconductor device of claim 15, wherein, the intermediate conductive layer includes a horizontal portion on the upper surface of the first gate electrode layer and an extended portion extending from the horizontal portion and covering the protrusions. the first gate electrode layer includes first metal grains having first metal grain portions, and 17. The semiconductor device of claim 15, wherein, the second gate electrode layer includes second metal grains having second metal grain portions, wherein the first metal grain portions have a crystal orientation substantially parallel to an upper surface of the substrate, and the second metal grain portions have a crystal orientation substantially perpendicular to an upper surface of the intermediate conductive layer. a film quality of the second gate electrode layer is denser than a film quality of the first gate electrode layer.

18. The semiconductor device of claim 15, wherein, 19. A semiconductor device comprising: a substrate including an active region; a gate trench disposed in the substrate and extending across the active region in a first horizontal direction; a gate structure disposed in the gate trench; a bit line structure extending across the gate structure in a second horizontal direction intersecting the first horizontal direction; a contact plug disposed on a side surface of the bit line structure; a landing pad disposed on the contact plug; and a capacitor structure electrically connected to the landing pad, wherein the gate structure includes: a buried gate electrode disposed in the gate trench; a gate cap layer disposed in the gate trench and on the buried gate electrode; and a gate dielectric layer disposed between the buried gate electrode and the gate trench and between the gate cap layer and the gate trench, the buried gate electrode includes: a first gate electrode layer; a second gate electrode layer on an upper surface of the first gate electrode layer; a third gate electrode layer on an upper surface of the second gate electrode layer; and an intermediate conductive layer between the upper surface of the first gate electrode layer and a lower surface of the second gate electrode layer, wherein side surfaces of the first gate electrode layer, side surfaces of the second gate electrode layer, side surfaces of the third gate electrode layer, and side surfaces of the intermediate conductive layer are in contact with the gate dielectric layer, ​ ​ The first gate electrode layer includes a first TiN including grain portions having a crystal orientation substantially parallel to an upper surface of the substrate, and The intermediate conductive layer includes a second TiN different from the first TiN and including grain portions having a crystal orientation substantially perpendicular to the upper surface of the substrate.

20. The semiconductor device of claim 19, wherein, The second gate electrode layer includes at least one of W or Mo having grain portions with a crystal orientation substantially perpendicular to an upper surface of the substrate.

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