Semiconductor device

Abstract

A semiconductor device includes: a first transistor including a first gate electrode, a first gate dielectric layer, a first source / drain region, a second source / drain region, and a first channel region; a second transistor at the same level as the first transistor, the second transistor including a second gate electrode, a second gate dielectric layer, a third source / drain region, a fourth source / drain region, and a second channel region; a first source / drain backside contact structure under the first source / drain region and connected to the first source / drain region; a conductive connection pattern including at least a portion at the same level as the first gate electrode and the second gate electrode; a backside connection pattern connected to the conductive connection pattern; a front side connection pattern connected to the conductive connection pattern; and a first front-side contact plug on the second transistor and connected to the second transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0052113 filed on April 18, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device. Background Art

[0004] As demands for higher performance, higher speed, and / or multifunctional implementation of semiconductor devices increase, the integration density of semiconductor devices has been increasing. In response to the trend toward higher integration density of semiconductor devices, semiconductor devices having a backside power delivery network (BSPDN) structure in which power rails are provided on the back side of a wafer have been developed. Summary of the Invention

[0005] Some example embodiments of the inventive concepts provide semiconductor devices having improved reliability and electrical performance.

[0006] According to an example embodiment of the present inventive concept, a semiconductor device includes: a first transistor including a first gate electrode, a first gate dielectric layer, a first source / drain region, a second source / drain region, and a first channel region; a second transistor located at the same level as the first transistor, the second transistor including a second gate electrode, a second gate dielectric layer, a third source / drain region, a fourth source / drain region, and a second channel region; a first source / drain backside contact structure located below the first source / drain region and connected to the first source / drain region; and a conductive connection pattern. The transistor includes at least a portion located at the same level as the first gate electrode and the second gate electrode; a backside connection pattern located below the conductive connection pattern, the backside connection pattern connected to the conductive connection pattern; a frontside connection pattern located above the conductive connection pattern, the frontside connection pattern connected to the conductive connection pattern; a first frontside contact plug located above the second transistor, the first frontside contact plug connected to the second transistor; and a first frontside interconnect structure located above the frontside connection pattern and the first frontside contact plug, the first frontside interconnect structure electrically connecting the frontside connection pattern and the first frontside contact plug to each other. The first channel region may include a first channel layer spaced apart from each other in a vertical direction. The second channel region may include a second channel layer spaced apart from each other in a vertical direction. The first channel layer may be located between the first source / drain region and the second source / drain region. The second channel layer may be located between the third source / drain region and the fourth source / drain region.

[0007] According to example embodiments of the present inventive concepts, a semiconductor device includes: a backside insulating layer; a gate structure on the backside insulating layer, the gate structure including a gate electrode extending in a first direction; a first source / drain region and a second source / drain region on opposite sides of the gate structure, the first source / drain region and the second source / drain region spaced apart from each other; a channel region between the first source / drain region and the second source / drain region, the channel region overlapping at least a portion of the gate electrode in a vertical direction; a conductive connection pattern extending in the first direction, the conductive connection pattern including at least a portion located at a same level as the gate electrode; a frontside connection pattern on the conductive connection pattern, the frontside connection pattern in contact with the conductive connection pattern; a backside connection pattern below the conductive connection pattern, the backside connection pattern in contact with the conductive connection pattern; a first frontside contact plug on the gate electrode, the first frontside contact plug connected to the gate electrode; a first frontside interconnect structure on the frontside connection pattern and the first frontside contact plug, the first frontside interconnect structure connecting the frontside connection pattern and the first frontside contact plug to each other; a first backside contact structure below the first source / drain region, the first backside contact structure connected to the first source / drain region; and

[0008] a first source / drain frontside contact plug on the second source / drain region, the first source / drain frontside contact plug connected to the second source / drain region. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects, features, and advantages of the present inventive concepts will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view of a semiconductor device according to example embodiments of the present inventive concepts;

[0011] Figure 2A is a cross-sectional view of the semiconductor device in Figure 1 taken along line I-I’, and Figure 2B is a cross-sectional view of the semiconductor device in Figure 1 taken along line II-II’;

[0012] Figure 3 is a plan view of a semiconductor device according to example embodiments of the present inventive concepts;

[0013] Figure 4A is a cross-sectional view of the semiconductor device in Figure 3 taken along line I-I’, and Figure 4B is a cross-sectional view of the semiconductor device in Figure 3 taken along line II-II’;

[0014] Figure 5 is a plan view of a semiconductor device according to an example embodiment of the inventive concept;

[0015] Figure 6 is a cross-sectional view of the semiconductor device in Figure 5 is a cross-sectional view of the semiconductor device in

[0016] Figure 7 is a cross-sectional view of the semiconductor device according to an example embodiment of the inventive concept taken along line II-

[0017] II’;

[0018] Figure 8 is a cross-sectional view of the semiconductor device according to an example embodiment of the inventive concept taken along line I-

[0019] I’;

[0020] Figure 9 is a cross-sectional view of the semiconductor device according to an example embodiment of the inventive concept taken along line I-

[0021] I’;

[0022] Figure 10 is a cross-sectional view of the semiconductor device according to an example embodiment of the inventive concept taken along line I-

[0023] I’;

[0024] Figure 11 is a cross-sectional view of the semiconductor device according to an example embodiment of the inventive concept taken along line I-

[0025] I’; and

[0026] Figures 12 to 23B is a cross-sectional view of a sequential process of a method of manufacturing a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0027] In the following, preferred example embodiments of the inventive concept will be described with reference to the accompanying drawings. In the following, terms such as "top", "upper", "upper surface", "above", "bottom", "lower", "lower surface", "below" and "side surface" can be understood to be referred to based on the drawings, in addition to being denoted by reference numerals.

[0028] As used in this text, when a phrase such as "at least one of' precedes a list of elements, the phrase "at least one of' modifies the entire list of elements and not the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0029] Figure 1 is a plan view of a semiconductor device 100A according to example embodiments of inventive concepts.

[0030] Figure 2A is Figure 1 is a cross-sectional view of the semiconductor device 100A in Figure 2B is Figure 1 in FIG. 1A taken along line II-II’. To aid in understanding, only some components in the semiconductor device 100A are shown in Figure 1

[0031] Referring to Figure 1 , Figure 2A and Figure 2B , the semiconductor device 100A according to example embodiments can include a first transistor TR1 and a second transistor TR2 spaced apart from each other. The semiconductor device 100A can also include a source / drain backside contact structure 191, a connection structure 170, a frontside connection pattern 250, a backside connection pattern 192, a first frontside contact plug (interchangeably referred to as a gate contact) 255, a first frontside interconnect structure M1, and a backside interconnect structure 180.

[0032] The first transistor TR1 can include a first gate electrode 165A, a first gate dielectric layer 162A, a first source / drain region 150A1, a second source / drain region 150A2, and a first channel region 140A. The second transistor TR2 can be disposed at a same level as the first transistor TR1 and can include a second gate electrode 165B, a second gate dielectric layer 162B, a third source / drain region 150B1, a fourth source / drain region 150B2, and a second channel region 140B, and the first transistor TR1 can be disposed spaced apart from the second transistor TR2 in a second direction (e.g., an X-axis direction). The connection structure 170, the frontside connection pattern 250, and the backside connection pattern 192 can be disposed between the first transistor TR1 and the second transistor TR2.

[0033] The semiconductor device 100A can also include a backside insulating layer 194.

[0034] ​The first transistor TR1 and the second transistor TR2 may be disposed on a backside insulating layer 194. The backside insulating layer 194 may have an upper surface extending in a first direction (e.g., a Y-axis direction) and a second direction (e.g., an X-axis direction). The backside insulating layer 194 may be a layer formed using an additional process after removing a semiconductor substrate formed of or including a semiconductor material during a manufacturing process, or may be a layer formed by oxidizing a semiconductor substrate. The backside insulating layer 194 may be in the form of a substrate insulating layer formed of an insulating material, and may include, for example, an oxide, a nitride, or a combination thereof. In some example embodiments, the backside insulating layer 194 may include a plurality of insulating layers having different materials.

[0035] A lower pattern 195 extending in a second direction (e.g., an X-axis direction) may be provided on the backside insulating layer 194. The lower pattern 195 may have a fin structure protruding in a third direction (e.g., a Z-axis direction). In some example embodiments, the lower pattern 195 may have a cross-section having a width that increases downward. The lower pattern 195 may include various insulating materials such as oxide, nitride, or oxynitride. In an example, in the lower pattern 195, the upper region may include a semiconductor material, and the lower region may include an insulating material. The lower pattern 195 may overlap with the channel region 140 in a vertical direction (e.g., a Z-axis direction), but the inventive concept is not limited thereto.

[0036] The gate structure GS may include a first gate structure GSA and a second gate structure GSB. The first gate structure GSA may be disposed on the lower pattern 195 to extend in a first direction (e.g., the Y-axis direction). The first gate structure GSA may include a first gate dielectric layer 162A, a first gate spacer layer 164A, and a first gate electrode 165A. In some example embodiments, the first gate structure GSA may further include a capping layer on the upper surface of the first gate electrode 165A. Alternatively, the portion of the first interlayer insulating layer 173 located on the first gate structure GSA may be referred to as a gate capping layer. The width of the first gate electrode 165A in the second direction (e.g., the X-axis direction) may be referred to as a first width w1. The second direction may be a direction intersecting with the first direction along which the first gate structure GSA extends.

[0037] The first gate dielectric layer 162A can be disposed between the lower pattern 195 and the first gate electrode 165A and between the first channel region 140A and the first gate electrode 165A, and can be disposed to cover at least a portion of a surface of the first gate electrode 165A. For example, the first gate dielectric layer 162A can be disposed to surround a surface of the first gate electrode 165A except for an uppermost surface of the first gate electrode 165A. The first gate dielectric layer 162A can extend to a space between the first gate electrode 165A and the first gate spacer layer 164A, but the inventive concept is not limited thereto. The first gate dielectric layer 162A can include an oxide, a nitride, or a high-k material. The high-k material can refer to a dielectric material having a dielectric constant higher than that of a silicon oxide film (SiO2). The high-k material can include, for example, at least one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), lanthanum hafnium oxide (LaHfO4), hafnium aluminum oxide (HfAlO4), and praseodymium oxide (Pr2O3). In some example embodiments, the first gate dielectric layer 162A can have a multi-layer structure. x O y x O y x O y x O y x O y TM O

[0001] The first gate electrode 165A can include a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to example embodiments, the first gate electrode 165A can have a multi-layer structure.

[0039] The first gate spacer layer 164A can be disposed on the first channel region 140A on opposite side surfaces of the first gate electrode 165A. The first gate spacer layer 164A can insulate the first source / drain region 150A1 and the second source / drain region 150A2 from each other with respect to the first gate electrode 165A. According to example embodiments, an upper end of the first gate spacer layer 164A can have a shape that varies in various ways, and the first gate spacer layer 164A can have a multi-layer structure. The first gate spacer layer 164A can be formed of a low-k material, and can include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.​​​​

[0040] The second gate structure GSB can include a second gate dielectric layer 162B, a second gate spacer layer 164B, and a second gate electrode 165B. The second gate structure GSB can have the same or similar features as those of the first gate structure GSA, and the description of the second gate structure GSB can be replaced with the above description of the first gate structure GSA. The second gate structure GSB can be spaced apart from the first gate structure GSA in the second direction (e.g., the X-axis direction), and the connection structure 170, the front-side connection pattern 250, and the backside connection pattern 192 can be disposed between the first gate structure GSA and the second gate structure GSB.

[0041] The channel region 140 can include a first channel region 140A disposed on the first transistor TR1 and a second channel region 140B disposed on the second transistor TR2. The first channel region 140A can be disposed on the lower pattern 195 in an area where the lower pattern 195 intersects the first gate structure GSA. The first channel region 140A can include two or more first channel layers 141, 142, and 143 disposed to be spaced apart from each other in the third direction (e.g., the Z-axis direction). The first channel region 140A can be disposed between the first source / drain region 150A1 and the second source / drain region 150A2, and the first channel region 140A can be connected to the first source / drain region 150A1 and the second source / drain region 150A2. The first channel region 140A can have a width equal to or less than a width of the lower pattern 195 in the second direction (e.g., the X-axis direction), and can have a width equal to or similar to a width of the first gate structure GSA in the second direction (e.g., the X-axis direction). In a cross-section in the first direction, among the plurality of first channel layers 141, 142, and 143, the lower channel layer 141 can have a width equal to or greater than a width of the upper channel layer 143. In some example embodiments, the first channel region 140A can have a reduced width compared to the first gate structure GSA, such that a side surface of the first channel region 140A can be located below the first gate structure GSA in the second direction.

[0042] The first channel region 140A can be formed of a semiconductor material, and can include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In example embodiments, the number and shape of channel layers included in a single channel structure can be varied in various ways.

[0043] In the semiconductor device 100A, the first gate electrode 165A may be provided between the lower pattern 195 and the first channel region 140A, between the plurality of first channel layers 141, 142, and 143 of the first channel region 140A, and on the first channel region 140A. Therefore, the semiconductor device 100A may include a multi-bridge channel FET (MBCFET). TM However, in some example embodiments, the semiconductor device 100A may not include the plurality of first channel layers 141, 142, and 143, and may have, for example, a FinFET structure.

[0044] The second channel region 140B may include a second channel layer spaced apart from each other in the vertical direction. The second channel region 140B may be disposed between the third source / drain region 150B1 and the fourth source / drain region 150B2, and the second channel region 140B may be electrically connected to the third source / drain region 150B1 and the fourth source / drain region 150B2. The second channel region 140B may have features that are the same or similar to those of the first channel region 140A, and the description of the second channel region 140B may be replaced with the above description of the first channel region 140A. The second channel region 140B may be spaced apart from the first channel region 140A in a second direction (e.g., the X-axis direction), and the connection structure 170, the front side connection pattern 250, and the back side connection pattern 192 may be disposed between the first channel region 140A and the second channel region 140B.

[0045] The source / drain region 150 may include a first source / drain region 150A1 and a second source / drain region 150A2 and a third source / drain region 150B1 and a fourth source / drain region 150B2. The first source / drain region 150A1 and the second source / drain region 150A2 may be respectively disposed on opposite sides of the first gate structure GSA to contact the first channel region 140A. The first source / drain region 150A1 may be disposed in regions in which the upper portion of the lower pattern 195 is partially recessed. The source / drain region 150 may be referred to differently depending on the region in which the source / drain region 150 is disposed. Figure 2AAs shown in FIG. 1, the first source / drain region 150A1 and the second source / drain region 150A2 can be electrically connected to the first source / drain backside contact structure 191A in contact with a lower surface of the first source / drain region 150A1 and the second source / drain region 150A2. The third source / drain region 150B1 can be electrically connected to the second source / drain backside contact structure 191B in contact with a lower surface of the third source / drain region 150B1, and the fourth source / drain region 150B2 can be electrically connected to the first source / drain frontside contact plug 260 in contact with an upper surface of the fourth source / drain region 150B2.

[0046] The upper surface of the source / drain region 150 can be located at the same or similar level as a lower surface of the gate structure GS on the channel region 140. However, the level of the upper surface of the source / drain region 150 can vary in various ways in example embodiments. The source / drain region 150 can include a semiconductor material such as silicon (Si) and / or germanium (Ge), and can also include impurities.

[0047] The semiconductor device 100A can further include a connection structure 170 and an intermediate insulating layer 174.

[0048] The connection structure 170 can extend on the backside insulating layer 194 in the first direction (e.g., Y-axis direction) to be parallel to the gate structure GS. At least a portion of the connection structure 170 can be located at the same level as at least a portion of the gate structure GS. The connection structure 170 can include a conductive connection pattern 175 and an insulating liner 172 surrounding the conductive connection pattern 175. At least a portion of the conductive connection pattern 175 can be disposed at the same level as the first gate electrode 165A and the second gate electrode 165B. The conductive connection pattern 175 can include the same material as the first gate electrode 165A, and can have the same or similar characteristics as the first gate electrode 165A. The description of the conductive connection pattern 175 can be replaced with the above description of the first gate electrode 165A. The insulating liner 172 can include the same material as the first gate dielectric layer 162A, and can have the same or similar characteristics as the first gate dielectric layer 162A. The description of the insulating liner 172 can be replaced with the above description of the first gate dielectric layer 162A.

[0049] The distance between the upper surface and the lower surface of the conductive connection pattern 175 can be greater than the distance between the upper surface and the lower surface of the first gate electrode 165A, but the inventive concept is not limited thereto. The lower surface of the first gate electrode 165A can be located at a level higher than the level of the lower surface of the conductive connection pattern 175. The upper surface of the conductive connection pattern 175 can be disposed at a level higher than the level of the uppermost first channel layer 143 among the first channel layers, and the lower surface of the conductive connection pattern 175 can be disposed at a level lower than the level of the lowermost first channel layer 141 among the first channel layers.

[0050] The width of the conductive connection pattern 175 in the second direction (e.g., the X-axis direction) can be referred to as a second width w2. The second width w2 of the conductive connection pattern 175 can be greater than the first width w1 of each of the first gate electrode 165A and the second gate electrode 165B, but the inventive concept is not limited thereto. The semiconductor device 100A according to the present example embodiment can include a conductive connection pattern 175 having a width greater than the width of the gate electrode, thereby providing a position on which a contact structure extending from the back side of the semiconductor device is disposed, in a case where electrical connection with the contact structure is easily achieved.

[0051] The intermediate insulating layer 174 can be disposed on the backside insulating layer 194 and can be disposed under the connection structure 170. The intermediate insulating layer 174 can include at least one of an oxide, a nitride, an oxynitride, and a low-k material. In an example embodiment, the intermediate insulating layer 174 can include an oxide. The intermediate insulating layer 174 can be disposed to surround at least a portion of the backside connection pattern 192. The intermediate insulating layer 174 can be disposed at a level the same as or lower than the level of the connection structure 170, and can provide an alignment position so that the backside connection pattern 192 can be in contact with the connection structure 170. At least a portion of the upper surface of the intermediate insulating layer 174 can be in contact with at least a portion of the insulating spacer 172. The upper surface of the intermediate insulating layer 174 can be located at a level the same as or similar to the level of the lowermost end of the source / drain regions 150 disposed to be spaced apart from each other in the second direction, but the inventive concept is not limited thereto. The lower surface of the intermediate insulating layer 174 can be located at a level the same as or similar to the level of the lower surface of each of the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 and the source / drain backside contact structure 191 disposed to be spaced apart from each other in the second direction, but the inventive concept is not limited thereto.

[0052] The semiconductor device 100A can further include a backside connection pattern 192, a source / drain backside contact structure 191, and a backside interconnection structure 180.

[0053] The source / drain backside contact structure 191 can be provided on the first transistor TR1 and the second transistor TR2. For example, the first source / drain backside contact structure 191A can be provided under the first source / drain region 150A1 and the second source / drain region 150A2. The first source / drain backside contact structure 191A can pass through the lower pattern 195 to be electrically connected to the first source / drain region 150A1 and the second source / drain region 150A2. The source / drain backside contact structure 191 can have an inclined side surface such that a width of a part of the upper region 191U is reduced toward the upper surface of the backside insulating layer 194 due to its aspect ratio, and the lower region 191L can have a width that does not change according to its level, and can have a certain shape, but the present inventive concept is not limited thereto. The lower end of the first source / drain backside contact structure 191A can be located on a level lower than the level of the lower end of the first source / drain region 150A1 and the second source / drain region 150A2. The first source / drain backside contact structure 191A can be provided to make the first source / drain region 150A1 and the second source / drain region 150A2 partially recessed and in contact with a part of a surface including the lower surface of the first source / drain region 150A1 and the second source / drain region 150A2. In an example embodiment, the form in which the source / drain backside contact structure 191 is connected to the source / drain region 150 can be changed in various ways.

[0054] The source / drain backside contact structure 191 can include the first source / drain backside contact structure 191A in contact with and electrically connected to the first source / drain region 150A1 and the second source / drain region 150A2 of the first transistor TR1, respectively, and the second source / drain backside contact structure 191B in contact with and electrically connected to the third source / drain region 150B1 of the second transistor TR2.

[0055] The first source / drain backside contact structure 191A can have an upper end extending into the first source / drain region 150A1 and the second source / drain region 150A2 such that the upper end is provided on a level higher than the level of the lower end of the first source / drain region 150A1 and the second source / drain region 150A2. The second source / drain backside contact structure 191B can have an upper end extending into the third source / drain region 150B1 such that the upper end is provided on a level higher than the level of the lower end of the third source / drain region 150B1.

[0056] The source / drain backside contact structure 191 can include a first contact barrier layer (not shown) forming its side surfaces and lower surface, and a first contact conductive layer on the first contact barrier layer. For example, the first contact barrier layer can include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). For example, the first contact conductive layer can include a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In example embodiments, the number and arrangement of conductive layers included in the source / drain backside contact structure 191 can vary in various ways.

[0057] The source / drain backside contact structure 191 can be in contact with the lower surfaces of the first source / drain region 150A1, the second source / drain region 150A2, and the third source / drain region 150B1, and can be used to apply a power voltage from the backside interconnect structure 180 to the source / drain regions of a power transistor in the semiconductor device.

[0058] The backside connection pattern 192 can be disposed below the connection structure 170. The backside connection pattern 192 can be disposed below and electrically connected to the conductive connection pattern 175. The backside connection pattern 192 can have sloped side surfaces such that its width decreases toward the connection structure 170. The backside connection pattern 192 can include a backside contact barrier layer 192S forming its side surfaces and upper surface, and a backside contact conductive layer 192M on the backside contact barrier layer 192S. The backside contact barrier layer 192S can include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The backside contact conductive layer 192M can include a metal material such as copper (Cu), aluminum (Al), tungsten (W), or molybdenum (Mo). In example embodiments, the number and arrangement of conductive layers included in the backside connection pattern 192 can vary in various ways. The backside contact barrier layer 192S can be in contact with the conductive connection pattern 175. For example, the backside contact barrier layer 192S can be in contact with the lower surface of the conductive connection pattern 175, and the insulating spacer 172 can be disposed around the backside contact barrier layer 192S. The backside connection pattern 192 can provide an electrical path for signal transmission from the backside interconnect structure 180.

[0059] The backside interconnection structure 180 can include a backside barrier layer 180S and a backside electrode layer 180M disposed on the backside barrier layer 180S. The backside interconnection structure 180 can contact a lower portion of the source / drain backside contact structure 191 and can be electrically connected to the first source / drain backside contact structure 191 through the source / drain backside contact structure 191. The first backside interconnection structure 180 can be disposed on a lower surface of the backside insulating layer 194. The backside interconnection structure 180 together with the source / drain backside contact structure 191 can form a backside power delivery network (BSPDN) that applies a power voltage or a ground voltage, and can also be referred to as a backside power rail or a buried power rail. For example, the backside interconnection structure 180 can be a buried interconnection line extending in one direction (e.g., a Y-axis direction) under the source / drain backside contact structure 191, but the form of the backside interconnection structure 180 is not limited thereto. For example, in some example embodiments, the backside interconnection structure 180 can include a via region and / or a line region. The backside interconnection structure 180 can include a first backside interconnection structure 180A in contact with the first source / drain backside contact structure 191A, and a second backside interconnection structure 180B in contact with the second source / drain backside contact structure 191B. The first backside interconnection structure 180A can be in contact with the first source / drain backside contact structure 191A and can be electrically connected to the first transistor TR1 through the first source / drain backside contact structure 191A. The second backside interconnection structure 180B can be in contact with the second source / drain backside contact structure 191B and can be electrically connected to the second transistor TR2 through the second source / drain backside contact structure 191B. In Figure 2A In the middle, it is shown that the backside interconnection structure 180 has a single interconnection layer, but the number of layers is not limited thereto. The backside interconnection structure 180 can include interconnection lines of a plurality of layers stacked in a vertical direction and electrically connected to each other.

[0060] The backside interconnection structure 180 can include a conductive material, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo).

[0061] The semiconductor device 100A can further include a front side connection pattern 250, a first source / drain front side contact plug 260, a first source / drain front side contact via 265, and a first front side interconnection structure M1.

[0062] The front-side connection pattern 250 can be disposed on the connection structure 170. The front-side connection pattern 250 can be disposed on and can be electrically connected to the conductive connection pattern 175. The front-side connection pattern 250 can have the same or similar features as those of the back-side connection pattern 192, and the description of the front-side connection pattern 250 can be partially replaced by the above description of the back-side connection pattern 192. The front-side connection pattern 250 can pass through a portion of the first interlayer insulating layer 173 and can be in contact with the upper surface of the connection structure 170. The front-side connection pattern 250 can be electrically connected to the connection structure 170 and can provide an electrical path for transmission of an operating signal from the back-side interconnection structure 180. The upper surface of the first interlayer insulating layer 173 can be located at a higher level than the lower surface of the conductive connection pattern 250, and the lower surface of the first interlayer insulating layer 173 is located at a lower level than the lower surface of the conductive connection pattern 250. In the semiconductor device 100A according to the present example embodiment, a direct electrical path passing through the back-side connection pattern 192, the connection structure 170, and the front-side connection pattern 250 can be used, thereby solving various electrical resistance problems that can occur due to an elongated electrical path.

[0063] On the second transistor TR2, the first source / drain front-side contact plug 260 can be disposed on the fourth source / drain region 150B2. The first source / drain front-side contact plug 260 can pass through the first interlayer insulating layer 173 to be electrically connected to the fourth source / drain region 150B2. The first source / drain front-side contact plug 260 can have an inclined side surface such that its width decreases toward the upper surface of the back-side insulating layer 194 due to its aspect ratio, but the present inventive concept is not limited thereto. The lower end of the first source / drain front-side contact plug 260 can be located on a higher level than the level of the lower end of the fourth source / drain region 150B2. The first source / drain front-side contact plug 260 can be disposed to partially recess the fourth source / drain region 150B2 and to be in contact with a portion of a surface including the upper surface of the fourth source / drain region 150B2. In an example embodiment, the form in which the first source / drain front-side contact plug 260 is connected to the fourth source / drain region 150B2 can vary in various ways.

[0064] The first source / drain front-side contact plug 260 can have the same or similar features as those of the source / drain back-side contact structure 191, and the description of the first source / drain front-side contact plug 260 can be partially replaced by the above description of the source / drain back-side contact structure 191.

[0065] The first source / drain front side contact plug 260 can be in contact with an upper surface of the fourth source / drain region 150B2, and can be used to transmit input / output signals from the first front side interconnect structure M1 to source / drain regions of logic transistors in the semiconductor device.

[0066] The first source / drain front side contact via 265 can be disposed on the first source / drain front side contact plug 260, and can be in contact with the first front side interconnect structure M1. The first source / drain front side contact via 265 can include the same material as that of the first source / drain front side contact plug 260. For example, the first source / drain front side contact via 265 can include the same conductive metal material as that of the first source / drain front side contact plug 260, and can be used as an electrical path for transmitting power from the first source / drain front side contact plug 260 to the first front side interconnect structure M1.

[0067] The first front side interconnect structure M1 can be disposed on the second interlayer insulating layer 177, the front side connection pattern 250, and the first source / drain front side contact via 265. The first front side interconnect structure M1 can be disposed on the same level as that of the front side insulating layer 176. The first front side interconnect structure M1 can have a structure in which the first front side interconnect structure M1 is divided into a plurality of portions, and the plurality of portions can be electrically connected to different contact structures. The first front side interconnect structure M1 can include a first interconnect line M1st in contact with the front side connection pattern 250 and the first front side contact plug 255, a second interconnect line M1sd in contact with the first source / drain front side contact via 265, and a third interconnect line M1g in contact with the first front side contact plug 255. The first front side interconnect structure M1 can have the same or similar features as those of the back side interconnect structure 180, and the description of the first front side interconnect structure M1 can be partially replaced with the above description of the back side interconnect structure 180. The first front side interconnect structure M1 can be electrically connected to the front side connection pattern 250 and the first source / drain front side contact plug 260, and can provide an electrical path for transmitting an operating signal. Only a single layer of the first front side interconnect structure M1 is illustrated, but the number or form thereof is not limited thereto, and a transmission path of an electrical signal can be provided by additional interconnect lines disposed on the illustrated first front side interconnect structure M1.

[0068] The semiconductor device 100A can further include first to fourth insulating separation patterns IP1, IP2, IP3, and IP4.

[0069] The first and second insulating separation patterns IP1 and IP2 can extend in a second direction (e.g., an X-axis direction) on the backside insulating layer 194. The first and second insulating separation patterns IP1 and IP2 can be spaced apart from each other in a first direction (e.g., a Y-axis direction). The first and second insulating separation patterns IP1 and IP2 can intersect the connection structure 170 extending in the first direction, and the first and second insulating separation patterns IP1 and IP2 can separate the conductive connection pattern 175 into a plurality of divided portions. The conductive connection pattern 175 can be disposed between the first and second insulating separation patterns IP1 and IP2. The first and second insulating separation patterns IP1 and IP2 can include an insulating material, and can include a material formed of an oxide, a nitride, an oxynitride, or a combination thereof. As Figure 1 As shown in FIG. 18B, the first and second insulating separation patterns IP1 and IP2 can not contact the gate structure GS. However, according to an example embodiment, the first and second insulating separation patterns IP1 and IP2 can extend to intersect the first and second gate structures GSA and GSB, and can separate each of the first and second gate structures GSA and GSB into a plurality of divided portions.

[0070] A third insulating separation pattern IP3 and a fourth insulating separation pattern IP4 can be disposed on the backside insulating layer 194. The third insulating separation pattern IP3 can be disposed between the first transistor TR1 and the connection structure 170, and the fourth insulating separation pattern IP4 can be disposed between the second transistor TR2 and the connection structure 170. The connection structure 170 can be disposed between the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4. The third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can extend in a first direction (e.g., a Y-axis direction). The third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can pass through at least a portion of the lower pattern 195, and can extend in a third direction (e.g., a Z-axis direction). A lower surface of each of the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can be located on a same level as a lower surface of the lower pattern 195 and an upper surface of the backside insulating layer 194, and can be located on a same level as a lower surface of the middle insulating layer 174, although the inventive concept is not limited thereto. An upper surface of each of the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can be disposed on a level higher than a level of an upper surface of the conductive connection pattern 175, and a lower surface of each of the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can be disposed on a level lower than a level of a lower surface of the conductive connection pattern 175, although the inventive concept is not limited thereto. In a second direction (e.g., an X-axis direction) perpendicular to the first direction, a maximum width w2 of the conductive connection pattern 175 can be greater than a width of each of the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4. The third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can include an insulating material, e.g., an oxide, a nitride, an oxynitride, or a combination thereof. The third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can pass through the channel region 140, and can serve to isolate electrical signals between the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 from each other.

[0071] The semiconductor device 100A can further include a first interlayer insulating layer 173, a second interlayer insulating layer 177, and a frontside insulating layer 176.

[0072] The first interlayer insulating layer 173 can be disposed to cover the source / drain region 150, the gate structure GS, and the middle insulating layer 174. The first interlayer insulating layer 173 can be disposed to surround at least a portion of each of the connection structure 170, the frontside connection pattern 250, and the first source / drain frontside contact plug 260. The first interlayer insulating layer 173 can include at least one of an oxide, a nitride, and an oxynitride, and can include, e.g., a low-k material. According to an example embodiment, the first interlayer insulating layer 173 can include a plurality of insulating layers.

[0073] A second interlayer insulating layer 177 can be disposed on the first interlayer insulating layer 173. The second interlayer insulating layer 177 can be disposed to surround at least a portion of each of the front-side connection pattern 250 and the gate contact 255. The second interlayer insulating layer 177 can have the same or similar features as those of the first interlayer insulating layer 173, and thus the description of the second interlayer insulating layer 177 can be partially replaced with the above description of the first interlayer insulating layer 173.

[0074] A front-side insulating layer 176 can be disposed on the second interlayer insulating layer 177. The front-side insulating layer 176 can be disposed to surround the first front-side interconnection structure M1. The front-side insulating layer 176 can have the same or similar features as those of the first interlayer insulating layer 173, and thus the description of the front-side insulating layer 176 can be partially replaced with the above description of the first interlayer insulating layer 173.

[0075] The second back-side interconnection structure 180B and the second source / drain back-side contact structure 191B can be a transmission path for applying a source / drain voltage to the third source / drain region 150B1. The fourth source / drain region 150B2 can be electrically connected to the second interconnection line M1sd through the first source / drain front-side contact plug 260 and the first source / drain front-side contact via 265.

[0076] A gate voltage applied to the second gate electrode 165B can be applied through the back-side connection pattern 192, the conductive connection pattern 175, the front-side connection pattern 250, the first interconnection line M1st, and the first front-side contact plug 255.

[0077] In an example, the second transistor TR2 can be a power transistor, but example embodiments are not limited thereto, and can be a transistor included in a logic circuit.

[0078] In the semiconductor device 100A according to the present example embodiment, the back-side connection pattern 192 in contact with the back-side power structure and the connection structure 170 disposed on the back-side connection pattern 192 can be used, thereby providing a shortened path for transmission of an operation signal from the back side to the front side. Accordingly, the semiconductor device can have improved performance. Further, a width w2 of the connection structure 170 in the second direction (e.g., the X-axis direction) can be greater than a width w1 of each of the first gate electrode 165A and the second gate electrode 165B in the second direction, such that the back-side connection pattern 192 can be aligned with the connection structure 170 in a vertical direction (e.g., the Z-axis direction), thereby providing a path for a power or input / output signal without interruption.

[0079] In the following description of the following example embodiments below, descriptions repeated with the above description with reference to Figures 1 to 2B the above description provided will be omitted.

[0080] Figure 3 is a plan view of the semiconductor device 100B according to an example embodiment of the present inventive concept.

[0081] Figure 4A is Figure 3 is a cross-sectional view of the semiconductor device 100B taken along the line I-I’ in Figure 4B is Figure 3 is a cross-sectional view of the semiconductor device 100B taken along the line II-II’ in

[0082] Referring to Figure 3 , Figure 4A and Figure 4B , the semiconductor device 100B can further include a device isolation layer 110. The device isolation layer 110 can fill spaces between the lower patterns 195 and can define the lower patterns 195 in the backside insulating layer 194. For example, the device isolation layer 110 can be formed using a shallow trench isolation (STI) process. The device isolation layer 110 can expose upper surfaces of the lower patterns 195 and can partially expose upper portions of the lower patterns 195. The device isolation layer 110 can be formed of an insulating material. The device isolation layer 110 can include, for example, an oxide, a nitride, or a combination thereof. In the semiconductor device 100A according to the present example embodiment, the lower patterns 195 and the device isolation layer 110 can be partially removed under the connection structure 170, but the present inventive concept is not limited thereto. The connection structure 170 can overlap the lower patterns 195 and the channel regions 140 disposed on the lower patterns 195 in a third direction (e.g., a Z-axis direction).

[0083] The semiconductor device 100B according to an example embodiment can have the same configuration as the semiconductor device 100A with reference to Figures 1 to 2BThe described features are the same or similar features. The conductive connection pattern 175 can include a first center portion CP, a first extension portion EP1 extending from the first center portion CP in a first direction (e.g., a Y-axis direction), the first extension portion EP1 disposed between the first center portion CP and a first insulating separation pattern IP1, and a second extension portion EP2 extending from the first center portion CP in a second direction, the second extension portion EP2 disposed between the first center portion CP and a second insulating separation pattern IP2. The plurality of first extension portions EP1 can be spaced apart from each other in a second direction (e.g., an X-axis direction) perpendicular to the first direction, and the second extension portion EP2 can be spaced apart from each other in the second direction. The semiconductor device 100B according to the present example embodiment can include a plurality of dummy channel layers 140D overlapping the backside connection pattern 192 in a vertical direction (e.g., a Z-axis direction). The dummy channel layers 140D can be disposed between the first insulating separation pattern IP1 and the second insulating separation pattern IP2 and between a third insulating separation pattern IP3 and a fourth insulating separation pattern IP4. The conductive connection pattern 175 can extend in the first direction (e.g., the Y-axis direction) and can cover an upper surface, a lower surface, and a side surface of at least one of the dummy channel layers 140D. The dummy channel layers 140D can include the same material as that of the plurality of first channel layers and the plurality of second channel layers of the first channel region 140A and the second channel region 140B, and can have the same or similar features as those of the plurality of first channel layers and the plurality of second channel layers of the first channel region 140A and the second channel region 140B. The dummy channel layers 140D can be in contact with dummy source / drain regions 150D. The dummy source / drain regions 150D can be disposed adjacent to the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4, respectively. The dummy source / drain regions 150D can be electrically insulated from each other by the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4. The dummy source / drain regions 150D can include a first dummy source / drain region and a second dummy source / drain region adjacent to the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4, respectively. The dummy channel layers 140D can be disposed in a region defined by the third insulating separation pattern IP3 and the fourth insulating separation pattern IP4, and the region can be an electrically insulating region. A lower pattern 195 can be disposed outside a region defined by the first insulating separation pattern IP1 and the second insulating separation pattern IP2. The first center portion CP can be disposed between the plurality of first extension portions EP1 and the second extension portion EP2, can serve to support the plurality of extension portions to mitigate or prevent collapse of the plurality of extension portions, and can be connected to the backside, and can provide an alignment position at which each of the backside connection pattern 192 and the frontside connection pattern 250 can be electrically connected to the connection structure 170.

[0084] Figure 5 is a plan view of the semiconductor device 100C according to an example embodiment of the inventive concepts.

[0085] Figure 6 is Figure 5 is a cross-sectional view of the semiconductor device 100C in FIG. 1 taken along line II-II’.

[0086] Referring to Figure 5 and Figure 6 , the semiconductor device 100C according to an example embodiment can have features that are the same as or similar to those described with reference to Figures 1 to 4B , except that the connection structure 170 is disposed in an area defined by the first and second insulating separation patterns IP1 and IP2. The first and second insulating separation patterns IP1 and IP2 can be disposed to be spaced apart from each other in a first direction (e.g., the Y-axis direction). The lower pattern 195 and the backside connection pattern 192 can be disposed between the first and second insulating separation patterns IP1 and IP2. The plurality of dummy channel layers can not be disposed in an area overlapping the backside connection pattern 192 in a vertical direction (e.g., the Z-axis direction), but the inventive concepts are not limited thereto.

[0087] Figure 7 is a cross-sectional view of the semiconductor device 100D according to an example embodiment of the inventive concepts taken along line II-II’.

[0088] Referring to Figure 7 , the semiconductor device 100D according to an example embodiment can have features that are the same as or similar to those described with reference to Figure 4B , except that the lower pattern 195 is disposed outside of an area defined by the first and second insulating separation patterns IP1 and IP2, and there are no dummy channel layers 140D (see Figures 1 to 6 ) overlapping the backside connection pattern 192 in a vertical direction. The first and second insulating separation patterns IP1 and IP2 can be spaced apart from each other in a first direction (e.g., the Y-axis direction). The backside connection pattern 192 can be disposed in an area defined by the first and second insulating separation patterns IP1 and IP2, and the lower pattern 195 can be disposed outside of the area defined by the first and second insulating separation patterns IP1 and IP2. The lower pattern 195 can be spaced apart from the backside connection pattern 192 in the first direction. The plurality of channel layers can not be disposed in an area overlapping the backside connection pattern 192 in a vertical direction (e.g., the Z-axis direction).

[0089] , except for the difference in the level at which the source / drain backside contact structure 191, the backside connection pattern 192, and the backside interconnect structure 180 are disposed, Figures 8 to 11The semiconductor devices 100E, 100F, 100G, and 100H according to the example embodiments of the inventive concept shown in FIGS. 1-4 can have the same or similar features as described with reference to Figures 1 to 7 features described.

[0090] Figure 8 is a cross-sectional view taken along line I-I’ of the semiconductor device 100E according to the example embodiments of the inventive concept, and shows regions corresponding to regions in Figure 2A .

[0091] Referring to Figure 8 , the semiconductor device 100E according to the example embodiments can include a backside interconnect structure 180, a lower backside interconnect line 182 disposed below the first backside interconnect structure 180, and a backside interconnect via 180V disposed between the backside interconnect structure 180 and the lower backside interconnect line 182. The backside interconnect via 180V can electrically connect the backside interconnect structure 180 and the lower backside interconnect line 182 to each other. In the example embodiments, the backside interconnect via 180V can be integral with the lower backside interconnect line 182. A backside connection pattern 192 can be electrically connected to the connection structure 170, and can be in contact with the lower backside interconnect line 182. A lower surface of the backside connection pattern 192 can be in contact with an upper surface of the lower backside interconnect line 182. The lower surface of the backside connection pattern 192 can be located at a lower level than a level of a lower surface of the backside interconnect structure 180.

[0092] Figure 9 is a cross-sectional view taken along line I-I’ of the semiconductor device 100F according to the example embodiments of the inventive concept, and shows regions corresponding to regions in Figure 2A .

[0093] Referring to Figure 9 , the semiconductor device 100F according to the example embodiments can include a backside connection pattern 192 and a backside interconnect structure 180 (shown as 192 in Figure 9 ) that are integral with each other. A backside contact barrier layer 192S can be formed to conformally cover a third recess region (“RS3” in Figure 22A and Figure 22B ). The backside contact barrier layer 192S can be in contact with a portion of a lower surface of the conductive connection pattern 175, and the backside contact barrier layer 192S can be in contact with a lower surface of the source / drain backside contact structure 191. A backside interconnect structure 180 and a backside contact conductive layer 192M (shown as 192M in Figure 9 ) can be formed on the backside contact barrier layer 192S, and can be formed using a single process.

[0094] Figure 10is a cross-sectional view of a semiconductor device 100G according to an example embodiment of the inventive concepts taken along line II′, and Figure 10 Shown with Figure 2A The area corresponding to the area in .

[0095] Reference Figure 10 , a semiconductor device 100G according to example embodiments may include a backside interconnection via 180V disposed between a backside interconnection structure 180 and a source / drain backside contact structure 191. Backside interconnection via 180V may have a cross-section having a width that gradually increases as the distance from the source / drain backside contact structure 191 increases. Backside interconnection via 180V may include the same material as that of the backside interconnection structure 180. Backside connection pattern 192 may extend such that a lowermost end of backside connection pattern 192 is located at the same level as a lowermost end of backside interconnection structure 180.

[0096] Figure 11 is a cross-sectional view of a semiconductor device 100H according to an example embodiment of the inventive concepts taken along line II′, and Figure 11 Shown with Figure 2A The area corresponding to the area in .

[0097] Reference Figure 11 , the semiconductor device 100H according to example embodiments may include a backside interconnect via 180V disposed between the backside interconnect structure 180 and the source / drain backside contact structure 191. The backside interconnect via 180V may have a cross-section having a width that gradually increases as the distance from the source / drain backside contact structure 191 increases. The backside connection pattern 192 may extend so that the lowermost end of the backside connection pattern 192 is located at the same level as the lowermost end of the backside interconnect via 180V. The lowermost end of the backside interconnect structure 180 may be located at a level lower than the level of the lowermost end of the backside connection pattern 192. The interconnect structure located at the same level as the backside interconnect structure 180 may be disposed below the backside connection pattern 192.

[0098] Figures 12 to 21B 100A are cross-sectional views illustrating sequential processes of a method of fabricating a semiconductor device 100A according to example embodiments of the inventive concepts. Figure 12 、 Figure 13A 、 Figure 14A 、 Figure 15 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19 、 Figure 20 and Figure 21A is with Figure 2A Shown inFigure 1 the manufacturing process of the cross section of the semiconductor device 100A in FIG. 1 corresponds to a cross-sectional view taken along the line I-I’, and Figure 13B 、 Figure 14B 、 Figure 16B 、 Figure 17B 、 Figure 18B and Figure 21B is a cross-sectional view taken along the line II-II’ corresponding to the manufacturing process of the cross section of the semiconductor device 100A in FIG. 2. Figure 2B Figure 1 the manufacturing process of the cross section of the semiconductor device 100A in FIG. 1 corresponds to a cross-sectional view taken along the line I-I’, and

[0099] Referring to Figure 12 , the horizontal sacrificial layers 120 and the channel layers 141, 142, and 143 can be alternately stacked on the semiconductor substrate 101.

[0100] The semiconductor substrate 101 can have an upper surface extending in the X-axis direction and the Y-axis direction. The semiconductor substrate 101 can include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The semiconductor substrate 101 can be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. The semiconductor substrate 101 can be removed using a subsequent process, and the semiconductor substrate 101 is subsequently changed to a backside insulating layer 194 in the form of an insulating substrate filled with an insulating material.

[0101] As shown in Figure 2A , the horizontal sacrificial layers 120 can be layers replaced with gate dielectric layers 162A and 162B and gate electrodes 165A and 165B below the uppermost channel layer 143 among the plurality of channel layers using a subsequent process. The horizontal sacrificial layers 120 can be formed of materials having etch selectivity with respect to the channel layers 141, 142, and 143, respectively. The channel layers 141, 142, and 143 can include materials different from those of the horizontal sacrificial layers 120. The horizontal sacrificial layers 120 and the channel layers 141, 142, and 143 can include, for example, a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), can include different materials, and can or can not include impurities. For example, the horizontal sacrificial layers 120 can include silicon germanium (SiGe), and the channel layers 141, 142, and 143 can include silicon (Si).

[0102] The horizontal sacrificial layers 120 and the channel layers 141, 142, and 143 can be formed by performing an epitaxial growth process from the substrate 101. In an example embodiment, the number of channel layers alternately stacked with the horizontal sacrificial layers can be modified in various ways.

[0103] Referring to​Figure 13A and Figure 13B The semiconductor pattern 105 including the active region can be formed, and a portion of the horizontal sacrificial layer 120 and the channel layers 141, 142, and 143 can be removed to form a first recessed region RS1.

[0104] The semiconductor pattern 105 including the active region can be formed on the semiconductor substrate 101. The semiconductor pattern 105 can extend in a second direction (e.g., an X-axis direction). The semiconductor pattern 105 can be defined to have a desired (or alternatively, predetermined) depth from an upper surface of a portion of the semiconductor substrate 101. The semiconductor pattern 105 can be formed as a portion of the semiconductor substrate 101, or can include an epitaxial layer grown from the semiconductor substrate 101. Each of the fin structures (e.g., semiconductor patterns) 105 can be in the form of an active fin protruding upward from an upper surface of the semiconductor substrate 101. The semiconductor pattern 105 can form, together with the channel region 140, an active structure in which a channel region of a transistor is formed.

[0105] Referring to Figure 3 , Figure 4A and Figure 4B together, the device isolation layer 110 can be located between the semiconductor patterns 105 adjacent to each other in the second direction (e.g., the X-axis direction). The upper surface of the semiconductor pattern 105 can be located at a level higher than that of the upper surface of the device isolation layer 110. The semiconductor pattern 105 can be formed by patterning the upper region of the horizontal sacrificial layer 120, the first to third channel layers 141, 142, and 143, and the semiconductor substrate 101.

[0106] As shown in Figure 1 , the semiconductor pattern 105 can be in the form of a line extending in one direction (e.g., the second direction (e.g., the X-axis direction)), and can be spaced apart from each other in the second direction.

[0107] A portion of the semiconductor pattern 105 can be removed to form a first recessed region RS1. In the first recessed region RS1, the upper surface RSU of the semiconductor substrate 101 can be exposed. The first recessed region RS1 can extend to a level lower than that of the lowermost horizontal sacrificial layer among the horizontal sacrificial layers 120. In an example embodiment, the first recessed region RS1 can extend to a lower surface of the device isolation layer 110 in the vertical direction on the semiconductor substrate 101, but the inventive concept is not limited thereto. The first recessed region RS1 can extend in the second direction.

[0108] Referring to Figure 14A and Figure 14BIn the first recess region RS1, the intermediate insulating layer 174 can be formed, and the first and second sacrificial gate structures 200A and 200B can be formed.

[0109] The intermediate insulating layer 174 can be formed on the upper surface of the RSU in the first recess region RS1. Figure 13A and Figure 13B The intermediate insulating layer 174 can include an oxide, and can be formed to extend along the first recess region RS1 in the first direction (e.g., the Y-axis direction). In some example embodiments, the intermediate insulating layer 174 can be formed to a level lower than the lower surface of the lowermost one of the horizontal sacrificial layers 120, but the present inventive concept is not limited thereto.

[0110] As shown in FIG. 1A, the first sacrificial gate structure 200A can be a sacrificial structure formed using a subsequent process in a region where the gate dielectric layers 162A and 162B and the gate electrodes 165A and 165B are disposed on the channel region 140. The first sacrificial gate structure 200A can have a linear shape intersecting the semiconductor pattern 105 and extending in the first direction. Figure 2A The first sacrificial gate structure 200A can include the first and second sacrificial gate layers 202A and 205A and the mask pattern layer 206A stacked in order. The first and second sacrificial gate layers 202A and 205A can be patterned using the mask pattern layer 206A. The first and second sacrificial gate layers 202A and 205A can be an insulating layer and a conductive layer, respectively, but the present inventive concept is not limited thereto, and the first and second sacrificial gate layers 202A and 205A can be formed as a single layer. For example, the first sacrificial gate layer 202A can include silicon oxide, and the second sacrificial gate layer 205A can include polysilicon. The mask pattern layer 206A can include silicon oxide and / or silicon nitride.

[0111] The second sacrificial gate structure 200B can have the same or similar features as those of the first sacrificial gate structure 200A, and thus the description of the second sacrificial gate structure 200B can be partially replaced with the above description of the first sacrificial gate structure 200A. The second sacrificial gate structure 200B can be formed on the intermediate insulating layer 174 to extend the second sacrificial gate structure 200B in the first direction. The second sacrificial gate structure 200B can be a dummy structure changed to the connection structure 170 in a subsequent process, and the width of the second sacrificial gate structure 200B in the second direction can be wider than the width of the first sacrificial gate structure 200A in the second direction.

[0112] Referring to FIG. 1A,

[0113] Figure 15 ​, the exposed horizontal sacrificial layer 120 and portions of the first to third channel layers 141 , 142 , and 143 may be removed using the first sacrificial gate structure 200A as a mask to form a second recess region RS2 .

[0114] The second recessed area RS2 may extend in a direction perpendicular to the upper surface of the substrate 101, and the lowermost end of each of the second recessed areas RS2 may be located at the same level as the upper surface of the intermediate insulating layer 174, but the present invention is not limited thereto. In this operation, the first to third channel layers 141, 142, and 143 may be formed into a channel area 140 having a limited length in the second direction (e.g., the X-axis direction). Next, the side surface of the horizontal sacrificial layer 120 exposed by the second recessed area RS2 may be partially removed to form a Figure 2A The inner spacer layer 130 in.

[0115] Reference Figure 16A and Figure 16B , the first and second sacrificial gate structures 200A and 200B may be removed, and the source / drain regions 150 , the gate structure GS, the connection structure 170 , and the third and fourth insulating separation patterns IP3 and IP4 may be formed.

[0116] The source / drain region 150 may be formed in the second recessed region RS2 and may be grown from the side surfaces of the semiconductor pattern 105 and the channel region 140 using, for example, a selective epitaxial growth process. The source / drain region 150 may include impurities through in-situ doping and may include a plurality of layers having different doping elements and / or doping concentrations. The source / drain region 150 may be referred to differently depending on the location where the source / drain region 150 is formed.

[0117] The first sacrificial gate structure 200A may be removed to form a gap region (not shown), and then a first gate structure GSA including a first gate dielectric layer 162A and a first gate electrode 165A filling the gap region may be formed. In the above process, multiple gate structures GS may be formed. During the removal and formation processes, the source / drain regions 150 may be protected by the inner spacer layer 130.

[0118] The process of forming the connection structure 170 may have the same or similar features as those of the process of forming the gate structure GS. The connection structure 170 may include an insulating pad 172 and a conductive connection pattern 175 formed on the insulating pad 172. The insulating pad 172 may be formed on the intermediate insulating layer 174 so that its lower surface contacts the upper surface of the intermediate insulating layer 174.

[0119] A third insulating separation pattern IP3 and a fourth insulating separation pattern IP4 can be formed in positions of the first sacrificial gate structures 200A among the first sacrificial gate structures adjacent to the second sacrificial gate structure 200B. The third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can include a material such as an oxide, a nitride, an oxynitride, or a combination thereof, can extend to the same level as a lowermost end of the device isolation layer 110, and can pass through the semiconductor substrate 101, but the inventive concept is not limited thereto. The third insulating separation pattern IP3 and the fourth insulating separation pattern IP4 can extend to the same level as a lower surface of the intermediate insulating layer 174, but the inventive concept is not limited thereto.

[0120] Referring to Figure 17A and Figure 17B The first interlayer insulating layer 173, the second interlayer insulating layer 177, and the front side insulating layer 176 can be formed, and the first source / drain front side contact plug 260, the front side connection pattern 250, the gate contact 255, and the first front side interconnection structure M1 can be formed.

[0121] The first interlayer insulating layer 173 can cover at least a portion of each of the gate structure GS, the source / drain regions 150A and 150B, the intermediate insulating layer 174, and the connection structure 170. The first interlayer insulating layer 173 can be formed to a level higher than an upper surface of each of the connection structure 170 and the gate structure GS.

[0122] The first source / drain front side contact plug 260, the front side connection pattern 250, and the gate contact 255 can be formed to pass through at least a portion of the first interlayer insulating layer 173. The first source / drain front side contact plug 260 can be formed to pass through at least a portion of one source / drain region (e.g., the fourth source / drain region 150B2). The first source / drain front side contact plug 260 can have a tapered shape having a width that gradually decreases toward the fourth source / drain region 150B2, but the inventive concept is not limited thereto. The front side connection pattern 250 and the gate contact 255 can be in contact with upper surfaces of the connection structure 170 and the gate structure GS, respectively. An upper surface of each of the front side connection pattern 250 and the gate contact 255 can be located at a level higher than a level of an upper surface of the first source / drain front side contact plug 260.

[0123] The first source / drain front side contact via member 265 can be disposed on the first source / drain front side contact plug 260. An upper surface of the first source / drain front side contact via member 265 can be located on the same level as an upper surface of each of the front side connection pattern 250 and the gate contact member 255. The first source / drain front side contact via member 265 can be surrounded by the second interlayer insulating layer 177 disposed on the same level. The first source / drain front side contact via member 265 can include the same material as that of the first source / drain front side contact plug 260, but the inventive concept is not limited thereto. Each of the first source / drain front side contact via member 265, the front side connection pattern 250, and the gate contact member 255 can be in contact with the first front side interconnection structure M1 disposed on an upper portion thereof, and can be electrically connected to the first front side interconnection structure M1. The first front side interconnection structure M1 can include a plurality of divided portions. The first front side interconnection structure M1 is illustrated as a single layer, but the inventive concept is not limited thereto, and the first front side interconnection structure M1 can include a plurality of interconnection lines stacked in a vertical direction (e.g., a Z-axis direction). In an example embodiment, the plurality of interconnection lines can include twelve interconnection lines, and the number thereof is not limited thereto. The plurality of interconnection lines further include interconnection via members electrically connecting the interconnection lines disposed on adjacent levels to each other, and can provide various connection paths for electrical signals of the semiconductor device.

[0124] Referring to Figure 18A and Figure 18B , the overall structure formed by Figures 12 to 17B can be attached to the carrier substrate CR, and the semiconductor substrate 101 can be removed.

[0125] The carrier substrate CR can be attached to the overall structure to perform a process on a lower surface of the semiconductor substrate 101 in Figure 17A and Figure 17B . The carrier substrate CR can be in contact with the first front side interconnection structure M1 and the front side insulating layer 176 surrounding the first front side interconnection structure M1. Specifically, the carrier substrate CR can be in contact with an uppermost insulating layer covering an uppermost interconnection line among the plurality of interconnection lines of the first front side interconnection structure M1. In the following drawings, for the sake of understanding, the overall structure is illustrated as being rotated or inverted in the form of a mirror image of the structure shown in Figure 17A and Figure 17B .

[0126] Referring to Figure 19 , the semiconductor pattern 105 (see Figure 18A and Figure 18B), and can form a lower pattern 195 covering at least a portion of each of the third and fourth insulating separation patterns IP3 and IP4 and the source / drain regions 150. In an example embodiment, the lower pattern 195 can include an insulating material such as an oxide or a nitride to protect other conductive contact structures and source / drain regions, but the inventive concept is not limited thereto. The lower pattern 195 can be in contact with at least a portion of the source / drain regions 150. A lower surface of the lower pattern 195 can be located at the same level as a lower surface of each of the third and fourth insulating separation patterns IP3 and IP4 and the intermediate insulating layer 174. According to an example embodiment, at least a portion of the semiconductor pattern 105 can be preserved, and a subsequent process can be performed in a state that at least a portion of the semiconductor pattern 105 is preserved.

[0127] Referring to Figure 20 The backside contact structure 191 can be formed to pass through at least a portion of the lower pattern 195, and to be connected to the first to third source / drain regions 150A1, 150A2, and 150B1. The backside contact structure 191 can include an upper region 191U passing through at least a portion of the first to third source / drain regions 150A1, 150A2, and 150B1, and a lower region 191L extending from the upper region 191U.

[0128] Referring to Figure 21A and Figure 21B The backside insulating layer 194 can be formed on the intermediate insulating layer 174 and the lower pattern 195. In an example embodiment, the backside insulating layer 194 can include the same material as that of the lower pattern 195, but the inventive concept is not limited thereto, and can be formed to include an insulating substrate of an insulating material such as an oxide or a nitride to protect other conductive contact structures, but the inventive concept is not limited thereto. The backside insulating layer 194 can extend in the first and second directions, and can be formed to cover each of the components of the overall structure attached to the carrier substrate CR. The backside insulating layer 194 can be disposed on the lower pattern 195. A lower surface of the lower pattern 195 and an upper surface of the backside insulating layer 194 can be located at the same level, and can correspond to an interface between the lower pattern 195 and the backside insulating layer 194.

[0129] Referring to Figure 22A and Figure 22BThe third recess region RS3 can be formed to expose at least a portion of the lower surface 175LS of the conductive connection pattern 175. The third recess region RS3 can have a cross-section that has a width that gradually increases as a distance from the connection structure 170 increases, in view of the aspect ratio of the third recess region RS3. The third recess region RS3 can be formed by removing a portion of each of the backside insulating layer 194, the middle insulating layer 174, and the insulating liner 172. When a portion of the insulating liner 172 is removed, a portion of the conductive connection pattern 175 can be exposed from the insulating liner 172 in the third recess region RS3.

[0130] In such a process, the form or level at which the third recess region RS3 is formed can be adjusted, thereby manufacturing the semiconductor device 100A according to the example embodiments in Figures 5 to 8 .

[0131] Referring to Figure 23A and Figure 23B , the backside connection pattern 192 can be formed. The backside contact barrier layer 192S can be formed to conformally cover the third recess region (see “RS3” in Figure 22A and Figure 22B ). The backside contact barrier layer 192S can be part of a seed layer required for a plating process of the backside contact conductive layer 192M in a subsequent process. The backside contact barrier layer 192S can include a metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The backside contact conductive layer 192M can include a metal material such as copper (Cu), aluminum (Al), tungsten (W), or molybdenum (Mo). The backside contact barrier layer 192S and the backside contact conductive layer 192M can undergo a subsequent planarization process to form the backside connection pattern 192.

[0132] Next, referring to Figure 1 , Figure 2A and Figure 2B together, the carrier substrate CR can be removed, and the backside interconnection structure 180 connected to the backside connection pattern 192 can be formed. The backside interconnection structure including the backside interconnection structure 180 is shown to have a single-layer structure, but the inventive concepts are not limited thereto and can have a multi-layer structure. Thus, the semiconductor device 100A in Figures 1 to 2B can be manufactured.

[0133] According to some example embodiments of the inventive concepts, a connection structure and a contact structure electrically connected to a lower end of the connection structure can be used, thereby providing a semiconductor device having improved reliability and electrical performance.

[0134] While the above has been described with some examples, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor device comprising: a first transistor including a first gate electrode, a first gate dielectric layer, a first source / drain region, a second source / drain region, and a first channel region; a second transistor located at the same level as the first transistor, the second transistor including a second gate electrode, a second gate dielectric layer, a third source / drain region, a fourth source / drain region, and a second channel region; a first source / drain backside contact structure located below the first source / drain region, the first source / drain backside contact structure connected to the first source / drain region; a conductive connection pattern including at least a portion located at the same level as the first gate electrode and the second gate electrode; a backside connection pattern located below the conductive connection pattern, the backside connection pattern connected to the conductive connection pattern; a frontside connection pattern located on the conductive connection pattern, the frontside connection pattern connected to the conductive connection pattern; a first frontside contact plug located on the second transistor, the first frontside contact plug connected to the second transistor; and a first frontside interconnect structure located on the frontside connection pattern and the first frontside contact plug, the first frontside interconnect structure electrically connecting the frontside connection pattern and the first frontside contact plug to each other, wherein the first channel region includes first channel layers spaced apart from each other in a vertical direction, wherein the second channel region includes second channel layers spaced apart from each other in the vertical direction, wherein the first channel layers are located between the first source / drain region and the second source / drain region, and wherein the second channel layers are located between the third source / drain region and the fourth source / drain region.

2. The semiconductor device according to claim 1, wherein each of the first gate electrode and the second gate electrode extends in a first direction, and a maximum width of the conductive connection pattern in a second direction perpendicular to the first direction is greater than a width of each of the first gate electrode and the second gate electrode. a distance between an upper surface and a lower surface of the conductive connection pattern is greater than a distance between an upper surface and a lower surface of the first gate electrode.

3. The semiconductor device according to claim 1, wherein 4. The semiconductor device according to claim 1, wherein the first gate electrode vertically overlaps the first channel layers, and a lower surface of the first gate electrode is located at a higher level than a lower surface of the conductive connection pattern.

5. The semiconductor device according to claim 1, wherein an upper surface of the conductive connection pattern is located at a higher level than an uppermost one of the first channel layers, and a lower surface of the conductive connection pattern is located at a lower level than a lowermost one of the first channel layers.

6. The semiconductor device according to claim 1, further comprising: a first insulating separation pattern and a second insulating separation pattern, wherein each of the first gate electrode and the second gate electrode extends in a first direction, ​ the first insulating separation pattern and the second insulating separation pattern are spaced apart from each other in the first direction, and the conductive connection pattern is located between the first insulating separation pattern and the second insulating separation pattern.

7. The semiconductor device according to claim 6, further comprising: first outer channel layers that are spaced apart from each other in the vertical direction; and second outer channel layers that are spaced apart from each other in the vertical direction, wherein the first insulating separation pattern and the second insulating separation pattern are located between the first outer channel layers and the second outer channel layers.

8. The semiconductor device according to claim 6, wherein the conductive connection pattern includes: a first central portion; a first extension portion that extends from the first central portion, the first extension portion being located between the first central portion and the first insulating separation pattern; and a second extension portion that extends from the first central portion, the second extension portion being located between the first central portion and the second insulating separation pattern, wherein the first extension portions are spaced apart from each other in a second direction perpendicular to the first direction, and the second extension portions are spaced apart from each other in the second direction.

9. The semiconductor device according to claim 6, further comprising: a third insulating separation pattern located between the first transistor and the conductive connection pattern; and a fourth insulating separation pattern located between the second transistor and the conductive connection pattern.

10. The semiconductor device according to claim 9, wherein an upper surface of each of the third insulating separation pattern and the fourth insulating separation pattern is located at a higher level than an upper surface of the conductive connection pattern, a lower surface of each of the third insulating separation pattern and the fourth insulating separation pattern is located at a lower level than a lower surface of the conductive connection pattern.

11. The semiconductor device according to claim 9, wherein each of the first gate electrode and the second gate electrode extends in the first direction, each of the third insulating separation pattern and the fourth insulating separation pattern extends in the first direction, in a second direction perpendicular to the first direction, a maximum width of the conductive connection pattern is greater than a width of each of the third insulating separation pattern and the fourth insulating separation pattern. the conductive connection pattern is in contact with the first insulating separation pattern and the second insulating separation pattern, and is spaced apart from the third insulating separation pattern and the fourth insulating separation pattern.

12. The semiconductor device according to claim 9, wherein 13. The semiconductor device according to claim 9, further comprising: dummy channel layers located between the first insulating separation pattern and the second insulating separation pattern, the dummy channel layers being located between the third insulating separation pattern and the fourth insulating separation pattern, the dummy channel layers being spaced apart from each other in the vertical direction, wherein the conductive connection pattern extends in the first direction and covers an upper surface, a lower surface, and side surfaces of at least one of the dummy channel layers.

14. The semiconductor device according to claim 13, wherein ​ Each of the dummy channel layers has a width in a second direction that is greater than a width of each of the first and second channel layers in the second direction, and The second direction is perpendicular to the first direction.

15. The semiconductor device of claim 14, further comprising: a first dummy source / drain region and a second dummy source / drain region, wherein the dummy channel layers are located between the first and second dummy source / drain regions, and the first and second dummy source / drain regions are located between the third and fourth insulating separation patterns.

16. The semiconductor device of claim 1, wherein an upper surface of the first source / drain backside contact structure is located at a higher level than a lower surface of the conductive connection pattern, and a lower surface of the first source / drain backside contact structure is located at a lower level than the lower surface of the conductive connection pattern.

17. The semiconductor device of claim 16, further comprising: a first source / drain backside interconnect structure located below the first source / drain backside contact structure, the first source / drain backside interconnect structure connected to the first source / drain backside contact structure, wherein the lower surface of the first source / drain backside contact structure is located at a higher level than a lower surface of the backside connection pattern.

18. The semiconductor device according to claim 17, wherein a lower surface of the first source / drain backside interconnect structure is coplanar with the lower surface of the backside connection pattern.

19. A semiconductor device, comprising: a backside insulating layer; a gate structure located on the backside insulating layer, the gate structure including a gate electrode extending in a first direction; a first source / drain region and a second source / drain region on opposite sides of the gate structure, the first and second source / drain regions spaced apart from each other; a channel region located between the first and second source / drain regions, the channel region overlapping at least a portion of the gate electrode in a vertical direction; a conductive connection pattern extending in the first direction, the conductive connection pattern including at least a portion located at a same level as the gate electrode; a frontside connection pattern located on the conductive connection pattern, the frontside connection pattern in contact with the conductive connection pattern; a backside connection pattern located below the conductive connection pattern, the backside connection pattern in contact with the conductive connection pattern; a first frontside contact plug located on the gate electrode, the first frontside contact plug connected to the gate electrode; a first frontside interconnect structure located on the frontside connection pattern and the first frontside contact plug, the first frontside interconnect structure connecting the frontside connection pattern and the first frontside contact plug to each other; a first backside contact structure located below the first source / drain region, the first backside contact structure connected to the first source / drain region; and a second backside contact structure located below the second source / drain region, the second backside contact structure connected to the second source / drain region. a first source / drain front side contact plug on the second source / drain region, the first source / drain front side contact plug being connected to the second source / drain region.

20. The semiconductor device according to claim 19, wherein the channel region comprises channel layers spaced apart from each other in the vertical direction, and a lower surface of the back side connection pattern is located at a lower level than a lower surface of the first back side contact structure.

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