TBC battery and preparation method thereof
By forming a PN junction on the back of a silicon substrate and isolating the P and N regions, and combining this with a specific process to fabricate metal electrodes, the problem of low efficiency and yield of TBC cells has been solved, and high-efficiency and high-yield TBC cell production has been achieved.
Patent Information
- Application Number
- CN202411132650.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2025-10-24
AI Technical Summary
The existing TBC battery structure and its process are not yet mature and cannot effectively improve battery efficiency and production yield.
A PN junction is formed on the back side of a silicon substrate, with the junction formed only in the P-region on the back side. The P-region and N-region on the back side are isolated from each other. Metal electrodes are fabricated using masking technology. P-Poly and N-Poly silicon layers are formed using specific diffusion and etching processes, combined with a SiO2 tunneling layer and a SiNx passivation contact structure.
It improves carrier transport rate, reduces leakage rate, and enhances battery efficiency and production yield, making it suitable for industrial mass production.
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Figure CN120835618A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of solar cells, in particular to a TBC cell and a preparation method thereof. BACKGROUND
[0002] The TBC (Tunnel Back Contact) solar cell is a new type of cell structure, which is obtained by combining the TOPCon cell technology and the IBC cell technology. By combining the high short-circuit current of the IBC technology and the excellent passivation contact characteristics of the TOPCon technology, the TBC cell is expected to achieve higher conversion efficiency.
[0003] However, the current TBC cell structure and process are not mature, which cannot effectively improve the cell efficiency and cannot effectively improve the cell production yield.
[0004] Therefore, the present application is proposed. SUMMARY
[0005] One of the purposes of the present application is to provide a TBC cell with high carrier transport rate and high cell efficiency.
[0006] The second purpose of the present application is to provide a preparation method of the TBC cell, which is beneficial to improve the production yield and is suitable for industrial mass production.
[0007] In order to achieve the above purposes of the present application, the following technical solutions are adopted:
[0008] In a first aspect, a TBC cell is provided, which forms a PN junction on the back surface of a silicon substrate, and the PN junction is formed only in the P region of the back surface of the silicon substrate.
[0009] The P region and the N region of the back surface of the silicon substrate are isolated from each other.
[0010] Further, the thickness of the SiO2 tunnel layer in the back surface passivation contact structure of the silicon substrate is 1.2-1.8 nm.
[0011] The thickness of the P-Poly silicon layer of the P region of the back surface of the silicon substrate is 80-150 nm.
[0012] The thickness of the N-Poly silicon layer of the N region of the back surface of the silicon substrate is 80-150 nm.
[0013] Further, the P region and the N region of the back surface of the silicon substrate are respectively provided with metal electrodes.
[0014] In a second aspect, a preparation method of the TBC cell is provided, which comprises the following steps:
[0015] The back surface of the silicon substrate is diffused to form a PN junction, the PN junction of the N region is removed, then a passivation contact structure is formed on the back surface, and then a P-Poly silicon layer and an N-Poly silicon layer are formed on the back surface P region and the back surface N region by diffusion, respectively, then the back surface P region and the back surface N region are isolated by a mask technology, and finally a metal electrode is prepared to obtain the TBC battery.
[0016] Further, the silicon substrate comprises an N-type silicon wafer;
[0017] The diffusion method for forming the PN junction comprises forming the PN junction by boron diffusion;
[0018] The flow ratio of BCl3, O2 and N2 used in the boron diffusion is (1-3) : (2-5) : (5-9);
[0019] The boron diffusion temperature is 900-1000 DEG C, and the time is 70-150 min.
[0020] Further, the method for removing the PN junction of the N region comprises removing the PN junction by laser patterning;
[0021] The step of removing the PN junction of the N region further comprises the step of removing the BSG layer on the front and back surfaces of the silicon substrate.
[0022] Further, the step of forming the passivation contact structure further comprises the step of depositing SiN x mask layer on the back surface of the silicon substrate;
[0023] The thickness of the SiN x mask layer is 30-60 nm;
[0024] The method for diffusing the back surface P region to form the P-Poly silicon layer comprises the following steps:
[0025] After removing the SiN x mask layer on the back surface P region of the silicon substrate, boron diffusion is performed to convert the intrinsic Poly silicon layer of the back surface P region into a P-Poly silicon layer;
[0026] The method for diffusing the back surface N region to form the N-Poly silicon layer comprises the following steps:
[0027] After removing the SiN x mask layer on the back surface N region of the silicon substrate, phosphorus diffusion is performed to convert the intrinsic Poly silicon layer of the back surface N region into an N-Poly silicon layer.
[0028] Further, the method for isolating the back surface P region and the back surface N region comprises the following steps:
[0029] First, the SiN xThe passivation film, the outermost layer of the back surface P region and the back surface N region of the silicon substrate is printed with a paraffin mask layer through a screen printing process, and then chemical etching is performed to separate the back surface P region and the back surface N region;
[0030] The SiN x The thickness of the passivation film is 60nm-100nm;
[0031] The width of the paraffin mask layer is 60nm-150nm, and the height is 10nm-40nm;
[0032] The chemical etching mode comprises etching through an acid solution;
[0033] The concentration of HNO3 in the acid solution is 5%-8%, and the concentration of HF is 4%-8%.
[0034] Further, the preparation method further comprises the step of forming a pyramid texture structure on the front surface of the silicon substrate;
[0035] The step of forming the pyramid texture structure further comprises the step of forming a SiN x film layer on the front surface of the silicon substrate.
[0036] Further, the method for preparing a metal electrode comprises the following steps:
[0037] The silver paste is printed on the back surface P region and the back surface N region of the silicon substrate, and then sintering treatment is performed to form a metal electrode.
[0038] Compared with the prior art, the present application has at least the following beneficial effects:
[0039] The TBC battery provided by the present application can accelerate the movement of carriers by forming a PN junction in the back surface P region of the silicon substrate, forming an internal electric field in the junction region, and thus can improve the carrier transmission rate, thereby being beneficial to improving the battery efficiency.
[0040] The preparation method of the TBC battery provided by the present application uses a mask technology to separate the P region and the N region of the back surface from each other, which can reduce the proportion of electric leakage and is beneficial to improving the production yield and is suitable for industrial mass production. BRIEF DESCRIPTION OF DRAWINGS
[0041] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.
[0042] Figure 1The structure schematic diagram of the N-type silicon wafer back surface after boron diffusion provided by one embodiment of the present application is shown in the figure;
[0043] Figure 2 The structure schematic diagram of the N-type silicon wafer back surface after printing the outermost paraffin mask layer provided by one embodiment of the present application is shown in the figure;
[0044] Figure 3 The structure schematic diagram of the TBC battery provided by one embodiment of the present application is shown in the figure.
[0045] Figure legend: 1-boron diffusion layer; 2-SiO2tunneling layer; 3-P-Poly silicon layer; 4-N-Poly silicon layer; 5-back surface SiN x film layer; 6-front surface SiN x film layer; 7-positive metal electrode; 8-negative metal electrode; 9-paraffin mask layer; 11-BSG layer. DETAILED DESCRIPTION
[0046] The technical solutions of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.
[0047] According to the first aspect of the present application, a high-efficiency TBC battery is provided, which forms a PN junction on the back surface of a silicon substrate, and the PN junction is formed only in the P region on the back surface of the silicon substrate.
[0048] Meanwhile, the P region and the N region on the back surface of the silicon substrate are isolated from each other.
[0049] The high-efficiency TBC battery provided by the present application can accelerate the movement of carriers by forming a PN junction in the P region on the back surface of the silicon substrate, and the PN junction forms a built-in electric field in the junction region, which can accelerate the movement of carriers, thereby improving the carrier transmission rate and further improving the battery efficiency.
[0050] In a preferred embodiment, the thickness of the SiO2tunneling layer in the back surface passivation contact structure of the silicon substrate can be 1.2 nm-1.8 nm, and its typical but non-limiting thickness is, for example, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, or 1.8 nm.
[0051] In a preferred embodiment, the thickness of the P-Poly silicon layer in the P region on the back surface of the silicon substrate can be 80 nm-150 nm, and its typical but non-limiting thickness is, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm.
[0052] In a preferred embodiment, the thickness of the N-Poly silicon layer of the back N region of the silicon substrate can be 80-150 nm, and a typical but non-limiting thickness can be, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm.
[0053] In the present application, metal electrodes are provided on the back P region and the back N region of the silicon substrate, and the metal electrodes include but are not limited to silver electrodes.
[0054] According to a second aspect of the present application, a method for preparing the TBC cell as described above is provided, and the method comprises the following steps:
[0055] First, the back of the silicon substrate is diffused to form a PN junction, and then the PN junction of the N region is removed. After that, a passivation contact structure is formed on the back, and then a P-Poly silicon layer and an N-Poly silicon layer are formed on the back P region and the back N region, respectively, by diffusion. After that, the back P region and the back N region are isolated by a mask technique, and then metal electrodes are prepared to obtain the TBC cell.
[0056] The method for preparing the TBC cell provided by the present application can separate the P region and the N region of the back from each other by using a mask technique, which can reduce the proportion of electric leakage and is conducive to improving the production yield of the cell and is suitable for industrial mass production.
[0057] In a preferred embodiment, the silicon substrate can be an N-type silicon wafer, and the PN junction on the back of the silicon substrate can be formed by boron diffusion. The flow ratio of BCl3, O2, and N2 used for boron diffusion can be (1-3):(2-5):(5-9), the temperature for boron diffusion can be 900-1000°C, and a typical but non-limiting temperature can be, for example, 900°C, 920°C, 940°C, 960°C, 980°C, or 1000°C. The time for boron diffusion can be 70-150 min, and a typical but non-limiting time can be, for example, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, 130 min, 140 min, or 150 min.
[0058] The boron diffusion and the process parameters thereof in the present application are more conducive to further improving the effect of forming a PN junction on the back of an N-type silicon wafer.
[0059] In a preferred embodiment, the method for removing the PN junction of the N region includes but is not limited to removing the PN junction by laser patterning.
[0060] The present application adopts laser patterning technology to remove the PN junction of the N region; wherein the laser power percentage can be 20%-80%, and its typical but non-limiting percentages are for example 20%, 30%, 40%, 50%, 60%, 70%, 80%; the scanning speed can be 20000mm / s-45000mm / s, and its typical but non-limiting speeds are for example 20000mm / s, 25000mm / s, 35000mm / s, 40000mm / s, 45000mm / s.
[0061] In a preferred embodiment, the step of removing the PN junction of the N region is followed by a step of removing the BSG layer on the front and back surfaces of the silicon substrate.
[0062] In the present application, the BSG layer on the front and back surfaces of the silicon substrate can be removed by polishing cleaning process, and the solution used can be HF solution; wherein the concentration of the HF solution can be 4%-8%, and its typical but non-limiting concentrations are for example 4%, 5%, 6%, 7%, 8%; the polishing cleaning process time can be 200s-600s, and its typical but non-limiting times are for example 200s, 300s, 400s, 500s, 600s. The above polishing cleaning and its process parameters are more conducive to further improving the BSG layer removal effect.
[0063] In a preferred embodiment, the step of forming the passivation contact structure is followed by a step of depositing SiN x mask layer on the back surface of the silicon substrate; wherein the SiN x The thickness of the SiN
[0064] In the present application, the SiN x mask layer on the back surface of the silicon substrate can be deposited by PECVD process, and the deposition temperature can be 350℃-500℃, and its typical but non-limiting temperatures are for example 350℃, 360℃, 370℃, 380℃, 390℃, 400℃, 420℃, 440℃, 460℃, 480℃, 500℃, and the deposition time can be 30min-60min, and its typical but non-limiting times are for example 30min, 40min, 50min, 60min. x The flow ratio of the gases NH3 and SiH4 required for the deposition of the SiN x mask layer can be (1-3):(5-15). The above PECVD process and its process parameters are more conducive to further improving the deposition effect of the SiN
[0065] The method for forming a P-Poly silicon layer on the back surface P region of the present application comprises the following steps:
[0066] SiN mask layer is removed from the back surface P region of the silicon substrate x After the mask layer is removed, boron diffusion is performed to convert the intrinsic Poly silicon layer of the back surface P region into a P-Poly silicon layer.
[0067] In the present application, laser patterning technology can be used to remove the SiN mask layer from the back surface P region of the silicon substrate x The mask layer is removed, and the laser power percentage can be 20%-80%, and the scanning speed can be 20000mm / s-45000mm / s; then, a boron diffusion process is used to convert the intrinsic Poly silicon layer of the back surface P region into a P-Poly silicon layer, and a BSG layer is formed on the surface; wherein the gas used for boron diffusion is BCl3, O2 and N2, the BCl3 gas flow can be 100sccm-600sccm, the O2 gas flow can be 1500sccm-10000sccm, and the N2 gas flow can be 15000sccm-30000sccm; the boron diffusion temperature can be 850℃-950℃, and the boron diffusion time can be 80min-120min.
[0068] The method for diffusing an N-Poly silicon layer on the back surface N region of the silicon substrate comprises the following steps:
[0069] SiN mask layer is removed from the back surface N region of the silicon substrate x After the mask layer is removed, phosphorus diffusion is performed to convert the intrinsic Poly silicon layer of the back surface N region into an N-Poly silicon layer.
[0070] In the present application, laser patterning technology can be used to remove the SiN mask layer from the back surface N region of the silicon substrate x The mask layer is removed, and the laser power percentage can be 20%-80%, and the scanning speed can be 20000mm / s-45000mm / s; then, a boron diffusion process is used to convert the intrinsic Poly silicon layer of the back surface P region into a P-Poly silicon layer, and a BSG layer is formed on the surface; wherein the gas used for boron diffusion is BCl3, O2 and N2, the BCl3 gas flow can be 100sccm-600sccm, the O2 gas flow can be 1500sccm-10000sccm, and the N2 gas flow can be 15000sccm-30000sccm; the boron diffusion temperature can be 850℃-950℃, and the boron diffusion time can be 80min-120min.
[0071] In a preferred embodiment, the BSG layer and the PSG layer on the surface of the silicon wafer can be removed by a wet chemical method, and the solution used in the wet chemical method can be a mixed solution containing HNO3 and HF, wherein the concentration of HNO3 in the solution can be 2%-6%, the concentration of HF in the solution can be 4%-8%, and the treatment time of the wet chemical method can be 200s-500s.
[0072] The wet chemical method and its process parameters are more conducive to fully removing the BSG layer and the PSG layer.
[0073] In a preferred embodiment, the method for isolating the back P region and the back N region comprises the following steps:
[0074] First, forming a SiN x passivation film on the back of the silicon substrate, then printing a paraffin mask layer on the outermost layer of the back P region and the back N region of the silicon substrate by a screen printing process, and then performing chemical etching to isolate the back P region and the back N region.
[0075] In the present application, a PECVD process can be used to deposit a SiN x passivation film on the back of the silicon substrate. x The thickness of the SiN x passivation film can be 60-100 nm, and its typical but non-limiting thickness is, for example, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.
[0076] In the present application, the SiN x passivation film is deposited at a temperature of 350-500°C, and its typical but non-limiting temperature is, for example, 350°C, 360°C, 370°C, 380°C, 390°C, 400°C, 420°C, 440°C, 460°C, 480°C, or 500°C, and the deposition time is 30-80 min, and its typical but non-limiting time is, for example, 30 min, 40 min, 50 min, 60 min, 70 min, or 80 min. x The flow ratio of the gases NH3, SiH4, and N2O required for the deposition of the SiN x passivation film can be (1-3):(5-15):(3-13).
[0077] In the present application, a screen printing process is used to print a paraffin mask layer on the outermost layer of the back P region and the back N region, which is prepared for the subsequent chemical etching process, and the purpose is to protect the SiN x passivation film that needs to be retained on the back of the silicon wafer.
[0078] The width of the paraffin mask layer can be 60-150 nm, and its typical but non-limiting width is, for example, 60 nm, 80 nm, 100 nm, 120 nm, or 150 nm, and the height of the paraffin mask layer can be 10-40 nm, and its typical but non-limiting height is, for example, 10 nm, 20 nm, 30 nm, or 40 nm.
[0079] The back P region and the back N region of the silicon substrate are isolated by chemical etching, so as to reduce the battery leakage; the chemical etching can be acid etching, the concentration of HNO3 in the acid can be 5%-8%, and the concentration of HF can be 4%-8%; the temperature of the chemical etching can be 40-70°C, and the time of the chemical etching can be 200-500s. The chemical etching and the process parameters thereof are more conducive to ensuring that the back P region and the back N region are fully isolated.
[0080] In a preferred embodiment, the preparation method further comprises the step of forming a pyramid texture structure on the front surface of the silicon substrate.
[0081] All the doped layers formed on the front surface of the silicon substrate are removed to expose the silicon wafer body, and then a pyramid texture structure is formed on the surface thereof to reduce reflection.
[0082] In a preferred embodiment, the step of forming a pyramid texture structure is followed by the step of forming a SiN x film layer (antireflection layer) on the front surface of the silicon substrate.
[0083] In the present application, a PECVD process can be used to deposit and prepare a SiN x film layer on the front surface of the silicon substrate as an antireflection layer, the thickness of the SiN x film layer can be 60-90nm, the deposition temperature thereof can be 350-500°C, and the deposition time thereof can be 30-50min; wherein the flow ratio of the gases NH3, SiH4 and N2O required for the deposition of the SiN x film layer can be (1-3):(5-15):(3-13). The PECVD process and the process parameters thereof are more conducive to further improving the deposition effect of the SiN x film layer.
[0084] In a preferred embodiment, the method for preparing a metal electrode comprises the following steps:
[0085] The silver paste is printed on the back P region and the back N region of the silicon substrate respectively, and then sintering treatment is performed to form a metal electrode, and thus a complete battery piece is obtained.
[0086] A typical preparation method of a TBC battery comprises the following steps:
[0087] Step 1: providing an N-type silicon wafer as a silicon substrate, and performing double-sided polishing treatment on the silicon substrate;
[0088] Step 2: performing boron diffusion on the back surface of the N-type silicon wafer to form a PN junction and a BSG layer;
[0089] The structure of the silicon wafer after boron diffusion is shown in the following figure:Figure 1 , forming a boron diffusion layer 1 and a BSG layer 11, the boron diffusion layer 1 being a PN junction;
[0090] The gas required for boron diffusion is BCl3, O2 and N2, the flow ratio is (1-3):(2-5):(5-9); the thickness of the BSG layer is 40-80 nm; the boron diffusion temperature is 900-1000℃, and the boron diffusion time is 70-150 min;
[0091] Step 3: The PN junction of the N region is removed by laser patterning, that is, the boron diffusion layer 1 of the N region is removed;
[0092] The laser power percentage is 20-80%, and the scanning speed is 20000-45000 mm / s;
[0093] Step 4: The BSG layer on the front and back surfaces of the silicon substrate is removed by polishing and cleaning process. The polishing and cleaning solution required is HF solution, the concentration is 4-8%, and the polishing and cleaning time is 200-600 s;
[0094] Step 5: The SiO2 tunnel layer 2 is deposited on the back surface of the silicon substrate by LPCVD process. The SiO2 tunnel layer 2 is deposited on the boron diffusion layer 1 and the surface of the silicon wafer, respectively, as shown in Figure 2 , and then an intrinsic amorphous silicon layer (i-Poly-Si) is deposited;
[0095] The thickness of the SiO2 tunnel layer is 1.2-1.8 nm, the gas used for deposition is O2, the gas flow is 20000-30000 sccm, the deposition time is 400-600 s, and the deposition temperature is 500-700℃;
[0096] The thickness of the intrinsic amorphous silicon layer is 80-150 nm, the gas used for deposition is SiH4 and N2, the gas flow is 10000-20000 sccm and 15000-30000 sccm, respectively, the deposition time is 1000-2000 s, and the deposition temperature is 500-700℃;
[0097] Step 6: A layer of SiN x mask layer is deposited on the back surface of the silicon substrate by PECVD process. The thickness of the SiN x mask layer is 30-60 nm, the deposition temperature is 350-500℃, the deposition time is 30-60 min, and the flow ratio of the gases NH3 and SiH4 required for deposition is (1-3):(5-15);
[0098] Step 7: The SiN xMask, for preparing P-Poly, laser power percentage is 20%-80%, scanning speed is 20000mm / s-45000mm / s;
[0099] Step 8: the intrinsic Poly silicon of back P region is converted into P-Poly silicon layer 3 by using boron diffusion process, see Figure 2 , and BSG layer is formed on the surface;
[0100] Wherein, the gas used for boron diffusion is BCl3, O2 and N2, BCl3 gas flow is 100sccm-600sccm, O2 gas flow is 1500sccm-10000sccm, N2 gas flow is 15000sccm-30000sccm; boron diffusion temperature is 850-950℃, boron diffusion time is 80-120min;
[0101] Step 9: SiN x Mask, for preparing N-Poly, laser power percentage is 20%-80%, scanning speed is 20000mm / s-45000mm / s;
[0102] Step 10: the intrinsic Poly silicon of back N region is converted into N-Poly silicon layer 4 by using phosphorus diffusion process, see Figure 2 , and PSG layer is formed on the surface;
[0103] Wherein, the gas used for phosphorus diffusion is POCl3, O2 and N2, flow ratio is (2-5):(1-3):(6-9); phosphorus diffusion temperature is 850-950℃, phosphorus diffusion time is 80-100min;
[0104] Step 11: BSG layer and PSG layer on the surface of silicon substrate are removed by using wet chemical method, the solution used is mixed solution containing HNO3 and HF, HNO3 concentration is 2%-6%, HF concentration is 4%-8%, processing time is 200-500s;
[0105] Step 12: SiN x Passivation film, that is, back SiN x layer 5, see Figure 2 , SiN x Passivation film thickness is 60-100nm, deposition temperature is 350-500℃, deposition time is 30-80min, the flow ratio of NH3, SiH4 and N2O required for deposition is (1-3):(5-15):(3-13);
[0106] Step 13: printing a layer of paraffin mask layer 9 on the outermost layer of the back P region and the back N region by using a silk screen printing process, see Figure 2 , to prepare for the next step of chemical etching treatment, i.e. to protect the SiN x layer on the back of the silicon substrate which needs to be reserved;
[0107] wherein the width of the paraffin mask layer is 60-150 nm and the height is 10-40 nm;
[0108] Step 14: removing all the doped layers formed on the front of the silicon substrate by using a wet chemical method to expose the silicon substrate, and forming a pyramid texture on the surface thereof to reduce reflection; at the same time, isolating the P region and the N region on the back of the silicon substrate by chemical etching, i.e. forming a gap between the P region and the N region to isolate them, see Figure 3 , to reduce the proportion of battery leakage;
[0109] wherein the P-Poly silicon layer on the front of the silicon substrate is removed by a chain alkali tank process and the tunneling layer is removed by an acid tank process; the alkali tank process formula is 3%-5% KOH, 0.5%-1% additive (main components are 0.1%-3% sodium hydroxide and 2%-10% isopropyl alcohol) and 4%-8% H2O2, and the process time is 300-600 s; the acid tank uses HF solution with a concentration of 4%-8% and a process time of 200-500 s;
[0110] The P region and the N region on the back are isolated by an acid tank process, the acid tank is HNO3 with a concentration of 5%-8% and HF with a concentration of 4%-8%, the process temperature is 40-70°C, and the process time is 200-500 s;
[0111] The front of the silicon substrate is prepared into a pyramid texture structure to reduce reflection by an alkali tank process, the alkali tank process formula is 3%-5% KOH, 0.5%-1% additive and 4%-8% H2O2, the process temperature is 60-80°C, and the process time is 400-600 s;
[0112] Step 15: depositing a reflection-reducing layer SiN x layer on the front of the silicon substrate by using a PECVD method, i.e. a front SiN x layer 6, see Figure 3 , with a thickness of 60-90 nm, a deposition temperature of 350-500°C, a deposition time of 30-50 min, and a flow ratio of the gases NH3, SiH4 and N2O required for deposition of (1-3):(5-15):(3-13);
[0113] Step 16: printing silver paste on the P region and the N region on the back of the silicon substrate respectively and performing sintering treatment to form a positive metal electrode 7 and a negative metal electrode 8, see Figure 3, and a complete battery cell is obtained, which is a TBC battery.
[0114] The present invention is further described below by way of examples. Unless otherwise specified, the materials in the examples were prepared according to existing methods or directly purchased from the market.
[0115] Example 1
[0116] A method for preparing a TBC battery comprises the following steps:
[0117] Step 1: Provide an N-type silicon wafer as a silicon substrate and perform double-sided polishing on the silicon substrate;
[0118] Step 2: Boron diffusion is performed on the back side of the N-type silicon wafer at a temperature of 950°C and a time of 110 minutes to form a PN junction and a BSG layer.
[0119] The gases required for boron diffusion are BCl3, O2, and N2, with a flow ratio of 2:4:7.
[0120] Step 3: Use laser patterning to remove the oxide layer and PN junction in the N region on the back of the silicon substrate;
[0121] Among them, the laser power percentage is 50%, and the scanning speed is 30000mm / s;
[0122] Step 4: Use a polishing and cleaning process to remove the BSG layer on the front and back sides of the silicon substrate. The solution required for polishing and cleaning is an HF solution (concentration 6%).
[0123] Step 5: Using the LPCVD process, a SiO2 tunneling layer and an intrinsic amorphous silicon layer (i-Poly-Si) are sequentially deposited on the back of the silicon substrate;
[0124] The thickness of the SiO2 tunneling layer is 1.5 nm, the gas used for deposition is O2, the gas flow rate is 25000 sccm, and the deposition temperature is 600°C.
[0125] The intrinsic amorphous silicon layer has a thickness of 120 nm and is deposited using SiH4 and N2 gases with flow rates of 15,000 sccm and 25,000 sccm, respectively, at a deposition temperature of 600°C.
[0126] Step 6: Use PECVD process to deposit a layer of SiN on the back of the silicon substrate x Mask layer, SiN x The mask layer thickness is 45 nm, the deposition temperature is 450 ° C, the deposition time is 45 min, and the flow ratio of NH3 and SiH4 required for deposition is 2:10;
[0127] Step 7: Use laser patterning to remove the SiN in the P region on the back of the silicon substrate xMask, for preparing P-Poly, in which the laser power percentage is 50% and the scanning speed is 30000 mm / s;
[0128] Step 8: The intrinsic Poly silicon in the back P region is converted into P-Poly silicon by a boron diffusion process, and a BSG layer is formed on the surface;
[0129] The boron diffusion temperature is 900℃, the gas used for boron diffusion is BCl3, O2 and N2, the BCl3 gas flow rate is 400 sccm, the O2 gas flow rate is 6000 sccm, and the N2 gas flow rate is 20000 sccm;
[0130] Step 9: SiN in the N region on the back of the silicon substrate is removed by laser patterning x Mask, for preparing N-Poly, in which the laser power percentage is 50% and the scanning speed is 30000 mm / s;
[0131] Step 10: The intrinsic Poly silicon in the back N region is converted into N-Poly silicon by a phosphorus diffusion process, and a PSG layer is formed on the surface;
[0132] The phosphorus diffusion temperature is 900℃, the gas used for phosphorus diffusion is POCl3, O2 and N2, and the flow rate ratio of the three is 4:2:7;
[0133] Step 11: The BSG layer and the PSG layer on the surface of the silicon substrate are removed by a wet chemical method, and the solution used is a mixed solution containing HNO3 and HF, in which the HNO3 concentration is 4%, the HF concentration is 6%, and the processing time is 300s;
[0134] Step 12: SiN is deposited on the back of the silicon substrate by PECVD method x Passivation film, SiN x The passivation film thickness is 80 nm, the deposition temperature is 400℃, and the flow rate ratio of the gases NH3, SiH4 and N2O required for deposition is 2:10:8;
[0135] Step 13: A layer of paraffin mask layer is printed on the outermost layer of the back P region and the back N region by a screen printing process, to prepare for the next step of chemical etching treatment, i.e. to protect the SiN x passivation film layer on the back of the silicon substrate;
[0136] The width of the paraffin mask layer is 100 nm and the height is 30 nm;
[0137] Step 14: All the doped layers formed on the front of the silicon substrate are removed by a wet chemical method, exposing the silicon substrate, and forming a pyramid texture on the surface to reduce reflection; at the same time, the P region and the N region on the back of the silicon substrate are isolated by chemical etching to reduce the proportion of battery leakage.
[0138] The P-Poly silicon layer on the front surface of the silicon substrate is removed by a chain alkali tank process, and the tunneling layer is removed by an acid tank process. The alkali tank process formula is 4% concentration KOH, 0.8% concentration additive (main component is sodium hydroxide 0.1%-3% concentration, isopropyl alcohol 2%-10% concentration) and 6% concentration H2O2; the acid tank uses HF solution, and the concentration is 6%;
[0139] The P region and the N region on the back surface are isolated by an acid tank process. The acid tank is HNO3 with a concentration of 6% and HF with a concentration of 6%;
[0140] The front surface of the silicon substrate is prepared into a pyramid suede structure by an alkali tank process to reduce reflection. The alkali tank process formula is 4% concentration KOH, 0.8% concentration additive and 6% concentration H2O2;
[0141] Step 15: A PECVD method is used to deposit a reflection-reducing layer SiN on the front surface of the silicon substrate x The thickness of the film layer is 75 nm, the deposition temperature is 400°C, and the flow ratio of the gases NH3, SiH4 and N2O required for deposition is 2:10:8;
[0142] Step 16: Silver paste is printed on the P region on the back surface and the N region on the back surface of the silicon substrate, respectively, and sintering treatment is performed to form a metal electrode, thereby obtaining a complete cell piece, i.e., a TBC cell.
[0143] Example 2
[0144] The difference between this embodiment and Example 1 is that in step 2, the boron diffusion temperature is 900°C, and the boron diffusion time is 150 min;
[0145] The remaining steps and their process parameters are the same as those of Example 1, and a TBC cell is obtained.
[0146] Example 3
[0147] The difference between this embodiment and Example 1 is that in step 2, the boron diffusion temperature is 1000°C, and the boron diffusion time is 70 min;
[0148] The remaining steps and their process parameters are the same as those of Example 1, and a TBC cell is obtained.
[0149] Example 4
[0150] The difference between this embodiment and Example 1 is that in step 5, the thickness of the SiO2 tunneling layer is 1.2 nm;
[0151] The remaining steps and their process parameters are the same as those of Example 1, and a TBC cell is obtained.
[0152] Example 5
[0153] The difference between this embodiment and embodiment 1 is that in step 5, the thickness of the SiO2tunneling layer is 1.8 nm;
[0154] The remaining steps and their process parameters are the same as those of embodiment 1, and a TBC battery is obtained.
[0155] Embodiment 6
[0156] The difference between this embodiment and embodiment 1 is that in step 5, the thickness of the intrinsic amorphous silicon layer is 80 nm;
[0157] The remaining steps and their process parameters are the same as those of embodiment 1, and a TBC battery is obtained.
[0158] Embodiment 7
[0159] The difference between this embodiment and embodiment 1 is that in step 5, the thickness of the intrinsic amorphous silicon layer is 150 nm;
[0160] The remaining steps and their process parameters are the same as those of embodiment 1, and a TBC battery is obtained.
[0161] Embodiment 8
[0162] The difference between this embodiment and embodiment 1 is that in step 8, the boron diffusion temperature is 850℃;
[0163] The remaining steps and their process parameters are the same as those of embodiment 1, and a TBC battery is obtained.
[0164] Embodiment 9
[0165] The difference between this embodiment and embodiment 1 is that in step 8, the boron diffusion temperature is 950℃;
[0166] The remaining steps and their process parameters are the same as those of embodiment 1, and a TBC battery is obtained.
[0167] Embodiment 10
[0168] The difference between this embodiment and embodiment 1 is that in step 10, the phosphorus diffusion temperature is 850℃;
[0169] The remaining steps and their process parameters are the same as those of embodiment 1, and a TBC battery is obtained.
[0170] Embodiment 11
[0171] The difference between this embodiment and embodiment 1 is that in step 10, the phosphorus diffusion temperature is 950℃;
[0172] The remaining steps and their process parameters are the same as those of embodiment 1, and a TBC battery is obtained.
[0173] Embodiment 12
[0174] The difference between this embodiment and embodiment 1 is that in step 14, when isolating the P region and the N region on the back side, the acid bath used has an HNO3 concentration of 5% and an HF concentration of 8%;
[0175] The remaining steps and process parameters are the same as those in Example 1 to obtain a TBC battery.
[0176] Example 13
[0177] The difference between this embodiment and embodiment 1 is that in step 14, when isolating the P region and the N region on the back side, the acid bath used has an HNO3 concentration of 8% and an HF concentration of 4%;
[0178] The remaining steps and process parameters are the same as those in Example 1 to obtain a TBC battery.
[0179] Comparative Example 1
[0180] The difference between this comparative example and Example 1 is that in step 2, boron diffusion is not performed on the back side of the N-type silicon wafer;
[0181] The remaining steps and process parameters are the same as those in Example 1 to obtain a TBC battery.
[0182] Comparative Example 2
[0183] The difference between this comparative example and Example 1 is that in step 3, the PN junction of the N region is not removed;
[0184] The remaining steps and process parameters are the same as those in Example 1 to obtain a TBC battery.
[0185] Comparative Example 3
[0186] The difference between this comparative example and Example 1 is that in step 3, the PN junction of the P region is removed;
[0187] The remaining steps and process parameters are the same as those in Example 1 to obtain a TBC battery.
[0188] Comparative Example 4
[0189] The difference between this comparative example and Example 1 is that in step 14, the P region and the N region on the back side of the silicon substrate are not isolated;
[0190] The remaining steps and process parameters are the same as those in Example 1 to obtain a TBC battery.
[0191] Test example
[0192] The TBC batteries obtained in each embodiment and comparative example were tested, and the results are shown in Table 1.
[0193] Table 1
[0194]
[0195]
[0196] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A TBC battery, characterized in that The TBC battery forms a PN junction on the back surface of the silicon substrate, and the PN junction is formed only in the P region on the back surface of the silicon substrate; The P region and the N region on the back surface of the silicon substrate are isolated from each other.
2. The TBC battery of claim 1, wherein, The thickness of the SiO2 tunneling layer in the passivation contact structure on the back surface of the silicon substrate is 1.2 nm to 1.8 nm; The thickness of the P-Poly silicon layer in the P region on the back surface of the silicon substrate is 80 nm to 150 nm; The thickness of the N-Poly silicon layer in the N region on the back surface of the silicon substrate is 80 nm to 150 nm.
3. The TBC battery of claim 2, wherein, Metal electrodes are arranged in the P region and the N region on the back surface of the silicon substrate, respectively.
4. A method for the production of a TBC cell according to any one of claims 1 to 3, characterized in that The method comprises the following steps: First, a PN junction is formed on the back surface of the silicon substrate by diffusion, and then the PN junction in the N region is removed, and then a passivation contact structure is formed on the back surface, and then a P-Poly silicon layer and an N-Poly silicon layer are formed in the P region and the N region on the back surface by diffusion, respectively, and then the P region and the N region on the back surface are isolated by mask technology, and then metal electrodes are prepared to obtain the TBC battery.
5. The preparation method according to claim 4, characterized in that The silicon substrate comprises an N-type silicon wafer; The method for forming a PN junction by diffusion comprises forming a PN junction by boron diffusion; The flow ratio of BCl3, O2 and N2 used in the boron diffusion is (1-3) : (2-5) : (5-9); The temperature of the boron diffusion is 900°C to 1000°C, and the time is 70 min to 150 min.
6. The preparation method according to claim 5, characterized in that The method for removing the PN junction in the N region comprises removing the PN junction by laser patterning; The method for removing the PN junction in the N region further comprises the step of removing the BSG layer on the front and back surfaces of the silicon substrate.
7. The preparation method according to claim 4, characterized in that The step of forming a passivated contact structure is followed by depositing SiN on the backside of the silicon substrate x a step of masking a layer The SiN x The thickness of the mask layer is 30-60 nm. The method for forming a P-Poly silicon layer in the P region on the back surface comprises the following steps: SiN x After the mask layer is removed, boron diffusion is performed to convert the intrinsic Poly silicon layer of the back P region into a P-Poly silicon layer. The method for forming an N-Poly silicon layer in the N region on the back surface comprises the following steps: SiN layer is formed on the back surface N region of the silicon substrate x After the mask layer is removed, phosphorus diffusion is performed to convert the intrinsic Poly silicon layer of the back surface N region into an N-Poly silicon layer.
8. The preparation method according to claim 7, characterized in that The method for isolating the P region and the N region on the back surface comprises the following steps: SiN is formed on the back of the silicon substrate first x A passivation film is formed, and then a paraffin mask layer is printed on the outermost layer of the back P region and the back N region of the silicon substrate by a screen printing process, and then chemical etching is performed to separate the back P region and the back N region; The SiN x The thickness of the passivation film is 60-100 nm. The width of the paraffin mask layer is 60 nm to 150 nm, and the height is 10 nm to 40 nm; The method for chemical etching comprises etching by an acid solution; The concentration of HNO3 in the acid solution is 5% to 8%, and the concentration of HF is 4% to 8%.
9. The preparation method according to claim 4, characterized in that The preparation method further comprises the step of forming a pyramid texture structure on the front surface of the silicon substrate; The step of forming the pyramid suede structure further comprises forming SiN x film layer on the front surface of the silicon substrate.
10. The method of claim 4, wherein, The method for preparing metal electrodes comprises the following steps: Silver paste is printed on the P region and the N region on the back surface of the silicon substrate, respectively, and then sintering treatment is performed to form metal electrodes.