Electronic detector and preparation method thereof

Abstract

The invention provides an electronic detector and a preparation method thereof, and belongs to the technical field of semiconductors. The electronic detector comprises a plurality of pixel units arranged in an array mode, each pixel unit comprises a substrate layer, an absorption layer and a conductive function layer which are sequentially arranged in a stacked mode, a detection structure and a protection ring structure are arranged on the side, away from the substrate layer, of the absorption layer, and the protection ring structure is arranged around the detection structure. The conductive function layer comprises a first metal wiring structure and a second metal wiring structure which are isolated from each other, the first metal wiring structure is connected with the detection structure, the second metal wiring structure is connected with the protection ring structure, an isolation structure is arranged between adjacent pixel units, and the isolation structure is connected with the first metal wiring structure and the second metal wiring structure. The thickness of the absorption layer is any value between 10 [mu] m and 500 [mu] m. The electron detector provided by the invention has relatively high response speed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to an electron detector and a preparation method thereof. BACKGROUND

[0002] An electron detector is a device capable of directly detecting an electron signal. After various energy electrons are directly incident into the electron detector, the electrons and PN junctions directly generate electron-hole pairs, which are converted into an electric signal after migrating to the detector substrate. The energy utilization rate is basically determined by the electron-hole pair generation rate, which means that a very low dose of electron beam is sufficient to produce a high-contrast photo. Therefore, the electron detector is commonly used in, for example, a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), and a cryo-EM.

[0003] In order to promote the development of the next generation of SEM, it is urgent to study the key technology of high-performance electron detector chips for secondary electron and backscattered electron detection. A general electron detector needs to make the thickness of the absorption layer reach several hundred microns, so as to obtain the smallest possible device capacitance in the case of full depletion, thereby increasing the response speed of the detector. However, the thicker absorption layer increases the movement distance of the carriers under the action of the electric field, which in turn reduces the response speed of the detector. Therefore, how to further improve the response speed of the electron detector is a problem to be solved in the field. SUMMARY

[0004] One object of the first aspect of the present application is to provide an electron detector with a higher response speed.

[0005] A further object of the present application is to increase the effective detection area.

[0006] Another object of the present application is to improve the sensitivity of the electron detector.

[0007] One object of the second aspect of the present application is to provide a preparation method of the above-mentioned electron detector.

[0008] Embodiments of the present application provide an electron detector, comprising a plurality of pixel units arranged in an array, the pixel units comprising a substrate layer, an absorption layer and a conductive functional layer arranged in sequence, the side of the absorption layer away from the substrate layer being provided with a detection structure and a protection ring structure, the protection ring structure being arranged around the detection structure, the conductive functional layer comprising a first metal wiring structure and a second metal wiring structure isolated from each other, the first metal wiring structure being connected with the detection structure, and the second metal wiring structure being connected with the protection ring structure, wherein an isolation structure is arranged between adjacent pixel units, and the thickness of the absorption layer is any value between 10 μm and 500 μm.

[0009] Further, the thickness of the absorption layer is any value between 10 μm and 280 μm.

[0010] Further, the first metal trace structure and the second metal trace structure are isolated by an oxide layer, the region of the oxide layer directly above the detection structure is a photosensitive region, and the thickness of the photosensitive region is any value between 10 nm and 300 nm.

[0011] Further, the isolation structure penetrates the absorption layer and extends to part of the substrate layer.

[0012] Further, the material of the substrate layer is a substrate wafer, and the absorption layer is formed by thinning an epitaxial wafer bonded to the substrate wafer.

[0013] Further, the top surfaces of the first metal trace structure and the second metal trace structure are at different heights, so as to respectively connect a signal metal lead and a GR metal lead at different heights.

[0014] In particular, the application also provides a preparation method for preparing the electronic detector, comprising:

[0015] S1, providing a substrate wafer and an epitaxial wafer, and bonding the substrate wafer and the epitaxial wafer;

[0016] S2, thinning the epitaxial wafer, and depositing a protective layer on the surface of the thinned epitaxial wafer to form a first base;

[0017] S3, forming an isolation groove around each unit region of the first base, and each unit region is arranged in an array on the first base;

[0018] S4, depositing a first oxide layer, and forming a first through groove and a second through groove in each unit region of the first oxide layer for exposing the epitaxial wafer, and forming a detection structure in the region of the epitaxial wafer corresponding to the first through groove, and forming a protection ring structure in the region of the epitaxial wafer corresponding to the second through groove;

[0019] S5, forming a first metal trace structure and a second metal trace structure isolated from each other at the detection structure and the protection ring structure, respectively.

[0020] Further, step S5 comprises:

[0021] removing the first oxide layer and the protective layer, and depositing a second oxide layer;

[0022] forming a first window region communicating with the protection ring structure on the second oxide layer, and forming a second metal trace structure in the first window region;

[0023] depositing a third oxide layer, and forming a second window region in communication with the detection structure on the third oxide layer, and forming a first metal trace structure in the second window region.

[0024] Further, after step S5, further comprising:

[0025] forming a groove in a target region of the oxide layer, so as to form a photosensitive region below the groove, the oxide layer comprising the second oxide layer and the third oxide layer, the photosensitive region being directly above the detection structure.

[0026] Further, in step S4, the detection structure and the guard ring structure are formed by an ion implantation process.

[0027] According to an aspect of the present application, by arranging the array of pixel units, the coverage area of the electrode is reduced, the capacitance is reduced, the response is accelerated, and by arranging the isolation structure between the pixel units, the isolation structure prevents crosstalk between the pixel units, further reduces the capacitance, and improves the response speed. Based on the above-mentioned scheme for reducing the capacitance, the thickness of the absorption layer is reduced as much as possible on the basis of matching the energy range requirement, so that the thinner absorption layer can reduce the movement distance of the carriers under the action of the electric field, greatly improving the response speed of the electron detector. That is, the present application gridded electrode, arrayed effective detection area, and arranged isolation structure effectively reduce the capacitance, give the absorption layer thinning space, and together achieve the goal of improving the response speed of the electron detector, meeting the detection needs of various product types.

[0028] Further, the array of each pixel unit realizes the array of effective areas, can realize the independence of each pixel unit, avoids mutual crosstalk, and can improve the imaging spatial resolution.

[0029] Further, the thinning of the absorption layer and the arrangement of the guard ring structure can reduce the dark current, thereby reducing the noise of the electron detector, improving the sensitivity, and improving the energy resolution. The arrangement of the guard ring structure can also effectively reduce the edge electric field aggregation, suppress the edge leakage current, and improve the device stability.

[0030] Further, by arranging a deeper isolation structure, each pixel unit can be better isolated, and the capacitance of the electron detector is lower.

[0031] According to another aspect of the present application, a double-layer metal wiring structure is provided, in which a first metal wiring structure connected with a signal metal lead and a second metal wiring structure connected with a GR metal lead are arranged in different layers, so that the layout of each layer of metal wiring structure is not limited, the wiring difficulty is reduced, the wiring of a large-scale pixel unit array is facilitated, the layered arrangement can better isolate the wiring and reduce mutual interference, the wiring length can be set shorter and the path is more direct, the crosstalk capacitance is reduced, and the signal fidelity is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 Structure diagram of an electronic detector according to an embodiment of the present application;

[0033] Figure 2 Structure diagram of a pixel unit of an electronic detector according to an embodiment of the present application;

[0034] Figure 3 Flowchart of a preparation method of an electronic detector according to an embodiment of the present application;

[0035] Figure 4 Principle diagram of a preparation method of an electronic detector according to an embodiment of the present application;

[0036] LIST OF REFERENCE SIGNS

[0037] 100-electronic detector, 110-pixel unit, 10-substrate layer, 20-absorption layer, 21-detection structure, 22-protection ring structure, 30-conductive functional layer, 31-first metal wiring structure, 32-second metal wiring structure, 33-oxide layer, 40-isolation structure, 50-signal metal lead, 60-GR metal lead, 1-substrate wafer, 2-epitaxial wafer, 3-protection layer, 4-isolation groove, 5-first oxide layer, 6-first through groove, 7-second through groove, 8-second oxide layer, 9-third oxide layer, 11-second window region, 12-groove, 13-photosensitive region. DETAILED DESCRIPTION

[0038] In order to make the above objectives, features and advantages of the present application more apparent and comprehensible, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. In the following description, a large number of specific details are set forth in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the spirit of the present application, so the present application is not limited to the specific embodiments disclosed below.

[0039] It is to be understood that when an element such as a layer, film or region is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. It will be understood that, when a component is referred to as being "fixed to" or "set to" another component, it can be directly on the other component or there can be intervening components. When a component is referred to as being "connected to" another component, it can be directly connected to the other component or there can be intervening components. The terms "vertical", "horizontal", "upper", "lower", "left", "right", and similar terms as used in the description are for illustrative purposes only and do not indicate the only implementation.

[0040] In addition, the terms "first", "second", etc. are used herein only to describe various elements, and are not intended to imply relative importance or a number of indications of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0041] In the present application, unless otherwise explicitly specified and limited, the first feature "on", "under" the second feature can be directly in contact with the second feature, or indirectly in contact with the second feature through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be directly above or obliquely above the second feature, or only indicate that the first feature is higher in horizontal height than the second feature. The first feature "below", "under" and "under" the second feature can be directly below or obliquely below the second feature, or only indicate that the first feature is lower in horizontal height than the second feature.

[0042] Unless otherwise defined, all technical and scientific terms used in the specification of the present application have the same meaning as commonly understood by a person skilled in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application. The term "and / or" used in the specification of the present application includes any and all combinations of one or more of the related listed items.

[0043] Figure 1 Structure diagram of an electronic detector 100 according to an embodiment of the present application. Figure 2 Structure diagram of a pixel unit 110 of the electronic detector 100 according to an embodiment of the present application. As shown in the figure, Figure 1 In one embodiment, the electronic detector 100 includes a plurality of pixel units 110 arranged in an array (see the dashed box in Figure 1 or Figure 2 ), the pixel unit 110 includes a substrate layer 10, an absorption layer 20 and a conductive functional layer 30 arranged in sequence. The side of the absorption layer 20 away from the substrate layer 10 is provided with a detection structure 21 and a protection ring structure 22 (seeFigure 2 ), a guard ring structure 22 is arranged around the detection structure 21, the conductive functional layer 30 comprises first metal trace structure 31 and second metal trace structure 32 which are isolated from each other, the first metal trace structure 31 is connected with the detection structure 21, and the second metal trace structure 32 is connected with the guard ring structure 22, wherein, the adjacent pixel units 110 are provided with an isolation structure 40, the thickness of the absorption layer 20 is any value between 10 μm and 500 μm, for example, the thickness of the absorption layer 20 is 10 μm, 30 μm, 50 μm, 100 μm, 150 μm, 200 μm, 300 μm, 350 μm, 400 μm, 460 m or 500 μm, and the thickness of the absorption layer 20 can also be any other value between 10 μm and 500 μm. In a further embodiment, the thickness of the absorption layer 20 is any value between 10 μm and 280 μm, for example, the thickness of the absorption layer 20 is 15 μm, 20 μm, 80 μm, 120 μm, 180 μm, 200 μm, 220 μm, 250 μm, 260 μm or 280 μm, and the thickness of the absorption layer 20 can also be any other value between 10 μm and 280 μm.

[0044] The materials of the substrate layer 10, the absorption layer 20, the first metal trace structure 31, the second metal trace structure 32 and the isolation structure 40 in the embodiment can adopt the common materials of the corresponding structures of the electronic detector 100, for example, the substrate layer 10 adopts high resistivity silicon, the absorption layer 20 adopts high purity and low doped high resistance silicon epitaxial material, the materials of the first metal trace structure 31 and the second metal trace structure 32 can be Al, Al alloy or Ti / TiN / Al and other common conductive materials of semiconductor devices, and the isolation material between the first metal trace structure 31 and the second metal trace structure 32 and the material of the above-mentioned isolation structure 40 can adopt common isolation materials such as SiO2 and Si3N4. The above-mentioned detection structure 21 and guard ring structure 22 can be formed on the absorption layer by ion implantation, for example, by implanting phosphorus (P + ) or arsenic (As + ) to form n + type detection region, implanting boron (B + ) to form P + type structure for edge field passivation.

[0045] The embodiment reduces the coverage area of the electrode by arranging the pixel units 110 in an array, reduces the capacitance, and accelerates the response. The isolation structure 40 between the pixel units 110 further reduces the capacitance and improves the response speed. Based on the above-mentioned scheme for reducing the capacitance, the thickness of the absorption layer 20 is reduced as much as possible on the basis of matching the energy range requirement, so that the thinner absorption layer 20 can reduce the movement distance of the carriers under the action of the electric field, greatly improving the response speed of the electron detector 100. That is, the grid of the common electrode, the array of the effective detection area, and the arrangement of the isolation structure 40 effectively reduce the capacitance, give the absorption layer 20 thinning space, and together achieve the goal of improving the response speed of the electron detector 100, meeting the detection needs of various product types.

[0046] The electron detector of the present application can break through the limitation of the minimum thickness of the existing absorption layer for reducing the capacitance. For example, in the prior art, in order to achieve the smallest possible capacitance in full depletion, the thickness of the absorption layer is generally between 300 μm and 600 μm, while the thickness of the absorption layer of the present application can be thinned to less than 300 μm, for example, 10 μm to 280 μm, and the response speed is greater than 450 MHz.

[0047] Further, the array of each pixel unit 110 realizes the array of the effective area, can realize the independence of each pixel unit 110, avoid mutual crosstalk, and improve the imaging spatial resolution.

[0048] Further, the thinning of the absorption layer 20 and the arrangement of the guard ring structure can reduce the dark current, thereby reducing the noise of the electron detector 100, improving the sensitivity, and improving the energy resolution. The arrangement of the guard ring structure can also effectively reduce the edge electric field aggregation, suppress the edge leakage current, and improve the device stability.

[0049] In one embodiment, the material of the substrate layer 10 is a substrate wafer, and the absorption layer 20 is formed by thinning an epitaxial wafer bonded to the substrate wafer. In the present embodiment, the substrate wafer can be low-resistance silicon (for example, resistivity less than 0.02 Ω·cm) or heavily doped P-type silicon, and the thickness is any value in the range of 300 μm to 500 μm, for example, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm, and the substrate wafer is used to provide a support function; the epitaxial wafer is a high-resistance silicon wafer with a resistivity greater than 1000 Ω·cm, and is used to form a high-sensitivity detection structure 21. The substrate wafer and the epitaxial wafer are directly connected by silicon-silicon bonding, and the bonding interface is free from interference from heterogeneous materials, which can ensure the electrical integrity and mechanical stability of the detection structure 21.

[0050] Since the above-mentioned arrayed pixel structure and the isolation structure 40 can effectively reduce the capacitance, the absorption layer 20 can be further thinned, and the epitaxial wafer is bonded with the substrate wafer in this embodiment, so that the epitaxial wafer can be accurately thinned, and the absorption layer 20 in this application can be thinned to a thickness less than the conventional 300 μm.

[0051] In one embodiment, the isolation structure 40 extends through the absorption layer 20 and extends to part of the substrate layer 10, for example, the depth of the isolation structure 40 in the substrate layer 10 is several microns.

[0052] In this application, the deeper isolation structure 40 can better isolate each pixel unit 110, and the capacitance of the electronic detector 100 is lower.

[0053] In one embodiment, the first metal wiring structure 31 and the second metal wiring structure 32 are isolated by the oxidation layer 33, and the oxidation layer 33 is located in the photosensitive region 13 directly above the detection structure 21. The thickness of the photosensitive region 13 is any value between 10 nm and 300 nm, for example, the thickness of the photosensitive region 13 is 10 nm, 30 nm, 50 nm, 100 nm, 160 nm, 200 nm, 220 nm, 250 nm or 300 nm. The thickness of the photosensitive region 33 can also be any other value between 10 nm and 300 nm, which is not limited here. The thickness of the other regions of the oxidation layer 33 except the photosensitive region 13 is any value between 500 nm and 2 μm, for example, the thickness of the other regions is 500 nm, 600 nm, 750 nm, 800 nm, 900 nm, 1 μm, 1.5 μm or 2 μm. The thickness of the other regions can also be any other value between 500 nm and 2 μm, which is not limited here.

[0054] By accurately controlling the thickness of the photosensitive region 13 and the thickness of the above-mentioned absorption layer 20, a wider range of energy electron detection can be achieved, for example, 1 keV to 50 keV energy electron detection.

[0055] In one embodiment, the resistivity of the absorption layer 20 is greater than 1000 Ω·cm, the ion implantation energy of the detection region is 1-5 keV, the PN junction depth of the absorption layer 20 is less than 30 nm, and the thickness of the oxidation layer 33 is 10 nm. The energy of the energy electron detection is about 1 keV.

[0056] Therefore, the present application can realize lower energy electron detection, especially for low-current detection of electron-sensitive samples, and realize effective imaging and partitioning of different chemical components in the sample.

[0057] In one embodiment, the top surfaces of the first metal trace structure 31 and the second metal trace structure 32 are of different heights, so as to connect the signal metal lead 50 and the GR metal lead 60 respectively at different heights.

[0058] That is, the present application provides a double-layer metal trace structure, the first metal trace structure 31 connected by the signal metal lead 50 and the second metal trace structure 32 connected by the GR metal lead 60 are in different layers, so that the layout of the metal trace structure of each layer is not limited, the wiring difficulty is reduced, which is conducive to the wiring of a large-scale pixel unit 110 array, and the layered arrangement can better isolate the wiring, reduce mutual interference, the wiring length can be set shorter, the path is more direct, which can reduce the crosstalk capacitance and improve the signal fidelity.

[0059] In the present application, a silicon-based direct detection method is adopted, combined with the above-mentioned thinning of the absorption layer 20, the setting of the isolation structure 40, and the double-layer wiring structure, which can effectively improve the detection efficiency of the electronic detector 100, especially for the effective detection of low-voltage detection of non-conductive samples.

[0060] Further, the above-mentioned electronic detector 100 can integrate a multi-channel high-speed preamplifier connected with the electronic detector 100 on the circuit board when performing chip integration, thereby further reducing noise.

[0061] The electronic detector 100 of the present application has the characteristics of large effective detection area, fast response speed, wide detection electron energy range, and low noise.

[0062] Figure 3 The flowchart of the preparation method of the electronic detector 100 according to one embodiment of the present application. Figure 4 The principle diagram of the preparation method of the electronic detector 100 according to one embodiment of the present application. As shown in Figure 3 The present application also provides a preparation method for preparing the above-mentioned electronic detector 100, which comprises the following steps S1 to S5:

[0063] S1, providing a substrate sheet 1 and an epitaxial sheet 2, and bonding the substrate sheet 1 and the epitaxial sheet 2.

[0064] In step S1, the substrate sheet 1 and the epitaxial sheet 2 are first cleaned to form a silicon-silicon direct bond, and the result is shown as a in Figure 4 Here, the substrate sheet 1 is the substrate layer 10 of the electronic detector 100.

[0065] S2, thinning the epitaxial sheet 2, and depositing a protective layer 3 on the surface of the thinned epitaxial sheet 2 to form a first base.

[0066] In step S2, the epitaxial wafer 2 is thinned by chemical laser polishing, so that high-precision thickness control is achieved and a low-roughness surface is obtained. The thickness of the epitaxial wafer 2 is controlled according to the performance of the device. After the epitaxial wafer 2 is thinned, an oxide is deposited as a protective layer 3. The result is shown in Fig. b of Figure 4

[0067] S3, isolation grooves 4 are formed around each unit region of the first substrate, and the unit regions are arranged in an array on the first substrate.

[0068] In step S3, the isolation grooves 4 are formed by photolithography and etching. The isolation grooves 4 can extend into the substrate wafer 1. The result is shown in Fig. c of Figure 4

[0069] S4, a first oxide layer 5 is deposited, and first and second through grooves 6 and 7 are formed in each unit region of the first oxide layer 5 for exposing the epitaxial wafer 2. A detection structure 21 is formed in the region of the epitaxial wafer 2 corresponding to the first through groove 6, and a protective ring structure 22 is formed in the region of the epitaxial wafer 2 corresponding to the second through groove 7.

[0070] In step S4, the first through groove 6 is formed by photolithography and etching. An oxide is deposited, and the detection structure 21 is formed by ion implantation. For example, when the epitaxial wafer 2 is a P-type substrate, a P + , As + region is formed by implanting P Figure 4 . The result is shown in Fig. d of Figure 4 . The second through groove 7 is formed by photolithography and etching. An oxide is deposited, and the protective ring structure 22 is formed by ion implantation. The result is shown in Fig. e of Figure 4 .

[0071] S5, first and second metal wiring structures 31 and 32 are formed in the detection structure 21 and the protective ring structure 22, respectively.

[0072] In one embodiment, step S5 includes steps S51 to S53.

[0073] S51, the first oxide layer 5 and the protective layer 3 are removed, and a second oxide layer 8 is deposited. The result is shown in Fig. f of Figure 4 .

[0074] S52, a first window region is formed in the second oxide layer 8 to communicate with the protective ring structure 22, and the second metal wiring structure 32 is formed in the first window region.

[0075] In step S52, the second oxide layer 8 is etched by photolithography and etching, and the etching is stopped at the protective ring structure 22 to form the first window region. Then, a first metal layer is deposited, and the second metal wiring structure 32 is formed by photolithography and etching. The result is shown in Fig. g of Figure 4as shown in Fig. h of the accompanying drawings; and then a second metal layer is deposited and a first metal trace structure 31 is formed by photolithography and etching, as shown in Fig. i of the accompanying drawings. The material of the first metal layer and the material of the second metal layer can be Al, Al alloy or Ti / TiN / Al, etc.

[0076] S53, a third oxide layer 9 is deposited, and a second window region 11 is formed on the third oxide layer 9 and communicates with the detection structure 21, and a first metal trace structure 31 is formed in the second window region 11.

[0077] In step S53, after the third oxide layer 9 is deposited, a polishing process can be used for surface planarization, and then a second window region 11 is formed by photolithography and etching, as shown in Fig. h of the accompanying drawings; and then a second metal layer is deposited and a first metal trace structure 31 is formed by photolithography and etching, as shown in Fig. i of the accompanying drawings. The material of the first metal layer and the material of the second metal layer can be Al, Al alloy or Ti / TiN / Al, etc. Figure 4 Figure 4 In step S53, after the third oxide layer 9 is deposited, a polishing process can be used for surface planarization, and then a second window region 11 is formed by photolithography and etching, as shown in Fig. h of the accompanying drawings; and then a second metal layer is deposited and a first metal trace structure 31 is formed by photolithography and etching, as shown in Fig. i of the accompanying drawings. The material of the first metal layer and the material of the second metal layer can be Al, Al alloy or Ti / TiN / Al, etc.

[0078] After step S5, the following steps are further included:

[0079] S6, a groove 12 is formed in a target region of the oxide layer 33, so as to form a photosensitive region 13 below the groove 12, and the photosensitive region 13 is located directly above the detection structure 21.

[0080] The oxide layer 33 in step S6 includes the second oxide layer 8 and the third oxide layer 9 deposited in the foregoing steps, and in the embodiment, the groove 12 is formed in the target region of the oxide layer 33 by photolithography and etching, and the oxide layer 33 at the bottom of the groove 12 is the photosensitive region 13, and the first oxide layer 5, the second oxide layer 8 and the third oxide layer 9 on the outer peripheral side of the protection ring structure 22 form an isolation structure 40, as shown in Fig. j of the accompanying drawings. The photosensitive region 13 with a target thickness can be formed by photolithography and etching, so as to adjust the energy electron detection range. Figure 4

[0081] The above-described embodiments only express several embodiments of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.​​

Claims

1. An electronic detector, characterized by The pixel unit comprises a substrate layer, an absorbing layer and a conductive functional layer arranged in sequence, the side of the absorbing layer away from the substrate layer is provided with a detection structure and a protection ring structure, the protection ring structure is arranged around the detection structure, the conductive functional layer comprises a first metal trace structure and a second metal trace structure which are isolated from each other, the first metal trace structure is connected with the detection structure, and the second metal trace structure is connected with the protection ring structure, wherein an isolation structure is arranged between adjacent pixel units, and the thickness of the absorbing layer is any value between 10 μm and 500 μm.

2. The electronic probe of claim 1, wherein, The thickness of the absorbing layer is any value between 10 μm and 280 μm.

3. The electronic probe of claim 1, wherein, The first metal trace structure and the second metal trace structure are isolated by an oxide layer, the area above the detection structure of the oxide layer is a photosensitive area, and the thickness of the photosensitive area is any value between 10 nm and 300 nm.

4. The electronic probe of claim 1, wherein, The isolation structure penetrates the absorbing layer and extends to part of the substrate layer.

5. The electronic probe of claim 1, wherein, The material of the substrate layer is a substrate wafer, and the absorbing layer is formed by thinning an epitaxial wafer bonded to the substrate wafer.

6. The electronic probe of any one of claims 1-5, wherein, The top surfaces of the first metal trace structure and the second metal trace structure are different in height, so as to respectively connect a signal metal lead and a GR metal lead at different heights.

7. A production method for producing the electron probe according to any one of claims 1 to 6, characterized by, Comprise: S1, providing a substrate wafer and an epitaxial wafer, bonding the substrate wafer and the epitaxial wafer; S2, thinning the epitaxial wafer, and depositing a protective layer on the surface of the thinned epitaxial wafer to form a first base; S3, forming an isolation groove around each unit area of the first base, and each unit area is arranged in an array on the first base; S4, depositing a first oxide layer, forming a first through groove and a second through groove for exposing the epitaxial wafer in each unit area of the first oxide layer, forming a detection structure in the area of the epitaxial wafer corresponding to the first through groove, and forming a protection ring structure in the area of the epitaxial wafer corresponding to the second through groove; S5, forming a first metal trace structure and a second metal trace structure which are isolated from each other at the detection structure and the protection ring structure respectively.

8. The preparation method according to claim 7, characterized in that Step S5 comprises: removing the first oxide layer and the protective layer, and depositing a second oxide layer; forming a first window area communicating with the protection ring structure on the second oxide layer, and forming a second metal trace structure in the first window area; depositing a third oxide layer, forming a second window area communicating with the detection structure on the third oxide layer, and forming a first metal trace structure in the second window area.

9. The production method according to claim 8, characterized by, After step S5, it further comprises: forming a groove in the target area of the oxide layer so as to form a photosensitive area below the groove, the oxide layer comprises the second oxide layer and the third oxide layer, and the photosensitive area is located directly above the detection structure.

10. The preparation method according to claim 7, characterized in that In step S4, the detection structure and the protection ring structure are formed by an ion implantation process.

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