Display device

Abstract

A display device according to an embodiment includes: a substrate including a display area and a non-display area; a pixel disposed on the substrate in the display area; and data lines including a first data line and a second data line disposed on the substrate in the display area and the non-display area. The non-display area includes a first wiring area in which a first data line is disposed and a second wiring area in which a second data line is disposed. And at least one data line disposed adjacent to a boundary between the first wiring region and the second wiring region among the data lines includes a protruding pattern protruding in a first direction intersecting a longitudinal direction of the data lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits derived from Korean Patent Application No. 10-2024-0053379 filed in the Korean Intellectual Property Office on April 22, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, more requirements are being placed on display devices for displaying images in various ways. In line with this trend, various types of display devices, including light-emitting display devices, are being developed.

[0005] The display device includes pixels connected to scan lines and data lines. Each of the pixels emits light having a brightness corresponding to the data signal in response to a scan signal and a data signal applied to the scan line and the data line, respectively. Summary of the Invention

[0006] Aspects of the present disclosure provide a display device capable of reducing capacitance variation of a data line.

[0007] However, aspects of the present disclosure are not limited to the embodiments set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0008] According to aspects of the present disclosure, a display device is provided, comprising: a substrate including a display area and a non-display area; pixels disposed on the substrate in the display area; and data lines, including a first data line and a second data line disposed on the substrate in the display area and the non-display area. The non-display area may include a first wiring area in which the first data line is disposed, and a second wiring area in which the second data line is disposed. At least one of the data lines, disposed adjacent to a boundary between the first wiring area and the second wiring area, may include a protrusion pattern that protrudes in a first direction that intersects a longitudinal direction of the data line.

[0009] In an embodiment, the first direction may be a width direction of the data line, and the width of the at least one data line may be partially expanded at a portion where the protrusion pattern is provided.

[0010] In an embodiment, a plurality of data lines disposed adjacent to the boundary among the data lines may include a protrusion pattern, and a gap between adjacent ones of the plurality of data lines may be partially reduced at a portion where the protrusion pattern is disposed.

[0011] In an embodiment, the display device can further include a driving circuit disposed on the substrate in the non-display area, and the data line can be connected between the driving circuit and the pixel.

[0012] In an embodiment, the non-display area can include a first non-display area, a bending area, and a second non-display area sequentially disposed between the display area and the driving circuit along a second direction intersecting the first direction.

[0013] In an embodiment, in the first non-display area, the bending area, and the second non-display area, the first wiring area and the second wiring area can be sequentially disposed along the first direction.

[0014] In an embodiment, the display device can further include an isolation area disposed in the non-display area between the first wiring area and the second wiring area. The data line can not be disposed in the isolation area.

[0015] In an embodiment, the first data line can be sequentially disposed along the first direction in the first wiring area, the second data line can be sequentially disposed along the first direction in the second wiring area, and the isolation area can be disposed in the non-display area between the first data line and the second data line.

[0016] In an embodiment, the display device can further include a power line disposed on the substrate in the display area and the non-display area, and the power line can be disposed in the isolation area in the non-display area.

[0017] In an embodiment, the data line can include a straight line portion extending in the second direction and an oblique line portion extending in an oblique direction intersecting the first direction and the second direction and arranged denser than the straight line portion.

[0018] In an embodiment, a plurality of data lines disposed adjacent to the above-described boundary among the data lines can include a protruding pattern, and the protruding pattern can protrude in the first direction from the respective straight line portion of the plurality of data lines.

[0019] In an embodiment, the first wiring area and the second wiring area can be sequentially disposed along the first direction in the second non-display area, and the data line disposed close to the above-described boundary among the data lines can include a protruding pattern.

[0020] In an embodiment, at least two data lines disposed adjacent to each other among the data lines can include different numbers of protruding patterns.

[0021] In an embodiment, the data line disposed close to the above-described boundary among the data lines can include a greater number of protruding patterns than the data line disposed away from the above-described boundary among the data lines.

[0022] In an embodiment, the first data line disposed adjacent to the boundary among the first data lines can include the protrusion pattern, and the second data line disposed adjacent to the boundary among the second data lines can not include the protrusion pattern.

[0023] In an embodiment, the second data line disposed adjacent to the boundary between the first wiring area and the second wiring area among the second data lines can include the protrusion pattern, and the first data line disposed adjacent to the boundary between the first wiring area and the second wiring area among the first data lines can not include the protrusion pattern.

[0024] In an embodiment, the first data line disposed adjacent to the boundary between the first wiring area and the second wiring area among the first data lines and the second data line disposed adjacent to the boundary between the first wiring area and the second wiring area among the second data lines can include the protrusion pattern.

[0025] In an embodiment, the protrusion pattern disposed in the first wiring area and the second wiring area can be symmetrically disposed with respect to the boundary between the first wiring area and the second wiring area.

[0026] In an embodiment, the protrusion patterns disposed adjacent to each other among the protrusion patterns can have an interlocking shape.

[0027] In an embodiment, the data line can be alternately disposed in the first conductive layer on the substrate and the second conductive layer covering the first conductive layer in at least a portion of the non-display area.

[0028] According to the display apparatus according to an embodiment, a change in capacitance of the data line can be reduced or minimized. Accordingly, a data signal can be stably transmitted to the pixel, and the image quality of the display apparatus can be improved.

[0029] However, effects according to embodiments of the disclosure are not limited to the above-exemplified effects, and various other effects are included herein. BRIEF DESCRIPTION OF DRAWINGS

[0030] Embodiments of the disclosure will become more fully understood from the detailed description and accompanying drawings, in which:

[0031] Figure 1 is a plan view illustrating a display apparatus according to one embodiment;

[0032] Figure 2 is an equivalent circuit diagram illustrating a pixel according to one embodiment;

[0033] Figure 3 is a cross-sectional view illustrating a display apparatus according to one embodiment;

[0034] Figure 4 is a plan view showing a region A1 of Figure 1 in detail;

[0035] Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 is a plan view showing a region A2 of Figure 4 in detail;

[0036] Figure 10 is a plan view showing a region A3 of Figure 5 in detail; and

[0037] Figure 11 is a sectional view showing a display device according to one embodiment. DETAILED DESCRIPTION

[0038] The present inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the present inventive concept are shown. The present inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present inventive concept to those skilled in the art.

[0039] It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In this specification, like reference numerals refer to like parts throughout the specification.

[0040] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present inventive concept. Similarly, a second element could be termed a first element.

[0041] The features of each of the various embodiments of the present disclosure can be partially or wholly combined with each other and can be technically coordinated with each other in various ways, and the respective embodiments can be realized independently of each other or can be realized together in association with each other.

[0042] Figure 1 is a plan view showing a display device according to one embodiment.

[0043] Reference is made to Figure 1The display device 100 can include a substrate 110 and pixels PX disposed on the substrate 110. The display device 100 can further include a driving circuit 150 electrically connected to the pixels PX. In one embodiment, the driving circuit 150 can be disposed on the substrate 110.

[0044] The substrate 110 can be a base layer for manufacturing or providing the display device 100. The substrate 110 and the display device 100 including the substrate 110 can include a display area DA and a non-display area NA.

[0045] The display area DA can be an area in which an image is displayed. The pixels PX and wirings (or some of the wirings) connected to the pixels PX can be disposed in the display area DA. In describing embodiments, the term "connected" can include electrical connection and / or physical connection.

[0046] In one embodiment, the display area DA can have a planar shape including a short side in a first direction DR1 and a long side in a second direction DR2 and have a substantially rectangular shape. Corner portions of the display area DA where the long side and the short side thereof intersect can be rounded or can be right angles. According to embodiments, the shape of the display area DA can be variously changed. For example, the display area DA can be formed in a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape, etc. In Figure 1 In one embodiment, the first direction DR1 and the second direction DR2 can be a horizontal direction and a vertical direction of the display device 100 (or the substrate 110), respectively. The third direction DR3 can be a direction crossing a main surface of the display device 100 defined by the first direction DR1 and the second direction DR2. For example, the third direction DR3 can be a thickness direction of the display device 100 or the substrate 110.

[0047] In one embodiment, the display device 100 defined by the first direction DR1 and the second direction DR2 can be substantially flat and can have a predetermined thickness (or height) in the third direction DR3. In another embodiment, the display device 100 can include an arc-shaped portion in at least a portion thereof. The display device 100 can be rigidly formed so as to be substantially not deformed, or can be flexibly formed so as to be bent, warped, folded, folded, or curled in at least a portion thereof.

[0048] The non-display area NA, which is an area other than the display area DA, can be disposed around the display area DA. For example, the non-display area NA can surround the display area DA. The wirings connected to the pixels PX (e.g., some of the wirings extending from the display area DA to the non-display area NA) can be disposed in the non-display area NA. In one embodiment, the driving circuit 150 can be further disposed in the non-display area NA.

[0049] The driving circuit 150 can include a data driving circuit. The data driving circuit can be electrically connected to the pixels PX through data lines DL.

[0050] In one embodiment, the driving circuit 150 can be formed as an integrated circuit (IC) chip, and can be disposed or mounted in the non-display area NA of the substrate 110, but the present disclosure is not limited thereto. For example, the driving circuit 150 can be disposed on a circuit board (e.g., FPCB) electrically connected to pads of the pad area PA.

[0051] The data lines DL can be disposed or connected between the driving circuit 150 and the pixels PX. For example, the data lines DL can be disposed in the display area DA and the non-display area NA, a portion (e.g., a spider line portion of each of the data lines DL) of the data lines DL located in the non-display area NA can be connected to the driving circuit 150, and other portions of the data lines DL located in the display area DA can be connected to the pixels PX. The data lines DL can transmit data signals output from the driving circuit 150 to the pixels PX.

[0052] Figure 1 A portion of the data lines DL disposed between the display area DA and the driving circuit 150 is illustrated. The portion of the data lines DL disposed between the display area DA and the driving circuit 150 can be distinguished from other portions of the data lines DL disposed in the display area DA, and can be referred to as a connection line, a spider line, or a fan-out line.

[0053] In one embodiment, a scan driving circuit (not illustrated) can be further disposed in the non-display area NA. For example, the display device 100 can further include a scan driving circuit disposed at at least one side (e.g., at least one of left and right sides) of the display area DA and a scan line connected between the scan driving circuit and the pixels PX. In one embodiment, the scan driving circuit can be formed on the substrate 110 together with the pixels PX, but the present disclosure is not limited thereto.

[0054] The substrate 110 and the display device 100 including the substrate 110 can further include a pad area PA. Pads electrically connected to the driving circuit 150 and the pixels PX can be disposed in the pad area PA. For example, power source pads and signal pads for transmitting driving voltages and driving signals to the pixels PX and the driving circuit 150 can be disposed in the pad area PA.

[0055] Although the pad area PA and the non-display area NA are distinguished and illustrated in Figure 1 , embodiments are not limited thereto. For example, the pad area PA can be considered as a portion of the non-display area NA.

[0056] In one embodiment, the display device 100 can further include additional components. For example, the display device 100 can further include a timing controller (not shown) and a power supply circuit (not shown).

[0057] In one embodiment, the display device 100 can be a light emitting display device including a light emitting element. For example, the display device 100 can be a light emitting display device such as an organic light emitting display device including an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a super small light emitting display device using a super small light emitting diode such as a micro or nano light emitting diode (micro LED or nano LED). However, embodiments are not limited thereto. For example, the display device 100 can be another type of display device other than a light emitting display device.

[0058] Hereinafter, an embodiment in which the display device 100 is an organic light emitting display device will be disclosed. However, the display device 100 according to the embodiment is not limited to an organic light emitting display device, and technical features of the embodiment to be described later can be applied to other types of display devices.

[0059] In one embodiment, the display device 100 can include a bend area BA (also referred to as a "bend portion"). In one embodiment, the bend area BA can be located in the non-display area NA of the lower side of the display area DA. For example, the bend area BA can be located between the display area DA and the pad area PA in the second direction DR2, and can extend in the first direction DR1.

[0060] The non-display area NA can include a first non-display area NA1 surrounding the display area DA, and a second non-display area NA2 disposed between the first non-display area NA1 and the pad area PA. In one embodiment, the non-display area NA can further include the bend area BA disposed between the first non-display area NA1 and the second non-display area NA2. The first non-display area NA1 can be immediately adjacent to the display area DA. The second non-display area NA2 can be spaced apart from the first non-display area NA1 with the bend area BA disposed therebetween. For example, between the display area DA and the driving circuit 150, the first non-display area NA1, the bend area BA, and the second non-display area NA2 can be sequentially disposed along the second direction DR2.

[0061] In one embodiment, the driving circuit 150 can be disposed in the second non-display area NA2. For example, the second non-display area NA2 can include a driving circuit arrangement area in which the driving circuit 150 is disposed.

[0062] The display device 100 can be bent in the bending area BA. For example, when the display device 100 is a front emission display device, the display device 100 can be bent so that the second non-display area NA2 and the pad area PA are located on the rear surface of the display device 100. Accordingly, the width of the bezel area can be reduced or minimized. According to an embodiment, whether the display device 100 is bent and / or the location of the bending area BA can be modified in various ways. For example, in another embodiment, the bending area BA can be located across the display area DA and the non-display area NA, and the display area DA can also be bent. In yet another embodiment, the display device 100 can not include the bending area BA, and can remain in a fully unfolded state.

[0063] Figure 2 is an equivalent circuit diagram illustrating a pixel according to an embodiment.

[0064] In Figure 2 , an embodiment in which the scan lines SL connected to each of the pixels PX include an initialization scan line GIL, a control scan line GCL, a write scan line GWL, and a bias scan line GBL will be disclosed. Further, in Figure 2 , an embodiment in which the power supply lines PL connected to each of the pixels PX include a first power supply line VDL, a second power supply line VSL, a first initialization voltage line VIL1, and a second initialization voltage line VIL2 will be disclosed. However, embodiments are not limited thereto. For example, the types or the number of the scan lines SL and the power supply lines PL connected to each of the pixels PX can vary depending on the type or the structure of the pixel PX.

[0065] Referring to Figure 2 , the pixel PX can include a light emitting unit EMU including at least one light emitting element EL and a pixel circuit PXC (also referred to as a "pixel driver") connected to the light emitting unit EMU.

[0066] The light emitting element EL can be connected between the second power supply line VSL to which the second driving voltage ELVSS is applied and the pixel circuit PXC. The light emitting element EL, which is a light source of the pixel PX, can emit light in response to a driving current supplied from the pixel circuit PXC.

[0067] The light emitting element EL can be an organic light emitting diode, but is not limited thereto. For example, the light emitting element EL can be an inorganic light emitting element, a quantum dot light emitting element, or other types of light emitting elements.

[0068] The pixel circuit PXC can control the emission timing and luminance of the light emitting element EL by controlling a drive current supplied to the light emitting element EL. The pixel circuit PXC can include a pixel transistor Tpx and a capacitor Cst. The pixel transistor Tpx can include a drive transistor DT and at least one switching element. In one embodiment, the pixel transistor Tpx can include first to sixth transistors T1, T2, T3, T4, T5, and T6 as the switching elements.

[0069] The drive transistor DT can include a gate electrode connected to the first node N1, a first electrode connected to the first power supply line VDL via the fourth transistor T4, and a second electrode connected to the light emitting unit EMU via the fifth transistor T5. One of the first electrode and the second electrode can be a source electrode, and the other of the first electrode and the second electrode can be a drain electrode. The drive transistor DT can control a source-drain current (hereinafter, referred to as a "drive current") flowing between the first electrode and the second electrode according to a voltage applied to the gate electrode of the drive transistor DT (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal).

[0070] The first transistor T1 can include a gate electrode connected to the write scan line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the drive transistor DT. The first transistor T1 can be turned on in response to a write scan signal supplied from the write scan line GWL to connect the first electrode of the drive transistor DT to the data line DL. When the first transistor T1 is turned on, a voltage of a data signal supplied from the data line DL can be supplied to the first electrode of the drive transistor DT.

[0071] The second transistor T2 can include a gate electrode connected to the control scan line GCL, a first electrode connected to the second electrode of the drive transistor DT, and a second electrode connected to the first node N1. The second transistor T2 can be turned on in response to a control scan signal supplied from the control scan line GCL to connect the second electrode and the gate electrode of the drive transistor DT. When the second transistor T2 is turned on, the drive transistor DT can be driven as a diode.

[0072] The third transistor T3 can include a gate electrode connected to the initialization scan line GIL, a first electrode connected to the first node N1, and a second electrode connected to the first initialization voltage line VIL1. The third transistor T3 can be turned on in response to an initialization scan signal supplied from the initialization scan line GIL to connect the first node N1 to the first initialization voltage line VIL1. When the third transistor T3 is turned on, a first initialization voltage VINT supplied from the first initialization voltage line VIL1 can be supplied to the first node N1.

[0073] The fourth transistor T4 can include a gate electrode connected to the emission control line ECL, a first electrode connected to the first power line VDL, and a second electrode connected to the first electrode of the driving transistor DT. The fourth transistor T4 can be turned on in response to an emission control signal supplied from the emission control line ECL to connect the first electrode of the driving transistor DT to the first power line VDL to which the first driving voltage ELVDD is supplied. When the fourth transistor T4 is turned on, the first driving voltage ELVDD can be supplied to the first electrode of the driving transistor DT.

[0074] The fifth transistor T5 can include a gate electrode connected to the emission control line ECL, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the light emitting element EL. The fifth transistor T5 can be turned on in response to an emission control signal supplied from the emission control line ECL to connect the driving transistor DT to the light emitting element EL. When both the fourth transistor T4 and the fifth transistor T5 are turned on, a driving current having a magnitude corresponding to a voltage of the gate electrode of the driving transistor DT (e.g., a voltage of the first node N1) can flow through the light emitting element EL.

[0075] The sixth transistor T6 can include a gate electrode connected to the bias scan line GBL, a first electrode connected to the anode electrode of the light emitting element EL, and a second electrode connected to the second initialization voltage line VIL2. The sixth transistor T6 can be turned on in response to a bias scan signal supplied from the bias scan line GBL to connect the anode electrode of the light emitting element EL to the second initialization voltage line VIL2. When the sixth transistor T6 is turned on, the second initialization voltage VAINT supplied from the second initialization voltage line VIL2 can be supplied to the anode electrode of the light emitting element EL.

[0076] The capacitor Cst can be connected between the first node N1 and the first power line VDL. The capacitor Cst can be charged with a voltage corresponding to a voltage of the first node N1.

[0077] In one embodiment, some of the pixel transistors Tpx and some of the other pixel transistors Tpx can be formed of different types of transistors. For example, as Figure 2As illustrated in FIG. 1, the drive transistor DT and the first to sixth transistors T1, T2, T3, T4, T5, and T6 can be formed as P-type transistors (e.g., P-type MOSFETs), and the second and third transistors T2 and T3 can be formed as N-type transistors (e.g., N-type MOSFETs). In one embodiment, the P-type transistors and the N-type transistors can include different semiconductor materials. For example, the active layer of each of the P-type transistors can be made of polysilicon, and the active layer of each of the N-type transistors can be made of an oxide semiconductor. In one embodiment, the transistors including different semiconductor materials can be disposed in different layers on the substrate 110.

[0078] However, embodiments are not limited thereto. For example, the pixel transistors Tpx can be formed as the same type of transistors, and can include the same semiconductor material. For example, the drive transistor DT and the first to sixth transistors T1, T2, T3, T4, T5, and T6 can be formed as P-type transistors including polysilicon, or can be formed as N-type transistors including an oxide semiconductor. Further, the type or material of the pixel transistors Tpx can be changed differently depending on embodiments.

[0079] Figure 3 is a cross-sectional view illustrating a display device according to one embodiment. For example, Figure 3 illustrates an example of a cross-section of a portion of Figure 1 corresponding to the line X1-X1’ of

[0080] Referring to Figure 3 In addition to Figure 1 and Figure 2 , the display device 100 can include a substrate 110, and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 disposed on the substrate 110. In one embodiment, the circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 can be sequentially disposed or stacked on the substrate 110 along a third direction DR3. In describing embodiments, the circuit layer 120 and the light emitting element layer 130 are described separately, but embodiments are not limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 can be integrated on the substrate 110. The encapsulation layer 140 can be replaced with another encapsulation member (e.g., an upper substrate, etc.).

[0081] The substrate 110 can be a base layer for forming the display device 100. For example, the substrate 110 can form a support for a display panel including the pixels PX.

[0082] In one embodiment, the substrate 110 can be a flexible substrate capable of being deformed (e.g., bent, folded, or rolled), and can be deformed in a direction along the first direction DR1, the second direction DR2, or the third direction DR3. Figure 1The substrate 110 can include an insulating material such as a polymer resin. For example, the substrate 110 can be made of polyimide or another insulating material.

[0083] However, embodiments are not limited thereto. For example, the substrate 110 can be a substrate including an insulating material such as glass and having a rigid characteristic, and can not be bent.

[0084] The circuit layer 120 can include circuit elements (e.g., pixel transistors Tpx and a capacitor Cst) of the pixels PX and wirings (e.g., scan lines SL, emission control lines ECL, data lines DL, and power lines PL) connected to the pixels PX. For example, the circuit layer 120 can be a thin film transistor layer or a panel circuit layer of a display panel including the pixels PX.

[0085] Figure 3 A first pixel transistor TFT1 (also referred to as "first thin film transistor") included in a pixel circuit PXC of each of the pixels PX, a second pixel transistor TFT2 (also referred to as "second thin film transistor"), and a capacitor Cst among the elements in the circuit layer 120 that can be provided in the display region DA are illustrated. Further, Figure 3 A display device 100 in which a first active layer ACT1 of the first pixel transistor TFT1 and a second active layer ACT2 of the second pixel transistor TFT2 are provided in different layers in the circuit layer 120 is illustrated. However, embodiments are not limited thereto. For example, the active layers of the pixel transistors Tpx included in the pixel circuit PXC can be provided in the same layer.

[0086] In one embodiment, the first pixel transistor TFT1 can denote a first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors Tpx constituting each of the pixel circuits PXC. Figure 3 A first type transistor connected to the light emitting element EL of the pixel PX through a connection electrode CNE as the first pixel transistor TFT1 is illustrated. For example, Figure 3 The first pixel transistor TFT1 of the display device 100 can be Figure 2 The fifth transistor T5 or the sixth transistor T6 of the display device 100, but is not limited thereto.

[0087] In one embodiment, the second pixel transistor TFT2 can denote a second type transistor (e.g., an N-type transistor) including a second semiconductor material (e.g., an oxide semiconductor) among the pixel transistors Tpx constituting each of the pixel circuits PXC. For example, Figure 3 The second pixel transistor TFT2 of the display device 100 can be Figure 2 The second transistor T2 or the third transistor T3 of the display device 100, but is not limited thereto.

[0088] The cross section of the pixel PX can be variously changed depending on each of the pixels PX and the type or structure of the display device 100 including the pixels PX. For example, the positions and formation sequence of the first pixel transistor TFT1, the second pixel transistor TFT2, and the capacitor Cst can be changed depending on an embodiment.

[0089] The circuit layer 120 can include a plurality of semiconductor layers (or a single semiconductor layer), a conductive layer, and an insulating layer provided between and / or around the semiconductor layers and the conductive layer, for forming circuit elements or wirings, and the like. For example, the circuit layer 120 can include a first semiconductor layer SCL1 (e.g., a polysilicon semiconductor layer), a first insulating layer 123, a first conductive layer GCDL1 (e.g., a first gate conductive layer), a second insulating layer 124, a second conductive layer GCDL2 (e.g., a second gate conductive layer), a third insulating layer 125, a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126, a third conductive layer GCDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127, a fourth conductive layer SCDL1 (e.g., a first data conductive layer or a first source-drain conductive layer), and a sixth insulating layer 128, which are sequentially provided or stacked over the substrate 110 with respect to the third direction DR3.

[0090] In one embodiment, the circuit layer 120 can not include the second semiconductor layer SCL2, and the like. For example, when the pixel transistor Tpx of each of the pixels PX includes an active layer provided in the same layer, the circuit layer 120 can not include the second semiconductor layer SCL2, the fourth insulating layer 126, and / or the third conductive layer GCDL3.

[0091] In one embodiment, the circuit layer 120 can further include at least one conductive layer and at least one insulating layer provided over the sixth insulating layer 128. For example, the circuit layer 120 can further include a fifth conductive layer SCDL2 (e.g., a second data conductive layer or a second source-drain conductive layer) and a seventh insulating layer 129, which are sequentially provided or stacked over the sixth insulating layer 128.

[0092] In one embodiment, the circuit layer 120 can further include at least one insulating layer and / or at least one conductive layer disposed between the substrate 110 and the first semiconductor layer SCL1. For example, the circuit layer 120 can further include a barrier layer 121 and a buffer layer 122 sequentially disposed or stacked between the substrate 110 and the first semiconductor layer SCL1. In one embodiment, the circuit layer 120 can further include a lower conductive layer (not shown) disposed between the barrier layer 121 and the buffer layer 122. The lower conductive layer can include at least one wiring and / or at least one conductive pattern (e.g., a conductive light-blocking layer). At least some of the insulating layers disposed in the circuit layer 120 in the display area DA can also be disposed in the non-display area NA.

[0093] Each of the barrier layer 121 and the buffer layer 122 can include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating material). The barrier layer 121 and the buffer layer 122 can protect the pixel PX from moisture penetration through the substrate 110 which is susceptible to moisture penetration. According to an embodiment, the materials of the barrier layer 121 and the buffer layer 122 can be varied differently.

[0094] The first pixel transistor TFT1, the second pixel transistor TFT2, and the capacitor Cst can be disposed on one surface of the substrate 110 on which the barrier layer 121 and the buffer layer 122 are disposed.

[0095] The first pixel transistor TFT1 can include a first active layer ACT1 and a first gate electrode G1. In one embodiment, the first pixel transistor TFT1 can further include a first source electrode S1 and a first drain electrode D1 connected to the first active layer ACT1. In another embodiment, the first pixel transistor TFT1 can not include a separate first source electrode S1 and / or a separate first drain electrode D1, and can include a source electrode and / or a drain electrode integrally formed with a source region and / or a drain region of the first active layer ACT1.

[0096] The second pixel transistor TFT2 can include a second active layer ACT2 and a second gate electrode G2. In one embodiment, the second pixel transistor TFT2 can further include a bottom gate electrode BG. In one embodiment, the second pixel transistor TFT2 can further include a second source electrode S2 and a second drain electrode D2 connected to the second active layer ACT2. In another embodiment, the second pixel transistor TFT2 can not include a separately provided second source electrode S2 and / or a second drain electrode D2, but can include a source electrode and / or a drain electrode integrally formed with a source region and / or a drain region of the second active layer ACT2.

[0097] The capacitor Cst can include a first capacitor electrode CAE1 and a second capacitor electrode CAE2. The first capacitor electrode CAE1 and the second capacitor electrode CAE2 can overlap each other in a plan view, with at least one insulating film (e.g., the second insulating layer 124) interposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2.

[0098] In particular, the first semiconductor layer SCL1 can be disposed on the buffer layer 122 disposed on the barrier layer 121. The first semiconductor layer SCL1 can include a first active layer ACT1 of the first pixel transistor TFT1. For example, the first semiconductor layer SCL1 can include an active layer of a first type of transistor among the pixel transistors Tpx.

[0099] The first active layer ACT1 can include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 can include a channel region overlapping the first gate electrode G1 and source and drain regions located on both sides of the channel region. In one embodiment, the source and drain regions of the first active layer ACT1 can be connected to the first source electrode S1 and the first drain electrode D1, respectively. In another embodiment, the source and drain regions of the first active layer ACT1 can be the source electrode and the drain electrode of the first pixel transistor TFT1, respectively.

[0100] The first insulating layer 123 can be disposed on the first semiconductor layer SCL1. The first insulating layer 123 can cover the first semiconductor layer SCL1.

[0101] The first conductive layer GCDL1 can be disposed on the first insulating layer 123. The first conductive layer GCDL1 can include the first gate electrode G1 of the first pixel transistor TFT1. The first gate electrode G1 can be disposed on the first active layer ACT1 to overlap a portion (e.g., a channel region) of the first active layer ACT1.

[0102] In one embodiment, the first conductive layer GCDL1 can further include at least one wire (or a portion of at least one wire), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer GCDL1 can further include the first capacitor electrode CAE1 of the capacitor Cst.

[0103] The second insulating layer 124 can be disposed on the first conductive layer GCDL1. The second insulating layer 124 can cover the first conductive layer GCDL1.

[0104] A second conductive layer GCDL2 can be provided on the second insulating layer 124. The second conductive layer GCDL2 can include one electrode of the capacitor Cst (e.g., a second capacitor electrode CAE2). In one embodiment, the second conductive layer GCDL2 can further include at least one electrode, at least one wiring (or a portion of at least one wiring), and / or a conductive pattern (e.g., a bridge pattern). For example, the second conductive layer GCDL2 can further include a bottom gate electrode BG of a second pixel transistor TFT2. In one embodiment, the bottom gate electrode BG of the second pixel transistor TFT2 can be connected to a second gate electrode G2 of the second pixel transistor TFT2, although the present disclosure is not limited thereto.

[0105] A third insulating layer 125 can be provided on the second conductive layer GCDL2. The third insulating layer 125 can cover the second conductive layer GCDL2.

[0106] A second semiconductor layer SCL2 can be provided on the third insulating layer 125. The second semiconductor layer SCL2 can include a second active layer ACT2 of the second pixel transistor TFT2. For example, the second semiconductor layer SCL2 can include an active layer of a second type transistor among the pixel transistors Tpx.

[0107] The second active layer ACT2 can include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 can include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium gallium tin oxide (IGTO), indium gallium oxide (IGO), or other oxide semiconductor.

[0108] The second active layer ACT2 can include a channel region overlapping the second gate electrode G2 and source and drain regions located on both sides of the channel region. In one embodiment, the source and drain regions of the second active layer ACT2 can be connected to the second source electrode S2 and the second drain electrode D2, respectively. In another embodiment, the source and drain regions of the second active layer ACT2 can be a source and a drain of the second pixel transistor TFT2, respectively.

[0109] A fourth insulating layer 126 can be provided on the second semiconductor layer SCL2. The fourth insulating layer 126 can cover the second semiconductor layer SCL2.

[0110] A third conductive layer GCDL3 can be disposed on the fourth insulating layer 126. The third conductive layer GCDL3 can include a second gate electrode G2 of the second pixel transistor TFT2. The second gate electrode G2 can be disposed on the second active layer ACT2 to overlap with a portion (e.g., a channel region) of the second active layer ACT2. In one embodiment, the third conductive layer GCDL3 can further include at least one wire (or a portion of at least one wire), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0111] A fifth insulating layer 127 can be disposed on the third conductive layer GCDL3. The fifth insulating layer 127 can cover the third conductive layer GCDL3.

[0112] A fourth conductive layer SCDL1 can be disposed on the fifth insulating layer 127. The fourth conductive layer SCDL1 can include a first source electrode S1 and a first drain electrode D1 of the first pixel transistor TFT1 (or at least one bridge pattern connected to the first source electrode S1 and / or the first drain electrode D1 of the first pixel transistor TFT1) and a second source electrode S2 and a second drain electrode D2 of the second pixel transistor TFT2 (or at least one bridge pattern connected to the second source electrode S2 and / or the second drain electrode D2 of the second pixel transistor TFT2).

[0113] The first source electrode S1 can be connected to a source region of the first active layer ACT1. For example, the first source electrode S1 can be connected to the source region of the first active layer ACT1 through a contact hole formed through the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127.

[0114] The first drain electrode D1 can be connected to a drain region of the first active layer ACT1. For example, the first drain electrode D1 can be connected to the drain region of the first active layer ACT1 through a contact hole formed through the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127.

[0115] The second source electrode S2 can be connected to a source region of the second active layer ACT2. For example, the second source electrode S2 can be connected to the source region of the second active layer ACT2 through a contact hole formed through the fourth insulating layer 126 and the fifth insulating layer 127.

[0116] The second drain electrode D2 can be connected to a drain region of the second active layer ACT2. For example, the second drain electrode D2 can be connected to the drain region of the second active layer ACT2 through a contact hole formed through the fourth insulating layer 126 and the fifth insulating layer 127.

[0117] In one embodiment, the fourth conductive layer SCDL1 can further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, a portion of the data line DL located in the display area DA can be provided or disposed in the fourth conductive layer SCDL1. In one embodiment, the other portion of the data line DL located in the non-display area NA can be disposed in another conductive layer (e.g., the first conductive layer GCDL1 or the second conductive layer GCDL2).

[0118] The sixth insulating layer 128 can be disposed on the fourth conductive layer SCDL1. The sixth insulating layer 128 can cover the fourth conductive layer SCDL1.

[0119] The fifth conductive layer SCDL2 can be disposed on the sixth insulating layer 128. The fifth conductive layer SCDL2 can include a connection electrode CNE. The connection electrode CNE can be connected to one electrode (e.g., the first drain electrode D1) of the first pixel transistor TFT1 through a contact hole or a via hole formed through the sixth insulating layer 128. In one embodiment, the fifth conductive layer SCDL2 can further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, a portion of the at least one power line PL located in the display area DA can be provided or disposed in the fifth conductive layer SCDL2.

[0120] The electrodes, conductive patterns, and / or wirings included in the first conductive layer GCDL1, the second conductive layer GCDL2, the third conductive layer GCDL3, the fourth conductive layer SCDL1, and the fifth conductive layer SCDL2 can include at least one conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metal materials, an alloy thereof, or other conductive materials) and can have a single layer or a multi-layer structure. At least two conductive layers among the first conductive layer GCDL1, the second conductive layer GCDL2, the third conductive layer GCDL3, the fourth conductive layer SCDL1, and the fifth conductive layer SCDL2 can include the same material, or can include different materials.

[0121] In one embodiment, each of the electrodes, conductive patterns, and wirings provided in the first conductive layer GCDL1, the second conductive layer GCDL2, and the third conductive layer GCDL3 can include molybdenum (Mo) or other metal materials. In one embodiment, each of the electrodes, conductive patterns, and wirings provided in the fourth conductive layer SCDL1 and the fifth conductive layer SCDL2 can be formed in a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0122] However, embodiments are not limited thereto. For example, the material and structure of each of the first conductive layer GCDL1, the second conductive layer GCDL2, the third conductive layer GCDL3, the fourth conductive layer SCDL1, and the fifth conductive layer SCDL2 can be variously changed depending on embodiments.

[0123] The seventh insulating layer 129 can be provided on the fifth conductive layer SCDL2. The seventh insulating layer 129 can cover the fifth conductive layer SCDL2.

[0124] Each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, the fifth insulating layer 127, the sixth insulating layer 128, and the seventh insulating layer 129 can include at least one insulating material, and can have a single layer or a multi-layer structure. At least two insulating layers among the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, the fifth insulating layer 127, the sixth insulating layer 128, and the seventh insulating layer 129 can include the same material, or can include different materials.

[0125] In one embodiment, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 can include an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating material). In one embodiment, the sixth insulating layer 128 and the seventh insulating layer 129 can include an organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or other organic insulating material). The top surface of the sixth insulating layer 128 and the seventh insulating layer 129 can be substantially flat. For example, the top surface of the circuit layer 120 can be planarized by the sixth insulating layer 128 and the seventh insulating layer 129.

[0126] The light emitting element layer 130 can be provided on the circuit layer 120, and can be located in the display area DA. For example, the light emitting element layer 130 can be provided on the circuit layer 120 in the display area DA.

[0127] The light emitting element layer 130 can include the light emitting element EL of the pixel PX. For example, the light emitting element layer 130 can include a pixel defining film 131 (also referred to as a "bank") that separates the emission area EA of each pixel PX, and the light emitting element EL located in the emission area EA of each pixel PX. In one embodiment, the light emitting element layer 130 can further include a spacer 132 provided on a portion of the pixel defining film 131.

[0128] In one embodiment, each light emitting element EL can be connected to at least one transistor (e.g., a first pixel transistor TFT1) included in the corresponding pixel PX through the connection electrode CNE. In another embodiment, the pixel PX can not include the connection electrode CNE, and the light emitting element EL can be directly connected to the at least one transistor without the connection electrode CNE.

[0129] Each light emitting element EL can include a first electrode ET1 (e.g., an anode electrode) and a second electrode ET2 (e.g., a cathode electrode) facing each other and a light emitting layer EML disposed between the first electrode ET1 and the second electrode ET2. In one embodiment, the first electrode ET1, the light emitting layer EML, and the second electrode ET2 can be sequentially disposed or stacked on the circuit layer 120.

[0130] In one embodiment, the light emitting element EL can further include at least one intermediate layer. As an example, the light emitting element EL can further include a first intermediate layer (e.g., a hole layer including a hole transport layer) interposed between the first electrode ET1 and the light emitting layer EML and a second intermediate layer (e.g., an electron layer including an electron transport layer) interposed between the light emitting layer EML and the second electrode ET2.

[0131] Although Figure 3 Embodiments in which the light emitting element EL includes a single light emitting layer EML are disclosed, but embodiments are not limited thereto. For example, the light emitting element EL can have a series structure in which at least two light emitting layers (e.g., Figure 3 the light emitting layer EML and an additional light emitting layer overlapping the light emitting layer EML) overlap each other in each emission area EA. Further, the light emitting element EL having the series structure can further include a charge generation layer interposed between the at least two light emitting layers.

[0132] The first electrode ET1 of the light emitting element EL can be disposed on the circuit layer 120. For example, the first electrode ET1 can be disposed on the seventh insulating layer 129 corresponding to each emission area EA. The first electrode ET1 can be connected to the connection electrode CNE through a contact hole or a via hole formed through the seventh insulating layer 129.

[0133] The first electrode ET1 can include an electrically conductive material. In one embodiment, the first electrode ET1 can include a metallic material having high reflectivity. For example, the first electrode ET1 can have a single layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or can have a multi-layer structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni) (e.g., ITO / Mg, ITO / MgF (or ITO / MgF2), ITO / Ag, and ITO / Ag / ITO).

[0134] The light emitting layer EML of the light emitting element EL can include a high molecular weight material or a low molecular weight material. Light emitted from the light emitting layer EML can contribute to image display. In one embodiment, the light emitting layer EML can be provided for each pixel PX, and the light emitting layer EML of each pixel PX can emit visible light of a color corresponding to the corresponding pixel PX. In another embodiment, the light emitting layer EML can be a common layer shared by pixels PX of different colors, and a wavelength conversion layer and / or a color filter corresponding to a color (or a wavelength band) of light desired to be emitted from each pixel PX can be disposed in an emission area EA of at least some of the pixels PX.

[0135] The second electrode ET2 of the light emitting element EL can include an electrically conductive material. In one embodiment, the second electrode ET2 can be a common layer formed throughout the entire display area DA to cover the light emitting layer EML and the pixel defining film 131. In one embodiment, the second electrode ET2 can include a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag), or a transparent conductive oxide (TCO) such as ITO or IZO capable of transmitting light.

[0136] The pixel defining film 131 can have an opening corresponding to each of the emission areas EA and can surround the emission areas EA. For example, the pixel defining film 131 can be formed to cover edges of the first electrode ET1 of the light emitting element EL and can include an opening exposing a remaining portion of the first electrode ET1. A region in which the exposed first electrode ET1 and the light emitting layer EML overlap (or a region including the exposed first electrode ET1 and the light emitting layer EML) can be defined as the emission area EA of each pixel PX.

[0137] In one embodiment, the pixel definition film 131 can include an organic insulating material. For example, the pixel definition film 131 can include an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, benzocyclobutene (BCB), or other organic insulating materials.

[0138] The spacer 132 can be disposed on a portion of the pixel definition film 131. In one embodiment, the spacer 132 can include at least one organic insulating layer including an organic insulating material. The spacer 132 can include the same material as the material of the pixel definition film 131, or can include a different material from the material of the pixel definition film 131.

[0139] The pixel definition film 131 and the spacer 132 can be integrated with each other and formed as a single pattern, or can be patterns formed separately and / or sequentially. For example, the pixel definition film 131 and the spacer 132 can be sequentially formed through separate mask processes, or can be simultaneously and / or integrally formed using a half-tone mask. In this case, when the pixel definition film 131 and the spacer 132 are integrally formed with each other, the pixel definition film 131 and the spacer 132 can be regarded as different portions of one pattern.

[0140] The encapsulation layer 140 can be disposed on the light emitting element layer 130. The encapsulation layer 140 can cover the light emitting element layer 130 in the display area DA, and can extend to the non-display area NA to be in contact with the circuit layer 120. For example, the encapsulation layer 140 can be disposed in the display area DA to cover the light emitting element layer 130, and an end portion of the encapsulation layer 140 can be disposed in a portion of the non-display area NA (e.g., the first non-display area NA1) disposed adjacent to the display area DA. The encapsulation layer 140 can block oxygen or moisture from penetrating into the light emitting element layer 130, and can mitigate electrical and / or physical effects on the circuit layer 120 and the light emitting element layer 130.

[0141] In one embodiment, the encapsulation layer 140 can be a composite encapsulation layer including a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 sequentially disposed on the light emitting element layer 130. The first encapsulation layer 141 and the third encapsulation layer 143 can be inorganic encapsulation layers including inorganic materials, and the second encapsulation layer 142 can be an organic encapsulation layer including an organic material. Each of the first encapsulation layer 141, the second encapsulation layer 142, and the third encapsulation layer 143 can be formed as a single layer or multiple layers.

[0142] In one embodiment, the display device 100 can further include additional elements disposed on the encapsulation layer 140. For example, the display device 100 can further include at least one of a sensor layer (e.g., a touch sensor layer) (not shown), an optical layer (e.g., an anti-reflective layer including a polarizing layer and / or a color filter layer) (not shown), and a protective layer (e.g., a window or a protective film) (not shown) disposed on the encapsulation layer 140.

[0143] Figure 4 is a plan view that illustrates in detail Figure 1 Area A1. For example, Figure 4 one embodiment of a portion of the data line DL disposed in Area A1 of Figure 1 and a portion of the power line PL disposed around the data line DL.

[0144] Referring to Figures 1 to 4 , the data line DL can be connected between the pixel PX in the display area DA and the driving circuit 150 in the non-display area NA. For example, on the substrate 110, the data line DL can extend from the display area DA in which the pixel PX is disposed, via the first non-display area NA1 and the bending area BA, to the second non-display area NA2 in which the driving circuit 150 is mounted.

[0145] The non-display area NA can include a data line area DLA in which the data line DL is disposed. The data line area DLA can include a data spider area or a data fan-out area in which the data line DL extends in a spider shape or a fan-out shape.

[0146] In one embodiment, the data line area DLA can include a plurality of wiring areas DLA1, DLA2, and DLA3 (e.g., sub-areas of the data line area DLA) spaced apart from each other in at least a portion of the non-display area NA, in which an isolation area SA (also referred to as a "separation area") is disposed between adjacent wiring areas, and a plurality of data lines DL can be disposed in each of the plurality of wiring areas DLA1, DLA2, and DLA3. For example, each of the data lines DL can be disposed in one of the plurality of wiring areas DLA1, DLA2, and DLA3.

[0147] In one embodiment, the data line area DLA can include a first wiring area DLA1 in which the first data line DL1 is disposed and a second wiring area DLA2 in which the second data line DL2 is disposed. In one embodiment, the data line area DLA can further include at least one wiring area including a third wiring area DLA3 in which the third data line DL3 is disposed.

[0148] The first wiring area DLA1, the second wiring area DLA2, and the third wiring area DLA3 can be sequentially disposed along the first direction DR1. For example, the first wiring area DLA1, the second wiring area DLA2, and the third wiring area DLA3 can be sequentially disposed along the first direction DR1 in each of the first non-display area NA1, the bending area BA, and the second non-display area NA2.

[0149] The isolation area SA can be disposed between adjacent wiring areas sequentially disposed in the first direction DR1. In an embodiment, the isolation area SA can be disposed in a portion of the non-display area NA including the bending area BA. For example, in the portion of the non-display area NA including the bending area BA, the isolation area SA can be disposed between the first wiring area DLA1 and the second wiring area DLA2 and between the second wiring area DLA2 and the third wiring area DLA3.

[0150] The first wiring area DLA1 and the second wiring area DLA2 can be sequentially disposed along the first direction DR1. The isolation area SA can be disposed between the first wiring area DLA1 and the second wiring area DLA2. Similarly, the second wiring area DLA2 and the third wiring area DLA3 can be sequentially disposed along the first direction DR1. The isolation area SA can be disposed between the second wiring area DLA2 and the third wiring area DLA3.

[0151] The data lines DL can be distributed and disposed in the plurality of wiring areas DLA1, DLA2, and DLA3. For example, the first data line DL1 can be sequentially or sequentially disposed along the first direction DR1 in the first wiring area DLA1. The second data line DL2 can be sequentially or sequentially disposed along the first direction DR1 in the second wiring area DLA2. The third data line DL3 can be sequentially or sequentially disposed along the first direction DR1 in the third wiring area DLA3.

[0152] The data lines DL can not be disposed in the isolation area SA. For example, in a portion of the non-display area NA, the first data line DL1 and the second data line DL2 can be disposed together with the isolation area SA disposed between the first wiring area DLA1 and the second wiring area DLA2. In an embodiment, in another portion of the non-display area NA, the first data line DL1 and the second data line DL2 can be sequentially or adjacently disposed. Similarly, in a portion of the non-display area NA, the second data line DL2 and the third data line DL3 can be disposed together with the isolation area SA disposed between the second wiring area DLA2 and the third wiring area DLA3. In an embodiment, in another portion of the non-display area NA, the second data line DL2 and the third data line DL3 can be sequentially or adjacently disposed.

[0153] In one embodiment, the power line PL can be disposed in the isolation area SA. For example, the power line PL can be disposed on the substrate 110 in the display area DA and the non-display area NA, and can be disposed in the isolation area SA. The power line PL can be connected to the pixel PX, and can transmit a driving voltage required to drive the pixel PX. For example, the power line PL can be connected between the pixel PX and a power pad located in the pad area PA.

[0154] Although Figure 4 Only one power line PL is illustrated in FIG. 11, but embodiments are not limited thereto. For example, a plurality of power lines PL (e.g., a plurality of power lines PL connected to the pixel PX) can be distributed and disposed in the isolation area SA. In addition, Figure 4 The approximate shape and position of the power line PL are illustrated, and the shape, size, and / or position of the power line PL can be variously changed depending on embodiments.

[0155] A portion of the power line PL can overlap the data line DL. At the portion where the power line PL and the data line DL overlap, the power line PL and the data line DL can be disposed in different conductive layers on the substrate 110. For example, in at least one of the first non-display area NA1 and the second non-display area NA2, the data line DL can be alternately disposed in the first conductive layer GCDL1 and the second conductive layer GCDL2 of the circuit layer 120, and the power line PL can be disposed in at least one of the third conductive layer GCDL3, the fourth conductive layer SCDL1, and the fifth conductive layer SCDL2 of the circuit layer 120.

[0156] Other portions of the power line PL can not overlap the data line DL. At the portion where the power line PL and the data line DL do not overlap, the power line PL and the data line DL can be disposed in different conductive layers or the same conductive layer on the substrate 110. For example, in the bending area BA, the data line DL and the power line PL can be disposed in the same conductive layer (e.g., the fourth conductive layer SCDL1 or the fifth conductive layer SCDL2). In the bending area BA, when the data line DL and the power line PL are disposed in the same conductive layer, the structure or thickness of the bending area BA can be reduced or minimized, and the flexibility of the bending area BA can be improved.

[0157] The positions or mutual arrangement structures of the data line DL and the power line PL are not limited to the above-described embodiments. For example, the positions or mutual arrangement structures of the data line DL and the power line PL can be variously changed depending on embodiments.

[0158] In one embodiment, the wiring areas DLA1, DLA2, and DLA3 can have different widths for each section or each location. The data lines DL can be arranged at intervals corresponding to the widths of the wiring areas DLA1, DLA2, and DLA3. For example, the data lines DL can be arranged at intervals corresponding to the widths or shapes of the wiring areas DLA1, DLA2, and DLA3.

[0159] In one embodiment, the data lines DL can include straight line portions extending in the second direction DR2 and diagonal line portions extending in diagonal directions intersecting the first direction DR1 and the second direction DR2.

[0160] Depending on the locations or extension directions of the data lines DL, the gaps between the data lines DL can be adjusted or changed for each section or each location. For example, the diagonal line portions of the data lines DL can be arranged more densely than the straight line portions of the data lines DL. As the diagonal line portions of the data lines DL are densely arranged, the non-display area NA can be reduced or minimized. For example, by making the gaps between the diagonal line portions of the data lines DL narrower, the length of the non-display area NA in the first direction DR1 can be reduced or minimized.

[0161] Figures 5 to 9 is a plan view showing the area A2 in detail. Figure 4 Figures 5 to 9 shows different embodiments of the portions of the data lines DL located in the area A2 of Figure 4

[0162] Referring to Figures 5 to 9 In addition Figure 4 In a portion of the non-display area NA, the data lines DL can be distributed and disposed in a plurality of wiring areas DLA1, DLA2, and DLA3 spaced apart from each other with at least one separation area SA interposed therebetween. Accordingly, in a portion of the non-display area NA, the data lines DL can be disposed in succession along the first direction DR1, and the gaps between adjacent data lines DL can be inconsistent. For example, the gaps between the data lines DL spaced apart from each other with the separation area SA interposed therebetween can be greater than the gaps between the data lines DL disposed in each of the wiring areas DLA1, DLA2, and DLA3. For example, near the separation area SA, the gap between the last first data line DL1 of the first wiring area DLA1 and the first second data line DL2 of the second wiring area DLA2 can be greater than the gaps between adjacent first data lines DL1 in the first wiring area DLA1 and the gaps between adjacent second data lines DL2 in the second wiring area DLA2.

[0163] In Figure 4 ​​In FIG, labels are given only to one first data line DL1 (eg, the last first data line DL1 of the first wiring area DLA1) and one second data line DL2 (eg, the first second data line DL2 of the second wiring area DLA2). Figure 5 As shown in , each of the data lines DL disposed in the first wiring area DLA1 may be a first data line DL1 , and each of the data lines DL2 disposed in the second wiring area DLA2 may be a second data line DL2 .

[0164] Since the data lines DL are not sequentially arranged in the non-display area NA, variations in resistance and / or capacitance between the data lines DL may occur. For example, variations in resistance and capacitance of the data lines DL may occur between the wiring areas DLA1, DLA2, and DLA3.

[0165] In one embodiment, the resistance of the data lines DL can be made uniform by adjusting or changing the width of the data lines DL. For example, the widths of the data lines DL can be made different to compensate for changes in the resistance of the data lines DL (e.g., to reduce or offset changes in the resistance). For example, by forming relatively long data lines DL with a larger width and relatively short data lines DL with a smaller width, the resistance of the data lines DL can be made uniform.

[0166] However, even if the resistance values ​​of the data lines DL become uniform, variations in capacitance between the data lines DL may occur due to non-sequential arrangement of the data lines DL. For example, variations in capacitance generated at the first data line DL1 and capacitance generated at the second data line DL2 may be relatively large at or near the boundary between the first wiring area DLA1 and the second wiring area DLA2.

[0167] Accordingly, in an embodiment, the shape of the data lines DL may be changed or made different at boundaries where the capacitance between the wiring areas DLA1, DLA2, and DLA3 varies significantly, thereby reducing or offsetting the capacitance variation between the data lines DL. In an embodiment, the shape of the data lines DL may be changed or made different at portions where the gaps between the data lines DL are relatively wide (e.g., portions where the data lines DL extend in the second direction DR2). For example, the shape of some data lines DL may be changed or made different at straight portions of the data lines DL adjacent to the drive circuit 150 (e.g., portions of the second non-display area NA2 where the wiring areas DLA1, DLA2, and DLA3 are sequentially arranged). The straight portions of the data lines DL may be arranged with a gap wider than the gaps between the oblique portions of the data lines DL, so that free space, which allows the data lines DL to be partially expanded, exists between the data lines DL.

[0168] In one embodiment, the plurality of data lines DL adjacent to the boundary between the first wiring area DLA1 and the second wiring area DLA2 among the first data lines DL1 and the second data lines DL2 can include a protruding pattern PRT (also referred to as an "addition pattern", an "auxiliary pattern", or an "extension pattern") protruding in a direction intersecting the longitudinal direction of the data lines DL. Accordingly, the width of each of the plurality of data lines DL can be partially enlarged at a portion where the protruding pattern PRT is provided. Further, the gap between the plurality of data lines DL can be partially reduced at a portion where the protruding pattern PRT is provided. Accordingly, the size of the capacitance generated at the plurality of data lines DL can be increased.

[0169] The protruding pattern PRT can be formed in the plurality of data lines DL having a relatively small capacitance than that of the adjacent other data lines DL. Accordingly, the variation in the capacitance between the data lines DL can be reduced or minimized.

[0170] For example, the plurality of first data lines DL1 and / or the plurality of second data lines DL2 adjacent to the boundary between the first wiring area DLA1 and the second wiring area DLA2 can include a protruding pattern PRT protruding from the corresponding straight portion in a first direction DR1 corresponding to the width direction of the data lines DL. Accordingly, the size of the capacitance generated at the plurality of first data lines DL1 and / or the plurality of second data lines DL2 can be increased, and the capacitance generated at the data lines DL including the first data lines DL1 and the second data lines DL2 can become more uniform overall.

[0171] In the same manner, at the boundary between the second wiring area DLA2 and the third wiring area DLA3 of the second data lines DL2 and the third data lines DL3, Figure 6 the variation in the capacitance between the data lines DL can also be reduced or minimized. For example, the plurality of second data lines DL2 and / or the plurality of third data lines DL3 adjacent to the boundary between the second wiring area DLA2 and the third wiring area DLA3 can include a protruding pattern protruding from the corresponding straight portion in a first direction DR1 corresponding to the width direction of the data lines DL. Accordingly, the size of the capacitance generated at the plurality of second data lines DL2 and / or the plurality of third data lines DL3 can be increased, and the capacitance generated at the data lines DL including the second data lines DL2 and the third data lines DL3 can become more uniform overall.

[0172] In one embodiment, the plurality of data lines DL can include different numbers of protrusion patterns PRT. For example, when compensation values of capacitances required for the plurality of data lines DL are different or the capacitances of the plurality of data lines DL need to be gradually varied, the amount of variation of the capacitances generated at the plurality of data lines DL or the amount of variation of the capacitances generated at the plurality of data lines DL can be adjusted by making the number or size of the protrusion patterns PRT different. For example, the plurality of data lines DL can include a larger number of protrusion patterns PRT toward the boundaries between the wiring regions DLA1, DLA2, and DLA3 (e.g., the boundary between the first wiring region DLA1 and the second wiring region DLA2 and / or the boundary between the second wiring region DLA2 and the third wiring region DLA3). Accordingly, rapid variation of the capacitances generated at the data lines DL in each of the wiring regions DLA1, DLA2, and DLA3 and / or at the boundaries between the wiring regions DLA1, DLA2, and DLA3 can be prevented or slowed down, and the capacitances of the data lines DL can become uniform.

[0173] In one embodiment, the size of the capacitance generated at the plurality of first data lines DL1 adjacent to the boundary between the first wiring region DLA1 and the second wiring region DLA2 can be smaller than the size of the capacitance generated at the second data line DL2 adjacent to the boundary between the first wiring region DLA1 and the second wiring region DLA2. In this case, as shown in FIG. 1A, by setting a portion of the first wiring region DLA1 as a capacitance matching region CMA and forming protrusion patterns PRT in the portion of the first data line DL1 located in the capacitance matching region CMA, the size of the capacitance generated at the first data line DL1 can be increased near the boundary between the first wiring region DLA1 and the second wiring region DLA2. When the capacitance matching region CMA does not include the second wiring region DLA2, the second data line DL2 can not include the protrusion patterns PRT. Figure 5 and Figure 6 In one embodiment, the size of the capacitance generated at the plurality of first data lines DL1 adjacent to the boundary between the first wiring region DLA1 and the second wiring region DLA2 can be smaller than the size of the capacitance generated at the second data line DL2 adjacent to the boundary between the first wiring region DLA1 and the second wiring region DLA2. In this case, as shown in FIG. 1A, by setting a portion of the first wiring region DLA1 as a capacitance matching region CMA and forming protrusion patterns PRT in the portion of the first data line DL1 located in the capacitance matching region CMA, the size of the capacitance generated at the first data line DL1 can be increased near the boundary between the first wiring region DLA1 and the second wiring region DLA2. When the capacitance matching region CMA does not include the second wiring region DLA2, the second data line DL2 can not include the protrusion patterns PRT.

[0174] In the embodiment of Figure 5 or Figure 6 , the first data line DL1 located in the capacitance matching region CMA can include different numbers and / or sizes of protrusion patterns PRT. For example, the number and / or size of the protrusion patterns PRT formed in the first data line DL1 located in the capacitance matching region CMA can gradually increase toward the second wiring region DLA2. Accordingly, rapid variation of the capacitances generated at the first data line DL1 can be prevented or slowed down, and the capacitances of the first data line DL1 can become uniform as appropriate.

[0175] In the embodiment of Figure 5 or Figure 6In an embodiment of FIG. 1, the length of the capacitance matching area CMA in the second direction DR2 can gradually increase toward the second wiring area DLA2. For example, the capacitance matching area CMA can have a trapezoidal shape or a triangular shape as shown in Figure 7 or Figure 8 FIG. 2, and the vertical length of the capacitance matching area CMA in the second direction DR2 can increase toward the second wiring area DLA2. Accordingly, the capacitance of the first data line DL1 located in the capacitance matching area CMA can gradually change toward the second wiring area DLA2.

[0176] In another embodiment, the size of the capacitance generated at the plurality of second data lines DL2 adjacent to the boundary between the first wiring area DLA1 and the second wiring area DLA2 can be smaller than the size of the capacitance generated at the first data line DL1 adjacent to the boundary between the first wiring area DLA1 and the second wiring area DLA2. In this case, as shown in Figure 7 and Figure 8 FIG. 3, by setting a portion of the second wiring area DLA2 as the capacitance matching area CMA and forming a protruding pattern PRT in the portion of the second data line DL2 located in the capacitance matching area CMA near the boundary between the first wiring area DLA1 and the second wiring area DLA2, the size of the capacitance generated at the second data line DL2 can be increased. When the capacitance matching area CMA does not include the first wiring area DLA1, the first data line DL1 can not include the protruding pattern PRT.

[0177] In an embodiment of FIG. 1, Figure 7 or Figure 8 the second data line DL2 located in the capacitance matching area CMA can include different numbers and / or sizes of the protruding pattern PRT. For example, the number and / or size of the protruding pattern PRT formed in the second data line DL2 located in the capacitance matching area CMA can gradually increase toward the first wiring area DLA1. Accordingly, a rapid change in the capacitance generated at the second data line DL2 can be prevented or slowed down, and the capacitance of the second data line DL2 can be appropriately made uniform.

[0178] In an embodiment of FIG. 1, Figure 7 or Figure 8 the length of the capacitance matching area CMA in the second direction DR2 can gradually increase toward the first wiring area DLA1. For example, the capacitance matching area CMA can have a trapezoidal shape or a triangular shape as shown in Figure 9 or Figure 9The capacitance matching area CMA may have a trapezoidal or triangular shape as shown in FIG, and a vertical length of the capacitance matching area CMA in the second direction DR2 may increase toward the first wiring area DLA1. Accordingly, the capacitance of the second data line DL2 located in the capacitance matching area CMA may gradually change toward the first wiring area DLA1.

[0179] In another embodiment, the size of the capacitance generated at the plurality of first data lines DL1 and the plurality of second data lines DL2 adjacent to the boundary between the first wiring area DLA1 and the second wiring area DLA2 may be smaller than the size of the capacitance generated at the other first data lines DL1 and / or other second data lines DL2. In addition, the change in capacitance may increase toward the boundary between the first wiring area DLA1 and the second wiring area DLA2. In this case, as Figure 9 As shown in , by setting a portion of the first wiring area DLA1 and a portion of the second wiring area DLA2, including the boundary between the first wiring area DLA1 and the second wiring area DLA2, as a capacitance matching area CMA and forming a protruding pattern PRT in portions of the plurality of first data lines DL1 located in the capacitance matching area CMA and portions of the plurality of second data lines DL2 located in the capacitance matching area CMA, the size of the capacitance generated at the plurality of first data lines DL1 and the plurality of second data lines DL2 can be increased.

[0180] exist Figures 5 to 9 In certain embodiments, the data lines DL located in the capacitance matching area CMA may include protrusion patterns PRT of varying numbers and / or sizes. For example, the number and / or size of the protrusion patterns PRT formed on the first and second data lines DL1 and DL2 located in the capacitance matching area CMA may gradually increase toward the boundary between the first and second wiring areas DLA1 and DLA2. Accordingly, rapid changes in capacitance generated on the first and second data lines DL1 and DL2 can be prevented or mitigated, and the capacitances of the first and second data lines DL1 and DL2 can be appropriately aligned.

[0181] exist Figures 5 to 9In an embodiment of the disclosure, the capacitance matching area CMA can have a symmetrical shape with respect to the boundary between the first wiring area DLA1 and the second wiring area DLA2. For example, the capacitance matching area CMA can have a trapezoidal shape or a triangular shape symmetrical with respect to the boundary between the first wiring area DLA1 and the second wiring area DLA2. Accordingly, the protrusion pattern PRT disposed in the capacitance matching area CMA can have a symmetrical shape with respect to the boundary between the first wiring area DLA1 and the second wiring area DLA2. Accordingly, the capacitances of the first data line DL1 and the second data line DL2 located in the capacitance matching area CMA can gradually change toward the boundary between the first wiring area DLA1 and the second wiring area DLA2.

[0182] In Figure 10 which is disclosed as an example, an embodiment for compensating for a change in capacitance between data lines DL at a boundary between the first wiring area DLA1 and the second wiring area DLA2 using the area A2, but the position of the capacitance matching area CMA is not limited thereto. For example, a change in capacitance between data lines DL at other boundaries (e.g., between the second wiring area DLA2 and the third wiring area DLA3) can be compensated for in substantially the same or similar manner.

[0183] Further, the position or shape of the capacitance matching area CMA and / or the position, shape, number, or size of the protrusion pattern PRT for compensating for a change in capacitance is not limited to Figure 5 the embodiment. For example, when it is necessary to adjust the capacitance of wiring including the data line DL, the position, shape, number, and / or size of the capacitance matching area CMA and / or the protrusion pattern PRT can be differently changed depending on a position at which it is desired to change the capacitance or an amount or direction of change in capacitance.

[0184] According to the embodiment, a change in capacitance of the data line DL can be prevented, reduced, or minimized. Accordingly, an imbalance in capacitance generated at the data line DL can be adjusted or mitigated, and distortion of a data signal can be prevented. Accordingly, the pixel PX can be stably driven, and the image quality of the display device 100 can be improved.

[0185] In one embodiment, the dummy pattern DMP can be provided in at least a portion of the isolation area SA. For example, in the second non-display area NA2 or the like, the dummy pattern DMP can be provided in the isolation area SA between the first data line DL1 and the second data line DL2 (e.g., between the last first data line DL1 of the first wiring area DLA1 and the first second data line DL2 of the second wiring area DLA2). Similarly, in the second non-display area NA2 or the like, the dummy pattern DMP can be provided in the isolation area SA between the second data line DL2 and the third data line DL3 (e.g., between the last second data line DL2 of the second wiring area DLA2 and the first third data line DL3 of the third wiring area DLA3). In one embodiment, the dummy pattern DMP can be provided only in one of the first non-display area NA1 and the second non-display area NA2, or can be provided in both the first non-display area NA1 and the second non-display area NA2.

[0186] In one embodiment, the dummy pattern DMP can be provided in the same conductive layer as the data line DL. For example, in the second non-display area NA2 or the like, the dummy pattern DMP can be alternately provided in the first conductive layer GCDL1 and the second conductive layer GCDL2. Since the dummy pattern DMP is provided in the isolation area SA, process deviation caused by providing the data line DL at an inconsistent interval can be prevented or reduced. In one embodiment, the dummy pattern DMP can be floating, or can be connected to the power supply line PL.

[0187] Figure 10 is a plan view that shows in detail Figure 5 the area A3. For example, Figure 11 shows in detail one embodiment of the protrusion pattern PRT formed in the data line DL (e.g., the first data line DL1) located in the area A3 of Figure 11

[0188] Figure 10 is a cross-sectional view that shows a display device according to one embodiment. For example, Figure 10 shows one embodiment of a cross-section of the display device 100 in a portion of the non-display area NA (e.g., the second non-display area NA2) corresponding to the line X2-X2’ and the line X3-X3’ of Figure 11

[0189] Referring to Figures 4 to 9 and ​ in addition to ​ ​​The protruding patterns PRT can be provided in a portion of each of the data lines DL located in the capacitance matching area CMA. For example, the protruding patterns PRT can be provided in a portion of each of the first data lines DL1 located in the capacitance matching area CMA.

[0190] In an embodiment, the protruding patterns PRT can be alternately provided in the data lines DL. In an embodiment, the protruding patterns PRT provided adjacent to each other can have an interlocking shape. Accordingly, the protruding patterns PRT can be formed while effectively utilizing spaces between the data lines DL, and variations in capacitance of the data lines DL can be appropriately compensated for by the protruding patterns PRT.

[0191] The data lines DL located in the capacitance matching area CMA can have first widths W1A and W1B at the respective straight portions STP. In an embodiment, the first widths W1A and W1B of the data lines DL provided in each of the wiring areas DLA1, DLA2, and DLA3 can be substantially the same or similar to each other. Alternatively, the first widths W1A and W1B of the data lines DL provided in each of the wiring areas DLA1, DLA2, and DLA3 can be different. For example, the first widths W1A and W1B of the data lines DL can be finely adjusted or made different to compensate for variations in resistance of the data lines DL provided in each of the wiring areas DLA1, DLA2, and DLA3.

[0192] In an embodiment, the data lines DL located in the capacitance matching area CMA can have a width wider than the first widths W1A and W1B at portions where the respective protruding patterns PRT are provided. Gaps (e.g., first gaps d1 in the first direction DR1 and / or second gaps d2 in the second direction DR2) between the data lines DL in the capacitance matching area CMA can be reduced due to the protruding patterns PRT. Accordingly, capacitance generated at the data lines DL located in the capacitance matching area CMA can be increased.

[0193] In an embodiment, the size of the capacitance generated at the data lines DL can be appropriately or easily adjusted by adjusting the number or gaps of the protruding patterns PRT. For example, the size of the capacitance generated at the data lines DL can be finely adjusted by adjusting at least one of a shape of the protruding patterns PRT, a number of the protruding patterns PRT, a size of the protruding patterns PRT, and a gap (e.g., the first gap d1 and / or the second gap d2) at which the protruding patterns PRT are provided, in the data lines DL.

[0194] Even though the protruding pattern PRT is formed only in the data lines DL located in the capacitance matching area CMA, the protruding pattern PRT is provided only in a portion of each of the data lines DL such that the resistance values of the data lines DL can be kept uniform overall. For example, the protruding pattern PRT can be provided only in a portion of the data lines DL located in the capacitance matching area CMA except for both end portions thereof, and the overall widths of each of the data lines DL can be kept uniform. Accordingly, by changing (e.g., increasing) the capacitance generated at the data lines DL without substantially changing the resistance values of each of the data lines DL located in the capacitance matching area CMA, the variation in the capacitance between the data lines DL can be compensated for.

[0195] In one embodiment, the data lines DL can be alternately arranged in at least two conductive layers (e.g., a first conductive layer GCDL1 and a second conductive layer GCDL2) provided on the substrate 110. For example, in at least a portion of the non-display area NA (e.g., a second non-display area NA2), the data lines DL can include data lines DL1A provided in the first conductive layer GCDL1 on the substrate 110 and data lines DL1B provided in the second conductive layer GCDL2 on a second insulating layer 124 covering the first conductive layer GCDL1. Further, the data lines DL1A in the first conductive layer GCDL1 and the data lines DL1B in the second conductive layer GCDL2 can be alternately provided along the first direction DR1.

[0196] However, embodiments are not limited thereto. For example, the data lines DL can be provided in the same conductive layer, or can be distributed and arranged in a plurality of conductive layers including at least one conductive layer other than the first conductive layer GCDL1 and the second conductive layer GCDL2. In addition, the positions of the data lines DL can be variously changed depending on embodiments.

[0197] As described above, the data lines DL can be provided non-successively in at least a portion of the non-display area NA. For example, in at least a portion of the non-display area NA, the data lines DL can be distributed and provided in wiring areas DLA1, DLA2, and DLA3 spaced apart from each other with an intervening isolation area SA in which a power line PL or the like is provided. The non-successive arrangement of the data lines DL can cause a variation in the capacitance of the data lines DL.

[0198] However, according to the above-described embodiment, the protrusion pattern PRT can be formed in at least some of the data lines DL to reduce or compensate for a change in the capacitance of the data lines DL. For example, the protrusion pattern PRT can be formed in at least some of the data lines DL to reduce or compensate for a change in the capacitance of the data lines DL between the wiring areas DLA1, DLA2, and DLA3. Accordingly, a change in the capacitance of the data lines DL can be reduced or minimized, and data signals can be stably transmitted to the pixels PX.

[0199] In summary of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the principles of the inventive concept. Accordingly, the disclosed embodiments of the inventive concept are used only in a generic and descriptive sense, and are not for limiting purposes.

Claims

1. A display device comprising: a substrate including a display region and a non-display region; a pixel provided on the substrate in the display region; and a data line including a first data line and a second data line provided on the substrate in the display region and the non-display region, wherein the non-display region includes a first wiring region in which the first data line is provided and a second wiring region in which the second data line is provided, and wherein at least one data line among the data line provided adjacent to a boundary between the first wiring region and the second wiring region includes a protruding pattern protruding in a first direction intersecting a longitudinal direction of the data line. The first direction is a width direction of the data line, and 2. The display device according to claim 1, wherein wherein a width of the at least one data line is partially enlarged at a portion in which the protruding pattern is provided. A plurality of data lines among the data line provided adjacent to the boundary include the protruding pattern, and 3. The display device according to claim 1, wherein wherein a gap between adjacent data lines among the plurality of data lines is partially reduced at a portion in which the protruding pattern is provided.

4. The display device according to claim 1, further comprising: a driver circuit provided on the substrate in the non-display region, wherein the data line is connected between the driver circuit and the pixel. The non-display region includes a first non-display region, a bending region, and a second non-display region sequentially provided along a second direction intersecting the first direction between the display region and the driver circuit.

5. The display device of claim 4, wherein, In the first non-display region, the bending region, and the second non-display region, the first wiring region and the second wiring region are sequentially provided along the first direction.

6. The display device of claim 5, wherein, 7. The display device according to claim 6, further comprising: an isolation region provided in the non-display region between the first wiring region and the second wiring region, wherein the data line is not provided in the isolation region. The first data line is sequentially provided in the first wiring region along the first direction, 8. The display device of claim 7, wherein, wherein the second data line is sequentially provided in the second wiring region along the first direction, and wherein the isolation region is provided in the non-display region between the first data line and the second data line.

9. The display device according to claim 7, further comprising: a power supply line provided on the substrate in the display region and the non-display region, wherein the power supply line is provided in the isolation region in the non-display region. The data line includes a straight line portion extending in the second direction and a slanted line portion extending in a slanted line direction intersecting the first direction and the second direction and arranged denser than the straight line portion.

10. The display device according to claim 5, wherein A plurality of data lines among the data line provided adjacent to the boundary include the protruding pattern, and 11. The display device of claim 10, wherein, wherein the protruding pattern protrudes in the first direction from a respective straight line portion of the plurality of data lines. ​ 12. The display device according to claim 5, wherein The first wiring region and the second wiring region are sequentially arranged along the first direction in the second non-display region, and The data line arranged close to the boundary among the data lines includes the protruding pattern.

13. The display device of claim 1, wherein, At least two data lines arranged adjacent to each other among the data lines include different numbers of the protruding pattern.

14. The display device of claim 13, wherein, The data line arranged close to the boundary among the data lines includes a greater number of the protruding pattern than the data line arranged away from the boundary among the data lines.

15. The display device of claim 1, wherein, The first data line arranged close to the boundary among the first data lines includes the protruding pattern, and the second data line arranged close to the boundary among the second data lines does not include the protruding pattern.

16. The display device of claim 1, wherein, The second data line arranged close to the boundary between the first wiring region and the second wiring region among the second data lines includes the protruding pattern, and the first data line arranged close to the boundary between the first wiring region and the second wiring region among the first data lines does not include the protruding pattern.

17. The display device of claim 1, wherein, The first data line arranged close to the boundary between the first wiring region and the second wiring region among the first data lines and the second data line arranged close to the boundary between the first wiring region and the second wiring region among the second data lines include the protruding pattern.

18. The display device of claim 17, wherein, The protruding pattern arranged in the first wiring region and the second wiring region is symmetrically arranged with respect to the boundary between the first wiring region and the second wiring region.

19. A display device according to any one of claims 1 to 18, wherein, The protruding patterns arranged adjacent to each other among the protruding patterns have an interlocking shape.

20. A display device according to any one of claims 1 to 18, wherein, The data line is alternately arranged on a first conductive layer and a second conductive layer covering the first conductive layer on the substrate in at least a portion of the non-display region.

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