Display substrate and display device

Abstract

A display substrate includes a substrate (10), a plurality of sub-pixels (Px), a plurality of gate lines (GL), and a plurality of data lines (DL) located in a display area (AA), a plurality of multiplexing circuits (36), a plurality of gate driving circuits (31a, 31b, 32, 33, 34, 35), and a plurality of driving signal lines (41) located in a frame area, the plurality of multiplexing circuits (36) being connected to the plurality of data lines (DL), each multiplexing circuit (36) including a plurality of multiplexing control transistors (M1, M2). The plurality of drive signal lines (41) are connected to the plurality of gate drive circuits (31a, 31b, 32, 33, 34, 35). The distance between the orthographic projection of the plurality of drive signal lines (41) on the substrate (10) and the orthographic projection of the active layers (M10, M20) of the multiplexing control transistors (M1, M2) of the plurality of multiplexing circuits (36) on the substrate (10) is greater than 0.

Description

Display substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] This embodiment provides a display substrate and a display device.

[0006] In one aspect, this embodiment provides a display substrate comprising a display area and a frame area surrounding the display area. The display substrate comprises: a substrate; a plurality of sub-pixels located in the display area and on one side of the substrate; a plurality of gate lines and a plurality of data lines located at least in the display area; a plurality of multiplexing circuits located in the frame area; a plurality of gate drive circuits and a plurality of drive signal lines located in the frame area. The plurality of gate lines extend along a first direction; the plurality of data lines extend along a second direction, the second direction intersecting the first direction. The plurality of gate lines and the plurality of data lines are electrically connected to the plurality of sub-pixels, respectively. A plurality of multiplexing circuits are connected to the plurality of data lines, each multiplexing circuit comprising a plurality of multiplexing control transistors. A plurality of gate drive circuits are connected to the plurality of gate lines. A plurality of drive signal lines are connected to the plurality of gate drive circuits, the plurality of drive signal lines being configured to provide drive signals to the plurality of gate drive circuits. The distance between the orthographic projections of the plurality of drive signal lines on the substrate and the orthographic projections of the active layers of the multiplexing control transistors of the plurality of multiplexing circuits on the substrate is greater than zero.

[0007] In some exemplary embodiments, the frame area includes a first frame area located on one side of the display area along the second direction, the multiplexing circuits are located in the first frame area, and the multiplexing circuits are sequentially arranged along the first direction within the first frame area.

[0008] In some exemplary embodiments, the multiplexing control transistors of each multiplexing circuit are arranged sequentially along the first direction.

[0009] In some exemplary embodiments, the first border area includes: a first fan-out area and a bending area arranged in sequence along a direction away from the display area; the multiple multiplexing circuits are located in the first fan-out area; in the first fan-out area, the multiple driving signal lines are located on a side of the multiple multiplexing circuits away from the display area.

[0010] In some exemplary embodiments, the first fan-out region is provided with a plurality of multiplexed data lines connected to the plurality of multiplexing circuits. One of the plurality of multiplexed data lines is connected to one of the plurality of multiplexing circuits. The one multiplexing circuit is configured to time-share a data signal transmitted by the one multiplexed data line to at least two of the plurality of data lines. The bending region is provided with at least a plurality of drive bending lines and a plurality of data bending lines. The plurality of drive bending lines are connected to the plurality of drive signal lines, and the plurality of data bending lines are connected to the plurality of multiplexed data lines. In the bending region, the plurality of drive bending lines are located on a side of the plurality of data bending lines that is closer to an edge of the display substrate.

[0011] In some exemplary embodiments, the display substrate further comprises: a plurality of data transfer lines located at least in the display area; at least one of the plurality of data lines is connected to the multiplexing circuit via the data transfer line; the at least one data line is located on a side of the connected data transfer line closer to an edge of the display area in the first direction.

[0012] In some exemplary embodiments, the plurality of gate drive circuits include: at least one first scan drive circuit; the at least one first scan gate drive circuit includes a plurality of cascaded first scan drive units, each of which includes at least one output transistor; the at least one output transistor of the first scan drive unit is configured to provide a first scan signal to at least one gate line; and a distance between an orthographic projection of the plurality of drive signal lines on the substrate and an active layer of the output transistor of the first scan drive unit on the substrate is greater than zero.

[0013] In some exemplary embodiments, the at least one first scan drive circuit is located on at least one side of the display area along the first direction. The active layer of the output transistor of the first scan drive unit includes: a first sub-active layer and a second sub-active layer spaced apart along the first direction. The multiple drive signal lines include: a first drive voltage line; the orthographic projection of the first drive voltage line on the substrate is located between the orthographic projection of the first sub-active layer and the second sub-active layer of the output transistor on the substrate, the orthographic projection of the first drive voltage line on the substrate does not overlap with the orthographic projection of the first sub-active layer on the substrate, and the orthographic projection of the first drive voltage line on the substrate does not overlap with the orthographic projection of the second sub-active layer on the substrate.

[0014] In some exemplary embodiments, the display substrate further includes: a plurality of electrostatic discharge circuits located in the border region, each electrostatic discharge circuit including a plurality of electrostatic discharge transistors. A distance between orthographic projections of the plurality of drive signal lines on the substrate and active layers of the electrostatic discharge transistors of the plurality of electrostatic discharge circuits on the substrate is greater than zero.

[0015] In some exemplary embodiments, the frame area includes: a first frame area and a second frame area located on both sides of the display area along the second direction, a third frame area and a fourth frame area located on both sides of the display area along the first direction, a first corner area connecting the first frame area and the third frame area, and a second corner area connecting the first frame area and the fourth frame area. The multiple electrostatic discharge circuits include: multiple first electrostatic discharge circuits located in the first corner area and the second corner area. The multiple first electrostatic discharge circuits are arranged in at least one row, each row including multiple first electrostatic discharge circuits arranged in sequence along the first direction, multiple electrostatic discharge transistors of each first electrostatic discharge circuit are arranged in sequence along the first direction, and the arrangement order of the multiple electrostatic discharge transistors of adjacent first electrostatic discharge circuits in the same row is different.

[0016] In some exemplary embodiments, the border area further includes: a third corner area connecting the second border area and the third border area, and a fourth corner area connecting the second border area and the fourth border area. The multiple electrostatic discharge circuits further include: a plurality of second electrostatic discharge circuits located in the third corner area and the fourth corner area. At least one of the plurality of second electrostatic discharge circuits includes a plurality of electrostatic discharge transistors arranged in an array.

[0017] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0018] On the other hand, this embodiment provides a display substrate comprising a display area and a frame area located around the display area. The display substrate comprises: a substrate, a plurality of sub-pixels located in the display area and on one side of the substrate, at least one first scan drive circuit located in the frame area and on one side of the substrate, and a plurality of drive signal lines. The at least one first scan drive circuit comprises a plurality of cascaded first scan drive units, each first scan drive unit comprising at least one output transistor, and the at least one first scan drive circuit is configured to provide a first scan signal to the plurality of sub-pixels in the display area. A plurality of drive signal lines are located in the frame area, and the at least one first scan drive circuit is connected to at least one of the plurality of drive signal lines. The distance between the orthographic projection of the plurality of drive signal lines on the substrate and the orthographic projection of the active layer of the output transistor of the at least one first scan drive circuit on the substrate is greater than zero.

[0019] In some exemplary embodiments, the at least one first scan driving circuit is located on at least one side of the display area along a first direction; the active layer of the output transistor of the first scan driving unit includes: a first sub-active layer and a second sub-active layer spaced apart along the first direction; and the plurality of driving signal lines include: a first driving voltage line, the orthographic projection of the first driving voltage line on the substrate being located between the orthographic projections of the first sub-active layer and the second sub-active layer of the output transistor on the substrate; the orthographic projection of the first driving voltage line on the substrate does not overlap with the orthographic projection of the first sub-active layer on the substrate, and the orthographic projection of the first driving voltage line on the substrate does not overlap with the orthographic projection of the second sub-active layer on the substrate.

[0020] In some exemplary embodiments, the first scan driving unit includes two output transistors, the first sub-active layers of the two output transistors are connected to each other as an integral structure, and the second sub-active layers of the two output transistors are connected to each other as an integral structure.

[0021] In some exemplary embodiments, the integrated structure of the first sub-active layers of the two output transistors of the first scan driving unit is a rectangular shape when projected onto the substrate, and the integrated structure of the second sub-active layers of the two output transistors is a rectangular shape when projected onto the substrate.

[0022] In some exemplary embodiments, the two output transistors of the first scan driving unit are a first output transistor and a second output transistor. The first scan driving unit further includes: a first shift storage capacitor and a second shift storage capacitor, the first shift storage capacitor being connected to the first output transistor, and the second shift storage capacitor being connected to the second output transistor; the first shift storage capacitor being located on a side of the first output transistor closer to the display area, and the second shift storage capacitor being located on a side of the second output transistor closer to the display area. The orthographic projection of one of the plurality of drive signal lines on the substrate overlaps with the orthographic projection of the first shift storage capacitor on the substrate, and overlaps with the orthographic projection of the second shift storage capacitor on the substrate.

[0023] In some example embodiments, the first driving voltage line is connected to the active layer of the first output transistor through an eighth scan link electrode, and the first driving voltage line is located on a side of the eighth scan link line away from the substrate.

[0024] In some exemplary embodiments, the border region includes: a third border region and a fourth border region located on either side of the display region along a first direction. The display substrate includes: a second scan driver circuit, a first reset driver circuit, a second reset driver circuit, a light-emitting driver circuit, and two first scan driver circuits. The second scan driver circuit is configured to provide a second scan signal to the multiple sub-pixels in the display region; the first reset driver circuit is configured to provide a first reset control signal to the multiple sub-pixels in the display region; the second reset driver circuit is configured to provide a second reset control signal to the multiple sub-pixels in the display region; and the light-emitting driver circuit is configured to provide a light-emitting control signal to the multiple sub-pixels in the display region. One first scan driver circuit, the second scan driver circuit, and the second reset driver circuit are located in the third border region and are arranged sequentially in a direction away from the display region. Another first scan driver circuit, the first reset driver circuit, and the light-emitting driver circuit are located in the fourth border region and are arranged sequentially in a direction away from the display region.

[0025] In some exemplary embodiments, the display substrate further includes: a plurality of electrostatic discharge circuits located in the border region, each electrostatic discharge circuit including a plurality of electrostatic discharge transistors. A distance between orthographic projections of the plurality of drive signal lines on the substrate and active layers of the electrostatic discharge transistors of the plurality of electrostatic discharge circuits on the substrate is greater than zero.

[0026] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0027] Summary of the Figures

[0028] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0029] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0030] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0031] 3A is a partial cross-sectional schematic diagram of a display region of a display substrate according to at least one embodiment of the present disclosure;

[0032] 3B is another partial cross-sectional schematic diagram of the display region of the display substrate according to at least one embodiment of the present disclosure;

[0033] FIG4 is a schematic diagram illustrating the configuration of a gate drive circuit according to at least one embodiment of the present disclosure;

[0034] FIG5 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0035] FIG6 is a partial schematic diagram of a first border area according to at least one embodiment of the present disclosure;

[0036] FIG7A is a schematic diagram of the first semiconductor layer in FIG6 ;

[0037] FIG7B is a schematic diagram of the first frame region after the second semiconductor layer is formed in FIG6 ;

[0038] 7C is a schematic diagram of the first frame region after the second interlayer insulating layer is formed in FIG6 ;

[0039] FIG7D is a schematic diagram of the first border region after the first source / drain metal layer is formed in FIG6 ;

[0040] FIG8 is a partial schematic diagram of a first border region and a first corner region according to at least one embodiment of the present disclosure;

[0041] 9 is an equivalent circuit diagram of a first scan driving unit of a first scan driving circuit according to at least one embodiment of the present disclosure;

[0042] FIG10A is a schematic diagram of a partial structure of a third frame region according to at least one embodiment of the present disclosure;

[0043] FIG10B is a schematic diagram of the first semiconductor layer in FIG10A ;

[0044] FIG10C is a schematic diagram of the first semiconductor layer and the first gate metal layer in FIG10A ;

[0045] FIG10D is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG10A ;

[0046] 10E is a schematic diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in FIG. 10A ;

[0047] 10F is a schematic diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the second source / drain metal layer in FIG. 10A ;

[0048] FIG11 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0049] FIG12 is a partial schematic diagram of a first corner area according to at least one embodiment of the present disclosure;

[0050] FIG13 is a partial schematic diagram of a third corner area according to at least one embodiment of the present disclosure;

[0051] FIG14 is a schematic diagram of a partial structure in FIG13;

[0052] FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0053] Details

[0054] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0055] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0056] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0057] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0058] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "connection" can include "electrical connection", and "electrical connection" can include the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.

[0059] In this specification, a transistor refers to a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0060] In this specification, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. Furthermore, the gate electrode can also be referred to as a control electrode. The functions of "source" and "drain" are sometimes interchangeable when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" can be interchangeable.

[0061] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0062] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0063] In this specification, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In this disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0064] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0065] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0066] To better meet people's demands for various functions and a better screen experience (for example, displays with an ultra-high screen-to-body ratio), narrow-bezel displays are becoming the mainstream form factor for display devices. However, this narrow-bezel design can cause some signal lines and circuit layouts within display products to cause poor display quality, impacting the product's image quality and competitiveness.

[0067] This embodiment provides a display substrate comprising a display area and a frame area surrounding the display area. The display substrate comprises: a substrate; a plurality of sub-pixels located in the display area and on one side of the substrate; a plurality of gate lines and a plurality of data lines located at least in the display area; a plurality of multiplexing circuits located in the frame area; a plurality of gate drive circuits; and a plurality of drive signal lines. The plurality of gate lines extend along a first direction; the plurality of data lines extend along a second direction, the second direction intersecting the first direction. For example, the first direction may be perpendicular to the second direction. The plurality of gate lines and the plurality of data lines are electrically connected to the plurality of sub-pixels, respectively. A plurality of multiplexing circuits are connected to the plurality of data lines, each multiplexing circuit comprising a plurality of multiplexing control transistors. A plurality of gate drive circuits are connected to the plurality of gate lines. A plurality of drive signal lines are connected to the plurality of gate drive circuits, the plurality of drive signal lines being configured to provide drive signals to the plurality of gate drive circuits. The distance between the orthographic projections of the plurality of drive signal lines on the substrate and the orthographic projections of the active layers of the multiplexing control transistors of the plurality of multiplexing circuits on the substrate is greater than zero. The distance between the orthographic projection of each drive signal line on the substrate and the orthographic projection of the active layers of the multiplexing control transistors of the multiplexing circuits on the substrate is greater than 0. In other words, the orthographic projections of the multiple drive signal lines on the substrate and the orthographic projections of the active layers of the multiplexing control transistors of the multiplexing circuits on the substrate do not overlap.

[0068] The display substrate provided in this embodiment optimizes the positional relationship between the multiplexing circuit and the drive signal line so that the drive signal line avoids the active layer of the multiplexing control transistor of the multiplexing circuit. This can improve the load difference caused by the overlap of the multiplexing circuit and the drive signal line, thereby avoiding display anomalies due to signal coupling, and can also facilitate the realization of a narrow bezel design, thereby improving display quality and competitiveness.

[0069] In some exemplary embodiments, the border region may include a first border region located on one side of the display region along the second direction. Multiple multiplexing circuits may be located in the first border region, and the multiple multiplexing circuits may be arranged sequentially along the first direction within the first border region. In some examples, multiple multiplexing control transistors of each multiplexing circuit may be arranged sequentially along the first direction. The arrangement of the multiple multiplexing circuits in this example can avoid overlap between the drive signal lines and the multiplexing circuits.

[0070] In some exemplary embodiments, the first border region may include a first fan-out region and a bend region, sequentially arranged in a direction away from the display region. Multiple multiplexing circuits may be located in the first fan-out region. Within the first fan-out region, multiple drive signal lines may be located on a side of the multiplexing circuits away from the display region. This exemplary arrangement avoids overlap between the drive signal lines and the multiplexing circuits.

[0071] In some exemplary embodiments, the display substrate may further include: a plurality of data transfer lines located at least in the display area. At least one data line may be connected to a multiplexing circuit via a data transfer line. At least one data line may be located in a first direction on a side of the connected data transfer line that is close to an edge of the display area. In this example, by providing data transfer lines, a FIP (Fanout In Panel) method may be used to introduce data signals from the border area to the display area, thereby avoiding the need to provide a multiplexing circuit in the corner area of ​​the border area, thereby helping to avoid the possibility of overlap between the drive signal lines and the multiplexing circuit.

[0072] In some exemplary embodiments, the multiple gate drive circuits may include: at least one first scan drive circuit. The first scan drive circuit may include multiple cascaded first scan drive units, each of which may include at least one output transistor. The at least one output transistor of the first scan drive unit may be configured to provide a first scan signal to at least one gate line. The distance between the orthographic projection of the multiple drive signal lines on the substrate and the orthographic projection of the active layer of the output transistor of the first scan drive unit on the substrate may be greater than zero. The distance between the orthographic projection of each drive signal line on the substrate and the orthographic projection of the active layer of the output transistor of the first scan drive unit of the first scan drive circuit on the substrate may be greater than zero. In other words, the orthographic projection of the multiple drive signal lines on the substrate and the orthographic projection of the active layer of the output transistor of the first scan drive circuit on the substrate may not overlap. In this example, by arranging the drive signal lines to avoid the active layer of the output transistor of the first scan drive circuit, load differences between different signals caused by overlap can be reduced, thereby avoiding display anomalies caused by signal coupling.

[0073] In some exemplary embodiments, the display substrate may further include: a plurality of electrostatic release circuits located in the border area, each electrostatic release circuit may include a plurality of electrostatic release transistors. The distance between the orthographic projections of the plurality of drive signal lines on the substrate and the orthographic projections of the active layers of the electrostatic release transistors of the plurality of electrostatic release circuits on the substrate may be greater than 0. Particularly, the distance between the orthographic projections of each drive signal line on the substrate and the orthographic projections of the active layers of the electrostatic release transistors of the plurality of electrostatic release circuits on the substrate may be greater than 0. In other words, the orthographic projections of the plurality of drive signal lines on the substrate and the orthographic projections of the active layers of the electrostatic release transistors of the plurality of electrostatic release circuits on the substrate may not overlap. In some examples, the plurality of electrostatic release circuits may include: a first electrostatic release circuit located in the lower corner area and a second electrostatic release circuit located in the upper corner area. This example reduces the load difference between different signals caused by overlap and avoids display anomalies caused by signal coupling by setting the drive signal lines to avoid the active layers of the electrostatic release transistors of the electrostatic release circuits.

[0074] The solution of this embodiment is illustrated below through some examples.

[0075] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may be a closed polygon including linear edges, such as a rectangular shape with rounded corners. The display substrate may include: a display area AA and a frame area BB located around the display area AA. For example, the display area AA may include: a first edge (lower edge) and a second edge (upper edge) arranged relative to each other in the second direction D2, and a third edge (left edge) and a fourth edge (right edge) arranged relative to each other in the first direction D1. The first edge and the second edge may be linear edges parallel to each other, and the third edge and the fourth edge may be linear edges parallel to each other. Adjacent linear edges may be connected by curved edges (e.g., arcuate edges).

[0076] In some examples, as shown in FIG1 , the border area BB may include: a first border area (lower border area) B11 and a second border area (upper border area) B12 arranged opposite to each other in the second direction D2, a third border area (left border area) B13 and a fourth border area (right border area) B14 arranged opposite to each other in the first direction D1. The first border area B11 is adjacent to the first edge of the display area AA, the second border area B12 is adjacent to the second edge of the display area AA, the third border area B13 is adjacent to the third edge of the display area AA, and the fourth border area B14 is adjacent to the fourth edge of the display area AA. The first border area B11 can be connected to the third border area B13 through the first corner area C11, and can also be connected to the fourth border area B14 through the second corner area C12. The second border area B12 can be connected to the third border area B13 through the third corner area C13, and can also be connected to the fourth border area B14 through the fourth corner area C14. The first corner area C11 to the fourth corner area C14 each correspond to the arc-shaped edge of the display area AA. The edges of the first to fourth corner regions C11 to C14 on the side away from the display area AA can all be curved edges (e.g., arc-shaped edges). The first and second corner regions C11 and C12 can be referred to as lower corner regions, and the third and fourth corner regions C13 and C14 can be referred to as upper corner regions.

[0077] In some examples, as shown in FIG1 , the display area AA of the display substrate may include at least: a plurality of sub-pixels Px, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction D1 and be arranged along a second direction D2; the plurality of data lines DL may extend along the second direction D2 and be arranged along the first direction D1. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels Px, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels Px. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels Px, and the plurality of gate lines GL may be configured to provide gate drive signals to the plurality of sub-pixels Px. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0078] In some examples, the first direction D1 may be the extending direction of the gate lines GL in the display area AA (e.g., the row direction); the second direction D2 may be the extending direction of the data lines DL in the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 may intersect each other, for example, may be perpendicular to each other.

[0079] In some examples, a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0080] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.

[0081] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0082] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0083] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight pixel transistors (i.e., a first pixel transistor T1 to an eighth pixel transistor T8) and a storage capacitor Cst. The first pixel transistor T1 may also be referred to as a first reset transistor, the second pixel transistor T2 may also be referred to as a threshold compensation transistor, the third pixel transistor T3 may also be referred to as a drive transistor, the fourth pixel transistor T4 may also be referred to as a data write transistor, the fifth pixel transistor T5 may also be referred to as a first light-emitting control transistor, the sixth pixel transistor T6 may also be referred to as a second light-emitting control transistor, the seventh pixel transistor T7 may also be referred to as a second reset transistor, and the eighth pixel transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0084] In some examples, the first pixel transistor T1 and the third pixel transistor T3 to the eighth pixel transistor T8 may be first-type transistors, such as P-type transistors, and the second pixel transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of pixel transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0085] In some examples, the first type of transistor of the pixel circuit (for example, including the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second pixel transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0086] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0087] In some examples, as shown in FIG2 , the gate of the third pixel transistor T3 is electrically connected to the first node N1, the first electrode of the third pixel transistor T3 is electrically connected to the second node N2, and the second electrode of the third pixel transistor T3 is electrically connected to the third node N3. The gate of the fourth pixel transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth pixel transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth pixel transistor T4 is electrically connected to the second node N2. The gate of the second pixel transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second pixel transistor T2 is electrically connected to the third node N3, and the second electrode of the second pixel transistor T2 is electrically connected to the first node N1. The gate of the fifth pixel transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth pixel transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth pixel transistor T5 is electrically connected to the second node N2. The gate of the sixth pixel transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth pixel transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth pixel transistor T6 is electrically connected to the fourth node N4. The gate of the first pixel transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first pixel transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first pixel transistor T1 is electrically connected to the third node N3. The first pixel transistor T1 can be configured to reset the third node N3. The gate of the seventh pixel transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh pixel transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh pixel transistor T7 is electrically connected to the fourth node N4. The seventh pixel transistor T7 can be configured to reset the fourth node N4. The gate of the eighth pixel transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth pixel transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth pixel transistor T8 is electrically connected to the second node N2. The eighth pixel transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0088] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second pixel transistor T2 and the third pixel transistor T3, the second node N2 is the connection point of the fifth pixel transistor T5, the fourth pixel transistor T4, the eighth pixel transistor T8 and the third pixel transistor T3, the third node N3 is the connection point of the first pixel transistor T1, the third pixel transistor T3, the second pixel transistor T2 and the sixth pixel transistor T6, and the fourth node N4 is the connection point of the sixth pixel transistor T6, the seventh pixel transistor T7 and the light-emitting element EL.

[0089] The operation process of the pixel circuit shown in Figure 2 is described below. In the pixel circuit, the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 are P-type transistors, and the second pixel transistor T2 is an N-type transistor.

[0090] In some examples, during a frame display period, the operation process of the pixel circuit may include at least: a first stage, a second stage, a third stage, and a fourth stage.

[0091] The first stage is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh pixel transistor T7 and the eighth pixel transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor T2. The eighth pixel transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be provided to the second node N2. The seventh pixel transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be provided to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth pixel transistor T4, the first pixel transistor T1, the fifth pixel transistor T5, and the sixth pixel transistor T6. During this stage, the light-emitting element EL does not emit light.

[0092] The second stage is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first pixel transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor T2. The first pixel transistor T1 and the second pixel transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, turning off the seventh pixel transistor T7, the eighth pixel transistor T8, the fourth pixel transistor T4, the fifth pixel transistor T5, and the sixth pixel transistor T6. During this stage, the light-emitting element EL does not emit light.

[0093] The third stage is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth pixel transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third pixel transistor T3 is turned on. The second pixel transistor T2, the fourth pixel transistor T4, and the third pixel transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third pixel transistor T3, the third node N3, and the turned-on second pixel transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third pixel transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third pixel transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the first pixel transistor T1, the seventh pixel transistor T7, the eighth pixel transistor T8, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected.

[0094] In the fourth stage, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth pixel transistor T5 and the sixth pixel transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second pixel transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth pixel transistor T4, the first pixel transistor T1, the seventh pixel transistor T7, and the eighth pixel transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth pixel transistor T5, the third pixel transistor T3, and the sixth pixel transistor T6, driving the light-emitting element EL to emit light.

[0095] During the driving process of the pixel circuit, the driving current flowing through the third pixel transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third pixel transistor T3 is: I=K×(Vgs-Vth) 2=K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 ;

[0096] Among them, I is the driving current flowing through the third pixel transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third pixel transistor T3, Vth is the threshold voltage of the third pixel transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0097] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third pixel transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third pixel transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0098] Figure 3A is a schematic partial cross-sectional view of a display region of a display substrate according to at least one embodiment of the present disclosure. Figure 3A illustrates the structure of a sub-pixel in the display region as an example. In this example, the multiple pixel transistors in the pixel circuit can be of different transistor types, such as low-temperature polysilicon thin-film transistors and oxide thin-film transistors.

[0099] In some examples, as shown in FIG3A , in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels. In other examples, the display substrate may further include: a touch structure layer located on a side of the encapsulation structure layer away from the substrate. For example, the touch structure layer may include at least one touch conductive layer.

[0100] In some examples, FIG3A illustrates an example of each sub-pixel including a first transistor 21, a second transistor 22, and a capacitor 23. The first transistor 21 and the second transistor 22 may be of different transistor types. The first transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second transistor 22 may be an oxide thin-film transistor.

[0101] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, disposed on a substrate 10. A first gate insulating (GI) layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a first interlayer insulating (ILD) layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a third gate insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a second interlayer insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a passivation (PVX) layer 106 and a first planarization (PLN) layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; the first planarization layer 107 may be located on a side of the passivation layer 106 away from the substrate 10; and a second planarization layer 108 may be disposed on a side of the second source / drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the first interlayer insulating layer 103, the third gate insulating layer 104, the second interlayer insulating layer 105 and the passivation layer 106 can be inorganic insulating layers, and the first flat layer 107 and the second flat layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be further provided on the side of the first semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate and can also increase the adhesion of the film layer in the display substrate to the substrate. In other examples, a bottom shading metal layer (BSM, Bottom Shielding Metal) can also be provided on the side of the buffer layer close to the substrate. The bottom shading metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first flat layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0102] In some examples, as shown in FIG3A , the first semiconductor layer in the display area may include at least a first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate electrode 213 of the first transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate electrode 213 of the first transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate electrode 224 of the second transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap. The second semiconductor layer may include at least a second active layer 220 of the second transistor 22. The third gate metal layer may include at least a second gate 223 of the second transistor 22. The orthographic projection of the second gate 223 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second transistor 22, and the second gate 223 may be the top gate of the second transistor 22.

[0103] In some examples, as shown in FIG3A , the first source / drain metal layer may include at least a first source 211 and a first drain 212 of the first transistor 21, and a second source 221 and a second drain 222 of the second transistor 22. The second interlayer insulating layer 106 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The second interlayer insulating layer 105, the third gate insulating layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The second interlayer insulating layer 105, the third gate insulating layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The second interlayer insulating layer 105 and the third gate insulating layer 104 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source electrode 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain electrode 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source electrode 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain electrode 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain electrode 212 of the first transistor 21 of the pixel circuit through a fifth pixel via defined through the passivation layer 106 and the first planarization layer 107. In this example, the first transition electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0104] In some examples, the multiple gate lines of the display substrate may include: a first scan line, a second scan line, a first reset control line, a second reset control line, and a light emission control line. The multiple gate lines may, for example, be located in a first gate metal layer and a third gate metal layer. For example, the first scan line, the first reset control line, the second reset control line, and the light emission control line may be located in the first gate metal layer, and the second scan line may be located in the third gate metal layer. The multiple data lines may, for example, be located in the second source / drain metal layer, and the first power line of the display area may, for example, be located in the second source / drain metal layer. However, this embodiment is not limited to this.

[0105] In some examples, as shown in FIG3A , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the second planar layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 108. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0106] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0107] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0108] In some examples, as shown in FIG3A , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress in the first and third encapsulation layers 141 and 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic / inorganic.

[0109] Figure 3B is another partial cross-sectional schematic diagram of the display region of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3B , the circuit structure layer 12 of the display region may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer, disposed on the substrate 10. A second planarization layer 108 may be disposed between the second source / drain metal layer and the third source / drain metal layer, and a third planarization layer 109 may be disposed on the side of the third source / drain metal layer facing away from the substrate. The third planarization layer 109 may be an organic insulating layer. The third source / drain metal layer may include at least: a second transfer electrode 242, which may be connected to a first transfer electrode 241 located on the second source / drain metal layer. In this example, the first transfer electrode 241 and the second transfer electrode 242 may be used to electrically connect the pixel circuit to the first electrode 131 of the light-emitting element. The remaining structure of the display region of the display substrate of this example can be referred to the description of the embodiment shown in Figure 3A , and will not be further described here.

[0110] Figure 4 is a schematic diagram illustrating the configuration of a gate drive circuit according to at least one embodiment of the present disclosure. In some examples, multiple gate drive circuits may be provided in the border region. These multiple gate drive circuits may include: two first scan drive circuits 31a and 31b, a second scan drive circuit 32, a first reset drive circuit 33, a second reset drive circuit 34, and a light-emitting drive circuit 35. The first scan drive circuits 31a and 31b may be configured to provide a first scan signal to multiple rows of pixel circuits in display area AA. The second scan drive circuit 32 may be configured to provide a second scan signal to multiple rows of pixel circuits in display area AA. The light-emitting drive circuit 35 may be configured to provide a light-emitting control signal to multiple rows of pixel circuits in display area AA. The first reset drive circuit 33 may be configured to provide a first reset control signal to multiple rows of pixel circuits in display area AA. The second reset drive circuit 34 may be configured to provide a second reset control signal to multiple rows of pixel circuits in display area AA. In this example, the first scan signal may be driven bilaterally, while the second scan signal, light-emitting control signal, first reset control signal, and second reset control signal may be driven unilaterally. However, this embodiment is not limited to this. In some other examples, the first scan signal, the second scan signal, the light emitting control signal, the first reset control signal, and the second reset control signal may all be driven on one side.

[0111] In some examples, the display area AA includes M rows of pixel circuits, where M is a positive integer. The multiple rows of pixel circuits within the display area AA can be labeled as rows 1 to M along the direction from the second border area B12 to the first border area B11. The multiple gate drive circuits can include: a first group of gate drive circuits located in the third border area B13 and a second group of gate drive circuits located in the fourth border area B14. The first group of gate drive circuits can include the following three gate drive circuits: a first scan drive circuit 31a, a second scan drive circuit 32, and a second reset drive circuit 34. For example, within the third border area B13, the first scan drive circuit 31a, the second scan drive circuit 32, and the second reset drive circuit 34 can be arranged sequentially in a direction away from the display area AA. The second group of gate drive circuits can include the following three gate drive circuits: a first scan drive circuit 31b, a first reset drive circuit 33, and a light-emitting drive circuit 35. For example, within the fourth border area B14, the first scan drive circuit 31b, the first reset drive circuit 33, and the light-emitting drive circuit 35 can be arranged sequentially in a direction away from the display area AA. However, this embodiment is not limited to this.

[0112] In some examples, the multiple gate drive circuits located in the third border area B13 can also be arranged in the first corner area C11 and the third corner area C13 connected to the third border area B13; the multiple gate drive circuits located in the fourth border area B14 can also be arranged in the second corner area C12 and the fourth corner area C14 connected to the fourth border area B14.

[0113] In some examples, the first scan driving circuits 31a and 31b can each include a plurality of cascaded first scan driving units (e.g., including GP(1) to GP(M)). Each level of the first scan driving unit can be configured to provide a first scan signal to a row of pixel circuits in the display area AA. For example, the first-level first scan driving unit GP(1) can be configured to provide a first scan signal to the first row of pixel circuits in the display area AA; the M-th level first scan driving unit GP(M) can be configured to provide a first scan signal to the M-th row of pixel circuits in the display area AA.

[0114] In some examples, the second scan driving circuit 32 may include a plurality of cascaded second scan driving units (e.g., including GN(1) to GN(M)). Each level of the second scan driving unit may be configured to provide a second scan signal to a row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of the second scan driving unit may be configured to provide a second scan signal to two adjacent rows of pixel circuits in the display area AA.

[0115] In some examples, the light-emitting driving circuit 35 may include a plurality of cascaded light-emitting driving units (e.g., including EM(1) to EM(M)). Each level of light-emitting driving units may be configured to provide a light-emitting control signal to a row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of light-emitting driving units may be configured to provide a light-emitting control signal to two adjacent rows of pixel circuits in the display area AA.

[0116] In some examples, the first reset driving circuit 33 may include a plurality of cascaded first reset driving units (e.g., including PR(1) to PR(M)). Each level of the first reset driving unit may be configured to provide a first reset control signal to a row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of the first reset driving unit may be configured to provide a first reset control signal to two adjacent rows of pixel circuits in the display area AA.

[0117] In some examples, the second reset driving circuit 34 may include a plurality of cascaded second reset driving units (e.g., including RH(1) to RH(M)). Each level of the second reset driving unit may be configured to provide a second reset control signal to a row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of the second reset driving unit may be configured to provide a second reset control signal to two adjacent rows of pixel circuits in the display area AA.

[0118] In some examples, multiple gate drive circuits can be connected to multiple drive signal lines. The multiple drive signal lines can be configured to provide drive signals (e.g., including a start signal, a clock signal, a voltage signal, etc.) to the multiple gate drive circuits. For example, the multiple drive signal lines may include: a start signal line connected to the gate drive circuit (e.g., including a first scan drive circuit, a second scan drive circuit, a first reset drive circuit, a second reset drive circuit, and a light-emitting drive circuit), a clock signal line, a drive output line, and other lines that transmit AC signals, as well as lines that transmit DC signals such as a drive voltage to the gate drive circuit.

[0119] FIG5 is an equivalent circuit diagram of a multiplexing circuit of at least one embodiment of the present disclosure. FIG5 illustrates three multiplexing circuits 36. In some examples, as shown in FIG5, one multiplexing circuit 36 ​​can be electrically connected to two multiplexing control lines (e.g., a first multiplexing control line 421a and a second multiplexing control line 421b), one multiplexing data line 422, and multiple data lines (e.g., a first data line DL1 and a second data line DL1). The multiplexing circuit 36 ​​of this example can transmit the data signal provided by one multiplexing data line 422 to two data lines in a time-sharing manner. However, this embodiment is not limited to this. In other examples, one multiplexing circuit can transmit the data signal provided by one multiplexing data line 422 to three, six, or nine data lines in a time-sharing manner.

[0120] In some examples, a multiplexing circuit 36 ​​may include two multiplexing control transistors (i.e., a first multiplexing control transistor M1 and a second multiplexing control transistor M2). The gates of the two multiplexing control transistors may be connected to different multiplexing control lines, i.e., the gate of the first multiplexing control transistor M1 is connected to the first multiplexing control line 421a, and the gate of the second multiplexing control transistor M2 is connected to the second multiplexing control line 421b. The first electrodes of the two multiplexing control transistors may be connected to the same multiplexing data line 422. The second electrodes of the two multiplexing control transistors are respectively connected to different data lines. For example, the second electrode of the first multiplexing control transistor M1 is connected to the first data line DL1, and the second electrode of the second multiplexing control transistor M2 is connected to the second data line DL2. Each data line may be connected to at least one column of pixel circuits.

[0121] Figure 6 is a partial schematic diagram of the first border area of ​​at least one embodiment of the present disclosure. Figure 6 primarily illustrates two multiplexing circuits and multiple traces within the first border area B11 adjacent to the first edge of the display area AA. Figure 7A is a schematic diagram of the first semiconductor layer in Figure 6. Figure 7B is a schematic diagram of the first border area after the second semiconductor layer is formed in Figure 6. Figure 7C is a schematic diagram of the first border area after the second interlayer insulating layer is formed in Figure 6. Figure 7D is a schematic diagram of the first border area after the first source and drain metal layer is formed in Figure 6.

[0122] In some examples, as shown in Figures 6 to 7D, the multiple multiplexing circuits 36 in the first border region can be arranged along the first direction D1, and a plurality of dummy semiconductor blocks (for example, including a first dummy semiconductor block 501 and a second dummy semiconductor block 502) can be arranged in an array between adjacent multiplexing circuits 36. The two multiplexing control transistors M1 and M2 in each multiplexing circuit 36 ​​can be arranged sequentially along the first direction D1.

[0123] In some examples, as shown in FIG7A , the first semiconductor layer in the first border region may include an active layer M10 of the multiplexing control transistor M1 and an active layer M20 of the multiplexing control transistor M2 of the multiplexing circuit 36, as well as a plurality of first dummy semiconductor blocks 501. The active layer M10 of the multiplexing control transistor M1 and the active layer M20 of the multiplexing control transistor M2 may be arranged adjacent to each other along a first direction D1. The active layer M10 may include a channel region corresponding to the gate M13, and first and second regions located on either side of the channel region. The active layer M20 may include a channel region corresponding to the gate M23, and first and second regions located on either side of the channel region. The first region of the active layer M10 may be adjacent to the first region of the active layer M20. The orthographic projections of the active layer M10 of the multiplexing control transistor M1 and the active layer M20 of the multiplexing control transistor M2 onto the substrate may both be rectangular. The three first dummy semiconductor blocks 501 may be located in the spacing region between adjacent multiplexing circuits 36. The orthographic projection of the first dummy semiconductor block 501 on the substrate may be a rounded rectangle or a circle.

[0124] In some examples, as shown in FIG7B , the first gate metal layer in the first border region may include: a gate M13 of the multiplexing control transistor M1 of the multiplexing circuit 36, a gate M23 of the multiplexing control transistor M2, and a multiplexing data line 422a. The multiplexing data line 422a may be located on a side of the active layer M10 of the multiplexing control transistor M1 of the connected multiplexing circuit 36 ​​away from the display area, and on a side of the gate M13 of the multiplexing control transistor M1 opposite to the first direction D1. The orthographic projection of the gate M13 on the substrate may be a strip extending along the second direction D2, and the orthographic projection of the gate M23 on the substrate may be a zigzag extending along the second direction D2.

[0125] In some examples, as shown in FIG7B , the second gate metal layer in the first border region may include a multiplexed data line 422 b. The multiplexed data line 422 b may be located on a side of the active layer M10 of the multiplexing control transistor M1 of the connected multiplexing circuit 36 ​​away from the display area, and on a side of the gate M13 of the multiplexing control transistor M1 opposite to the first direction D1. The multiple multiplexed data lines in the first border region may be alternately arranged in the first gate metal layer and the second gate metal layer, and adjacent multiplexed data lines may be located in different conductive layers. The orthographic projections of the multiple multiplexed data lines on the substrate may not overlap.

[0126] In some examples, as shown in FIG7B , the second semiconductor layer in the first border region may include: a plurality of second dummy semiconductor blocks 502. One second dummy semiconductor block 502 and three first dummy semiconductor blocks 501 may be arranged in a 2*2 array, and the array may be located between adjacent multiplexing circuits 36. In this example, by providing the array formed by the first and second dummy semiconductor blocks between the multiplexing circuits, it can facilitate pattern uniformity of the first and second semiconductor layers.

[0127] In some examples, as shown in FIG7C , the second interlayer insulating layer in the first frame area may be provided with a plurality of vias, for example, including a first via V1 to a ninth via V9. The first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer in the first via V1, the second via V2, the third via V3, the fourth via V4, and the eighth via V8 may be removed to expose a portion of the surface of the first semiconductor layer. The second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer in the sixth via V6 and the seventh via V7 may be removed to expose a portion of the surface of the first gate metal layer. The first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer in the fifth via V5 may be removed to expose a portion of the surface of the second gate metal layer. The third gate insulating layer and the second interlayer insulating layer in the ninth via V9 may be removed to expose a portion of the surface of the second semiconductor layer. In this example, by opening the eighth via hole V8 on the first dummy semiconductor block and the ninth via hole V9 on the second dummy semiconductor block, the uniformity of the punching in the first border area can be improved.

[0128] In some examples, as shown in FIG7D , the first source-drain metal layer in the first border region may include: a first peripheral initial signal line 401, a second peripheral initial signal line 402, a first multiplexing control line 421a, a second multiplexing control line 421b, a first electrode M11 and a second electrode M12 of a multiplexing control transistor M1 of a multiplexing circuit 36, and a first electrode M21 and a second electrode M22 of a multiplexing control transistor M2. For example, the first peripheral initial signal line 401 may be configured to transmit a first initial signal to a first initial signal line in a display region, and the second peripheral initial signal line 402 may be configured to transmit a second initial signal to a second initial signal line in a display region.

[0129] In some examples, the first and second peripheral initial signal lines 401 and 402 may extend at least along the first direction D1 and be located on a side of the multiplexing circuit 36 ​​close to the display area. The second peripheral initial signal line 402 may be located on a side of the first peripheral initial signal line 401 away from the multiplexing circuit.

[0130] In some examples, the first multiplexing control line 421a and the second multiplexing control line 421b extend at least along the first direction D1 and are located on a side of the multiplexing circuit 36 ​​away from the display area. The second multiplexing control line 421b can be located on a side of the first multiplexing control line 421a away from the multiplexing circuit 36. The line widths of the first multiplexing control line 421a and the second multiplexing control line 421b can be greater than the line widths of the first peripheral initial signal line 401 and the second peripheral initial signal line 402. The first multiplexing control line 421a can be connected to the gate M13 of the multiplexing control transistor M1 through two sixth vias V6 arranged side by side; the second multiplexing control line 421b can be connected to the gate M23 of the multiplexing control transistor M2 through two seventh vias V7 arranged side by side. In this example, side-by-side arrangement refers to arrangement along the first direction D1, and vertical arrangement refers to arrangement along the second direction D2.

[0131] In some examples, the orthographic projection of the first electrode M11 of the multiplexing control transistor M1 on the substrate may be a strip extending along the second direction D2. The orthographic projection of the first electrode M21 of the multiplexing control transistor M2 on the substrate may be a strip extending along the second direction D2. The first electrode M11 of the multiplexing control transistor M1 may be connected to the first region of the active layer M10 through four second vias V2 arranged in a vertical row. The second electrode M12 of the multiplexing control transistor M1 may be connected to the second region of the active layer M10 through four first vias V1 arranged in a vertical row. The first electrode M21 of the multiplexing control transistor M2 may be connected to the first region of the active layer M20 through four third vias V3 arranged in a vertical row, and the second electrode M22 of the multiplexing control transistor M2 may be connected to the second region of the active layer M20 through four fourth vias V4 arranged in a vertical row. The first electrode M11 of the multiplexing control transistor M1 and the first electrode M21 of the multiplexing control transistor M2 may be an integrated structure connected to each other, and the integrated structure may be connected to the multiplexing data line 422b located in the second gate metal layer through two fifth vias V5 arranged side by side.

[0132] In some examples, as shown in FIG6 , the second source / drain metal layer in the first frame region may include at least: a plurality of drive signal lines (e.g., a first drive output line 411, a second drive output line 412, and a third drive output line 413), a third peripheral initial signal line 403, and a first peripheral power line 404. For example, the third peripheral initial signal line 403 may be configured to transmit a third initial signal to the third initial signal line in the display region; and the first peripheral power line 404 may be configured to provide a first voltage signal VDD to the first power line in the display region. The first drive output line 411 may be a first scan drive output line connected to the first scan drive circuit; the second drive output line 412 may be a second scan drive output line connected to the second scan drive circuit, or may be a first reset drive output line connected to the first reset drive circuit; and the third drive output line 413 may be a second reset drive output line connected to the second reset drive circuit, or may be a light-emitting drive output line connected to the light-emitting drive circuit. This embodiment is not limited to this.

[0133] In some examples, the plurality of drive signal lines, the third peripheral signal line 403, and the first peripheral power supply line 404 can be located on a side of the multiplexing circuit 36 ​​away from the display area. For example, the first drive output line 411, the second drive output line 412, the first peripheral power supply line 404, the third drive output line 413, and the third peripheral initial signal line 403 can be arranged sequentially in a direction away from the multiplexing circuit 36.

[0134] In some examples, the data line DL in the display area can be located in the second source / drain metal layer. The data line DL can extend from the display area to the first frame area and be connected to the second electrode M12 (or second electrode M22) of the multiplexing control transistor M1 (or M2) of the multiplexing circuit through a via hole opened in the first planar layer and the passivation layer.

[0135] In some examples, as shown in Figures 6 to 7D, the multiple drive signal lines located in the first frame area can be located on the side of the active layer of the multiplexing control transistor of the multiplexing circuit 36 ​​that is away from the display area. The multiple drive signal lines do not overlap with the orthographic projection of the active layer of the multiplexing control transistor of the multiplexing circuit 36 ​​on the substrate. In this way, the overlap of the routing of the AC signal in the drive signal line and the multiplexing control transistor of the multiplexing circuit can be reduced, resulting in signal coupling and load differences, thereby avoiding display anomalies caused by signal coupling.

[0136] Figure 8 is a partial schematic diagram of the first border area and the first corner area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 8, the first border area may include: a first fan-out area B111, a bending area B112, and a second fan-out area B113 arranged in sequence along a direction away from the display area AA. The first fan-out area B111 can be connected to the first corner area C11 and the second corner area C12, and connected to the display area AA. The bending area B112 can connect the first fan-out area B111 and the second fan-out area B113. The bending area B112 can be configured to bend the second fan-out area B113 to the back of the display area AA. The second fan-out area B113 can be provided with a plurality of first contact pads connected to the driver chip, and a plurality of second contact pads connected to the flexible circuit board, and the plurality of second contact pads can be located on the side of the plurality of first contact pads away from the bending area B112.

[0137] In some examples, as shown in FIG8 , the display area AA may be provided with multiple data lines DL and multiple data transfer lines 25. The multiple data lines DL may extend along the second direction D2 and be arranged along the first direction D1. The data transfer lines 25 may include a first transfer segment 251 extending along the first direction D1 and a second transfer segment 252 extending along the second direction D2. The second transfer segments 252 of the data transfer lines 25 may be arranged at intervals between the multiple data lines DL. At least one data line DL is connected to the first transfer segment 251 of the data transfer line 25, which is connected to the second transfer segment 252. The data line DL may be located on a side of the second transfer segment 252 of the data transfer line 25 to which it is connected, closer to an edge of the display area AA, in the first direction D1. The second transfer segment 252 of the data transfer line 25 may extend to the first fan-out area B111 and be connected to the multiplexing circuit 36 ​​within the first fan-out area B111. In some examples, the film layer structure of the display area can be as shown in FIG3B , where the first transfer segment 251 of the data transfer line 25 can be located in the third source-drain metal layer away from the second source-drain metal layer, and the second transfer segment 252 and the data line DL can be located in the second source-drain metal layer. However, this embodiment is not limited to this.

[0138] In some examples, the plurality of data lines DL may include a first group of data lines and a second group of data lines. The first group of data lines may extend directly to the first fan-out area B111 and be connected to the corresponding multiplexing circuit 36. The second group of data lines may be connected to the multiplexing circuit 36 ​​via a plurality of data adapter lines 25. The first group of data lines may be located on a side of the second group of data lines away from the edge of the display substrate. However, this embodiment is not limited to this. In other examples, the plurality of data lines within the display area may all be connected to the multiplexing circuit via data adapter lines.

[0139] In some examples, as shown in FIG8 , the first fan-out area B111 may be provided with a plurality of multiplexing circuits 36, a plurality of multiplexing data lines 422, and a plurality of drive signal lines 41. The plurality of drive signal lines 41 may extend to the first corner area C11 and the third border area to connect to the gate drive circuit. The plurality of multiplexing data lines 422 may be connected to the multiplexing circuit 36. The plurality of multiplexing circuits 36 may be arranged sequentially along the first direction D1. Within the first fan-out area B111, the plurality of drive signal lines 41 may be located on a side of the plurality of multiplexing circuits 36 away from the display area AA.

[0140] In some examples, as shown in FIG8 , the bending region B112 may include at least a first group of driving bending lines 51, a first group of composite bending lines 52, a first group of data bending lines 53a, a second group of data bending lines 53b, and a first group of first power bending lines 54. The first group of driving bending lines 51, the first group of touch bending lines 52, the first group of data bending lines 53a, the second group of data bending lines 53b, and the first group of first power bending lines 54 may be sequentially arranged along the first direction D1.

[0141] In some examples, the first and second groups of data bending lines may each include multiple data bending lines. The first and second groups of data bending lines 53a and 53b may connect multiplexed data lines 422 within the first fan-out region B111 and multiple data lead lines 62 within the second fan-out region B113. The multiple data lead lines 62 may extend to connect to the multiple first contact pads to transmit data signals.

[0142] In some examples, the first set of drive meandering lines 51 may include a plurality of drive meandering lines. The first set of drive meandering lines 51 may connect the drive signal lines 41 located in the first fan-out region B111 and the plurality of control lead lines 61 located in the second fan-out region B113. The plurality of control lead lines 61 may extend to connect to the plurality of second contact pads to transmit drive signals provided to the gate driver circuit.

[0143] In some examples, the first group of composite meander lines 52 may include multiple touch meander lines and at least one second power meander line; the second power meander line may be connected to a second peripheral power line transmitting a second voltage signal within the first fan-out region B111. The first group of first power meander lines 54 may be connected to a first peripheral power line within the first fan-out region B111.

[0144] In this example, the data lines DL and the multiplexing circuit 36 ​​are connected via data adapter lines 25 located in the display area AA. This eliminates the need to extend the data lines from the curved edge of the display area AA to the first fan-out area, and eliminates the need to arrange the multiplexing circuit along the curved edge of the display area. This eliminates the need to arrange the multiplexing circuit in the first corner area, allowing the multiplexing circuit 36 ​​to be arranged along a straight line segment in the first direction D1 within the first fan-out area B111. Multiple drive signal lines 41 extend from both sides of the multiplexed data lines to the first corner area and the second corner area, respectively, thereby avoiding the possibility of overlap between the drive signal lines 41 and the multiplexing circuit 36. Furthermore, the structure of the connection between the first border area and the second corner area is similar to that of the connection between the first border area and the first corner area, and therefore will not be further described here.

[0145] FIG9 is an equivalent circuit diagram of a first scan drive unit of a first scan drive circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG9 , the first scan drive unit may include: a first shift transistor GT1, a second shift transistor GT2, a third shift transistor GT3, a fourth shift transistor GT4, a fifth shift transistor GT5, a sixth shift transistor GT6, a seventh shift transistor GT7, an eighth shift transistor GT8, a first shift storage capacitor GC1, and a second shift storage capacitor GC2. The fourth shift transistor GT4 may also be referred to as a first output transistor, and the fifth shift transistor GT5 may also be referred to as a second output transistor.

[0146] In some examples, as shown in FIG9 , the gate of the first shift transistor GT1 is electrically connected to the first clock signal line GCK, the first electrode of the first shift transistor GT1 is electrically connected to the shift input terminal GIN, and the second electrode of the first shift transistor GT1 is electrically connected to the first shift node GN1. The gate of the second shift transistor GT2 is electrically connected to the first shift node GN1, the first electrode of the second shift transistor GT2 is electrically connected to the first clock signal line GCK, and the second electrode of the second shift transistor GT2 is electrically connected to the second shift node GN2. The gate of the third shift transistor GT3 is electrically connected to the first clock signal line GCK, the first electrode of the third shift transistor GT3 is electrically connected to the second drive voltage line VGL, and the second electrode of the third shift transistor GT3 is electrically connected to the second shift node GN2. The gate of the fourth shift transistor GT4 is electrically connected to the second shift node GN2, the first electrode of the fourth shift transistor GT4 is electrically connected to the first drive voltage line VGH, and the second electrode of the fourth shift transistor GT4 is electrically connected to the shift output terminal GOUT. The gate of the fifth shift transistor GT5 is electrically connected to the third shift node GN3, the first electrode of the fifth shift transistor GT5 is electrically connected to the second clock signal line GCB, and the second electrode of the fifth shift transistor GT5 is electrically connected to the shift output terminal GOUT. The gate of the sixth shift transistor GT6 is electrically connected to the second shift node GN2, the first electrode of the sixth shift transistor GT6 is electrically connected to the first drive voltage line VGH, and the second electrode of the sixth shift transistor GT6 is electrically connected to the first electrode of the seventh shift transistor GT7. The gate of the seventh shift transistor GT7 is electrically connected to the second clock signal line GCB, and the second electrode of the seventh shift transistor GT7 is electrically connected to the first shift node GN1. The gate of the eighth shift transistor GT8 is electrically connected to the second drive voltage line VGL, the first electrode of the eighth shift transistor GT8 is electrically connected to the first shift node GN1, and the second electrode of the eighth shift transistor GT8 is electrically connected to the third shift node GN3. The second electrode of the first shift storage capacitor GC1 is electrically connected to the first drive voltage line VGH, and the first electrode of the first shift storage capacitor GC1 is electrically connected to the second shift node GN2. A second electrode of the second shift storage capacitor GC2 is electrically connected to the shift output terminal GOUT, and a first electrode of the second shift storage capacitor GC2 is electrically connected to the third shift node GN3. The first drive voltage line VGH can be configured to continuously provide a high-level signal, and the second drive voltage line VGL can be configured to continuously provide a low-level signal.

[0147] In this example, as shown in FIG9 , the first shift node GN1 is a connection point between the first shift transistor GT1, the second shift transistor GT2, the seventh shift transistor GT7, and the eighth shift transistor GT8. The second shift node GN2 is a connection point between the second shift transistor GT2, the third shift transistor GT3, the fourth shift transistor GT4, the sixth shift transistor GT6, and the first shift storage capacitor GC1. The third shift node GN3 is a connection point between the eighth shift transistor GT8, the fifth shift transistor GT5, and the second shift storage capacitor GC2.

[0148] In some examples, the first shift transistor GT1 to the eighth shift transistor GT8 of the first scan driving unit shown in FIG9 may all be P-type transistors or N-type transistors. However, this embodiment is not limited thereto.

[0149] Figure 10A is a schematic diagram of the partial structure of the third border area of ​​at least one embodiment of the present disclosure. Figure 10A illustrates the structure of a first scan drive unit of the first scan drive circuit in the third border area. Figure 10B is a schematic diagram of the first semiconductor layer in Figure 10A. Figure 10C is a schematic diagram of the first semiconductor layer and the first gate metal layer in Figure 10A. Figure 10D is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 10A. Figure 10E is a schematic diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the first source and drain metal layer in Figure 10A. Figure 10F is a schematic diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the second source and drain metal layer in Figure 10A.

[0150] In some examples, as shown in FIG10B , the first semiconductor layer of the third frame region may include at least an active layer GT10 of a first shift transistor of a first scan driving unit, an active layer GT20 of a second shift transistor, an active layer GT30 of a third shift transistor, an active layer GT40 of a fourth shift transistor, an active layer GT50 of a fifth shift transistor, an active layer GT60 of a sixth shift transistor, an active layer GT70 of a seventh shift transistor, and an active layer GT80 of an eighth shift transistor. Each active layer may include a channel region corresponding to a gate, and a first region and a second region located on both sides of the channel region.

[0151] In some examples, as shown in FIG10B , the active layer GT40 of the fourth shift transistor and the active layer GT50 of the fifth shift transistor may be located on one side of the active layers of the remaining shift transistors in the first direction D1. The active layer GT50 of the fifth shift transistor may be located on one side of the active layer GT40 of the fourth shift transistor in the second direction D2. The active layer GT40 of the fourth shift transistor may include a first sub-active layer GT40-1 and a second sub-active layer GT40-2 sequentially arranged along the first direction D1. The active layer GT50 of the fifth shift transistor may include a first sub-active layer GT50-1 and a second sub-active layer GT50-2 sequentially arranged along the first direction D1. The first sub-active layer GT40-1 and the first sub-active layer GT50-1 can be interconnected as an integral structure, and the orthographic projection of the integral structure of the first sub-active layer GT40-1 and the first sub-active layer GT50-1 on the substrate can be a rectangle. The second sub-active layer GT40-2 and the second sub-active layer GT50-2 can be interconnected as an integral structure, and the orthographic projection of the integral structure of the second sub-active layer GT40-2 and the second sub-active layer GT50-2 on the substrate can be a rectangle. The second region of the first sub-active layer GT40-1 and the second region of the first sub-active layer GT50-1 can be directly connected, and the second region of the second sub-active layer GT40-2 and the second region of the second sub-active layer GT50-2 can be directly connected. The integral structure of the first sub-active layer GT40-1 and the first sub-active layer GT50-1, and the integral structure of the second sub-active layer GT40-2 and the second sub-active layer GT50-2 are arranged sequentially along the first direction D1.

[0152] In some examples, as shown in FIG10B , the active layer GT10 of the first shift transistor may be in the shape of a strip extending in the first direction D1 when projected onto the substrate. The active layer GT20 of the second shift transistor and the active layer GT30 of the third shift transistor may be interconnected as an integral structure, and the orthographic projection of the integral structure onto the substrate may be in the shape of a strip extending in the second direction D2. The second region of the active layer GT20 of the second shift transistor and the second region of the active layer GT30 of the third shift transistor are directly connected. The active layer GT60 of the sixth shift transistor and the active layer GT70 of the seventh shift transistor may be in the shape of a strip extending in the second direction D2 when projected onto the substrate. The second region of the active layer GT60 of the sixth shift transistor and the first region of the active layer GT70 of the seventh shift transistor may be directly connected. The active layer GT80 of the eighth shift transistor may be located on one side of the active layer GT30 of the third shift transistor along the first direction D1 , and an orthographic projection of the active layer GT80 on the substrate may be a strip extending along the second direction D2 .

[0153] In some examples, as shown in Figure 10C, the first gate metal layer of the third border area may include at least: the gate GT11 of the first shift transistor, the gate GT21 of the second shift transistor, the gate GT31 of the third shift transistor, the gate GT41 of the fourth shift transistor, the gate GT51 of the fifth shift transistor, the gate GT61 of the sixth shift transistor, the gate GT71 of the seventh shift transistor, the gate GT81 of the eighth shift transistor, the first plate GC1-1 of the first shift storage capacitor, and the first plate GC2-1 of the second shift storage capacitor.

[0154] In some examples, the orthographic projection of the gate GT11 of the first shift transistor on the substrate can be an N-shaped structure. The orthographic projection of the gate GT21 of the second shift transistor, the gate GT71 of the seventh shift transistor, the gate GT81 of the eighth shift transistor, the gate GT41 of the fourth shift transistor, and the gate GT61 of the sixth shift transistor on the substrate can be approximately strip-shaped and extend along the first direction D1. The orthographic projection of the gate GT31 of the third shift transistor on the substrate can be approximately L-shaped. The gate GT51 of the fifth shift transistor can include three strip-shaped structures extending along the first direction D1, and the three strip-shaped structures are arranged along the second direction D2.

[0155] In some examples, the gate GT41 of the fourth shift transistor, the gate GT61 of the sixth shift transistor, and the first plate GC1-1 of the first shift storage capacitor can be interconnected as an integral structure. The first plate GC1-1 of the first shift storage capacitor can serve as the second electrode of the first shift storage capacitor. The gate GT51 of the fifth shift transistor and the first electrode GC2-1 of the second shift storage capacitor can be interconnected as an integral structure. The first electrode GC2-1 of the second shift storage capacitor can serve as the second electrode of the second shift storage capacitor.

[0156] In some examples, as shown in FIG10D , the second gate metal layer in the third border region may include at least: a second plate GC1-2 of a first shift storage capacitor; and a second plate GC2-2 of a second shift storage capacitor. The orthographic projection of the second plate GC1-2 on the substrate is within the orthographic projection of the first plate GC1-1 on the substrate; and the orthographic projection of the second plate GC2-2 on the substrate is within the orthographic projection of the first plate GC2-1 on the substrate.

[0157] In some examples, the first shift storage capacitor GC1 can be located on one side of the fourth shift transistor GT4 in the first direction D1, and the second shift storage capacitor GC2 can be located on one side of the fifth shift transistor GT5 in the first direction D1. The first shift storage capacitor GC1 and the second shift storage capacitor GC2 can be arranged sequentially along the second direction D2.

[0158] In some examples, as shown in FIG. 10E , the first source-drain metal layer in the third frame region may include at least a plurality of scan connection electrodes (eg, including a first scan connection electrode 601 to a tenth scan connection electrode 610 ).

[0159] In some examples, the first scan connection electrode 601 can be connected to the first region of the active layer GT10 of the first shift transistor GT1. The first scan connection electrode 601 can serve as the shift input terminal GIN of the first scan driving unit of the current stage, for example, it can be connected to the shift output terminal of the first scan driving unit of the previous stage. The second scan connection electrode 602 can be connected to GT11 of the first shift transistor GT1, the gate GT31 of the third shift transistor GT3, and the first region of the active layer GT20 of the second shift transistor GT2. The third scan connection electrode 603 can be connected to the second region of the active layer GT20 of the second shift transistor GT2, the second region of the active layer GT30 of the third shift transistor GT3, and the gate GT61 of the sixth shift transistor GT6. The third scan connection electrode 603 can serve as the second shift node of the first scan driving unit. The fourth scan connection electrode 604 can be connected to the first region of the active layer GT30 of the third shift transistor GT3 and the gate GT81 of the eighth shift transistor GT8. The fifth scan connection electrode 605 can be connected to the gate electrode GT21 of the second shift transistor GT2, the first region of the active layer GT10 of the first shift transistor GT1, the first region of the active layer GT80 of the eighth shift transistor GT8, and the second region of the active layer GT70 of the seventh shift transistor GT7. The fifth scan connection electrode 605 can serve as the first shift node of the first scan driving unit. The sixth scan connection electrode 606 can be connected to the gate electrode GT71 of the seventh shift transistor GT7 for subsequent connection to the second clock signal line GCB. The seventh scan connection electrode 607 can be connected to the second region of the active layer GT80 of the eighth shift transistor GT8 and the gate electrode GT51 of the fifth shift transistor GT5. The seventh scan connection electrode 607 can serve as the third shift node of the first scan driving unit. The eighth scanning connection electrode 608 can be connected to the first region of the active layer GT60 of the sixth shift transistor GT6, the first regions of the first sub-active layer GT40-1 and the second sub-active layer GT40-2 of the fourth shift transistor GT4, and the second plate GC1-2 of the first shift storage capacitor GC1. The second plate GC1-2 of the first shift storage capacitor GC1 can serve as the first electrode of the first shift storage capacitor GC1. The ninth scanning connection electrode 609 can be connected to the gate electrode GT71 of the seventh shift transistor GT7, the first region of the first sub-active layer GT50-1 and the second sub-active layer GT50-2 of the fifth shift transistor GT5. The tenth scanning connection electrode 610 can be connected to the second region of the first sub-active layer GT40-1 and the second sub-active layer GT40-2 of the fourth shift transistor GT4, the second region of the first sub-active layer GT50-1 and the second sub-active layer GT50-2 of the fifth shift transistor GT5, and the second plate GC2-2 of the second shift storage capacitor GC2.The second electrode plate GC2-2 of the second shift storage capacitor GC2 can serve as the first electrode of the second shift storage capacitor GC2. The tenth scan connection electrode 610 can serve as the shift output terminal of the first scan driving unit.

[0160] In some examples, as shown in Figures 10A and 10F, the second source-drain metal layer in the third border region may include at least: a plurality of driving signal lines (for example, including a first start signal line GSTV, a second start signal line NSTV, a third start signal line HSTV, a first clock signal line GCK, a second clock signal line GCB, a first driving voltage line VGH, and a second driving voltage line VGL), a third peripheral initial signal line 403, and an eleventh scan connection electrode 611. The first start signal line GSTV, the second start signal line NSTV, the third start signal line HSTV, the first clock signal line GCK, the second clock signal line GCB, the first driving voltage line VGH, the second driving voltage line VGL, and the third peripheral initial signal line 403 may all extend at least along the second direction D2.

[0161] In some examples, the first clock signal line GCK can be connected to the second scan connection electrode 602 located on the first source-drain metal layer to achieve electrical connection with the first shift transistor GT1, the second shift transistor GT2, and the third shift transistor GT3. The second clock signal line GCB can be connected to the sixth scan connection electrode 606 located on the first source-drain metal layer to achieve electrical connection with the seventh shift transistor GT7; the second clock signal line GCB can be electrically connected to the fifth shift transistor GT5 through the sixth scan connection electrode 606, the gate GT71 of the seventh shift transistor GT7, and the ninth scan connection electrode 609. The first drive voltage line VGH can be connected to the eighth scan connection electrode 608 located on the first source-drain metal layer to achieve electrical connection with the sixth shift transistor GT6, the fourth shift transistor GT4, and the first shift storage capacitor GC1. The second drive voltage line VGL can be connected to the fourth scan connection electrode 604 located on the first source-drain metal layer to achieve electrical connection with the third shift transistor GT3 and the eighth shift transistor GT8. The eleventh scan connection electrode 611 may be connected to the tenth scan connection electrode 610 located on the first source / drain metal layer. The eleventh scan connection electrode 611 may extend toward the display area to facilitate connection to at least one first scan line in the display area.

[0162] In some examples, the first start signal line GSTV can be located on one side of the fourth shift transistor GT4 and the fifth shift transistor GT5 along the first direction D1, and the third peripheral initial signal line 403 can be located on one side of the first start signal line GSTV along the first direction D1. The first start signal line GSTV can be connected to the first scan drive circuit (e.g., the first scan drive circuit 31a shown in Figure 4) and configured to provide a start signal to the first scan drive circuit. The orthographic projections of the first start signal line GSTV and the third peripheral initial signal line 403 on the substrate do not overlap with the orthographic projections of the active layer GT40 of the fourth shift transistor GT4 and the active layer GT50 of the fifth shift transistor GT5 on the substrate, but may partially overlap with the orthographic projections of the first shift storage capacitor GC1 and the second shift storage capacitor GC2 on the substrate.

[0163] In some examples, the second start signal line NSTV, the first clock signal line GCK, the second clock signal line GCB, the second drive voltage line VGL, and the third start signal line HSTV can be located on a side opposite to the first direction D1 of the fourth shift transistor GT4 and the fifth shift transistor GT5. The second start signal line NSTV can be connected to the second scan drive circuit (the second scan drive circuit 32 shown in FIG4 ) and configured to provide a start signal to the second scan drive circuit. The third start signal line HSTV can be connected to the second reset drive circuit (the second reset drive circuit 34 shown in FIG4 ) and configured to provide a start signal to the second reset drive circuit. The first clock signal line GCK can be connected to the first scan drive circuit 31a and configured to provide a first clock signal to the first scan drive circuit 31a. The second clock signal line GCB can be connected to the first scan drive circuit 31a and configured to provide a second clock signal to the first scan drive circuit 31a. The second drive voltage line VGL can be connected to the first scan drive circuit 31a and configured to provide a low-level second drive voltage to the first scan drive circuit 31a. The orthographic projections of the second start signal line NSTV, the first clock signal line GCK, the second clock signal line GCB, the second driving voltage line VGL and the third start signal line HSTV on the substrate may not overlap with the orthographic projections of the active layer GT40 of the fourth shift transistor GT4 and the active layer GT50 of the fifth shift transistor GT5 on the substrate.

[0164] In some examples, the first drive voltage line VGH can be configured to provide a high-level first drive voltage. The orthographic projection of the first drive voltage line VGH on the substrate can be located between the orthographic projections of the first sub-active layer GT40-1 and the second sub-active layer GT40-2 of the fourth shift transistor GT4 on the substrate, and between the orthographic projections of the first sub-active layer GT50-1 and the second sub-active layer GT50-2 of the fifth shift transistor GT5 on the substrate. The orthographic projection of the first drive voltage line VGH on the substrate does not overlap with the orthographic projections of the first sub-active layer GT40-1 and GT50-1 on the substrate, and the orthographic projection of the first drive voltage line VGH on the substrate does not overlap with the orthographic projections of the second sub-active layer GT40-2 and GT50-2 on the substrate. For example, the distance between the orthographic projection of the first drive voltage line VGH on the substrate and the orthographic projection of the first sub-active layer GT40-1 (or the second sub-active layer GT40-2) of the fourth shift transistor GT4 on the substrate can be equal to the distance between the orthographic projection of the first drive voltage line VGH on the substrate and the orthographic projection of the first sub-active layer GT50-1 (or the second sub-active layer GT50-2) of the fifth shift transistor GT5 on the substrate, for example, can be greater than or equal to the minimum spacing between adjacent conductive layers that meets the process conditions.

[0165] This example reduces the load differences between different signals caused by the overlap of wiring and circuits by setting multiple drive signal lines (for example, including a first drive voltage line) to avoid the active layers of the first output transistor and the second output transistor of the first scan drive circuit, and avoids display anomalies caused by signal coupling.

[0166] In some examples, the structure of the first scan drive circuit in the fourth border area is similar to the structure of the first scan drive circuit in the third border area. In the fourth border area, the position corresponding to the second start signal line NSTV can be replaced by the fourth start signal line PSTV, and the position corresponding to the third start signal line HSTV can be replaced by the fifth start signal line ESTV. The fourth start signal line PSTV can be connected to the first reset drive circuit (the first reset drive circuit 33 as shown in Figure 4), and is configured to provide a start signal to the first reset drive circuit. The fifth start signal line ESTV can be connected to the light-emitting drive circuit (the light-emitting drive circuit 35 as shown in Figure 4), and is configured to provide a start signal to the light-emitting drive circuit. The structure of the first scan drive circuit in the fourth border area is not repeated here.

[0167] FIG11 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG11 , an electrostatic discharge circuit can be connected to a frame signal line XL and configured to discharge static electricity from the frame signal line XL to which it is connected. An electrostatic discharge circuit can include first to fourth release transistors ST1 to ST4. A first electrode of the first release transistor ST1 is electrically connected to the second drive voltage line VGL, a gate and a second electrode of the first release transistor ST1 are electrically connected to the first electrode of the second release transistor ST2, a gate and a second electrode of the second release transistor ST2 are electrically connected to the frame signal line XL corresponding to the electrostatic discharge circuit, a first electrode of the third release transistor ST3 is electrically connected to the frame signal line XL corresponding to the electrostatic discharge circuit, a gate and a second electrode of the third release transistor ST3 are electrically connected to the first electrode of the fourth release transistor ST4, and a gate and a second electrode of the fourth release transistor ST4 are electrically connected to the first drive voltage line VGH. The first drive voltage line VGH is configured to transmit a high-level signal, and the second drive voltage line VGL is configured to transmit a low-level signal.

[0168] In one example, providing an electrostatic discharge circuit can prevent static electricity accumulation in the border signal line from causing discharge breakdown and resulting in damage. By releasing the static electricity accumulated in the border signal line, the border signal line is protected.

[0169] In another example, the electrostatic discharge circuit may include two discharge transistors, each with one electrode connected to its own gate, forming an equivalent diode connection. The signal line to be protected is connected between the two "diodes," and the other two ends of the two "diodes" are connected to a first drive voltage line VGH and a second drive voltage line VGL, respectively. Thus, when a transient high voltage (e.g., 100V) appears in the signal line due to accumulated positive charge, one of the "diodes" conducts, releasing the positive charge in the signal line. When a transient low voltage (e.g., -100V) appears in the signal line due to accumulated negative charge, the other "diode" conducts, releasing the negative charge in the signal line.

[0170] In some examples, the multiple electrostatic discharge circuits provided in the border region may include: multiple first electrostatic discharge circuits located in a first corner region and a second corner region, and multiple second electrostatic discharge circuits located in a third corner region and a fourth corner region. In the multiple corner regions, orthographic projections of the multiple drive signal lines on the substrate may not overlap with orthographic projections of the multiple electrostatic discharge circuits on the substrate.

[0171] Figure 12 is a partial schematic diagram of the first corner region of at least one embodiment of the present disclosure. In some examples, the first corner region may be provided with multiple first electrostatic discharge circuits connected to multiple drive signal lines. Figure 12 illustrates three first electrostatic discharge circuits 37a, 37b, and 37c as an example. The structure of the second corner region is similar to that of the first corner region and will not be further described here.

[0172] In some examples, multiple first electrostatic discharge circuits can be arranged in an array within the first corner region. For example, the multiple first electrostatic discharge circuits can be arranged in at least one row, with each row of first electrostatic discharge circuits including multiple first electrostatic discharge circuits arranged sequentially along the first direction D1. Multiple rows of first electrostatic discharge circuits can be arranged along the second direction D2. As shown in FIG12 , three first electrostatic discharge circuits 37a, 37b, and 37c can be arranged in a row along the first direction D1. The fourth release transistor ST4, third release transistor ST3, second release transistor ST2, and first release transistor ST1 of the first electrostatic discharge circuit 37a can be arranged sequentially along the first direction D1; the first release transistor ST1, second release transistor ST2, third release transistor ST3, and fourth release transistor ST4 of the first electrostatic discharge circuit 37b can be arranged sequentially along the first direction D1; and the fourth release transistor ST4, third release transistor ST3, second release transistor ST2, and first release transistor ST1 of the first electrostatic discharge circuit 37c can be arranged sequentially along the first direction D1. In this example, the arrangement order of the four release transistors in adjacent first electrostatic release circuits in the same row can be reversed, so that the adjacent first electrostatic release circuits can be connected to the first driving voltage line VGH or the second driving voltage line VGL through the same connection electrode.

[0173] In some examples, multiple drive signal lines can be set in the first corner area, for example, including a first scan drive output line Gout located in the first gate metal layer, a third clock signal line NCK using a double-layer routing design of the first gate metal layer and the second gate metal layer, a first start signal line GSTV using a double-layer routing design of the first gate metal layer and the second gate metal layer, a first clock signal line GCK using a double-layer routing design of the first gate metal layer and the second gate metal layer, a second clock signal line GCB using a routing design of the first gate metal layer and the second gate metal layer, and a second scan drive output line Nout located in the first gate metal layer.

[0174] In some examples, the orthographic projections of the plurality of drive signal lines on the substrate may not overlap with the orthographic projections of the active layers of the release transistors of the plurality of first electrostatic discharge circuits on the substrate. For example, the first scan drive output line Gout, the third clock signal line NCK, the first start signal line GSTV, and the first clock signal line GCK may be located on one side of the plurality of first electrostatic discharge circuits 37a, 37b, and 37c in the opposite direction of the second direction D2; the second clock signal line GCB and the second scan drive output line Nout may be located on one side of the plurality of first electrostatic discharge circuits 37a, 37b, and 37c in the second direction D2.

[0175] In some examples, multiple connection electrodes located in the first source-drain metal layer can electrically connect the active layers and gates of the release transistors of multiple first electrostatic discharge circuits, and can also electrically connect multiple first electrostatic discharge circuits to multiple drive signal lines. For example, the first electrostatic discharge circuit 37a is connected to the third clock signal line NCK and is configured to release static electricity in the third clock signal line NCK; the first electrostatic discharge circuit 37b is connected to the first start signal line GSTV and is configured to release static electricity in the first start signal line GSTV; and the first electrostatic discharge circuit 37c is connected to the first clock signal line GCK and is configured to release static electricity in the first clock signal line GCK. The first electrostatic discharge circuit connected to the second clock signal line GCB and the second scan drive output line Nout can be located on one side of the second clock signal line GCB and the second scan drive output line Nout along the second direction D2. This embodiment is not limited to this.

[0176] In some examples, the first drive connection electrode 331 located in the first source-drain metal layer can connect the two voltage transmission line segments of the first drive voltage line in the first corner area and the fourth electrostatic release transistor ST4 of the first electrostatic release circuit 37a to achieve the transmission of the first drive voltage. The second drive connection electrode 332 located in the first source-drain metal layer can connect the first electrostatic release transistor ST1 of the first electrostatic release circuit 37a and the first electrostatic release transistor ST1 of the first electrostatic release transistor 37b, and can also be connected to the second drive voltage line in the first corner area. The third drive connection electrode 333 located in the first source-drain metal layer can connect the fourth electrostatic release transistor ST4 of the first electrostatic release circuit 37b and the fourth electrostatic release transistor ST4 of the first electrostatic release circuit 37c, and can also be connected to a voltage transmission line segment of the first drive voltage line in the first corner area.

[0177] In some examples, a plurality of third dummy semiconductor blocks 503 and a plurality of fourth dummy semiconductor blocks 504 may be provided on one side of the first scan drive output line Gout in the opposite direction of the second direction D2 and on one side of the first electrostatic discharge circuit 37a in the opposite direction of the first direction D1. The plurality of third dummy semiconductor blocks 503 may be located in the first semiconductor layer, and the plurality of fourth dummy semiconductor blocks 504 may be located in the second semiconductor layer. The plurality of third dummy semiconductor blocks 503 and the plurality of fourth dummy semiconductor blocks 504 may be arranged in an array and alternately disposed. In this example, by providing a plurality of third dummy semiconductor blocks and a plurality of fourth dummy semiconductor blocks, pattern uniformity in the lower corner region is facilitated.

[0178] In this example, in the lower corner area (including the first corner area and the second corner area), the driving signal line can avoid multiple first electrostatic release circuit settings, which can reduce the load difference between different signals caused by the overlap of the routing and the first electrostatic release circuit, and avoid display abnormalities caused by signal coupling.

[0179] FIG13 is a partial schematic diagram of the third corner region of at least one embodiment of the present disclosure. FIG14 is a partial structural schematic diagram of FIG13. FIG14 omits the structure of the second source / drain metal layer in FIG13. In some examples, a plurality of second electrostatic discharge circuits may be provided in the third corner region. FIG13 illustrates a second electrostatic discharge circuit 38 in the third corner region as an example. The structure of the fourth corner region is similar to that of the third corner region, and therefore will not be described in detail here.

[0180] In some examples, as shown in Figures 13 and 14, at least one second electrostatic discharge circuit 38 is provided in the third corner region. The four electrostatic discharge transistors of the second electrostatic discharge circuit 38 can be arranged in an array, for example, in a 2*2 array. The first electrostatic discharge circuit ST1 and the second electrostatic discharge circuit ST2 can be arranged in a row, the third electrostatic discharge circuit ST3 and the fourth electrostatic discharge circuit ST4 can be arranged in a row, the first electrostatic discharge circuit ST1 and the fourth electrostatic discharge circuit ST4 can be arranged in a column, and the second electrostatic discharge circuit ST2 and the third electrostatic discharge circuit ST3 can be arranged in a column.

[0181] In some examples, the first electrostatic discharge transistor ST1 of the second electrostatic discharge circuit 38 can be connected to the second driving voltage line via the fourth driving connection electrode 334 located on the first source-drain metal layer. The fourth electrostatic discharge transistor ST4 can be connected to the first driving voltage line VGH located on the second source-drain metal layer via the fifth driving connection electrode 335 located on the first source-drain metal layer.

[0182] In some examples, the second electrostatic discharge transistor ST2 and the third electrostatic discharge transistor ST3 can be connected to the second connection line 342 located in the first source-drain metal layer. The second connection line 342 can be connected to the first connection line 341 located in the first source-drain metal layer through an auxiliary wiring 351 located in the first semiconductor layer, and can also be connected to the third connection line 343 and the fourth connection line 344 located in the second source-drain metal layer. The auxiliary wiring 351 can reduce the current of the first connection line 341. The first connection line 341, the second connection line 342, the third connection line 343 and the fourth connection line 344 can be configured to transmit the same drive signal, for example, they can be connected to the same drive output line or the same start signal line.

[0183] In some examples, multiple fifth dummy semiconductor blocks 505 and multiple sixth dummy semiconductor blocks 506 can be disposed around the second electrostatic discharge circuit 38. The multiple fifth dummy semiconductor blocks 505 can be located on the first semiconductor layer, and the multiple sixth dummy semiconductor blocks 506 can be located on the second semiconductor layer. The multiple fifth dummy semiconductor blocks 505 and the multiple sixth dummy semiconductor blocks 506 can be arranged in an array and alternately disposed. In this example, by disposing multiple fifth dummy semiconductor blocks and multiple sixth dummy semiconductor blocks, pattern uniformity in the upper corner region is facilitated.

[0184] In some examples, in the third corner region, the first clock signal line GCK and the second clock signal line GCB may be located in the second source / drain metal layer and may be located on a side of the second electrostatic discharge circuit 38 opposite to the second direction D2. The first clock signal line GCK is located on a side of the second clock signal line GCB that is closer to the second electrostatic discharge circuit 38. The orthographic projection of the first clock signal line GCK on the substrate may not overlap with the orthographic projection of the electrostatic discharge transistor of the second electrostatic discharge circuit 38 on the substrate.

[0185] In this example, in the upper corner area (including the third corner area and the fourth corner area), the driving signal line can avoid multiple second electrostatic release circuit settings, which can reduce the load difference between different signals caused by the overlap of the routing and the second electrostatic release circuit, and avoid display abnormalities caused by signal coupling.

[0186] In the display substrate of this embodiment, the driving signal lines in the border area can be set to avoid the active layer of the multiplexing control transistor of the multiplexing circuit, the electrostatic release transistor of the electrostatic release circuit, and the output transistor of the first scanning driving circuit. This can reduce the load difference between different signals caused by the overlap of wiring and circuits, thereby avoiding display anomalies caused by signal coupling, and thus improving display quality and competitiveness.

[0187] This embodiment also provides a display substrate comprising a display area and a frame area surrounding the display area. The display substrate comprises: a substrate, a plurality of sub-pixels located in the display area and on one side of the substrate, at least one first scan drive circuit located in the frame area and on one side of the substrate, and a plurality of drive signal lines. The first scan drive circuit comprises a plurality of cascaded first scan drive units, each of which comprises at least one output transistor. The first scan drive circuit is configured to provide a first scan signal to the display area. The first scan drive circuit is connected to at least one drive signal line. The distance between the orthographic projection of the plurality of drive signal lines on the substrate and the orthographic projection of the active layer of the output transistor of the first scan drive circuit on the substrate is greater than zero. In other words, the orthographic projection of the plurality of drive signal lines on the substrate does not overlap with the orthographic projection of the active layer of the output transistor of the first scan drive circuit on the substrate.

[0188] In the display substrate provided in this embodiment, the driving signal lines in the border area can be arranged to avoid the active layer of the output transistor of the first scan driving circuit, which can reduce the load difference between different signals caused by the overlap of the driving signal lines and the first scan driving circuit, thereby avoiding display anomalies caused by signal coupling, and further improving display quality and competitiveness.

[0189] In some exemplary embodiments, the first scan drive circuit is located on at least one side of the display area along the first direction. The active layer of the output transistor of the first scan drive unit includes: a first sub-active layer and a second sub-active layer spaced apart along the first direction. The multiple drive signal lines may include: a first drive voltage line, the orthographic projection of the first drive voltage line on the substrate is located between the orthographic projection of the first sub-active layer and the second sub-active layer of the output transistor on the substrate. The orthographic projection of the first drive voltage line on the substrate does not overlap with the orthographic projection of the first sub-active layer on the substrate, and the orthographic projection of the first drive voltage line on the substrate does not overlap with the orthographic projection of the second sub-active layer on the substrate. The setting method of this example can ensure that the drive signal line avoids the active layer of the output transistor of the first scan drive circuit and is conducive to saving wiring space.

[0190] In some exemplary embodiments, the first scan driving unit includes two output transistors, wherein the first sub-active layers of the two output transistors are interconnected as an integrated structure, and the second sub-active layers of the two output transistors are interconnected as an integrated structure. In some examples, the orthographic projection of the integrated structure of the first sub-active layers of the two output transistors of the first scan driving unit onto the substrate may be a rectangle, and the orthographic projection of the integrated structure of the second sub-active layers of the two output transistors onto the substrate may be a rectangle.

[0191] In some exemplary embodiments, the two output transistors of the first scan drive unit are a first output transistor and a second output transistor. The first scan drive unit may further include: a first shift storage capacitor and a second shift storage capacitor, the first shift storage capacitor being connected to the first output transistor, and the second shift storage capacitor being connected to the second output transistor. The first shift storage capacitor may be located on a side of the first output transistor closer to the display area, and the second shift storage capacitor may be located on a side of the second output transistor closer to the display area. The orthographic projection of one of the multiple drive signal lines on the substrate overlaps with the orthographic projection of the first shift storage capacitor on the substrate, and overlaps with the orthographic projection of the second shift storage capacitor on the substrate. In some examples, the first drive voltage line may be connected to the active layer of the first output transistor via the eighth scan connection electrode, and the first drive voltage line may be located on a side of the eighth scan connection line away from the substrate. For example, the first drive voltage line may be located in the second source-drain metal layer, and the eighth scan connection line may be located in the first source-drain metal layer. This configuration ensures that the drive signal lines avoid the active layers of the output transistors of the first scan drive circuit.

[0192] In some exemplary embodiments, the frame area may include: a third frame area and a fourth frame area located on both sides of the display area along the first direction. The display substrate may include: a second scan drive circuit, a first reset drive circuit, a second reset drive circuit, a light-emitting drive circuit, and two first scan drive circuits. The second scan drive circuit is configured to provide a second scan signal to the display area; the first reset drive circuit is configured to provide a first reset control signal to the display area; the second reset drive circuit is configured to provide a second reset control signal to the display area; and the light-emitting drive circuit is configured to provide a light-emitting control signal to the display area. One first scan drive circuit, the second scan drive circuit, and the second reset drive circuit are located in the third frame area and are arranged in sequence in a direction away from the display area. Another first scan drive circuit, the first reset drive circuit, and the light-emitting drive circuit are located in the fourth frame area and are arranged in sequence in a direction away from the display area.

[0193] In some exemplary embodiments, the display substrate may further include: a plurality of electrostatic discharge circuits located in the border region, each electrostatic discharge circuit including a plurality of electrostatic discharge transistors. The distance between the orthographic projections of the plurality of drive signal lines on the substrate and the orthographic projections of the active layers of the electrostatic discharge transistors of the plurality of electrostatic discharge circuits on the substrate is greater than zero. In this example, the drive signal lines can be arranged away from the active layers of the electrostatic discharge transistors of the electrostatic discharge circuits, thereby reducing the load differences between different signals caused by the overlap of the drive signal lines and the electrostatic discharge circuits, thereby avoiding display anomalies caused by signal coupling, thereby improving display quality and competitiveness.

[0194] The description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0195] Figure 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 15 , display substrate 910 may be an OLED display substrate. Display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited to this.

[0196] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example" or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0197] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate comprising a display area and a frame area surrounding the display area, the display substrate comprising: substrate; a plurality of sub-pixels located in the display area and on one side of the substrate; a plurality of gate lines and a plurality of data lines, located at least in the display area, the plurality of gate lines extending along a first direction, the plurality of data lines extending along a second direction, the second direction intersecting the first direction, the plurality of gate lines and the plurality of data lines being electrically connected to the plurality of sub-pixels respectively; A plurality of multiplexing circuits are located in the frame area and connected to the plurality of data lines; each multiplexing circuit includes a plurality of multiplexing control transistors; A plurality of gate driving circuits are located in the frame area and connected to the plurality of gate lines; a plurality of drive signal lines, located in the frame area and connected to the plurality of gate drive circuits, the plurality of drive signal lines being configured to provide drive signals to the plurality of gate drive circuits; A distance between an orthographic projection of the plurality of driving signal lines on the substrate and an orthographic projection of active layers of multiplexing control transistors of the plurality of multiplexing circuits on the substrate is greater than zero.

2. The display substrate according to claim 1, wherein The frame area includes: a first frame area located on one side of the display area along the second direction; The multiplexing circuits are located in the first frame area, and the multiplexing circuits are arranged sequentially along the first direction in the first frame area.

3. The display substrate according to claim 2, wherein: The multiplexing control transistors of each multiplexing circuit are arranged in sequence along the first direction.

4. The display substrate according to claim 2, wherein: The first frame area includes: a first fan-out area and a bending area arranged in sequence along a direction away from the display area; the multiple multiplexing circuits are located in the first fan-out area; in the first fan-out area, the multiple driving signal lines are located on a side of the multiple multiplexing circuits away from the display area.

5. The display substrate according to claim 4, wherein: The first fan-out region is provided with a plurality of multiplexed data lines connected to the plurality of multiplexing circuits, one of the plurality of multiplexed data lines is connected to one of the plurality of multiplexing circuits, and the one multiplexing circuit is configured to transmit a data signal transmitted by the one multiplexed data line to at least two data lines of the plurality of data lines in a time-sharing manner; The bending region is provided with at least a plurality of driving bending lines and a plurality of data bending lines, the plurality of driving bending lines are connected to the plurality of driving signal lines, and the plurality of data bending lines are connected to the plurality of multiplexed data lines; In the bending region, the plurality of driving bending lines are located on a side of the plurality of data bending lines close to an edge of the display substrate.

6. The display substrate according to any one of claims 1 to 5, further comprising: a plurality of data transfer lines at least located in the display area; At least one data line among the plurality of data lines is connected to the multiplexing circuit via the data adapter line; The at least one data line is located on a side of the connected data transfer line close to an edge of the display area in the first direction.

7. The display substrate according to claim 1, wherein: The plurality of gate driving circuits include: at least one first scan driving circuit; the at least one first scan gate driving circuit includes a plurality of cascaded first scan driving units, each of the first scan driving units includes at least one output transistor; the at least one output transistor of the first scan driving unit is configured to provide a first scan signal to at least one gate line; A distance between an orthographic projection of the plurality of driving signal lines on the substrate and an orthographic projection of an active layer of an output transistor of the first scan driving unit on the substrate is greater than zero.

8. The display substrate according to claim 7, wherein: The at least one first scan driving circuit is located on at least one side of the display area along the first direction; The active layer of the output transistor of the first scan driving unit includes: a first sub-active layer and a second sub-active layer spaced apart along the first direction; The multiple driving signal lines include: a first driving voltage line; the orthographic projection of the first driving voltage line on the substrate is located between the orthographic projection of the first sub-active layer and the second sub-active layer of the output transistor on the substrate, the orthographic projection of the first driving voltage line on the substrate does not overlap with the orthographic projection of the first sub-active layer on the substrate, and the orthographic projection of the first driving voltage line on the substrate does not overlap with the orthographic projection of the second sub-active layer on the substrate.

9. The display substrate according to claim 1, further comprising: a plurality of electrostatic discharge circuits located in the border area, each electrostatic discharge circuit comprising a plurality of electrostatic discharge transistors; A distance between an orthographic projection of the plurality of driving signal lines on the substrate and an orthographic projection of active layers of electrostatic discharge transistors of the plurality of electrostatic discharge circuits on the substrate is greater than zero.

10. The display substrate according to claim 9, wherein: The frame area includes: a first frame area and a second frame area located on both sides of the display area along the second direction, a third frame area and a fourth frame area located on both sides of the display area along the first direction, a first corner area connecting the first frame area and the third frame area, and a second corner area connecting the first frame area and the fourth frame area; The plurality of electrostatic discharge circuits include: a plurality of first electrostatic discharge circuits located in the first corner area and the second corner area; The multiple first electrostatic release circuits are arranged in at least one row, each row includes multiple first electrostatic release circuits arranged in sequence along the first direction, and the multiple electrostatic release transistors of each first electrostatic release circuit are arranged in sequence along the first direction. The setting order of the multiple electrostatic release transistors of adjacent first electrostatic release circuits in the same row is different.

11. The display substrate according to claim 10, wherein: The frame area further includes: a third corner area connecting the second frame area and the third frame area, and a fourth corner area connecting the second frame area and the fourth frame area; The plurality of electrostatic discharge circuits further include: a plurality of second electrostatic discharge circuits located in the third corner region and the fourth corner region; A plurality of electrostatic discharge transistors of at least one of the plurality of second electrostatic discharge circuits are arranged in an array.

12. A display device comprising the display substrate according to any one of claims 1 to 11.

13. A display substrate comprising a display area and a frame area surrounding the display area, the display substrate comprising: substrate; a plurality of sub-pixels located in the display area and on one side of the substrate; At least one first scan driving circuit is located in the frame area and on one side of the substrate, a first scan driving circuit comprising a plurality of cascaded first scan driving units, each of which comprises at least one output transistor, wherein the at least one first scan driving circuit is configured to provide a first scan signal to a plurality of sub-pixels in the display area; a plurality of driving signal lines located in the frame area, wherein the at least one first scanning driving circuit is connected to at least one driving signal line among the plurality of driving signal lines; A distance between an orthographic projection of the plurality of driving signal lines on the substrate and an orthographic projection of an active layer of an output transistor of the at least one first scan driving circuit on the substrate is greater than zero.

14. The display substrate according to claim 13, wherein: The at least one first scan driving circuit is located on at least one side of the display area along a first direction; The active layer of the output transistor of the first scan driving unit includes: a first sub-active layer and a second sub-active layer spaced apart along the first direction; The multiple driving signal lines include: a first driving voltage line, the orthographic projection of the first driving voltage line on the substrate is located between the orthographic projection of the first sub-active layer and the second sub-active layer of the output transistor on the substrate, the orthographic projection of the first driving voltage line on the substrate does not overlap with the orthographic projection of the first sub-active layer on the substrate, and the orthographic projection of the first driving voltage line on the substrate does not overlap with the orthographic projection of the second sub-active layer on the substrate.

15. The display substrate according to claim 14, wherein: The first scan driving unit includes two output transistors, the first sub-active layers of the two output transistors are connected to each other as an integral structure, and the second sub-active layers of the two output transistors are connected to each other as an integral structure.

16. The display substrate according to claim 15, wherein: The integrated structure of the first sub-active layers of the two output transistors of the first scan driving unit is a rectangular shape when projected onto the substrate, and the integrated structure of the second sub-active layers of the two output transistors is a rectangular shape when projected onto the substrate.

17. The display substrate according to claim 15, wherein: The two output transistors of the first scan driving unit are a first output transistor and a second output transistor. The first scan driving unit further includes: a first shift storage capacitor and a second shift storage capacitor, the first shift storage capacitor being connected to the first output transistor, and the second shift storage capacitor being connected to the second output transistor; the first shift storage capacitor being located on a side of the first output transistor close to the display area, and the second shift storage capacitor being located on a side of the second output transistor close to the display area; An orthographic projection of one of the plurality of driving signal lines on the substrate overlaps with an orthographic projection portion of the first shift storage capacitor on the substrate, and overlaps with an orthographic projection portion of the second shift storage capacitor on the substrate.

18. The display substrate according to claim 17, wherein: The first driving voltage line is connected to the active layer of the first output transistor through the eighth scan connection electrode. The first driving voltage line is located on a side of the eighth scan connection line away from the substrate.

19. The display substrate according to claim 13, wherein: The frame area includes: a third frame area and a fourth frame area located on both sides of the display area along the first direction; The display substrate includes: a second scan driving circuit, a first reset driving circuit, a second reset driving circuit, a light emitting driving circuit and two first scan driving circuits; The second scan driving circuit is configured to provide a second scan signal to the plurality of sub-pixels in the display area; the first reset driving circuit is configured to provide a first reset control signal to the plurality of sub-pixels in the display area; the second reset driving circuit is configured to provide a second reset control signal to the plurality of sub-pixels in the display area; and the light emitting driving circuit is configured to provide a light emitting control signal to the plurality of sub-pixels in the display area; A first scan driving circuit, the second scan driving circuit and the second reset driving circuit are located in the third frame area and are sequentially arranged in a direction away from the display area; Another first scan driving circuit, the first reset driving circuit and the light emitting driving circuit are located in the fourth frame area and are sequentially arranged in a direction away from the display area.

20. The display substrate according to claim 13, further comprising: a plurality of electrostatic discharge circuits located in the border area, each electrostatic discharge circuit comprising a plurality of electrostatic discharge transistors; A distance between an orthographic projection of the plurality of driving signal lines on the substrate and an orthographic projection of active layers of electrostatic discharge transistors of the plurality of electrostatic discharge circuits on the substrate is greater than zero.

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