Solenoid valve control circuit based on detection factors and self-checking method

Abstract

The invention discloses an electromagnetic valve control circuit based on a detection factor and a self-checking method. The circuit architecture comprises a DSP (Digital Signal Processor), a level conversion circuit, a magnetic isolation circuit, an AD (Analog to Digital) acquisition and driving circuit and a self-checking circuit. The driving and self-checking circuit integrates electromagnetic valve driving and self-checking functions, electromagnetic valve driving voltage is provided by a power supply Vcc, a PMOS (P-channel Metal Oxide Semiconductor) power device, a control switch transistor and a bleeder circuit are integrated, and on and off behavior monitoring in a control signal state is realized through a voltage division network and a self-checking branch. The circuit can carry out self-inspection aiming at different control signal output states, the self-inspection process can be not influenced by the change of a driving power supply through a self-inspection method based on a detection factor, the self-adaptive capacity of the circuit is improved, the electromagnetic valve is periodically self-inspected through the circuit, instant alarm and positioning of faults of the electromagnetic valve can be realized, and the reliability of the electromagnetic valve is improved. Operation interruption and safety risks possibly caused by electromagnetic valve faults of an aviation system are effectively avoided.

Description

Technical Field

[0001] This invention relates to the fields of power electronics and automatic control technology, specifically to solenoid valve control and self-testing technology. In particular, it relates to a solenoid valve control circuit and self-testing method based on detection factors, which is used to realize real-time status monitoring and fault determination of the solenoid valve control channel, thereby improving system integration and operational safety. Background Technology

[0002] With the rapid development of all-electric control systems for aircraft, solenoid valves are widely used in aviation systems such as fuel, hydraulics, pneumatics, and cooling to achieve functions such as multi-channel switching, on / off control, and status maintenance. The normal operation of the solenoid valve control channels is directly related to the reliable operation of the flight, therefore, the requirements for reliable control and fault diagnosis capabilities of solenoid valves are becoming increasingly stringent.

[0003] In existing technologies, a typical solenoid valve control circuit mainly consists of a control unit, a drive module, and a protection circuit. The logic level signal output by the controller is converted and amplified to drive a power device, thereby applying a control voltage to the solenoid valve coil and controlling the on / off state of the solenoid valve. In practical applications, abnormal states of the solenoid valve coil can lead to execution failures, resulting in system malfunction and, in severe cases, even safety accidents. Therefore, introducing a self-checking function into the solenoid valve control system to improve fault predictability and safety redundancy has become a core concern in engineering applications.

[0004] However, current mainstream solenoid valve control circuits have certain problems. First, the self-test function in the control circuit is mostly designed separately, with the drive circuit and self-test circuit designed independently, resulting in a complex circuit structure and low system integration. Especially for the need for multi-channel control circuits, this not only occupies a large amount of board space but also increases design costs. Second, the detection conditions are limited, and self-test can only be completed when the control circuit switch is in a single on or off state, making it difficult to achieve continuous online monitoring. This results in a limited detection window and an inability to capture sudden or intermittent faults in real time. Third, the self-test circuit has low compatibility. Most detection circuits are designed for a specific type of load. If a different specification of solenoid valve or a change in load characteristics is required, the circuit needs to be redesigned, increasing time costs. Fourth, the self-test circuit has poor adaptability. The power supply voltage of avionics systems may fluctuate to a certain extent due to factors such as power load changes, temperature fluctuations, and electrical interference. If the voltage applied to the load fluctuates, the detection signal will change accordingly, which may lead to misjudgment and potentially cause false alarms or missed detections.

[0005] For example, Chinese patent CN101956857A discloses a control and protection self-test circuit for an automotive solenoid valve, which uses a high / low-side control terminal in conjunction with a feedback terminal to detect the solenoid valve status. However, its self-test signal depends on the absolute value of the voltage, making it susceptible to power fluctuations, and the circuit structure is complex with low integration. CN102777665A discloses a solenoid valve connection self-test method, which determines the solenoid valve connection status by sampling the voltage difference. However, its detection dimension is singular, limited to physical connection detection, and cannot distinguish between fault types such as short circuits / open circuits, and it does not solve the detection error problem caused by power fluctuations. None of these solutions achieve the high reliability, full-state detection, and power adaptive capability required for aviation solenoid valve control.

[0006] In summary, existing solenoid valve control circuits still have many shortcomings in terms of self-test integration, self-test coverage, criterion adaptability, and power supply fluctuation robustness, making it difficult to meet the technical requirements of modern avionics systems for high reliability, high integration, and intelligent fault diagnosis. Therefore, it is necessary to develop a solenoid valve control circuit status self-testing technology with high integration, unrestricted testing conditions, strong compatibility, and good self-adaptability to solve the above problems. Summary of the Invention

[0007] (1) Purpose of the invention

[0008] To address the aforementioned shortcomings and deficiencies of existing technologies, this invention proposes a solenoid valve control circuit and self-testing method that integrates drive control and self-testing. By introducing a self-testing mechanism based on detection factors, drive control and fault detection functions are integrated into a unified circuit architecture. A normalized judgment factor, independent of power supply voltage, is constructed using voltage acquisition results from the solenoid valve control channel. Combined with characteristic interval criteria under high and low control signal states, real-time monitoring and fault identification of the solenoid valve's operating status are achieved. This invention not only enables self-testing throughout the entire timeframe, regardless of whether the control signal is high or low, improving the system's online detection capability, but also effectively avoids the problem of uncertain detection thresholds caused by changes in drive power supply. It solves problems such as low integration, limited detection conditions, low compatibility of the self-testing circuit, and poor adaptability, thereby improving the reliability of the control path and reducing design costs.

[0009] (II) Technical Solution

[0010] To achieve the objective of this invention and solve its technical problems, the present invention adopts the following technical solution:

[0011] The first objective of this invention is to provide a solenoid valve control circuit based on a detection factor, used for controlling and self-testing the on / off state of the solenoid valve, including a drive and self-test circuit, an AD acquisition chip, a DSP processor chip, a level conversion chip, and a magnetic isolation chip, wherein:

[0012] The drive and self-test circuit is used to perform control drive and status self-test of the solenoid valve. Its control signal input terminal is connected to the magnetic isolation chip, its power input terminal is connected to the drive power supply, its control output terminal is connected to the solenoid valve, and its self-test signal output terminal is connected to the AD acquisition chip.

[0013] The AD acquisition chip has a first input terminal connected to the self-test signal output node of the driving and self-test circuit, a second input terminal connected to the driving power supply, and an output terminal connected to the DSP processor chip. It is used to acquire self-test signals and power signals and transmit them to the DSP processor chip.

[0014] The DSP processor chip has its input end connected to the AD acquisition chip and its output end connected to the level conversion chip. It is configured to: generate control signals for opening or closing the solenoid valve; receive and process the self-test signal and power signal transmitted by the AD acquisition chip; construct a normalized detection factor JugFactor that is not affected by power voltage fluctuations by calculating the ratio between the two signal voltages; and perform status judgment and fault identification of the solenoid valve control path based on this factor.

[0015] The level conversion chip has its input end connected to the DSP processor chip and its output end connected to the magnetic isolation chip. It is used to convert the level of the received control signal and enhance the signal driving capability.

[0016] The magnetic isolation chip has its input end connected to the level conversion chip and its output end connected to the drive and self-test circuit. It is used to establish an electrical isolation barrier between the low-voltage control domain where the DSP processor chip is located and the high-voltage power domain where the drive and self-test circuit is located, to isolate the internal control signal from the external solenoid valve drive signal, and to transmit the isolated control signal to the drive and self-test circuit.

[0017] The second objective of this invention is to provide a self-testing method for a solenoid valve control circuit based on a detection factor. The solenoid valve control circuit based on this invention includes at least the following steps:

[0018] SS1. Control Signal Generation and Transmission:

[0019] The DSP processor chip N1 generates control signals for opening or closing the solenoid valve. After level conversion and drive enhancement by the level conversion chip N2, electrical isolation is achieved by the magnetic isolation chip N3 and the signals are transmitted to the drive and self-test circuit D&B.

[0020] SS2. Solenoid Valve Actuation and Signal Acquisition:

[0021] The drive and self - check circuit D&B drives the PMOS power device M1 to perform the on - or off - operation of the solenoid valve according to the control signal. The AD acquisition chip N4 synchronously acquires the self - check signal V_DOBIT and the drive power supply voltage Vcc and transmits them to the DSP processor chip N1;

[0022] SS3. Normalized detection factor calculation:

[0023] The DSP processing chip N1 calculates the normalized detection factor JugFactor = V_DOBIT / Vcc based on the received V_DOBIT and Vcc, which is used to eliminate the interference of power supply fluctuations on state recognition;

[0024] SS4. State recognition and threshold judgment:

[0025] Judge the logic level state of the control signal. If the control signal is high level, the system should be in the on - state, the detection factor is H_JugFactor, and compare it with the preset reference threshold HighFactor; if the control signal is low level, the system should be in the off - state, the detection factor is L_JugFactor, and compare it with the preset reference threshold LowFactor;

[0026] SS5. Fault trend counter update:

[0027] Dynamically update the state counter according to the criterion result. If H_JugFactor < HighFactor, the high - level anomaly counter H_Numb increments, otherwise it decrements; if L_JugFactor > LowFactor, the low - level anomaly counter L_Numb increments, otherwise it decrements;

[0028] SS6. Fault flag determination:

[0029] Compare each counter value with the preset threshold Lim_Numb and execute the following logic:

[0030] If H_Numb > Lim_Numb, limit H_Numb to Lim_Numb and set the high - level fault flag FlagFail_High = 1. If H_Numb ≤ 1, set H_Numb = 1 and clear the high - level fault flag bit FlagFail_High = 0;

[0031] If L_Numb > Lim_Numb, limit L_Numb to Lim_Numb and set the low - level fault flag FlagFail_Low = 1. If L_Numb ≤ 1, set L_Numb = 1 and clear the low - level fault flag bit FlagFail_Low = 0;

[0032] SS7. Fault Status Output:

[0033] Based on the logical OR operation result of FlagFail_High and FlagFail_Low, the final fault flag FlagFail is output. If the flag is 1, it indicates that there is a fault in the solenoid valve control channel; otherwise, it is judged as normal. This realizes the fault detection and diagnosis of the solenoid valve control channel under different working conditions.

[0034] (3) Technical effects

[0035] Compared with the prior art, the solenoid valve control circuit and self-testing method based on detection factors of the present invention have the following beneficial and significant technical effects:

[0036] 1) This invention integrates the drive control circuit and the self-test circuit into one, realizing the reuse of drive and self-test functions, improving the integration of this part of the circuit and the compactness of the system, reducing external circuit dependence and wiring complexity, and facilitating modular deployment in engineering applications.

[0037] 2) This invention adopts a self-testing method based on detection factors. It uses the normalized detection factors as self-testing criteria and combines the ratio analysis of the power supply voltage Vcc and the self-testing sampling voltage V_DOBIT to effectively eliminate the interference of power supply voltage fluctuations on the accuracy of self-testing. At the same time, it can adjust the self-testing criteria according to different load characteristics, which improves the adaptability of the detection circuit.

[0038] 3) This invention can perform self-testing on the channel when the control signal is high or low, and adaptively identify various fault modes such as short circuit, open circuit, breakdown and failure. Therefore, it can monitor the control channel at all times, improving the reliability of the control system. Attached Figure Description

[0039] Figure 1 This is a block diagram of a solenoid valve control circuit based on a detection factor, provided in an embodiment of the present invention.

[0040] Figure 2 This is a flowchart of the solenoid valve self-test provided in an embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] DSP processor chip N1, level conversion chip N2, magnetic isolation chip N3, AD acquisition chip N4, drive and self-test circuit D&B, PMOS power device M1, control switch transistor Q1, bleeder diode D1, and resistors R1 to R8. Detailed Implementation

[0043] This invention aims to provide a solenoid valve control circuit and self-testing method integrating drive control and self-testing, used for controlling and self-testing the on / off state of a solenoid valve. To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be described in more detail below with reference to the accompanying drawings. The described embodiments are some, but not all, embodiments of this invention, and are exemplary, intended to explain the invention, and should not be construed as limiting the invention.

[0044] Example 1: Control Circuit

[0045] Figure 1 This is a connection block diagram of a solenoid valve control circuit based on a detection factor, provided for an embodiment of the present invention. Figure 1 As shown, the solenoid valve control circuit mainly comprises: a DSP processor chip N1, a level conversion chip N2, a magnetic isolation chip N3, an AD acquisition chip N4, and a drive and self-test circuit D&B. The DSP processor chip N1 is connected to both the level conversion chip N2 and the AD acquisition chip N4, and is used to process the solenoid valve control circuit's self-test signal and issue the solenoid valve control signal; the level conversion chip N2 is used for control signal level conversion and enhancing signal driving capability; the magnetic isolation chip N3 is used to isolate internal control signals from external solenoid valve drive signals; the AD acquisition chip N4 is used to acquire the solenoid valve control circuit's self-test signal and the power supply Vcc signal; and the drive and self-test circuit D&B is used to execute the solenoid valve's control drive and status self-test.

[0046] Preferably, the DSP processor chip N1 can be SM320F2812PGFMEP. The level conversion chip N2 can be CLVC16T245MDGGEP. The magnetic isolation chip N3 can be ISO7760DW. The AD acquisition chip N4 can be TLV2556MPWREP. The Vcc power supply is preferably set to 16-40VDC. In the drive and self-test circuit D&B, R6, R7, and Q1 form a control signal switching circuit. By changing the voltage division value between R1 and R2, the conduction and turn-off of PMOS transistor M1 are controlled. R3 and D1 form the discharge path of PMOS transistor, ensuring reliable turn-off of PMOS transistor.

[0047] In this embodiment of the invention, the entire solenoid valve control circuit preferably adopts a hierarchical architecture design. The low-voltage control domain includes a DSP processor chip, an AD acquisition chip, and a level conversion chip, which are responsible for signal processing, algorithm operation, and logic control. The high-voltage power domain includes the output side of the magnetic isolation chip, the drive and self-test circuit, and the solenoid valve load. The operating voltage is the aviation standard voltage, which is responsible for power drive and load control. The two domains are electrically isolated from each other through the magnetic isolation chip.

[0048] More specifically, such as Figure 1 As shown, the drive and self-test circuit D&B includes a PMOS power device M1, a control switching transistor Q1, a bleeder diode D1, and several resistors R1 to R8, forming a composite circuit structure for solenoid valve drive control and self-testing, wherein:

[0049] The PMOS power device M1 includes a source, a drain, and a gate. The source is connected to the drive power supply Vcc, the drain outputs a control voltage V_DO to the solenoid valve, and the gate potential is used to control the on and off states of the PMOS power device M1. Furthermore, a voltage divider network consisting of resistors R1 and R2 connected in series is connected between the source and the collector of the control switching transistor Q1. The gate is connected to the voltage divider node between resistors R1 and R2 via a discharge path formed by a discharge diode D1 and a resistor R3 connected in parallel, so that the gate potential is controlled by the on and off states of the control switching transistor Q1.

[0050] The control switch transistor Q1 includes a base, a collector, and an emitter. The base is connected to the output of the magnetic isolation chip N3 through a current-limiting resistor R6 to receive the control signal. The base is also grounded through a pull-down resistor R7 to suppress leakage conduction when the control signal is removed or left floating. The emitter is directly grounded, and the collector is connected to the lower node of the resistor R2. The resistors R6 and R7, together with the control switch transistor Q1, constitute a control signal switching circuit, which dynamically adjusts the gate potential of the PMOS power device M1 in response to the control signal.

[0051] Resistor R4 is connected between the source and drain of PMOS power device M1. When M1 is turned off, it provides a weak pull-up path through the solenoid valve load to maintain the high level of V_DO for the drive power supply Vcc. It also provides a self-test current loop from the drive power supply Vcc to ground. Resistors R5 and R8 are connected in series between the drain and ground to form a voltage divider detection network. A self-test signal V_DOBIT is led out from the voltage divider node between resistors R5 and R8 to reflect the real-time status of the solenoid valve control channel.

[0052] Furthermore, in the drive and self-test circuit D&B of the present invention, when the control signal is high, the base current of the control switch transistor Q1 flows in through the resistor R6, and overcomes the pull-down effect of the resistor R7 to turn on the control switch transistor Q1, the collector potential drops to near ground potential, the gate potential of the PMOS power device M1 is pulled low and turns on to output a high level; when the control signal is low or in the off state, the base potential is pulled to ground potential by the resistor R7, the control switch transistor Q1 is turned off, the gate potential of the PMOS power device M1 is pulled up by the resistor R1 to near the source potential, and at the same time, the discharge branch ensures that the PMOS power device M1 is reliably turned off.

[0053] Furthermore, when the control switch transistor Q1 is turned on, the gate potential is pulled down to near ground potential through resistor R2, causing the PMOS power device M1 to turn on; when the control switch transistor Q1 is turned off, the gate potential is pulled up to near source potential through resistor R1, and at the same time, the discharge path formed by diode D1 and resistor R3 ensures reliable release of gate charge, so that the PMOS power device M1 is reliably turned off, thereby realizing the control of the turn-on and turn-off of the PMOS power device M1.

[0054] In the drive and self-test circuit (D&B) of this invention, the discharge path formed by the parallel connection of the discharge diode D1 and the resistor R3 has a fast turn-off function. When the control switching transistor Q1 switches from on to off, the stored charge at the gate of the PMOS power device M1 is quickly released to the voltage divider node through this discharge path. Diode D1 provides a low-impedance, fast discharge path, and resistor R3 limits the discharge current and prevents overcurrent surges. This design significantly shortens the turn-off time of the PMOS power device M1, improves the switching frequency response capability, and avoids the risk of device mis-turn-on caused by residual gate charge.

[0055] In the drive and self-test circuit D&B of this invention, the voltage divider detection network composed of resistors R5 and R8 is precisely designed to match the input characteristics of the AD acquisition chip N4. The resistance ratio of resistors R5 and R8 ensures that the self-test signal V_DOBIT can generate a voltage change range that the AD acquisition chip can recognize under various solenoid valve states. At the same time, the voltage divider network has high input impedance characteristics, minimizing the impact on the main drive circuit. Resistors R5 and R8 also provide filtering for transient interference, ensuring the stability and reliability of the self-test signal, and providing a high-quality analog signal source for subsequent digital processing.

[0056] In the drive and self-test circuit D&B of this invention, the magnetic isolation chip N3 uses opto-isolation or magnetic isolation technology to establish an electrical isolation barrier between the low-voltage control domain where the DSP processor chip is located and the high-voltage power domain where the drive and self-test circuit is located. This effectively blocks electrical crosstalk and fault propagation from the high-voltage power domain to the low-voltage control domain, while maintaining the complete transmission of control signals. This design protects the digital control circuit from high-voltage impacts and also meets the safety isolation requirements of avionics equipment, improving the reliability and safety of the system.

[0057] In the drive and self-test circuit D&B of this invention, the level conversion chip N2 has signal conditioning and drive enhancement functions, converting the logic level output by the DSP processor chip into the drive level required by the magnetic isolation chip, and enhancing the driving capability of the signal to ensure that it can still reliably drive the subsequent circuit after passing through the isolation barrier. The chip also has Schmitt trigger characteristics, providing good noise tolerance and anti-interference capability, preventing false triggering caused by noise during signal transmission, and ensuring the integrity and timing accuracy of the control signal during transmission.

[0058] In the drive and self-test circuit (D&B) of this invention, resistor R1 serves as a gate pull-up resistor. The selection of its resistance value needs to balance the turn-off reliability and switching speed of the PMOS power device M1. If the resistance value is too small, it will increase the drive burden of the control switching transistor Q1 and increase the static power consumption. If the resistance value is too large, it may lead to incomplete turn-off or slow turn-off speed. Through optimized design, R1 minimizes power consumption while ensuring reliable turn-off of M1. At the same time, it forms a reasonable voltage division ratio with resistor R2 to provide a stable bias voltage for the gate, ensuring reliable operation of the PMOS power device under various operating conditions.

[0059] In the drive and self-test circuit D&B of this invention, the base bias network of the control switching transistor Q1 is composed of a current-limiting resistor R6 and a pull-down resistor R7. Resistor R6 limits the base current within a safe range and protects the transistor from overcurrent damage. Its resistance value is optimized according to the output capability of the magnetic isolation chip and the current gain of the transistor. Resistor R7 provides a reliable pull-down bias to ensure that the base potential is firmly pulled to ground potential when the control signal is missing or floating, preventing false turn-on caused by external interference signals. This bias network design takes into account multiple requirements of switching speed, anti-interference capability and power consumption control.

[0060] In the drive and self-test circuit D&B of this invention, resistor R4 plays a key current limiting role in the solenoid valve's self-test function. When the PMOS power device M1 is turned off, R4 is connected in series with the solenoid valve coil to form a self-test current loop. The resistance value of R4 is designed to ensure that the self-test current is sufficient to generate a detectable voltage signal, while not triggering the mechanical action of the solenoid valve. This resistor also provides a weak pull-up function for the solenoid valve, maintaining the high level of the output terminal V_DO when M1 is turned off, preventing the output from floating. The selection of its resistance value needs to comprehensively consider multiple factors such as self-test sensitivity, power consumption limitation, and the solenoid valve's action threshold.

[0061] In this embodiment of the invention, when the control signal is high, the PMOS power device M1 is turned on, and the solenoid valve control output voltage V_DO is approximately equal to the drive power supply voltage Vcc, satisfying V_DO≈Vcc, thus achieving normal energization control of the solenoid valve; when the control signal is low or in the off state, the PMOS power device M1 is turned off, the PMOS power device is turned off, and resistor R4 provides a weak pull-up path from Vcc to V_DO, while the solenoid valve coil resistance R valve R5 and R8 form a voltage divider path, and the solenoid valve ultimately controls the output voltage. in R represents the resistance of the solenoid valve coil. valve The equivalent parallel resistance formed with the pull-down resistor network R5+R8.

[0062] The DSP processing chip N1 acquires the self-test signal of the solenoid valve control circuit and the power supply Vcc signal through the AD acquisition chip N4, and calculates the detection factor JugFactor, whose calculation formula is: The self-test signal of the solenoid valve control circuit satisfies When the control signal is high, the value of the detection factor H_JugFactor under the high level satisfies The value depends only on the values ​​of R5 and R8; when the control signal is low, the value of the detection factor L_JugFactor under low level satisfies Its value depends only on R4, R5, R8 and the resistance R of the solenoid valve coil. valve related.

[0063] Furthermore, the DSP processor chip N1 selects a self-test criterion factor and sets a corresponding detection factor fault range as the self-test criterion for the solenoid valve control channel status based on the control signal status and the typical fault modes in the corresponding status:

[0064] If the control signal is high, the PMOS power device M1 should be in the on state. The self-test fault judgment factor HighFactor is set to a reference threshold between the normal working state and the short circuit state when it is in the normal fault-free state, satisfying H_JugFactor,short≤HighFactor≤H_JugFactor,normal, where H_JugFactor,short represents the lower limit of the detection factor under the short circuit of the solenoid valve coil, and H_JugFactor,normal represents the detection factor value under the normal on state.

[0065] If the control signal is low, the PMOS power device M1 should be in the off state. The self-test fault factor LowFactor is set to a reference threshold between the normal off state and the leakage conduction state when the fault-free state is normal. It should satisfy L_JugFactor,normal≤LowFactor≤L_JugFactor,open, where L_JugFactor,normal represents the lower limit of the detection factor in the normal off state and L_JugFactor,open represents the upper limit of the detection factor in the solenoid valve open or PMOS power device M1 breakdown state.

[0066] When the DSP processor chip N1 performs a self-test on the solenoid valve control channel based on JugFactor data, it includes:

[0067] When the control signal is high, if H_JugFactor < HighFactor for n consecutive times, it is judged as a failure to conduct and the flag bit FlagFail_High = 1; if H_JugFactor ≥ HighFactor for n consecutive times, it is considered to be normal conduction and the flag bit FlagFail_High = 0.

[0068] When the control signal is low, if L_JugFactor > LowFactor for n consecutive times, it is judged as a shutdown failure or leakage conduction abnormality, and the flag bit FlagFail_Low = 1; if L_JugFactor ≤ LowFactor for n consecutive times, it is considered that the shutdown state is normal, and the flag bit FlagFail_Low = 0.

[0069] When FlagFail_High = 1 or FlagFail_Low = 1, it is determined that there is a fault in the current solenoid valve control path. If both are 0, the control circuit is considered to be working normally.

[0070] In this embodiment 1, by constructing an integrated PMOS power device, control switching transistor, and drive and self-test circuit, and combining it with an adaptive fault diagnosis algorithm based on detection factors, online monitoring of the solenoid valve drive status and accurate fault identification are achieved. It features a simple structure, high reliability, and strong applicability.

[0071] Example 2: Self-testing method

[0072] Based on Embodiment 1 above, Embodiment 2 further elaborates on a self-testing method for solenoid valve control circuits based on detection factors, aiming to achieve online monitoring and fault determination of the solenoid valve's driving state, such as... Figure 2 As shown, the method mainly includes the following steps when implemented:

[0073] SS1. Control Signal Generation and Transmission:

[0074] The DSP processor chip N1 generates control signals for opening or closing the solenoid valve. After level conversion and drive enhancement by the level conversion chip N2, the signals are electrically isolated by the magnetic isolation chip N3 and transmitted to the drive and self-test circuit D&B to achieve stable and safe transmission of control signals.

[0075] SS2. Solenoid Valve Actuation and Signal Acquisition:

[0076] After receiving the isolated control signal, the drive and self-test circuit D&B drives the PMOS power device M1 to perform the solenoid valve's on or off operation according to the control signal. The AD acquisition chip N4 synchronously acquires the self-test signal V_DOBIT and the drive power supply voltage Vcc and transmits them to the DSP processor chip N1, providing a data basis for subsequent status identification and fault diagnosis.

[0077] SS3. Normalized Detection Factor Calculation:

[0078] The DSP processing chip N1 calculates the normalized detection factor JugFactor = V_DOBIT / Vcc based on the received V_DOBIT and Vcc, which is used to eliminate the interference of power supply fluctuations on state recognition and provide a basic quantization index for subsequent state judgment;

[0079] SS4. State Recognition and Threshold Judgment:

[0080] Judge the logic level state of the control signal. If the control signal is high level, the system should be in the on state, and the detection factor is H_JugFactor, which is compared with the preset reference threshold HighFactor; if the control signal is low level, the system should be in the off state, and the detection factor is L_JugFactor, which is compared with the preset reference threshold LowFactor;

[0081] SS5. Fault Trend Counter Update:

[0082] Dynamically update the state counter according to the criterion result. If H_JugFactor < HighFactor, the high-level anomaly counter H_Numb increments, otherwise it decrements; if L_JugFactor > LowFactor, the low-level anomaly counter L_Numb increments, otherwise it decrements;

[0083] SS6. Fault Flag Determination:

[0084] Compare each counter value with the preset threshold Lim_Numb and execute the following logic:

[0085] If H_Numb > Lim_Numb, limit H_Numb to Lim_Numb and set the high-level fault flag FlagFail_High = 1. If H_Numb ≤ 1, set H_Numb = 1 and clear the high-level fault flag bit FlagFail_High = 0;

[0086] If L_Numb > Lim_Numb, limit L_Numb to Lim_Numb and set the low-level fault flag FlagFail_Low = 1. If L_Numb ≤ 1, set L_Numb = 1 and clear the low-level fault flag bit FlagFail_Low = 0;

[0087] SS7. Fault State Output:

[0088] Based on the logical OR operation result of FlagFail_High and FlagFail_Low, the final fault flag FlagFail is output. If the flag is 1, it indicates that there is a fault in the solenoid valve control channel; otherwise, it is judged as normal. This realizes the fault detection and diagnosis of the solenoid valve control channel under different working conditions.

[0089] Through the above steps, this embodiment 2 can effectively utilize the hardware circuit structure described in embodiment 1 to realize real-time status monitoring and fault diagnosis of the solenoid valve control path, providing a strong guarantee for improving the reliability and safety of the solenoid valve control system.

[0090] The objectives of this invention have been fully and effectively achieved through the above embodiments. Those skilled in the art will understand that this invention includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments described above. Although the invention has been described with reference to what is currently considered the most practical and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments, and any modifications that do not depart from the functional and structural principles of the invention will be included within the scope of the claims.

Claims

1. A solenoid valve control circuit based on a detection factor, characterized in that, At least including: A drive and self-test circuit is used to control and drive the solenoid valve and perform status self-test. Its control signal input terminal is connected to the magnetic isolation chip, its power input terminal is connected to the drive power supply, its control output terminal is connected to the solenoid valve, and its self-test signal output terminal is connected to the AD acquisition chip. An AD acquisition chip has its first input terminal connected to the self-test signal output node of the driver and self-test circuit, its second input terminal connected to the driver power supply, and its output terminal connected to the DSP processor chip. It is used to acquire self-test signals and power signals and transmit them to the DSP processor chip. A DSP processor chip, whose input is connected to an AD acquisition chip and whose output is connected to a level conversion chip, is configured to: generate control signals for opening or closing the solenoid valve; receive and process the self-test signal and power signal transmitted by the AD acquisition chip; construct a normalized detection factor that is not affected by power supply voltage fluctuations by calculating the ratio between the two signal voltages; and perform status judgment and fault identification of the solenoid valve control path based on this factor. A level conversion chip, whose input is connected to a DSP processor chip and whose output is connected to a magnetic isolation chip, is used to convert the level of received control signals and enhance the signal driving capability. A magnetic isolation chip, whose input is connected to a level conversion chip and whose output is connected to a drive and self-test circuit, is used to establish an electrical isolation barrier between the low-voltage control domain where the DSP processor chip is located and the high-voltage power domain where the drive and self-test circuit is located, to isolate the internal control signal from the external solenoid valve drive signal, and to transmit the isolated control signal to the drive and self-test circuit.

2. The control circuit according to claim 1, characterized in that, The entire control circuit adopts a hierarchical architecture design. The low-voltage control domain includes a DSP processor chip, an AD acquisition chip, and a level conversion chip, with an operating voltage of 3.3V or 5V. It is responsible for signal processing, algorithm calculation, and logic control. The high-voltage power domain includes the output side of the magnetic isolation chip, the drive and self-test circuit, and the solenoid valve load. It operates at the aviation standard voltage and is responsible for power drive and load control. The two domains are electrically isolated from each other through the magnetic isolation chip.

3. The control circuit according to claim 1, characterized in that, The drive and self-test circuit includes a PMOS power device, a control switching transistor, a bleeder diode, and several resistors R1 to R8, forming a composite circuit structure for solenoid valve drive control and self-testing, wherein: The PMOS power device includes a source, a drain, and a gate. The source is connected to the driving power supply, the drain outputs a control voltage to the solenoid valve, and the gate potential is used to control the on and off states of the PMOS power device. Furthermore, a voltage divider network consisting of resistors R1 and R2 connected in series is connected between the source and the collector of the control switching transistor. The gate is connected to the voltage divider node between resistors R1 and R2 via a discharge path formed by a discharge diode and a resistor R3 connected in parallel, so that the gate potential is controlled by the on and off states of the control switching transistor. The control switch transistor includes a base, a collector, and an emitter. The base is connected to the output of the magnetic isolation chip through a current-limiting resistor R6 to receive the control signal. The base is also grounded through a pull-down resistor R7 to suppress leakage conduction when the control signal is removed or left floating. The emitter is directly grounded, and the collector is connected to the lower node of resistor R2. Resistors R6 and R7 together with the control switch transistor constitute a control signal switching circuit, which dynamically adjusts the gate potential of the PMOS power device in response to the control signal. The resistor R4 is connected between the source and drain of the PMOS power device, and the resistors R5 and R8 are connected in series between the drain and ground to form a voltage divider detection network. A self-test signal is led out at the voltage divider node between the resistors R5 and R8 to reflect the real-time status of the solenoid valve control channel.

4. The control circuit according to claim 3, characterized in that, When the control signal is high, the base current of the control switching transistor flows in through resistor R6, overcoming the pull-down effect of resistor R7 to turn on the control switching transistor. The collector potential drops to near ground potential, and the gate potential of the PMOS power device is pulled low and turns on to output a high level. When the control signal is low or in the off state, the base potential is pulled to ground potential by resistor R7, the control switching transistor is turned off, and the gate potential of the PMOS power device is pulled up by resistor R1 to near source potential. At the same time, the discharge branch ensures that the PMOS power device is reliably turned off.

5. The control circuit according to claim 4, characterized in that, When the control switch transistor is turned on, the gate potential is pulled down to near ground potential through resistor R2, turning on the PMOS power device. When the control switch transistor is turned off, the gate potential is pulled up to near source potential through resistor R1. At the same time, the discharge path formed by diode and resistor R3 ensures reliable release of gate charge, turning off the PMOS power device reliably, thus realizing the control of the PMOS power device's turn-on and turn-off.

6. The control circuit according to any one of claims 3 to 5, characterized in that, When the control signal is high, the PMOS power device is turned on, and the solenoid valve control output voltage V_DO is approximately equal to the drive power supply voltage Vcc, satisfying V_DO≈Vcc, thus achieving normal energization control of the solenoid valve. When the control signal is low or in an off state, the PMOS power device is turned off, and resistor R4 provides a weak pull-up path from Vcc to V_DO. Simultaneously, the solenoid valve coil resistance R... valve R5 and R8 form a voltage divider path, and the solenoid valve ultimately controls the output voltage. in R represents the resistance of the solenoid valve coil. valve The equivalent parallel resistance formed with the pull-down resistor network R5+R8.

7. The control circuit according to claim 6, characterized in that, The DSP processing chip calculates the normalized detection factor based on the self-test signal and the drive power signal. Among them: the self-test signal satisfies When the control signal is high, the value of the detection factor H_JugFactor under the high level satisfies When the control signal is low, the value of the detection factor L_JugFactor under the low level satisfies 8. The control circuit according to claim 7, characterized in that, The DSP processor chip N1 selects a self-test criterion factor and sets a corresponding detection factor fault range as the self-test criterion for the solenoid valve control channel status based on the control signal status and the typical fault modes under the corresponding status: If the control signal is high, the PMOS power device M1 should be in the on state. The self-test fault judgment factor HighFactor is set to a reference threshold between the normal working state and the short circuit state when it is in the normal fault-free state, satisfying H_JugFactor,short≤HighFactor≤H_JugFactor,normal, where H_JugFactor,short represents the lower limit of the detection factor under the short circuit of the solenoid valve coil, and H_JugFactor,normal represents the detection factor value under the normal on state. If the control signal is low, the PMOS power device M1 should be in the off state. The self-test fault factor LowFactor is set to a reference threshold between the normal off state and the leakage conduction state when the fault-free state is normal. It should satisfy L_JugFactor,normal≤LowFactor≤L_JugFactor,open, where L_JugFactor,normal represents the lower limit of the detection factor in the normal off state and L_JugFactor,open represents the upper limit of the detection factor in the solenoid valve open or PMOS power device M1 breakdown state.

9. The control circuit according to claim 8, characterized in that, When the DSP processor chip performs a self-test on the solenoid valve control channel based on JugFactor data, it includes: When the control signal is high, if H_JugFactor < HighFactor for n consecutive times, it is judged as a failure to conduct and the flag bit FlagFail_High = 1; if H_JugFactor ≥ HighFactor for n consecutive times, it is considered to be normal conduction and the flag bit FlagFail_High = 0. When the control signal is low, if L_JugFactor > LowFactor for n consecutive times, it is judged as a shutdown failure or leakage conduction abnormality, and the flag bit FlagFail_Low = 1; if L_JugFactor ≤ LowFactor for n consecutive times, it is considered that the shutdown state is normal, and the flag bit FlagFail_Low = 0. When FlagFail_High = 1 or FlagFail_Low = 1, it is determined that there is a fault in the current solenoid valve control path. If both are 0, the control circuit is considered to be working normally.

10. A self-testing method for a solenoid valve control circuit based on a detection factor, wherein the solenoid valve control circuit is based on any one of claims 1 to 9, characterized in that, It should include at least the following steps: SS1. Control signal generation and transmission: The DSP processor chip generates control signals for opening or closing the solenoid valve. After level conversion and drive enhancement by the level conversion chip, the signals are electrically isolated by the magnetic isolation chip and transmitted to the drive and self-test circuit. SS2. Solenoid Valve Drive and Signal Acquisition: The drive and self-test circuit drives the PMOS power device to perform the solenoid valve's on or off operation according to the control signal. The AD acquisition chip synchronously acquires the self-test signal V_DOBIT and the drive power supply voltage Vcc and transmits them to the DSP processor chip. SS3. Normalized detection factor calculation: The DSP processing chip calculates the normalized detection factor JugFactor = V_DOBIT / Vcc based on the received V_DOBIT and Vcc. SS4. State Recognition and Threshold Judgment: Determine the logic level state of the control signal. If the control signal is high, the system should be in the on state. The detection factor is H_JugFactor, which is compared with the preset reference threshold HighFactor. If the control signal is low, the system should be in the off state. The detection factor is L_JugFactor, which is compared with the preset reference threshold LowFactor. SS5. Fault trend counter update: Dynamically update the status counter according to the criterion result. If H_JugFactor < HighFactor, the high-level anomaly counter H_Numb increments; otherwise, it decrements. If L_JugFactor > LowFactor, the low-level anomaly counter L_Numb increments; otherwise, it decrements. SS6. Fault flag determination: Compare each counter value with the preset threshold Lim_Numb. If H_Numb > Lim_Numb, limit H_Numb to Lim_Numb and set the high-level fault flag FlagFail_High = 1. If H_Numb ≤ 1, set H_Numb = 1 and clear the high-level fault flag bit FlagFail_High = 0. If L_Numb > Lim_Numb, limit L_Numb to Lim_Numb and set the low-level fault flag FlagFail_Low = 1. If L_Numb ≤ 1, set L_Numb = 1 and clear the low-level fault flag bit FlagFail_Low = 0. SS7. Fault status output: Output the final fault flag FlagFail according to the logical OR operation result of FlagFail_High and FlagFail_Low. If this flag is 1, it indicates that there is a fault in the solenoid valve control channel; otherwise, it is determined to be in a normal state, realizing fault detection and diagnosis of the solenoid valve control path under different working conditions.

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