Full-CMOS low-power-consumption band-gap reference voltage source with segmented compensation structure

Abstract

The invention discloses a full CMOS (complementary metal oxide semiconductor) low-power-consumption band-gap reference voltage source with a segmented compensation structure, which comprises a band-gap reference circuit, a high-temperature segment compensation circuit and a low-temperature segment compensation circuit, and is characterized in that the band-gap reference circuit is connected with the low-temperature segment compensation circuit through the high-temperature segment compensation circuit; the voltage source can output reference voltage with a low temperature drift coefficient in a wide voltage range, and nW-level power consumption is achieved.

Description

Technical Field

[0001] This invention belongs to the field of power management technology and relates to a segmented compensation structure all-CMOS low-power bandgap reference voltage source. Background Technology

[0002] Bandgap voltage references are an indispensable component of analog and mixed-signal systems, widely used in modules such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), low-dropout linear regulators (LDLs), and phase-locked loops (PLLs). These structures require high-precision voltage references to ensure the accuracy of data bits in modern processing systems. Traditional bandgap voltage references are mainly based on bipolar junction transistors (BJTs), with typical operating voltages of 1.2V to 2.5V and power consumption typically in the μW range. However, with the rise of portable devices, IoT terminals, and implantable medical devices, higher demands are placed on voltage references with low voltage, low power consumption, high temperature stability, and wide temperature range adaptability. In recent years, transistors operating in the subthreshold region have replaced bipolar transistors, allowing operation at even lower voltages, achieving nW-level power consumption, and requiring smaller layout areas. However, subthreshold transistors are greatly affected by voltage drop across the PVT, especially in wide-voltage applications, increasing the difficulty of outputting a stable voltage reference. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a segmented compensation structure all-CMOS low-power bandgap reference voltage source. This voltage source can output a reference voltage with a low temperature drift coefficient over a wide voltage range and achieve power consumption in the nW range.

[0004] To achieve the above objectives, the present invention discloses a segmented compensation structure all-CMOS low-power bandgap reference voltage source, including a bandgap reference circuit, a high-temperature segment compensation circuit, and a low-temperature segment compensation circuit, wherein the bandgap reference circuit is connected to the low-temperature segment compensation circuit via the high-temperature segment compensation circuit.

[0005] The further improvement of the segmented compensation structure all-CMOS low-power bandgap reference voltage source described in this invention lies in:

[0006] Furthermore, the bandgap reference circuit includes a self-biased two-stage operational amplifier with a common source and common gate structure, which increases the power supply rejection ratio while achieving a high-gain clamping voltage to generate PTAT and CTAT currents, thus producing a first-order compensated reference voltage.

[0007] Furthermore, the bandgap reference circuit includes a first resistor, a second resistor, a high-voltage source VDD, a self-biased operational amplifier, an operational amplifier, a first nMOS transistor, a second nMOS transistor, a first pMOS transistor, a second pMOS transistor, a third pMOS transistor, a fourth pMOS transistor, a fifth pMOS transistor, a sixth pMOS transistor, a seventh pMOS transistor, and an eighth pMOS transistor;

[0008] The source of the first nMOS transistor, the source of the second nMOS transistor, one end of the first resistor, and one end of the third resistor are all grounded; the drain of the first nMOS transistor is connected to the gate of the first nMOS transistor, the inverting input of the self-biased operational amplifier, and the source of the second pMOS transistor; one end of the second resistor is connected to the drain and gate of the second pMOS transistor; the other end of the second resistor is connected to the non-inverting input of the self-biased operational amplifier, the source of the fourth pMOS transistor, and the inverting input of the operational amplifier; the source of the first pMOS transistor is connected to the drain of the second pMOS transistor; and the source of the third pMOS transistor is connected to the drain of the fourth pMOS transistor.

[0009] The high-voltage source is connected to the drains of the first, third, fifth, seventh, and eighth pMOS transistors. The source of the fifth pMOS transistor is connected to the drain of the sixth pMOS transistor. The source of the sixth pMOS transistor is connected to the source of the seventh pMOS transistor, one end of the first resistor, and the high-temperature compensation circuit. The other end of the third resistor is connected to the source of the eighth pMOS transistor and the non-inverting input of the operational amplifier. The output of the operational amplifier is connected to the gates of the seventh and eighth pMOS transistors. The output of the self-biased operational amplifier is connected to the gates of the first, second, third, and fourth pMOS transistors.

[0010] Furthermore, the first nMOS transistor, the second nMOS transistor, the first pMOS transistor, the second pMOS transistor, the third pMOS transistor, the fourth pMOS transistor, the fifth pMOS transistor, the sixth pMOS transistor, the seventh pMOS transistor, and the eighth pMOS transistor are designed using a standard 0.18μm CMOS process.

[0011] Furthermore, the self-biased operational amplifier includes a capacitor, a third nMOS transistor, a fourth nMOS transistor, a fifth nMOS transistor, a sixth nMOS transistor, a seventh nMOS transistor, a ninth pMOS transistor, a tenth pMOS transistor, an eleventh pMOS transistor, a twelfth pMOS transistor, a fourth resistor, a fifth resistor, and a power supply.

[0012] Among them, the high voltage source VDD is connected to the drain of the ninth pMOS transistor and the drain of the twelfth pMOS transistor; the source of the ninth pMOS transistor is connected to the drain of the tenth pMOS transistor; the source of the tenth pMOS transistor is connected to the drain of the third nMOS transistor and the drain of the sixth nMOS transistor; the source of the third nMOS transistor is connected to the drain of the fourth nMOS transistor; the source of the sixth nMOS transistor is connected to the drain of the fifth nMOS transistor, one end of the fifth resistor, and the gate of the seventh nMOS transistor; the other end of the fifth resistor is connected to one end of the capacitor; the drain of the seventh nMOS transistor is connected to one end of the fourth resistor and the gate of the eleventh pMOS transistor; the other end of the fourth resistor is connected to the source of the eleventh pMOS transistor and the gate of the twelfth pMOS transistor; the drain of the eleventh pMOS transistor is connected to the source of the twelfth pMOS transistor; and the source of the fourth nMOS transistor, the source of the fifth nMOS transistor N5, the other end of the capacitor, and the source of the seventh nMOS transistor are all grounded.

[0013] The positive terminal of the power supply is connected to the gate of the sixth nMOS transistor, and the negative terminal of the power supply is connected to the gate of the third nMOS transistor.

[0014] Furthermore, the gate of the ninth pMOS transistor is connected to the gates of the first and third pMOS transistors, and the gate of the tenth pMOS transistor is connected to the gates of the second and fourth pMOS transistors.

[0015] Furthermore, the third, fourth, fifth, sixth, seventh, ninth, tenth, eleventh, and twelfth pMOS transistors are designed using a standard 0.18μm CMOS process.

[0016] Furthermore, the low-temperature compensation circuit and the high-temperature compensation circuit utilize the idea of ​​piecewise linear compensation to extract current in the low-temperature segment and the high-temperature segment respectively.

[0017] Furthermore, by using the amplifier clamping, the generated PTAT current is increased by the current mirror copy and the CTAT current is superimposed to achieve segmented compensation.

[0018] Furthermore, the temperature compensation circuit and the two-stage operational amplifier of PSRR enable the bandgap reference circuit to output a reference voltage with a temperature drift coefficient of less than 12ppm / ℃ under voltages of 1.2V to 5V.

[0019] The present invention has the following beneficial effects:

[0020] In practical operation, the segmented compensation structure of the all-CMOS low-power bandgap reference voltage source described in this invention utilizes MOS transistors operating in the subthreshold region to replace the BJT transistors in traditional circuits, greatly reducing the operating voltage and current of the reference source circuit. It employs segmented compensation technology to achieve high-order curvature compensation of the voltage-temperature drift curve, enabling the bandgap reference circuit to output a reference voltage with a temperature drift coefficient of less than 12ppm / ℃ within a power supply voltage range of 1.2V to 5.0V, while ensuring that the power consumption does not exceed 1μW. Attached Figure Description

[0021] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 This is a structural diagram of the present invention;

[0023] Figure 2 This is a block diagram of a self-biased operational amplifier;

[0024] Figure 3 This is a structural diagram of the low-temperature compensation circuit;

[0025] Figure 4 This is a structural diagram of the high-temperature compensation circuit. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0028] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0029] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0030] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0031] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0033] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] As is widely known, a MOSFET is short for Metal-Oxide-Semiconductor Field-Effect Transistor. As a voltage-controlled device, it regulates the current between the source and drain by controlling the gate voltage, playing a core role in electronic circuits such as switching, amplification, and voltage regulation. The following analysis will cover its structure, classification, working principle, characteristics, and application areas:

[0035] I. Structure and Classification

[0036] Basic structure

[0037] A MOSFET consists of a source (S), a drain (D), a gate (G), and a substrate (B). The gate and substrate are isolated by a silicon dioxide insulating layer, forming a capacitor structure, which is crucial for its high input impedance. NMOS: Two N+ regions are fabricated on a P-type substrate to form an N-channel; it conducts when a positive voltage is applied to the gate. PMOS: Two P+ regions are fabricated on an N-type substrate to form a P-channel; it conducts when a negative voltage is applied to the gate.

[0038] Based on their working principle, they are divided into enhancement type (requires gate voltage to form a channel) and depletion type (a channel already exists when the gate voltage is zero).

[0039] Combination types: There are 4 types (N-channel enhancement type, N-channel depletion type, P-channel enhancement type, and P-channel depletion type), among which the N-channel enhancement type is the most widely used.

[0040] II. Working Principle

[0041] Enhancement-mode MOSFET (NMOS): When a positive voltage (VGS > threshold voltage VT) is applied to the gate, electrons accumulate on the surface of the P-substrate to form an N-type inversion layer (conductive channel), and the drain and source are connected. The larger VGS is, the thicker the channel and the smaller the on-resistance.

[0042] PMOS: When a negative voltage is applied to the gate (VGS < threshold voltage VT), holes accumulate on the surface of the N substrate to form a P-type inversion layer, and the drain and source are connected.

[0043] Depletion-type MOSFETs have their initial channel formed during manufacturing via ion implantation, allowing them to conduct without a gate voltage. The gate voltage adjusts the channel width: NMOS: positive gate voltage enhances conductivity, negative gate voltage weakens conductivity. PMOS: negative gate voltage enhances conductivity, positive gate voltage weakens conductivity.

[0044] refer to Figure 1 The segmented compensation structure of the all-CMOS low-power bandgap reference voltage source of the present invention includes a bandgap reference circuit, a high-temperature segment compensation circuit and a low-temperature segment compensation circuit, wherein the bandgap reference circuit is connected to the low-temperature segment compensation circuit via the high-temperature segment compensation circuit.

[0045] The bandgap reference circuit includes a first resistor R1, a second resistor R2, a high voltage source VDD, a self-biased operational amplifier, an operational amplifier, a first nMOS transistor N1, a second nMOS transistor N2, a first pMOS transistor P1, a second pMOS transistor P2, a third pMOS transistor P3, a fourth pMOS transistor P4, a fifth pMOS transistor P5, a sixth pMOS transistor P6, a seventh pMOS transistor P7, and an eighth pMOS transistor P8.

[0046] The source of the first nMOS transistor N1, the source of the second nMOS transistor N2, one end of the first resistor R1, and one end of the third resistor R3 are all grounded. The drain of the first nMOS transistor N1 is connected to the gate of the first nMOS transistor N1, the inverting input of the self-biased operational amplifier, and the source of the second pMOS transistor P2. One end of the second resistor R2 is connected to the drain and gate of the second pMOS transistor P2, and the other end of the second resistor R2 is connected to the non-inverting input of the self-biased operational amplifier, the source of the fourth pMOS transistor P4, and the inverting input of the operational amplifier. The source of the first pMOS transistor P1 is connected to the drain of the second pMOS transistor P2, and the source of the third pMOS transistor P3 is connected to the drain of the fourth pMOS transistor P4.

[0047] The high-voltage source VDD is connected to the drains of the first pMOS transistor P1, the third pMOS transistor P3, the fifth pMOS transistor P5, the seventh pMOS transistor P7, and the eighth pMOS transistor P8. The source of the fifth pMOS transistor P5 is connected to the drain of the sixth pMOS transistor P6. The source of the sixth pMOS transistor P6 is connected to the source of the seventh pMOS transistor P7, one end of the first resistor R1, and the high-temperature compensation circuit. The other end of the third resistor R3 is connected to the source of the eighth pMOS transistor P8 and the non-inverting input of the operational amplifier. The output of the operational amplifier is connected to the gate of the seventh pMOS transistor P7 and the gate of the eighth pMOS transistor P8. The output of the self-biased operational amplifier is connected to the gates of the first pMOS transistor P1, the second pMOS transistor P2, the third pMOS transistor P3, and the fourth pMOS transistor P4.

[0048] The bandgap reference circuit uses a first-order positive temperature coefficient voltage to generate current to compensate for the current generated by the negative temperature coefficient voltage of the transistor operating in the subthreshold region. It utilizes a self-biased operational amplifier to clamp the input voltage, thus converting the gate-source voltage difference in the subthreshold region into a positive temperature coefficient ΔV. GS The current PTAT is generated by the flow across R1; an operational amplifier is used to convert V... GS The current falling on R2 generates a CTAT current, and then the reference current is obtained by copying the current using a common source cascode current mirror, which generates a reference voltage across the resistor.

[0049] In the bandgap reference circuit, compared to the traditional structure, two resistor branches are removed. The purpose of this design is to reduce the current flowing through the two branches and reduce the area. Furthermore, the operational amplifier can be linked with higher-order compensation to achieve a simplified design.

[0050] refer to Figure 2 The self-biased operational amplifier includes a capacitor C1, a third nMOS transistor N3, a fourth nMOS transistor N4, a fifth nMOS transistor N5, a sixth nMOS transistor N6, a seventh nMOS transistor N7, a ninth pMOS transistor P9, a tenth pMOS transistor P10, an eleventh pMOS transistor P11, a twelfth pMOS transistor P12, a fourth resistor R4, a fifth resistor R5, and a power supply.

[0051] The high-voltage source VDD is connected to the drain of the ninth pMOS transistor P9 and the drain of the twelfth pMOS transistor P12. The source of the ninth pMOS transistor P9 is connected to the drain of the tenth pMOS transistor P10. The source of the tenth pMOS transistor P10 is connected to the drain of the third nMOS transistor N3 and the drain of the sixth nMOS transistor N6. The source of the third nMOS transistor N3 is connected to the drain of the fourth nMOS transistor N4. The source of the sixth nMOS transistor N6 is connected to the drain of the fifth nMOS transistor N5, one end of the fifth resistor R5, and the gate of the seventh nMOS transistor N7. Connect the other end of the fifth resistor R5 to one end of the capacitor C1. Connect the drain of the seventh nMOS transistor N7 to one end of the fourth resistor R4 and the gate of the eleventh pMOS transistor P11. Connect the other end of the fourth resistor R4 to the source of the eleventh pMOS transistor P11 and the gate of the twelfth pMOS transistor P12. Connect the drain of the eleventh pMOS transistor P11 to the source of the twelfth pMOS transistor P12. Connect the source of the fourth nMOS transistor N4, the source of the fifth nMOS transistor N5, the other end of the capacitor C1, and the source of the seventh nMOS transistor N7 to ground.

[0052] The positive terminal of the power supply is connected to the gate of the sixth nMOS transistor N6, and the negative terminal of the power supply is connected to the gate of the third nMOS transistor N3.

[0053] The gate of the ninth pMOS transistor P9 is connected to the gate of the first pMOS transistor P1 and the gate of the third pMOS transistor P3, and the gate of the tenth pMOS transistor P10 is connected to the gate of the second pMOS transistor P2 and the gate of the fourth pMOS transistor P4.

[0054] The self-biased operational amplifier uses MP1 and MP2 to form a common-source cascode current mirror structure to improve PSRR. The two-stage op-amp effectively improves the open-loop gain, thereby improving the rejection characteristics of the reference power supply. It can provide a larger input-output swing while maintaining a large gain and output impedance. The OPAMP forms an inverting feedback loop to clamp nodes V- and V+.

[0055] To meet the demands of high-precision and high-stability applications, the accuracy and stability of bandgap reference sources must be improved. Simple first-order linear compensation is often insufficient; therefore, the high-temperature and low-temperature compensation circuits involved in this invention are as follows: Figure 3 and Figure 4 As shown.

[0056] refer to Figure 3 The current flowing through the tenth CMOS transistor M3 is equal to I. PTAT Subtract the I copied by the current mirror of the ninth nCMOS transistor M2 and the eighth nCMOS transistor M1 CTAT Current, only when I PTAT When the current exceeds the copy current, the tenth n-CMOS transistor M3 will then carry current. Combining the characteristics of subtracting two currents, this current gradually decreases with temperature until it reaches zero, only not becoming zero below a certain temperature. Finally, the current flowing through the eleventh n-CMOS transistor M4 is a mirror image of the current flowing through the tenth n-CMOS transistor M3. Below a certain temperature, a current of magnitude I1 is drawn from the output reference voltage circuit to achieve low-temperature compensation.

[0057] Figure 4 The high-temperature compensation circuit structure shown has a current flowing through the fourteenth nCMOS transistor M7 equal to I. CTAT Subtract the I copied by the current mirror through the thirteenth nCMOS transistor M6 and the twelfth nCMOS transistor M5 PTAT Current, only when I CTAT When the current exceeds the copy current, the fourteenth n-CMOS transistor M7 begins to flow. Combining the characteristics of the two subtracted currents, this current gradually increases with temperature, starting from 0, and only becomes non-zero above a certain temperature. Finally, the current I2 flowing through the fifteenth n-CMOS transistor M8 is a mirror image of the current in the fourteenth n-CMOS transistor M7. Above a certain temperature, a current of magnitude I2 is drawn from the output reference voltage circuit to achieve high-temperature compensation.

[0058] This invention has the function of stabilizing the output reference under different power supply voltages. Under power supply voltages of 1.2V to 5V, the reference voltage source stabilizes the output voltage; the temperature compensation circuit can extract current in segments to reduce the temperature drift coefficient of the output voltage.

[0059] This invention employs a standard 0.18μm CMOS process. The temperature compensation circuit and a two-stage operational amplifier with high PSRR enable the bandgap reference circuit to output a reference voltage with a temperature drift coefficient of less than 12ppm / ℃ within a voltage range of 1.2V to 5V, while consuming no more than 1μW. The excellent performance of the bandgap reference described in this invention indicates that it is highly suitable for applications with a wide voltage range and low power consumption.

[0060] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0061] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

[0062] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent structural change made to the above embodiment based on the technical essence of the present invention shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A segmented compensation structure all-CMOS low-power bandgap reference voltage source, characterized in that, It includes a bandgap reference circuit, a high-temperature compensation circuit, and a low-temperature compensation circuit, wherein the bandgap reference circuit is connected to the low-temperature compensation circuit via the high-temperature compensation circuit.

2. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 1, characterized in that, The bandgap reference circuit includes a self-biased two-stage operational amplifier with a common source and common gate structure, which increases the power supply rejection ratio while achieving a high-gain clamping voltage to generate PTAT and CTAT currents, thus producing a first-order compensated reference voltage.

3. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 1, characterized in that, The bandgap reference circuit includes a first resistor (R1), a second resistor (R2), a high voltage source (VDD), a self-biased operational amplifier, an operational amplifier, a first nMOS transistor (N1), a second nMOS transistor (N2), a first pMOS transistor (P1), a second pMOS transistor (P2), a third pMOS transistor (P3), a fourth pMOS transistor (P4), a fifth pMOS transistor (P5), a sixth pMOS transistor (P6), a seventh pMOS transistor (P7), and an eighth pMOS transistor (P8). The source of the first nMOS transistor (N1), the source of the second nMOS transistor (N2), one end of the first resistor (R1), and one end of the third resistor (R3) are all grounded; the drain of the first nMOS transistor (N1) is connected to the gate of the first nMOS transistor (N1), the inverting input of the self-biased operational amplifier, and the source of the second pMOS transistor (P2); one end of the second resistor (R2) is connected to the drain and gate of the second pMOS transistor (P2); the other end of the second resistor (R2) is connected to the non-inverting input of the self-biased operational amplifier, the source of the fourth pMOS transistor (P4), and the inverting input of the operational amplifier; the source of the first pMOS transistor (P1) is connected to the drain of the second pMOS transistor (P2); and the source of the third pMOS transistor (P3) is connected to the drain of the fourth pMOS transistor (P4). The high-voltage source VDD is connected to the drains of the first pMOS transistor (P1), the third pMOS transistor (P3), the fifth pMOS transistor (P5), the seventh pMOS transistor (P7), and the eighth pMOS transistor (P8). The source of the fifth pMOS transistor (P5) is connected to the drain of the sixth pMOS transistor (P6). The source of the sixth pMOS transistor (P6) is connected to the source of the seventh pMOS transistor (P7), one end of the first resistor (R1), and the high-temperature compensation circuit. The circuit is connected; the other end of the third resistor (R3) is connected to the source of the eighth pMOS transistor (P8) and the non-inverting input of the operational amplifier. The output of the operational amplifier is connected to the gate of the seventh pMOS transistor (P7) and the gate of the eighth pMOS transistor (P8). The output of the self-biased operational amplifier is connected to the gate of the first pMOS transistor (P1), the gate of the second pMOS transistor (P2), the gate of the third pMOS transistor (P3), and the gate of the fourth pMOS transistor (P4).

4. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 3, characterized in that, The first nMOS transistor (N1), the second nMOS transistor (N2), the first pMOS transistor (P1), the second pMOS transistor (P2), the third pMOS transistor (P3), the fourth pMOS transistor (P4), the fifth pMOS transistor (P5), the sixth pMOS transistor (P6), the seventh pMOS transistor (P7), and the eighth pMOS transistor (P8) are designed using a standard 0.18μm CMOS process.

5. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 3, characterized in that, The self-biased operational amplifier includes a capacitor (C1), a third nMOS transistor (N3), a fourth nMOS transistor (N4), a fifth nMOS transistor (N5), a sixth nMOS transistor (N6), a seventh nMOS transistor (N7), a ninth pMOS transistor (P9), a tenth pMOS transistor (P10), an eleventh pMOS transistor (P11), a twelfth pMOS transistor (P12), a fourth resistor (R4), a fifth resistor (R5), and a power supply; The high-voltage source (VDD) is connected to the drain of the ninth pMOS transistor (P9) and the drain of the twelfth pMOS transistor (P12). The source of the ninth pMOS transistor (P9) is connected to the drain of the tenth pMOS transistor (P10). The source of the tenth pMOS transistor (P10) is connected to the drain of the third nMOS transistor (N3) and the drain of the sixth nMOS transistor (N6). The source of the third nMOS transistor (N3) is connected to the drain of the fourth nMOS transistor (N4). The source of the sixth nMOS transistor (N6) is connected to the drain of the fifth nMOS transistor (N5), one end of the fifth resistor (R5), and the gate of the seventh nMOS transistor (N7). Connect the other end of the fifth resistor (R5) to one end of the capacitor (C1). Connect the drain of the seventh nMOS transistor (N7) to one end of the fourth resistor (R4) and the gate of the eleventh pMOS transistor (P11). Connect the other end of the fourth resistor (R4) to the source of the eleventh pMOS transistor (P11) and the gate of the twelfth pMOS transistor (P12). Connect the drain of the eleventh pMOS transistor (P11) to the source of the twelfth pMOS transistor (P12). Connect the source of the fourth nMOS transistor (N4), the source of the fifth nMOS transistor (N5), the other end of the capacitor (C1), and the source of the seventh nMOS transistor (N7) to ground. The positive terminal of the power supply is connected to the gate of the sixth nMOS transistor (N6), and the negative terminal of the power supply is connected to the gate of the third nMOS transistor (N3).

6. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 5, characterized in that, The gate of the ninth pMOS transistor (P9) is connected to the gate of the first pMOS transistor (P1) and the gate of the third pMOS transistor (P3), and the gate of the tenth pMOS transistor (P10) is connected to the gate of the second pMOS transistor (P2) and the gate of the fourth pMOS transistor (P4).

7. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 5, characterized in that, The third nMOS transistor (N3), the fourth nMOS transistor (N4), the fifth nMOS transistor (N5), the sixth nMOS transistor (N6), the seventh nMOS transistor (N7), the ninth pMOS transistor (P9), the tenth pMOS transistor (P10), the eleventh pMOS transistor (P11), and the twelfth pMOS transistor (P12) are designed using a standard 0.18μm CMOS process.

8. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 1, characterized in that, The low-temperature and high-temperature compensation circuits utilize the idea of ​​piecewise linear compensation, extracting current in the low-temperature and high-temperature ranges respectively.

9. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 1, characterized in that, The generated PTAT current is increased by using the amplifier clamping to achieve segmented compensation by superimposing the current mirror copy and CTAT current.

10. The segmented compensation structure all-CMOS low-power bandgap reference voltage source according to claim 1, characterized in that, The temperature compensation circuit and the two-stage operational amplifier of PSRR enable the bandgap reference circuit to output a reference voltage with a temperature drift coefficient of less than 12ppm / ℃ under voltages of 1.2V to 5V.

Images