Memory system, operating method thereof, and storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and a storage medium, and the memory system comprises at least one memory device and a memory controller. The memory controller is coupled with the host and the memory device, and comprises a write buffer and a control part coupled with the write buffer; the control portion is configured to: in response to execution of an erase event of a memory block in the memory device, configure a portion of free memory space of the memory controller as a newly added memory space of the write buffer; in response to the execution of the erase event, writing data received from the host into the newly added storage space of the write buffer; in response to completion of the erase event, the newly added memory space of the write buffer is released.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory system, its operation method, and a storage medium. Background Technology

[0002] With the advancement of technology and the rapid development of the internet, people have increasingly higher demands for the storage and retention of information and data. Therefore, improving the performance of storage systems is crucial. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a memory system, its operation method, and a storage medium.

[0004] In a first aspect, embodiments of this application provide a memory system including at least one memory device and a memory controller; the memory controller is coupled to both a host and the memory device, and includes a write buffer and a control unit coupled to the write buffer; the control unit is configured to: in response to the impending execution of an erase event of a memory block in the memory device, configure a portion of the free memory space of the memory controller as new memory space for the write buffer; in response to the execution of the erase event, write data received from the host into the new memory space of the write buffer; and in response to the completion of the erase event, release the new memory space of the write buffer.

[0005] In some embodiments, the control unit is configured to allocate the same amount of new storage space to the write buffer in response to erase events of different storage blocks.

[0006] In some embodiments, the amount of additional storage space allocated to the write buffer is positively correlated with the average duration of erase events on the storage block.

[0007] In some embodiments, the control unit is configured to write data stored in the write buffer into the memory device in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold.

[0008] In some embodiments, the control unit is configured to: in response to the memory device needing to open a new memory block for data writing, control the memory device to perform an erase operation on the new memory block before writing data to the new memory block; wherein the start of the erase operation is the execution of the erase event, and the end of the erase operation is the completion of the erase event.

[0009] In some embodiments, the control unit is configured to: in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold, and the memory device needing to open a new storage block for data writing, determine that an erase event of the memory device is about to be executed, generate an erase command, and send the erase command to the memory device.

[0010] In some embodiments, the control unit is configured to: in response to the completion of an erase event, sequentially write data in the original storage space of the write buffer and data in the new storage space of the write buffer to the memory device in the order of writing to the original storage space of the write buffer and the new storage space of the write buffer; and release the new storage space of the write buffer in response to the completion of writing data in the new storage space of the write buffer to the memory device.

[0011] In some embodiments, the original storage space of the write buffer is smaller than the preset storage space.

[0012] In some embodiments, the memory controller further includes a volatile memory device, a portion of which is used as the original memory space of the write buffer and the additional memory space of the write buffer.

[0013] In some embodiments, the memory device includes NAND, and the volatile memory device includes SRAM / DRAM.

[0014] In some embodiments, the memory system includes an enterprise-class solid-state drive (eSSD).

[0015] In a second aspect, embodiments of this application provide an operation method for a memory system, comprising: in response to the impending execution of an erase event of a memory block in a memory device coupled to a memory controller of the memory system, a control unit of the memory controller configures a portion of the free memory space of the memory controller as additional memory space for a write buffer of the memory controller coupled to the control unit; in response to the execution of the erase event, writing data received from a host coupled to the memory controller into the additional memory space of the write buffer; and in response to the completion of the erase event, releasing the additional memory space of the write buffer.

[0016] In some embodiments, a portion of the free storage space of the memory controller is allocated to the write buffer, the operation method including: in response to erase events of different storage blocks, the newly added storage space allocated to the write buffer is of the same size.

[0017] In some embodiments, the operation method includes: writing data stored in the write buffer into the memory device in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold.

[0018] In some embodiments, the operation method includes: in response to the memory device needing to open a new memory block for data writing, controlling the memory device to perform an erase operation on the new memory block before writing data to the new memory block; wherein the start of the erase operation is the execution of the erase event, and the end of the erase operation is the completion of the erase event.

[0019] In some embodiments, the operation method includes: in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold, and the memory device needing to open a new storage block for data writing, determining that an erase event of the memory device is about to be executed, generating an erase command, and sending the erase command to the memory device.

[0020] In some embodiments, releasing the newly added storage space of the write buffer includes: in response to the completion of an erase event, writing data in the original storage space of the write buffer and data in the newly added storage space of the write buffer to a memory device in the order of writing; and in response to the completion of writing data in the newly added storage space of the write buffer to the memory device, releasing the newly added storage space of the write buffer.

[0021] Thirdly, embodiments of this application provide a storage medium storing executable instructions, which, when executed, implement the steps of the operation method of the memory system provided in the second aspect.

[0022] In various embodiments of this application, the control unit of the memory system is configured to dynamically increase the storage space of the write buffer. Specifically, when an erase event of a memory block in the memory system is detected to be about to occur, the storage space of the write buffer is briefly increased. The increased write buffer is used to cache write data sent by the host during the erase operation. After the erase operation is completed, the write buffer is restored to its original size. During the erase operation, the storage space available to the write buffer includes the original storage space of the write buffer and the increased storage space. After the erase operation is completed, the increased storage space of the write buffer is released. In this way, by using the expanded storage space of the write buffer to buffer write data sent by the host during the erase operation, the latency caused by the write buffer not having its storage space increased and thus not being able to respond to the host's write data during the erase operation is alleviated, thereby reducing the write latency generated during the erase operation and improving the performance of the memory system. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of this application;

[0024] Figure 2A This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of this application;

[0025] Figure 2B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of an exemplary composition structure of a memory system provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram illustrating an exemplary programming operation performed using a memory system according to an embodiment of this application;

[0029] Figure 6 This is a schematic diagram illustrating an exemplary erasure operation performed on a memory system according to an embodiment of this application;

[0030] Figure 7 This is a schematic diagram illustrating another exemplary operation of a memory system according to an embodiment of this application.

[0031] Figure 8 This is a schematic diagram illustrating another exemplary execution of an erase operation in a memory system according to another embodiment of this application;

[0032] Figure 9 This is another exemplary schematic diagram of a memory system having completed an erase operation according to another embodiment of this application;

[0033] Figure 10 A flowchart illustrating an operation method of a memory system provided in an embodiment of this application;

[0034] Figure 11 This is a schematic diagram of the composition structure of a storage medium provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0042] The memory devices in the embodiments of this application include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0043] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this application is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0044] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0045] In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment in a solid state disk (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0046] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104.

[0047] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0048] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0049] In such Figure 2A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0050] In such Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0051] Figure 3 A schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of this application is shown. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0052] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0053] It should be noted that the storage state mentioned here is the same as the storage state of the storage cell in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has two storage states (i.e., two memory states), which include one programming state and one erase state. Another example is an MLC type storage cell with four storage states, including one erase state and three programming states. Yet another example is a TLC type storage cell with eight storage states, including one erase state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, including one erase state and fifteen programming states.

[0054] like Figure 3As shown, each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source-side selection transistor) at its source end and an upper selection transistor (TSG) 312 (also known as a drain-side selection transistor) at its drain end. BSG 310 and TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0055] like Figure 3 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some implementations, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0056] refer to Figure 3 Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the above selection transistor (TSG) 312).

[0057] refer to Figure 4 In some specific embodiments, the memory system 102 is coupled to the host and responds to host instructions to perform various feedback. The memory system 102 may include a memory controller 106 and a memory device 104. The memory controller 106 is used to control the memory device 104 to perform read, write, erase and other operations. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner.

[0058] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, and a bus 1060. The host interface 1061 is the connection interface between the host 108 and the memory controller 106, allowing the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is the connection interface between the memory controller 106 and the memory device 104, and is used to implement data transfer between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 102 as a whole; the specific steps performed by the memory controller mentioned above are mainly executed and completed by the control unit 1063. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU) or a microprocessor (MCU). The ROM 1069 typically contains firmware or firmware program code for the memory controller 106, which is used to initialize and operate the various components of the memory controller. The RAM 1070 is typically used for buffering data. The error correction module 1064 may further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible erroneous data during data transmission.

[0059] The garbage collection module 1065 is used to read out the valid data from some memory blocks, rewrite it, and then mark these memory blocks to obtain new spare memory blocks after the storage space of the memory device reaches a certain threshold. The general implementation of garbage collection can be divided into three steps: selecting source memory blocks with less valid data; finding valid data from the source memory blocks; and writing the valid data to the target memory block. At this point, all data in the source memory block becomes invalid data, and the source memory block is marked as a new spare memory block. The wear leveling module 1066 is used to maintain a balanced wear (erase count) of each memory block in the memory system through data statistics and algorithms. The general implementation of wear leveling can be divided into two steps: selecting source memory blocks containing cold data; reading the valid data from the source memory blocks and writing it to memory blocks with a relatively high number of erase counts. At this point, the valid data in the source memory blocks becomes invalid data and is marked. RAM 1070 can be used to buffer data.

[0060] In the field of storage systems, such as solid-state drives (SSDs), consumer-grade SSDs store users' personal data, while enterprise-grade SSDs (eSSDs) store users' private information. This data is crucial for both individuals and businesses. Write latency is an important evaluation metric for storage systems (such as eSSDs). Write latency refers to the time it takes for the host to send a command to the storage system and for the system to send the command back. The shorter the command return time, the better the performance of the storage system.

[0061] refer to Figure 5 Because the time it takes for the host to transfer data is faster than the time it takes to write data to the memory device (such as NAND), a write buffer is introduced into the memory system to reduce the impact of data writing to the memory device. In response to a write command sent by the host, the data transferred by the host is first accumulated in the write buffer, that is, the host's write data is written to the write buffer. After the data in the write buffer has accumulated to a certain amount, it is written / programmed to the memory device all at once, which can reduce the write latency of the memory system. However, in some scenarios, such as when an erase event is triggered every time a new memory block is used, data cannot be written to the memory device during the erase operation, causing blocking and increasing write latency. Therefore, write latency optimization is needed for this scenario.

[0062] refer to Figure 6In the use of memory devices, an erase event is triggered before each new memory block is programmed. If the erase event cannot be interrupted, data cannot be written to the memory device during the erase operation, resulting in a write delay that needs to be superimposed on the delay caused by the erase operation. When the duration of the erase operation is longer, the impact of the delay caused by the superimposed erase operation on the performance of the memory system becomes more severe.

[0063] While write buffers can effectively reduce the impact of programming time, when an erase event occurs, data cannot be written to the memory device during the erase operation, resulting in increased write latency.

[0064] In view of the above, embodiments of this application provide a memory system, its operation method, and a storage medium.

[0065] In a first aspect, embodiments of this application provide a memory system, with reference to Figure 7 , Figure 8 and Figure 9 The memory system includes at least one memory device and a memory controller; the memory controller is coupled to both the host and the memory device, and includes a write buffer and a control unit coupled to the write buffer; the control unit is configured to: in response to the impending execution of an erase event of a memory block in the memory device, configure a portion of the free memory space of the memory controller as new memory space for the write buffer; in response to the execution of an erase event, write data received from the host into the new memory space of the write buffer; and in response to the completion of an erase event, release the new memory space of the write buffer.

[0066] Here, the structure of the memory system can be referred to the above. Figure 1 , Figure 2A , Figure 2B , Figure 3 and Figure 4 The relevant descriptions will be understood and will not be repeated here.

[0067] Here, the control unit of the memory controller can be referenced. Figure 4 The control unit 1063 of the memory controller 106 is understood. The control unit 1063 is used to control the memory system 102 as a whole. The control unit 1063 can be coupled to the RAM 1070 via the bus 1060.

[0068] Here, the write buffer of the memory controller can be referenced. Figure 4The RAM 1070 of the memory controller 106 is understood to be used for buffering data transferred by the host. In some embodiments, the write buffer may be part of the RAM 1070, which may also store other intermediate data of the memory controller during firmware operation. The write buffer may not be a fixed hardware storage structure; it may be refreshed periodically, and may represent storage space in the memory system allocated for write data.

[0069] Here, the memory space of the memory controller may include Figure 4 The RAM 1070 of the memory controller 106 is used to buffer the data processed by the memory controller. The free storage space of the memory controller may include... Figure 4 The space that can be utilized in RAM 1070 can be allocated as an extended write buffer, for example, a portion of the RAM 1070's storage space can be allocated as an extended write buffer. The extended write buffer can be used to buffer data transferred by the host (e.g., host write data), and the storage space of the extended write buffer serves as additional storage space for the write buffer. The extended write buffer is released as a free buffer, and the storage space of the free buffer continues to serve as the storage space of the memory controller to buffer the data processed by the memory controller. The storage space of the write buffer serves as the original storage space of the write buffer and is still used to buffer data transferred by the host.

[0070] In this embodiment of the application, the new storage space of the write buffer can be understood as the expansion of the storage space of the write buffer, and the original storage space of the write buffer can be understood as the storage space of the write buffer.

[0071] As mentioned earlier, when a memory block is full and a new memory block needs to be opened to continue writing data, an erase operation must first be performed on the new memory block. In some embodiments, the entire erase process experienced by each new memory block can be referred to as an erase event. It is understood that an erase event is an event executed by the memory controller controlling the memory device. The memory controller can decide whether to open a new memory block based on the current usage of the memory block and the status of the data to be written, thereby making a decision on whether to execute an erase event. In some embodiments, the point at which an erase event is about to be executed can be defined as the memory controller sending an erase command to the memory device or preparing to send an erase command to the memory device (e.g., the memory controller has made the decision to execute an erase event but has not yet issued the erase command).

[0072] refer to Figure 7In response to a write command sent by the host, the data transmitted by the host is buffered into a write buffer. When the data in the write buffer accumulates to a certain amount, a programming operation is performed on the memory device, writing / programming the accumulated data in the write buffer to the memory device all at once. An erase event may be triggered during the programming operation; for example, an erase event is triggered each time a new memory block is used.

[0073] In some embodiments, the execution of an erase event can be understood as the entire process of the peripheral circuitry of the memory device controlling the memory block to perform an erase operation. During the erase operation, because the peripheral circuitry is occupied by the erase process, the memory device can no longer respond to the write command from the memory controller and perform the corresponding write operation. At this time, since the original write buffer is also relatively full and ready to write data to the memory device, the original write buffer space is insufficient and can no longer respond to the host's write command. Furthermore, because the erase operation lasts for a relatively long time, it will cause a long delay in the host writing data.

[0074] In some embodiments, the completion of an erase event can be understood as the end of the entire execution process of the peripheral circuitry of the memory device controlling the memory block execution to carry out the erase operation.

[0075] refer to Figure 8 Because an erase event is triggered during the programming operation, data cannot be written to the memory device during the erase operation itself, and the programming operation stops. The timing of the erase event can be detected; for example, in response to the impending execution of an erase event on a memory block in the memory device, a portion of the memory controller's free storage space can be configured as an extended write buffer. In response to the execution of the erase event, data received from the host is written to the extended write buffer's storage space. During the erase operation, the extended write buffer's storage space can be utilized to increase the amount of data buffered from the host to the extended write buffer.

[0076] In some embodiments, the firmware (FW) can detect whether an erase event is about to be executed, the start of an erase event, and the completion of an erase event from input / output (I / O) scheduling. In some specific embodiments, the determination of whether an erase event is about to be executed can be made by whether the memory controller sends an erase command to the memory device; the determination can be made by the memory device sending feedback information to the memory controller indicating the start and completion of the erase operation; or the determination can be made by querying the busy signal inside the memory device.

[0077] Before executing an erase event, additional free space in the memory controller (e.g., free space in SRAM or DRAM) is allocated as an extended write buffer, increasing the buffer space (including the buffer space of the original write buffer and the buffer space of the extended write buffer). For new write commands from the host, the host's write data is buffered into the space of the extended write buffer, mitigating the impact of the erase operation. In some specific embodiments, the firmware (FW) can be a program stored in the electrically erasable programmable read-only memory (EEPROM) or FLASH chip of the memory system, and can be upgraded by the host through a specific refresh procedure. The firmware controls the read / write and transfer algorithms of the memory system and allocates data storage appropriately. (Reference) Figure 9 In response to the completion of the erase event, the extended write buffer is released as a free buffer, which can be used as a data buffer other than the write data buffer. After the erase operation is completed, the extended write buffer is released as a free buffer to avoid occupying the memory controller's storage space for an extended period of time.

[0078] For example, the write buffer size is M (MB), and the duration during which data cannot be programmed into the memory device during the erase operation is t_ERS, which can be understood as the duration of the erase operation. Here, M (MB) = M * 256 IOs (each IO is 4KB in size), the read / write performance per 4KB is (M * 256) / t_ERS, the average time spent per IO is t_ERS / (M * 256), the queue data QD = 256, and the write latency during the erase operation is t_ERS / (M * 256) * QD = t_ERS / M.

[0079] For example, if the write buffer size is 4MB, t_ERS = 10ms, and QD = 256, the write latency is 10ms / 4 = 2.5ms. Under the same conditions, using an extended write buffer with a size of 1MB on top of the 4MB write buffer, the write latency for QD = 256 is 10ms / (4+1) = 2ms, a 20% reduction in write latency.

[0080] In some embodiments, the control unit is configured to allocate the same amount of new storage space to the write buffer in response to erase events of different storage blocks.

[0081] Here, considering that the average duration of erase events for different memory blocks in the same memory device will not differ significantly, the size of the additional storage space allocated to the write buffer is fixed.

[0082] In some specific embodiments, the size of the additional storage space allocated to the write buffer can be an empirical value; or it can be a default value configured at the time the memory device leaves the factory, which is obtained through a large number of simulation experiments before the memory device leaves the factory. For example, the size of the additional storage space allocated to the write buffer can be determined based on the average duration of the erase event of different memory blocks obtained from simulation experiments.

[0083] In this embodiment, the size of the additional storage space allocated to the write buffer is fixed, which can increase the stability of the memory system.

[0084] In other embodiments, the control unit is configured to allocate different amounts of new storage space to the write buffer in response to different erase events of different storage blocks.

[0085] Here, different memory blocks in different memory devices have different storage capacities and different average durations of their erase events; or, for different memory blocks in the same memory device, due to differences in manufacturing processes, their average durations of erase events also differ. In this case, more granular control can be considered, that is, the size of the new storage space allocated to the write buffer can be determined based on the duration of the erase events for different memory blocks.

[0086] In some specific embodiments, the size of the additional storage space allocated to the write buffer is positively correlated with the average duration of the erase event of the storage block.

[0087] As previously mentioned, due to differences in manufacturing processes, the duration of erase events may vary between different memory blocks within the same memory device. Here, the average duration of erase events corresponding to different memory blocks within the same memory device can be used as the average duration of erase events for each memory block in that memory device.

[0088] In some specific embodiments, the average duration of an erase event for a memory block can be a default value configured at the factory, which is derived through extensive simulation experiments before the memory device leaves the factory. For example, once the type of memory device is determined, the average duration of an erase event for a memory block is essentially determined as well.

[0089] In some specific embodiments, the average duration of the erase event of a memory block can be obtained during the use of the memory device. For example, the process of obtaining the average duration of the erase event can be as follows: during the erase operation of the first memory block, the duration of the erase event is obtained by detecting the busy signal inside the memory device to determine whether the erase event has started / completed; and the duration of the erase event of the first memory block obtained is used as the average duration of the erase events of all other memory blocks of the memory device.

[0090] In this embodiment, the size of the additional storage space allocated to the write buffer varies depending on the average duration of the erase event of the storage block, which can increase the flexibility of the memory system to reduce write latency.

[0091] In some embodiments, the control unit is configured to write data stored in the write buffer into the memory device in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold.

[0092] Here, to improve the utilization of the write buffer, the preset threshold can be set to be close to or equal to the amount of data in the original storage space of the write buffer. When the amount of data stored in the original storage space of the write buffer is greater than or equal to the preset threshold, a programming operation of the memory device is triggered. Here, the preset threshold can be the amount of data stored in at least a portion of the original storage space of the write buffer. The preset threshold can be the amount of data stored when the original storage space is full or nearly full. For example, the preset threshold can be the amount of data stored at 100% of the original storage space (i.e., when the original storage space is full), the preset threshold can also be the amount of data stored at 80% of the original storage space (i.e., when the original storage space is nearly full), or the preset threshold can also be any value between 80% and 100% of the original storage space (i.e., when the original storage space is nearly full).

[0093] In some embodiments, the control unit is configured to: in response to the memory device needing to open a new memory block for data writing, control the memory device to perform an erase operation on the new memory block before writing data to the new memory block; wherein the start of the erase operation is the execution of the erase event, and the end of the erase operation is the completion of the erase event.

[0094] In this embodiment, when one storage block is full, another storage block needs to be opened for data writing. The storage block to be opened can be referred to as the new storage block. Before writing data to the new storage block, an erase operation needs to be performed on the new storage block.

[0095] In some embodiments, the execution of an erase event can be understood as the entire execution process of the peripheral circuitry of the memory device controlling the memory block to perform a specific erase operation. The completion of an erase event can be understood as the start of the entire execution process of the peripheral circuitry of the memory device controlling the memory block to perform a specific erase operation, and the completion of an erase event can be understood as the end of the entire execution process of the peripheral circuitry of the memory device controlling the memory block to perform a specific erase operation. As mentioned above, the start and completion of the erase operation can be determined by the memory device sending feedback information to the memory controller, or by querying the busy signal inside the memory device.

[0096] In some embodiments, the control unit is configured to: in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold, and the memory device needing to open a new storage block for data writing, determine that an erase event of the memory device is about to be executed, generate an erase command, and send the erase command to the memory device.

[0097] If the amount of data stored in the original storage space of the write buffer is greater than or equal to a preset threshold, it is necessary to write the data stored in the write buffer into the memory device, which means that the memory device needs to be programmed. At the same time, during the programming operation, the control unit detects that a new storage block needs to be opened for data writing, generates an erase command, and sends the erase command to the memory device, triggering an erase event for the new storage block.

[0098] In some embodiments, the control unit is configured to: in response to the completion of an erase event, sequentially write data in the original storage space of the write buffer and data in the new storage space of the write buffer to the memory device in the order of writing to the original storage space of the write buffer and the new storage space of the write buffer; and release the new storage space of the write buffer in response to the completion of writing data in the new storage space of the write buffer to the memory device.

[0099] For example, the write buffer and the extended write buffer can be considered as a single buffer. Data written to this single buffer is sequentially written to the memory device according to the order in which the host writes data to this single buffer. For instance, before an erase operation, the host writes data to the write buffer; during the erase operation, the host writes data to the extended write buffer. Data written to the write buffer is written to the memory device before data written to the extended write buffer.

[0100] Releasing the newly added storage space in the write buffer, i.e., freeing the write buffer to a free buffer. The write buffer is still used to buffer host write data, while the free buffer is no longer used to buffer host write data, but instead is used to buffer data processed by the memory controller.

[0101] In some embodiments, the original storage space of the write buffer is smaller than the preset storage space.

[0102] Here, if the original storage space of the write buffer is allocated to be large, and the preset threshold for transferring data from the write buffer to the memory device is still set to the original storage space of the write buffer being full / nearly full, when it is necessary to transfer data from the write buffer to the memory device, the amount of data stored in the write buffer is large. In this case, the time taken to write the data stored in the write buffer to the memory device is long. Furthermore, when transferring data from the write buffer to the memory device, the write buffer cannot respond to the host's write operation, and the transfer of data from the write buffer itself will cause serious host write latency. Conversely, if the preset threshold for transferring data from the write buffer to the memory device is set relatively small, the utilization rate of the original storage space of the write buffer will be low.

[0103] Therefore, when setting the original storage space of the write buffer, it is generally not set to a large amount, but rather a relatively small amount, and the preset threshold for transferring data from the write buffer to the memory device is set to the original storage space of the write buffer being full or nearly full.

[0104] Because the write buffer's storage space is not large enough, the time elapsed from 0% to filling the write buffer is insufficient to cover the duration of an erase operation. Furthermore, the write time to the memory device is shorter than the erase operation's duration. For example, if the write buffer's storage space is 4MB, the erase operation lasts 10ms, and writing 4MB of data from the write buffer to the memory device takes 1ms. During the process of transferring data from the write buffer to the memory device, the write buffer cannot respond to host write operations. In other words, the write latency caused by the erase operation (e.g., erase operation lasting 10ms) is significantly greater than the write latency caused by the write operation (writing data from the write buffer to the memory device, e.g., writing data from the write buffer to the memory device taking 1ms). Therefore, the mitigation of write latency caused by the erase operation in this embodiment is highly effective.

[0105] In some embodiments, the memory controller further includes a volatile memory device, a portion of which is used as the original memory space of the write buffer and the additional memory space of the write buffer.

[0106] Here, volatile storage devices may include Figure 4 The RAM 1070 of the memory controller 106 can be used to buffer data transferred by the host or to buffer data processed by the memory controller. For example, at least a portion of the RAM 1070 can be configured as the original storage space of a write buffer for buffering data transferred by the host (e.g., host write data); at least a portion of the space available in the RAM 1070 during firmware operation can be allocated as additional storage space for the write buffer (extending the write buffer's storage space) for buffering data transferred by the host (e.g., host write data).

[0107] In some embodiments, the volatile storage device includes Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random-Access Memory (SDRAM), or Double-Data-Rate Fourth-Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM). In some embodiments, the volatile storage device may further include Static Random-Access Memory (SRAM).

[0108] In some embodiments, the memory device may include a FLASH chip (e.g., a three-dimensional NAND Flash memory). The FLASH chip can serve as the storage medium for storing data in the aforementioned memory system.

[0109] In some embodiments, the memory device includes NAND, and the volatile memory device includes SRAM / DRAM.

[0110] In some embodiments, the memory system includes an enterprise-class solid-state drive (eSSD).

[0111] Since eSSDs have the advantage of large DRAM space, the overall benefit of reducing write latency is greater than using part of the DRAM space to increase the buffer space of the write buffer. Moreover, in the embodiments of the application, the dynamically adjusted buffer is only added during the erase operation, avoiding long-term occupation of DRAM space.

[0112] In some embodiments, the control unit is configured to: in response to the impending execution of an erase event of a memory block in the memory device, generate an erase command, and configure a portion of the free memory space of the memory controller as additional memory space for the write buffer.

[0113] In this embodiment of the application, when an erase command is generated after the erase event of a storage block in the memory device is about to be executed, the storage space of the write buffer is dynamically increased.

[0114] In some embodiments, the control unit is further configured to: during the period from the execution of the erase event to the completion of the erase event, configure another portion of the free storage space of the memory controller as another new storage space of the write buffer, and write data received from the host into the other new storage space of the write buffer; and release the other new storage space of the write buffer in response to the completion of the erase event.

[0115] In this embodiment of the application, the storage space of the write buffer can be dynamically increased before the erase event is executed; and the storage space of the write buffer can also be dynamically increased during the period from the execution of the erase event to the completion of the erase event.

[0116] In various embodiments of this application, the control unit of the memory system is configured to dynamically increase the storage space of the write buffer. Specifically, when an erase event of a memory block in the memory system is detected to be about to occur, the storage space of the write buffer is briefly increased. The increased write buffer is used to cache write data sent by the host during the erase operation. After the erase operation is completed, the write buffer is restored to its original size. During the erase operation, the storage space available to the write buffer includes the original storage space of the write buffer and the increased storage space. After the erase operation is completed, the increased storage space of the write buffer is released. In this way, by using the expanded storage space of the write buffer to buffer write data sent by the host during the erase operation, the latency caused by the write buffer not having its storage space increased and thus not being able to respond to the host's write data during the erase operation is alleviated, thereby reducing the write latency generated during the erase operation and improving the performance of the memory system.

[0117] In a second aspect, embodiments of this application provide an operation method for a memory system, comprising: in response to the impending execution of an erase event of a memory block in a memory device coupled to a memory controller of the memory system, a control unit of the memory controller configures a portion of the free memory space of the memory controller as additional memory space for a write buffer of the memory controller coupled to the control unit; in response to the execution of the erase event, writing data received from a host coupled to the memory controller into the additional memory space of the write buffer; and in response to the completion of the erase event, releasing the additional memory space of the write buffer.

[0118] refer to Figure 10 and Figure 7 In response to a write command sent by the host, the data transmitted by the host is buffered into a write buffer. When the data in the write buffer accumulates to a certain amount, a programming operation is performed on the memory device, writing / programming the accumulated data in the write buffer to the memory device all at once. An erase event may be triggered during the programming operation; for example, an erase event is triggered each time a new memory block is used.

[0119] refer to Figure 10 and Figure 8 Because an erase event is triggered during the programming operation, data cannot be written to the memory device during the erase operation itself, causing the programming operation to stop. (Reference) Figure 10 Step S101 can detect the timing of an erase event, such as the impending execution of an erase event in response to a memory block in the memory device; see reference. Figure 10 Step S102: Configure a portion of the memory controller's free storage space as an extended write buffer; refer to Figure 10 In step S103, in response to the execution of the erase event, the data received from the host is written to the storage space of the extended write buffer. During the erase operation, the storage space of the extended write buffer can be used to increase the amount of data buffered by the host to the extended write buffer.

[0120] refer to Figure 10 and Figure 9 In response to the completion of the erase event, the storage space of the extended write buffer is released, and the extended write buffer becomes a free buffer. (See reference) Figure 10 Step S104: Determine whether the erase event has been completed; refer to Figure 10 In step S105, after the erase operation is completed, the extended write buffer is released as a free buffer. This avoids occupying the memory controller's storage space after the erase operation is completed.

[0121] In some embodiments, reference Figure 10 If no erasure event is detected in step S106, step S101 can be executed to detect whether to trigger an erasure event.

[0122] In some embodiments, reference Figure 10 If the erase event is not completed in step S107, step S103 can be executed to buffer the written data in the extended write buffer.

[0123] The memory system operation method provided in this application embodiment detects the occurrence of an erase event through the file system (FW), requests an extended write buffer based on the existing write buffer, writes host data to the extended write buffer until the erase operation of the memory device is completed, and finally releases the extended write buffer as a free buffer. This memory system operation method allows the FW to adjust the size of the extended write buffer, reducing the impact of the erase operation on write latency.

[0124] The memory system operation method provided in this application embodiment can be detected in continuous / random write scenarios. In sequential write scenarios, the memory system operation method can allocate the size of an additional extended write buffer according to the short duration (during the erase operation) to reduce the high latency that occurs during the erase operation, such as reducing the write latency per input / output.

[0125] In some embodiments, a portion of the free storage space of the memory controller is allocated to the write buffer, the operation method including: in response to erase events of different storage blocks, the newly added storage space allocated to the write buffer is of the same size.

[0126] In some embodiments, the operation method includes: writing data stored in the write buffer into the memory device in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold.

[0127] In some embodiments, the operation method includes: in response to the memory device needing to open a new memory block for data writing, controlling the memory device to perform an erase operation on the new memory block before writing data to the new memory block; wherein the start of the erase operation is the execution of the erase event, and the end of the erase operation is the completion of the erase event.

[0128] In some embodiments, the operation method includes: in response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold, and the memory device needing to open a new storage block for data writing, determining that an erase event of the memory device is about to be executed, generating an erase command, and sending the erase command to the memory device.

[0129] In some embodiments, releasing the newly added storage space of the write buffer includes: in response to the completion of an erase event, writing data in the original storage space of the write buffer and data in the newly added storage space of the write buffer to a memory device in the order of writing; and in response to the completion of writing data in the newly added storage space of the write buffer to the memory device, releasing the newly added storage space of the write buffer.

[0130] In various embodiments of this application, the method for dynamically increasing the storage space of the write buffer specifically involves: when an erase event of a memory block in the memory system is detected to be about to occur, briefly increasing the storage space of the write buffer. This increased write buffer is used to cache write data sent by the host during the erase operation. After the erase operation is completed, the write buffer is restored to its original size. During the erase operation, the storage space available to the write buffer includes the original storage space of the write buffer and the increased storage space. After the erase operation is completed, the increased storage space of the write buffer is released. In this way, by utilizing the expanded storage space of the write buffer to buffer write data sent by the host during the erase operation, the latency caused by the write buffer not having its storage space increased and thus failing to respond to the host's write data during the erase operation is alleviated, thereby reducing the write latency generated during the erase operation and improving the performance of the memory system.

[0131] refer to Figure 11 , Figure 11 This is a schematic diagram illustrating the structural composition of a storage medium provided in an embodiment of this application. Thirdly, embodiments of this application provide a storage medium, such as... Figure 11 As shown, the storage medium stores executable instructions, which, when executed by a processor, implement the steps of an operation method for any memory system provided in the second aspect.

[0132] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0133] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0134] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0135] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0136] In some specific embodiments, reference is made to Figure 11 , Figure 11 This is a schematic diagram of the composition structure of a storage medium provided in an embodiment of this application; wherein, the storage medium includes a portion of the storage medium corresponding to the memory system 102; the portion of the storage medium can be used to implement the steps of the operation method of the memory system in the above embodiments of this application.

[0137] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0138] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A memory system, characterized in that, It includes at least one memory device and a memory controller; the memory controller is coupled to both the host and the memory device, and includes a write buffer and a control unit coupled to the write buffer; the control unit is configured to: In response to the impending execution of an erase event of a memory block in the memory device, a portion of the free memory space of the memory controller is configured as additional memory space for the write buffer; In response to the execution of the erase event, the data received from the host is written to the newly added storage space of the write buffer; In response to the completion of the erase event, the newly added storage space of the write buffer is released.

2. The memory system according to claim 1, characterized in that, The control unit is configured to: In response to different erase events of the memory blocks, the amount of new storage space allocated to the write buffer is the same.

3. The memory system according to claim 2, characterized in that, The amount of new storage space allocated to the write buffer is positively correlated with the average duration of the erase event of the storage block.

4. The memory system according to claim 1, characterized in that, The control unit is configured to: In response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold, the data stored in the write buffer is written into the memory device.

5. The memory system according to claim 4, characterized in that, The control unit is configured to: In response to the memory device needing to open a new memory block for data writing, before writing data to the new memory block, the memory device is controlled to perform an erase operation on the new memory block; wherein, the start of the erase operation is the execution of the erase event, and the end of the erase operation is the completion of the erase event.

6. The memory system according to claim 5, characterized in that, The control unit is configured to: In response to the fact that the amount of data stored in the original storage space of the write buffer is greater than or equal to the preset threshold, and the memory device needs to open a new storage block for data writing, it is determined that the erase event of the memory device is about to be executed, an erase command is generated, and the erase command is sent to the memory device.

7. The memory system according to claim 1, characterized in that, The control unit is configured to: In response to the completion of the erase event, the data in the original storage space of the write buffer and the data in the newly added storage space of the write buffer are written to the memory device in the order of the time of writing to the original storage space of the write buffer and the newly added storage space of the write buffer. In response to the completion of writing data from the newly added storage space of the write buffer to the memory device, the newly added storage space of the write buffer is released.

8. The memory system according to claim 1, characterized in that, The original storage space of the write buffer is smaller than the preset storage space.

9. The memory system according to claim 1, characterized in that, The memory controller further includes a volatile memory device, a portion of which is used as the original memory space of the write buffer and the additional memory space of the write buffer.

10. The memory system according to claim 9, characterized in that, The memory device includes NAND, and the volatile memory device includes SRAM / DRAM.

11. The memory system according to claim 1, characterized in that, The memory system includes enterprise-grade solid-state drives (eSSDs).

12. A method for operating a memory system, characterized in that, include: In response to the impending execution of an erase event of a memory block in a memory device coupled to the memory controller of the memory system, the control unit of the memory controller configures a portion of the free memory space of the memory controller as additional memory space for the write buffer of the memory controller coupled to the control unit. In response to the execution of the erase event, data received from the host coupled to the memory controller is written to the newly added storage space of the write buffer; In response to the completion of the erase event, the newly added storage space of the write buffer is released.

13. The operating method according to claim 12, characterized in that, The method of allocating a portion of the free storage space of the memory controller to the write buffer includes: In response to different erase events of the memory blocks, the amount of new storage space allocated to the write buffer is the same.

14. The operating method according to claim 12, characterized in that, The operation method includes: In response to the amount of data stored in the original storage space of the write buffer being greater than or equal to a preset threshold, the data stored in the write buffer is written into the memory device.

15. The operating method according to claim 14, characterized in that, The operation method includes: In response to the memory device needing to open a new memory block for data writing, before writing data to the new memory block, the memory device is controlled to perform an erase operation on the new memory block; wherein, the start of the erase operation is the execution of the erase event, and the end of the erase operation is the completion of the erase event.

16. The operating method according to claim 15, characterized in that, The operation method includes: In response to the fact that the amount of data stored in the original storage space of the write buffer is greater than or equal to the preset threshold, and the memory device needs to open a new storage block for data writing, it is determined that the erase event of the memory device is about to be executed, an erase command is generated, and the erase command is sent to the memory device.

17. The operating method according to claim 12, characterized in that, The operation method for releasing the newly added storage space of the write buffer includes: In response to the completion of the erase event, the data in the original storage space of the write buffer and the data in the newly added storage space of the write buffer are written to the memory device in the order of writing. In response to the completion of writing data from the newly added storage space of the write buffer to the memory device, the newly added storage space of the write buffer is released.

18. A storage medium, characterized in that, The storage medium stores executable instructions, which, when executed, implement the steps of the operation method as described in any one of claims 12 to 17.

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