Instruction scheduling method, system, apparatus, device, storage medium and program product

Abstract

The application relates to an instruction scheduling method, system, device, equipment, storage medium and program product. The method comprises the following steps: a first processor in a heterogeneous chip constructs a conditional execution instruction according to a target instruction set architecture; and the first processor sends the conditional execution instruction to a second processor, wherein the conditional execution instruction carries instruction parameter information, and the instruction parameter information is used for instructing the second processor to detect an execution state of an associated instruction of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instruction of the conditional execution instruction according to the execution state of the associated instruction. The method can reduce the CPU instruction scheduling overhead and improve the CPU performance.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an instruction scheduling method, system, apparatus, device, storage medium, and program product. Background Technology

[0002] Heterogeneous chips refer to chips composed of different types of computing units, including central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs).

[0003] In heterogeneous chip instruction scheduling systems, a circular buffer is typically used to facilitate instruction exchange between different computing units. Taking CPU and GPU as an example, in related technologies, the CPU generates instructions that the GPU needs to execute based on task requirements and schedules these instructions to the circular buffer. The GPU then reads the instructions from the circular buffer for processing. The CPU is usually responsible for deciding which data processing instructions to issue, and the GPU executes the computational tasks based on these instructions. When handling complex and large-scale computations, the CPU needs to determine which instruction to issue next based on real-time conditions. For example, the CPU may need data in a certain memory block to exceed a specified value before proceeding with subsequent calculations. Accessing memory data and writing new instructions to the circular buffer both incur overhead, and the CPU risks becoming a performance bottleneck.

[0004] Therefore, how to reduce the overhead of CPU instruction scheduling and improve CPU performance has become an urgent technical problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide an instruction scheduling method, system, device, equipment, storage medium, and program product to address the above-mentioned technical problems, which can reduce the CPU's overhead in instruction scheduling and improve CPU performance.

[0006] In a first aspect, embodiments of this application provide an instruction scheduling method applied to a first processor in a heterogeneous chip; the heterogeneous chip further includes a second processor of a different type from the first processor; the method includes:

[0007] Instructions are executed based on conditions constructed according to the target instruction set architecture.

[0008] A conditional execution instruction is sent to the second processor. The conditional execution instruction carries instruction parameter information, which instructs the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0009] In one embodiment, constructing conditional execution instructions based on target instruction set architecture information includes:

[0010] Obtain the instruction parameter information for the conditional execution instruction; the instruction parameter information includes the instruction opcode, read address, reference data, and number of conditional executions.

[0011] Based on the target instruction set architecture, the instruction parameter information is combined to obtain the conditional execution instruction.

[0012] In one embodiment, the second processor includes an instruction read / write module; the instruction read / write module includes a circular buffer; sending conditional execution instructions to the second processor includes:

[0013] Get the latest address pointed to by the write pointer in the circular buffer;

[0014] Based on the latest address pointed to by the write pointer, the conditional execution instruction is written into the circular buffer.

[0015] Secondly, embodiments of this application also provide an instruction scheduling method applied to a second processor in a heterogeneous chip; the heterogeneous chip further includes a first processor of a different type from the second processor; the method includes:

[0016] Receive the conditional execution instruction sent by the first processor;

[0017] The conditional execution instruction is parsed to obtain the parameter information carried in the conditional execution instruction;

[0018] Based on the parameter information carried in the conditional execution instruction, detect the execution status of the associated instructions of the conditional execution instruction;

[0019] Based on the execution status of the associated instructions, the associated instructions of the conditional execution instructions are scheduled.

[0020] In one embodiment, the second processor includes a storage module; and detects the execution status of associated instructions of the conditional execution instruction based on parameter information carried in the conditional execution instruction, including:

[0021] Retrieve the data read address from the parameter information;

[0022] Based on the data read address, the corresponding data is read from the storage module to determine the candidate data;

[0023] Based on candidate data and parameter information, detect the execution status of associated instructions of conditional execution instructions.

[0024] In one embodiment, the execution status of the associated instructions of the conditional execution instruction is detected based on candidate data and parameter information, including:

[0025] Obtain reference data from the parameter information;

[0026] If the candidate data is less than the reference data, the execution status of the associated instruction is determined to be non-execution;

[0027] If the candidate data is greater than or equal to the reference data, the execution status of the associated instruction is determined to be "execution".

[0028] In one embodiment, the second processor further includes an instruction read / write module and multiple instruction status control modules; scheduling the associated instructions of the conditional execution instructions according to the execution status of the associated instructions, including:

[0029] If the execution status of the associated instruction is "executed", the associated instruction is sent to the instruction status control module that matches the instruction type of the associated instruction through the instruction read / write module, and the associated instruction is executed.

[0030] If the execution status of the associated instruction is "not executed", then the associated instruction is sent to the no-operation instruction status control module through the instruction read / write module.

[0031] In one embodiment, the instruction state control module further includes a conditional execution instruction state control module; the instruction read / write module includes a circular buffer;

[0032] When the instruction read / write module receives the execution status of the associated instruction from the conditional execution instruction status control module, it reads the associated instruction from the circular buffer according to the number of conditional executions in the parameter information, and sends the associated instruction to the corresponding instruction status control module according to the execution status.

[0033] Thirdly, embodiments of this application also provide an instruction scheduling system, which includes a heterogeneous chip, and the heterogeneous chip includes a first processor and a second processor;

[0034] The first processor is configured to implement the steps of the method described in any one of the first aspects above;

[0035] The second processor is used to implement the steps of the method described in any one of the second aspects above.

[0036] Fourthly, embodiments of this application also provide an instruction scheduling device, including:

[0037] The instruction construction module is used to construct conditional execution instructions based on the conditional execution identifier;

[0038] The instruction sending module is used to send conditional execution instructions to the second processor. The conditional execution instructions carry instruction parameter information, which instructs the second processor to detect the execution status of the associated instructions of the conditional execution instructions according to the parameter information carried in the conditional execution instructions, and to schedule the associated instructions of the conditional execution instructions according to the execution status of the associated instructions.

[0039] Fifthly, embodiments of this application also provide an instruction scheduling device, including:

[0040] The instruction receiving module is used to receive conditional execution instructions sent by the first processor;

[0041] The instruction parsing module is used to parse conditional execution instructions to obtain the parameter information carried in the conditional execution instructions;

[0042] The status detection module is used to detect the execution status of the associated instructions of the conditional execution instruction based on the parameter information carried in the conditional execution instruction.

[0043] The instruction scheduling module is used to schedule the associated instructions of conditional execution instructions based on the execution status of the associated instructions.

[0044] In a sixth aspect, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the embodiments of the first or second aspect described above.

[0045] In a seventh aspect, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the embodiments of the first or second aspect described above.

[0046] Eighthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method in any of the embodiments of the first or second aspect described above.

[0047] The instruction scheduling method, system, apparatus, device, storage medium, and program product provided in this application embodiment involve a first processor in a heterogeneous chip constructing a conditional execution instruction according to a target instruction set architecture, and then sending the conditional execution instruction to a second processor. The conditional execution instruction carries instruction parameter information, which is used to instruct the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions. In this method, after the first processor in the heterogeneous chip constructs the conditional execution instruction, it sends the conditional execution instruction to the second processor in the heterogeneous chip. The second processor detects the execution status of the associated instructions of the conditional execution instruction based on the parameter information carried in the conditional execution instruction. After obtaining the detection result, it schedules the associated instructions of the conditional execution instruction according to their execution status. In other words, the first processor only needs to construct the conditional execution instruction and send it to the second processor, while the second processor performs the detection of the execution status of the associated instructions and the scheduling of the associated instructions. In this way, by transferring the operation of instruction status detection and instruction scheduling to the second processor, the computational burden of the first processor is reduced and the performance of the first processor is improved. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a diagram illustrating the application environment of the instruction scheduling method in one embodiment;

[0050] Figure 2 This is a flowchart illustrating an instruction scheduling method in one embodiment;

[0051] Figure 3 This is a flowchart illustrating the construction of conditional execution instructions in one embodiment;

[0052] Figure 4 This is a flowchart illustrating the process of sending a conditional execution instruction to a second processor in one embodiment.

[0053] Figure 5 This is a schematic diagram illustrating instruction writing and reading in a circular buffer in one embodiment;

[0054] Figure 6 This is a flowchart illustrating the instruction scheduling method in another embodiment;

[0055] Figure 7 This is a flowchart illustrating the process of detecting the execution status of associated instructions in one embodiment;

[0056] Figure 8 This is a schematic diagram of a storage module in one embodiment;

[0057] Figure 9 This is a schematic diagram of a conditional execution instruction management system in one embodiment;

[0058] Figure 10 This is a schematic diagram of the instruction scheduling operation flow in one embodiment;

[0059] Figure 11 This is a state diagram of the conditional execution state control module in one embodiment;

[0060] Figure 12 This is a schematic diagram of the instruction scheduling device in one embodiment;

[0061] Figure 13 This is a schematic diagram of the instruction scheduling device in another embodiment;

[0062] Figure 14 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0064] The technical background of the embodiments of this application will be described below.

[0065] With the rapid development of Artificial Intelligence (AI) technology, the demand for computing power in fields such as computer vision, deep learning, and natural language processing has increased dramatically. In this context, the computing power provided by heterogeneous chips becomes particularly important. Heterogeneous chips refer to chips composed of different types of computing units, such as central processing units, graphics processing units, field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Their main purpose is to improve the flexibility, performance, and energy efficiency of computing systems by combining various computing resources. In the future, heterogeneous computing will continue to be a crucial cornerstone for the development of AI technology, providing computing power support for various innovative applications.

[0066] In heterogeneous computing systems, a ring buffer is typically used to facilitate data exchange between different computing units. Taking a CPU and GPU as an example, the CPU acts as the producer, writing instructions into the ring buffer, while the GPU acts as the consumer, reading instructions from the ring buffer. Writing and reading instructions are independent of each other. In current technology, the CPU is usually responsible for deciding which data processing instructions to issue, and another computing unit executes the computation task based on these instructions. When handling complex and large-scale computations, this approach requires the CPU to determine the next instruction to execute based on real-time conditions. For example, the CPU might need data in a certain memory block to exceed a specified value before proceeding with subsequent calculations. Accessing memory data and writing new instructions into the ring buffer both incur overhead, and the CPU risks becoming a performance bottleneck.

[0067] Based on this, this application provides an instruction scheduling method. After constructing a conditional execution instruction, the first processor in the heterogeneous chip sends the conditional execution instruction to the second processor in the heterogeneous chip. The second processor detects the execution status of the associated instructions of the conditional execution instruction based on the parameter information carried in the conditional execution instruction. After obtaining the detection result, it schedules the associated instructions of the conditional execution instruction according to their execution status. In other words, the first processor only needs to construct the conditional execution instruction and send it to the second processor. The detection process of the execution status of the associated instructions and the scheduling process of the associated instructions are both performed by the second processor. In this way, by transferring the operations of instruction status detection and instruction scheduling to the second processor, the computational burden of the first processor is reduced, and the performance of the first processor is improved. Of course, the technical solution provided in the embodiments of this application is not limited to solving only the above problems, and other technical effects also exist. For details, please refer to the following embodiments.

[0068] It should be noted that the beneficial effects or technical problems solved by the embodiments of this application are not limited to this one, but may also be other implicit or related problems. For details, please refer to the description of the embodiments below.

[0069] The following describes the application environment of the instruction scheduling method provided in the embodiments of this application, which can be applied to, for example... Figure 1In the application environment shown, the second processor 102 communicates with the first processor 104 via a network. Both the first processor 104 and the second processor 102 are located in heterogeneous chips, but they are of different types. After constructing a conditional execution instruction, the first processor 104 sends the conditional execution instruction to the second processor 102. This allows the second processor 102 to detect the execution status of the associated instructions based on the parameter information carried in the conditional execution instruction, and to schedule the associated instructions according to their execution status.

[0070] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0071] In one exemplary embodiment, such as Figure 2 As shown, an instruction scheduling method is provided, which can be applied to... Figure 1 Taking the first processor 104 as an example, the explanation includes the following steps 201 to 202. Wherein:

[0072] S201, execute instructions based on the conditions constructed according to the target instruction set architecture.

[0073] In this embodiment, the heterogeneous chip includes a first processor and a second processor of a different type. The first or second processor may include a CPU, GPU, FPGA, and ASIC, etc. When the first processor is one of a CPU, GPU, FPGA, and ASIC, the second processor can only be selected from the remaining processors. For example, if the first processor is a GPU, then the second processor can only be a CPU, FPGA, or ASIC. In this embodiment, the first processor is a CPU, and the second processor is a GPU, FPGA, or ASIC.

[0074] Conditional execution instructions are instructions that determine whether to execute a certain operation or instruction sequence based on specific conditions. They allow a computer to dynamically control the execution flow of a program based on various conditions during program execution, such as data comparison results and flag states. This enables the program to respond differently to different situations, thereby achieving more complex logic and functions. Conditional execution instructions first evaluate one or more conditions, and then, based on the result of these evaluations, determine whether to execute subsequent operations or instruction sequences.

[0075] The first processor needs to construct conditional execution instructions based on the target instruction set architecture, and then send the conditional execution instructions to the second processor.

[0076] In one embodiment, the target instruction set architecture can be obtained from the board-level configuration file of the heterogeneous chip. In the hardware design of heterogeneous chips, the board-level configuration file typically contains detailed information about the hardware components, including the processor model and instruction set architecture. This information can be obtained by reading the board-level configuration file during chip startup.

[0077] In another embodiment, the target instruction set architecture can be obtained through system calls or query interfaces provided by the operating system. During startup, the operating system performs a comprehensive hardware detection and identification, storing the hardware information in the system's data structure. Heterogeneous chips can obtain instruction set architecture information through system calls or query interfaces provided by the operating system.

[0078] The method for constructing conditional execution instructions based on the target instruction set architecture can be as follows: First, determine the condition judgment requirements, including the scenario and type of condition judgment. Then, based on the condition judgment requirements, select suitable instructions from the instruction set manual of the target instruction set architecture. Next, set the operands. Finally, combine the selected instructions and set operands according to the instruction format specified by the target instruction set architecture, and encode the combined instructions according to the encoding rules of the target instruction set architecture to obtain the constructed conditional execution instructions.

[0079] S202, a conditional execution instruction is sent to the second processor. The conditional execution instruction carries instruction parameter information, which is used to instruct the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0080] After constructing the conditional execution instruction, the first processor sends the conditional execution instruction to the second processor, so that the second processor can detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0081] Among them, the associated instructions of a conditional execution instruction refer to other instructions that are closely related to the conditional execution instruction in terms of function, operation, or execution logic. For example, the associated instructions of a conditional execution instruction can be the instructions that are actually executed after the condition is judged in the conditional execution instruction, or they can be instructions that are related to the conditional execution instruction before (or after) it.

[0082] After receiving the conditional execution instruction from the first processor, the second processor checks the execution status of the associated instructions based on the instruction parameter information carried in the conditional execution instruction; that is, it checks whether the associated instructions of the conditional execution instruction should be executed. After obtaining the execution status of the associated instructions, it performs scheduling according to them. For example, if it detects that an associated instruction of the conditional execution instruction needs to be executed, it schedules the associated instructions to the target operation unit in the second processor, whereby the second processor executes the associated instructions. The target operation unit contains the instructions that the second processor needs to execute; if an instruction is detected in the target operation unit, it executes the instruction and obtains the processing result for that instruction.

[0083] In the instruction scheduling method provided in this application embodiment, the first processor in the heterogeneous chip constructs a conditional execution instruction according to the target instruction set architecture, and then sends the conditional execution instruction to the second processor. The conditional execution instruction carries instruction parameter information, which is used to instruct the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions. In this method, after the first processor in the heterogeneous chip constructs the conditional execution instruction, it sends the conditional execution instruction to the second processor in the heterogeneous chip. The second processor detects the execution status of the associated instructions of the conditional execution instruction based on the parameter information carried in the conditional execution instruction. After obtaining the detection result, it schedules the associated instructions of the conditional execution instruction according to their execution status. In other words, the first processor only needs to construct the conditional execution instruction and send it to the second processor, while the second processor performs the detection of the execution status of the associated instructions and the scheduling of the associated instructions. In this way, by transferring the operation of instruction status detection and instruction scheduling to the second processor, the computational burden of the first processor is reduced and the performance of the first processor is improved.

[0084] Based on the above embodiments, an embodiment of the process of executing the above-described construction conditions instructions will be provided for illustration.

[0085] In one exemplary embodiment, such as Figure 3 As shown, conditional execution instructions are constructed based on the target instruction set architecture information, including:

[0086] S301, obtain the instruction parameter information of the conditional execution instruction; the instruction parameter information includes the instruction opcode, read address, reference data, and conditional execution quantity.

[0087] In this embodiment, the instruction parameter information of the conditional execution instruction includes the instruction opcode, read address, reference data, and conditional execution count. The instruction opcode is used to identify the conditional execution instruction; the read address is the starting and destination address of this read operation; the reference data is the comparison object for the data read in this read operation, and its content is specified by the first processor; the conditional execution count represents how many dword-length instructions following the conditional execution command in the circular buffer are included in the decision-making process.

[0088] S302 combines instruction parameter information according to the target instruction set architecture to obtain conditional execution instructions.

[0089] Instruction set architecture is the interface between hardware and software in a computer system. It defines the set of instructions that computer hardware can understand and execute, as well as the specifications such as the format, operand types, and addressing modes of these instructions.

[0090] The target instruction set architecture includes specific instruction formats, encoding rules, and instruction set specifications. When constructing conditional execution instructions, these specifications of the target instruction set must be followed.

[0091] For example, after obtaining the instruction opcode, read address, reference data, and conditional execution count, the instruction opcode, read address, reference data, and conditional execution count are combined according to the instruction format specified in the target instruction set architecture. Then, the combined instructions are encoded according to the encoding rules of the target instruction set architecture, converting the instructions into binary code that the computer hardware can recognize, thus obtaining candidate conditional execution instructions. These candidate conditional execution instructions are then integrated into the test program and run in a simulator or actual hardware environment to check whether the instructions are executed according to the expected conditions. If the test results do not meet expectations, debugging tools (such as debuggers, logic analyzers, etc.) are used to debug the program, find the problem, and optimize the candidate conditional execution instructions to obtain the conditional execution instructions.

[0092] In the instruction scheduling method provided in this application embodiment, the first processor obtains the instruction parameter information of a conditional execution instruction, and then combines the instruction parameter information according to the target instruction set architecture to obtain the conditional execution instruction. The instruction parameter information includes the instruction opcode, read address, reference data, and the number of conditional executions. This method, after obtaining the instruction parameter information of the conditional execution instruction, combines the instruction parameters based on the target instruction set architecture to obtain the conditional execution instruction. This ensures that the conditional execution instruction conforms to the instruction format and other specifications of the encoding rules, guaranteeing that the instruction can be correctly identified and executed, and improving the reliability of the conditional execution instruction.

[0093] Based on the above embodiments, an embodiment of the process of sending conditional execution instructions to the second processor will be described.

[0094] In one exemplary embodiment, such as Figure 4 As shown, the second processor includes an instruction read / write module; the instruction read / write module includes a circular buffer; sending conditional execution instructions to the second processor includes:

[0095] S401, retrieves the latest address pointed to by the write pointer in the circular buffer.

[0096] A circular buffer is essentially a fixed-size array that tracks the read and write positions of data using two key elements (read pointer and write pointer) or their corresponding indices. The write pointer indicates where new data should be written, while the read pointer marks the position of the next piece of data to be read. As data is written and read, the pointers move cyclically through the buffer array, forming a circular operating pattern.

[0097] For example, the way to obtain the latest address pointed to by the write pointer in the circular buffer can be to send an address acquisition request to the instruction read / write module. When the instruction read / write module receives the address acquisition request sent by the first processor, it feeds back the address pointed to by the write pointer in the circular buffer to the first processor, and the first processor determines the address as the latest address pointed to by the write pointer in the circular buffer.

[0098] When the first processor wants to write data to the circular buffer, the write pointer points to the currently writable address. After the write operation is complete, the write pointer is updated to the next available address. At this point, the system can send the memory address pointed to by the write pointer back to the processor, so the processor knows where the new data has been stored.

[0099] S402 writes the conditional execution instruction into the circular buffer based on the latest address pointed to by the write pointer.

[0100] After obtaining the latest address pointed to by the write pointer in the circular buffer, the first processor writes the conditional execution instruction into the circular buffer based on the latest address.

[0101] The latest instruction is written to the next address in the circular buffer. The circular buffer is a first-in, first-out (FIFO) buffer with a depth of M bytes and an address range of 0 to M-1 bytes. When an instruction is written to the last address M-1 of the circular buffer, it restarts from address 0. Instructions written first are read first. For example... Figure 5 The diagram shown illustrates the writing and reading of instructions in a circular buffer.

[0102] In the instruction scheduling method provided in this application embodiment, the latest address pointed to by the write pointer in the circular buffer is first obtained, and then the conditional execution instruction is written into the circular buffer according to the latest address pointed to by the write pointer. In this method, the circular buffer is set in the instruction read / write module of the second processor. When the first processor sends a conditional execution instruction to the second processor, it obtains the latest data pointed to by the write pointer in the circular buffer as the write address of the conditional execution instruction, and then writes the conditional execution instruction into the circular buffer in the instruction read / write module according to the address, thus providing a data basis for the second processor to perform instruction scheduling.

[0103] The above describes embodiments with the first processor as the execution subject. Based on this, this application also provides embodiments corresponding to the above process with a second processor as the execution subject. Below, embodiments of the instruction scheduling method with a second processor as the execution subject will be described.

[0104] In one exemplary embodiment, such as Figure 6 As shown, an instruction scheduling method is provided, applied to a second processor in a heterogeneous chip, wherein the heterogeneous chip also includes a first processor of a different type from the second processor; the method includes:

[0105] S501 receives a conditional execution instruction sent by the first processor.

[0106] After constructing the conditional execution instruction according to the target instruction set architecture, the first processor sends the conditional execution instruction to the second processor and writes the conditional execution instruction into the circular buffer in the instruction read / write module of the second processor.

[0107] S502 performs instruction parsing on the conditional execution instruction to obtain the parameter information carried in the conditional execution instruction.

[0108] After receiving a conditional execution instruction, the instruction read / write module reads the conditional execution instruction from the circular buffer and sends it to the conditional execution instruction status control module in the second processor, which then parses the conditional execution instruction.

[0109] After receiving a conditional execution instruction, the conditional execution instruction status control module parses the instruction to obtain the parameter information carried in it.

[0110] S503 detects the execution status of the associated instructions of the conditional execution instruction based on the parameter information carried in the conditional execution instruction.

[0111] After parsing the parameter information carried in the conditional execution instruction, the conditional execution instruction status control module detects the execution status of the associated instructions based on the parameter information.

[0112] For example, the method for detecting the execution status of associated instructions of a conditional execution instruction based on the parameter information carried in the conditional execution instruction can be to obtain target data from the target location based on the parameter information carried in the conditional execution instruction, and then detect the execution status of the associated instructions of the conditional execution instruction based on the target data. For example, the target data can be compared with a preset value, and the execution status of the associated instructions of the conditional execution instruction can be determined based on the comparison result. If the target data is greater than or equal to the preset value, the execution status of the associated instructions of the conditional execution instruction is determined to be executed; otherwise, it is determined to be not executed.

[0113] S504 schedules the associated instructions of the conditional execution instructions according to the execution status of the associated instructions.

[0114] After obtaining the execution status of the associated instruction of the conditional execution instruction, the associated instruction is scheduled according to its execution status. For example, when it is detected that the associated instruction of the conditional execution instruction needs to be executed, the associated instruction of the conditional execution instruction is scheduled to the target operation unit in the second processor, and the second processor executes the associated instruction of the conditional execution instruction.

[0115] In the instruction scheduling method provided in this application embodiment, the second processor receives a conditional execution instruction sent by the first processor. First, it parses the conditional execution instruction to obtain the parameter information carried in the instruction. Then, based on the parameter information, it detects the execution status of the associated instructions of the conditional execution instruction and schedules them accordingly. In this method, after constructing the conditional execution instruction, the first processor in the heterogeneous chip sends it to the second processor. The second processor detects the execution status of the associated instructions based on the parameter information carried in the conditional execution instruction. After obtaining the detection result, it schedules the associated instructions based on their execution status. Essentially, the first processor only needs to construct the conditional execution instruction and send it to the second processor. The detection and scheduling processes for the associated instructions are performed by the second processor. By transferring both instruction status detection and instruction scheduling to the second processor, the computational burden on the first processor is reduced, and its performance is improved.

[0116] Based on the above embodiments, an embodiment is provided to illustrate the process of executing the associated instructions of the above detection condition execution instructions.

[0117] In one exemplary embodiment, such as Figure 7As shown, the second processor includes a storage module; based on the parameter information carried in the conditional execution instruction, it detects the execution status of the associated instructions of the conditional execution instruction, including:

[0118] S601, retrieve the data read address from the parameter information.

[0119] The conditional execution instruction carries a read address among its parameter information. After parsing the conditional execution instruction to obtain the parameter information, the read address is retrieved from the parameter information and determined as the data read address.

[0120] S602, based on the data read address, reads the corresponding data from the storage module to determine it as candidate data.

[0121] After obtaining the data read address, the conditional execution instruction status control module initiates a read request to the storage module in the second processor to read the data corresponding to the data read address from the storage module, and uses the read data as candidate data.

[0122] In this embodiment, the storage module mainly performs variable storage, read operations, and write operations, such as... Figure 8 As shown. Storage methods can include registers, SRAM (Static Random-Access Memory), DDR (Double Data Rate Synchronous Dynamic Random-Access Memory), HBM (High Bandwidth Memory), etc., without restriction. The storage space range is the maximum value that the address width in the conditional execution instruction can represent. When the memory receives a write operation from the conditional execution instruction status control module, the memory module will write the new variable data into the corresponding memory cell according to the write address and write data. No write operations to memory are involved during the execution of the conditional execution instruction.

[0123] S603, based on candidate data and parameter information, detects the execution status of the associated instructions of the conditional execution instruction.

[0124] After reading the candidate data, the execution status of the associated instructions of the conditional execution instruction is detected based on the candidate data and parameter information.

[0125] For example, the reference data in the parameter information is obtained; if the candidate data is less than the reference data, the execution status of the associated instruction is determined to be non-execution; if the candidate data is greater than or equal to the reference data, the execution status of the associated instruction is determined to be execution.

[0126] In this embodiment, reference data is obtained from the parameter information and compared with candidate data to determine the execution status of the associated instruction of the conditional execution instruction based on the comparison result. If the candidate data is less than the reference data, the execution status of the associated instruction of the conditional execution instruction is determined to be non-execution; conversely, if the candidate data is greater than or equal to the reference data, the execution status of the associated instruction of the conditional execution instruction is determined to be execution.

[0127] In the instruction scheduling method provided in this application embodiment, the data read address in the parameter information is first obtained. Then, based on the data read address, the corresponding data is read from the storage module to determine the candidate data. Afterwards, based on the candidate data and the parameter information, the execution status of the associated instruction of the conditional execution instruction is detected. This method obtains the data read address from the parameter information and requests candidate data from the storage module based on the read address. Based on this candidate data, the execution status of the associated instruction is accurately detected, thereby achieving accurate scheduling of the associated instruction.

[0128] Based on the above embodiments, an embodiment of the process of the above scheduling association instruction is provided for description.

[0129] In an exemplary embodiment, the second processor further includes an instruction read / write module and multiple instruction status control modules; scheduling the associated instructions of conditional execution instructions according to the execution status of the associated instructions, including:

[0130] If the execution status of the associated instruction is "executed", the associated instruction is sent to the instruction status control module that matches the instruction type of the associated instruction through the instruction read / write module, and the associated instruction is executed; if the execution status of the associated instruction is "not executed", the associated instruction is sent to the no-operation instruction status control module through the instruction read / write module.

[0131] If the execution status of an associated instruction is "executed," the associated instruction needs to be sent to the instruction status control module that matches its instruction type. The instruction read / write module then forwards the associated instruction to the corresponding instruction status control module, where it is processed—that is, executed. For example, if the associated instruction is a Poll instruction, the instruction status control module matching its instruction type is the Poll instruction status control module; if the associated instruction is a Reg Write instruction, the instruction status control module matching its instruction type is the Reg Write instruction status control module.

[0132] If the execution status of an associated instruction is "not executed," the associated instruction needs to be sent to the No Operation instruction status control module. This is done via the instruction read / write module. For example, if the execution status of an associated instruction is "not executed," it is treated as a No Operation instruction and sent to the No Operation instruction status control module.

[0133] In one embodiment, the instruction status control module further includes a conditional execution instruction status control module; the instruction read / write module includes a circular buffer; when the instruction read / write module receives the execution status of the associated instruction sent by the conditional execution instruction status control module, it reads the associated instruction from the circular buffer according to the number of conditional executions in the parameter information, and sends the associated instruction to the corresponding instruction status control module according to the execution status.

[0134] In this embodiment, after determining the execution status of the associated instruction of the conditional execution instruction, the conditional execution instruction status control module sends the execution status of the associated instruction to the instruction read / write module. Upon receiving the execution status of the associated instruction, the instruction read / write module first determines the corresponding instruction status control module based on the execution status of the associated instruction. For example, if the execution status is "not executed," it corresponds to the "No Operation" instruction status control module; if the execution status is "executed," it determines the corresponding instruction status control module based on the instruction type of the associated instruction. Secondly, the instruction read / write module reads the associated instructions from the circular buffer according to the number of conditional executions in the parameter information; that is, the instruction read / write module reads a specified number of instructions of dword length sequentially from the circular buffer as associated instructions. Finally, the associated instructions are written into the corresponding instruction status control module. The associated instructions are written to the circular buffer by the first processor along with the conditional execution instructions.

[0135] It is understood that in this embodiment of the application, the first processor and the second processor only interact when writing conditional execution instructions and associated instructions. All other operations are completed by the second processor alone, which reduces the data transmission requirements between the first processor and the second processor and makes the overall system efficiency higher.

[0136] In the instruction scheduling method provided in this application embodiment, the second processor further includes an instruction read / write module and multiple instruction status control modules. If the execution status of an associated instruction is "executed," the instruction read / write module sends the associated instruction to the instruction status control module that matches the instruction type of the associated instruction, and executes the associated instruction. If the execution status of the associated instruction is "not executed," the instruction read / write module sends the associated instruction to the no-operation instruction status control module. In this method, by setting different types of instruction status control modules, after detecting the execution status of the associated instruction, the instruction read / write module writes the associated instruction into the matching instruction status control module, thus completing the fast and accurate scheduling of the associated instruction.

[0137] In addition, a conditional execution instruction management system is described in an exemplary embodiment.

[0138] like Figure 9 As shown, the conditional execution instruction management system includes three modules: an instruction reading and writing module, a conditional execution status control module (i.e., the conditional execution instruction status control module in the aforementioned embodiment), and a storage module.

[0139] The instruction scheduling operation process is as follows: Figure 10 As shown.

[0140] 1. The first processor writes conditional execution instructions and other instructions sequentially into the Ring Buffer. The latest instruction is written to the end of the instruction Ring Buffer. The Ring Buffer is a first-in, first-out circular buffer with a depth of M bytes and an address range of 0 to M-1 bytes. When an instruction is written to the last address M-1 of the Ring Buffer, it restarts from address 0.

[0141] 2. When the Ring Buffer is not empty, it indicates that a new instruction has been written. At this time, the instruction read / write module will actively send the conditional execution instruction to the conditional execution status control module. The length of each instruction sent is L. L has a minimum of 1 byte and a maximum of the instruction length.

[0142] 3. The conditional execution status control module parses the conditional execution instructions, extracting information such as the read address, reference data, and number of condition executions.

[0143] 4. The conditional execution status control module initiates a read operation request to the storage module based on the read address.

[0144] 5. After receiving a read operation request, the storage module returns the read data to the condition execution status control module according to the read address.

[0145] 6. After a successful read operation, the conditional execution status control module compares the read data with the reference data. If the read data is less than the reference data, the instruction read / write module treats the following specified number of dword-length instructions read sequentially from the Ring Buffer as No Operation instructions and sends them to the No Operation instruction status control module. Otherwise, the instruction read / write module continues to read instructions sequentially from the Ring Buffer and sends them to the instruction status control module that matches the instruction type of the read instructions.

[0146] 7. After completing the current instruction, the conditional execution status control module sends the completion status to the first processor and returns to the idle state, waiting for the next conditional execution instruction.

[0147] The state diagram of the conditional execution state control module is as follows: Figure 11 As shown. First, in the initial state, the conditional execution state control module is in an idle state. When the conditional execution state control module receives a conditional execution instruction from the instruction read / write module, it enters the instruction parsing state. It obtains information such as the read address, reference data, and the number of conditional executions carried by the instruction. Then, it enters the read operation state, sends a read operation request to the memory, and waits for a response. Next, after a successful read operation, it enters the comparison state, comparing whether the read return data is greater than the reference data. If the read return data is less than the reference data, the instruction read / write module treats the next specified number of dword-length instructions read sequentially from the Ring Buffer as NoOperation instructions and sends them to the NoOperation instruction state control module. Otherwise, the instruction read / write module continues to read instructions sequentially from the Ring Buffer and sends them to the instruction state control module that matches the instruction type of the read instruction. After the comparison is complete, it enters the completion state. Finally, it returns to the idle state, waiting for the next conditional execution instruction.

[0148] The instruction scheduling process in the embodiments of this application will be described below by way of example.

[0149] Implementation Method 1:

[0150] 1. Initially, the Ring Buffer contains no conditional execution instructions or other instructions written by the first processor; its address is 0, and its size is 1 MB. When the first processor writes instructions to the Ring Buffer, it starts from address 0, writing the conditional execution instructions first, and then writing the other instructions sequentially. The conditional execution instructions prepared by the first processor include: a conditional execution identifier of 0x10 (OP CODE, user-defined), a read address of 0x16, reference data of 0x5, and a conditional execution count of 0x20. Each conditional execution instruction is 20 bytes long, including a 4-byte instruction header, 8 bytes of write address information, 4 bytes of reference data information, and 4 bytes of conditional execution count information. Typically, to simplify software address management, conditional execution instructions are defined as 4-byte aligned instructions.

[0151] 2. When the Ring Buffer is not empty, it indicates that an instruction has been written to the Ring Buffer. At this time, the instruction read / write module will actively send an instruction to the conditional execution status control module.

[0152] 3. The conditional execution status control module will parse the conditional execution instructions and extract information such as the read address, reference data, and number of conditional executions for each instruction.

[0153] 4. The conditional execution status control module initiates a read operation request to the storage module based on the read address.

[0154] 5. After receiving a read operation, the storage module returns the read data to the condition execution status control module according to the read address.

[0155] 6. After a successful read operation, the conditional execution status control module compares the read data with the reference data. If the read data is 0x0, which is less than the reference data 0x5, the instruction read / write module will read the 0x20 dword-length instructions sequentially from the Ring Buffer as No Operation instructions and send them to the No Operation instruction status control module.

[0156] 7. After completing the current instruction, the conditional execution status control module sends the completion status to the first processor and returns to the idle state, waiting for the next conditional execution instruction.

[0157] Implementation Method Two:

[0158] 1. Initially, the Ring Buffer contains no conditional execution instructions or other instructions written by the first processor; its address is 0, and its size is 1 MB. When the first processor writes instructions to the Ring Buffer, it starts from address 0, writing the conditional execution instructions first, and then writing the other instructions sequentially. The conditional execution instructions prepared by the first processor include: a conditional execution identifier of 0x10 (OP CODE, user-defined), a read address of 0x16, reference data of 0x5, and a conditional execution count of 0x20. Each conditional execution instruction is 20 bytes long, including a 4-byte instruction header, 8 bytes of write address information, 4 bytes of reference data information, and 4 bytes of conditional execution count information. Typically, to simplify software address management, conditional execution instructions are defined as 4-byte aligned instructions.

[0159] 2. When the Ring Buffer is not empty, it indicates that an instruction has been written to the Ring Buffer. At this time, the instruction read / write module will actively send an instruction to the conditional execution status control module.

[0160] 3. The conditional execution status control module will parse the conditional execution instructions and extract information such as the read address, reference data, and number of conditional executions for each instruction.

[0161] 4. The conditional execution status control module initiates a read operation request to the storage module based on the read address.

[0162] 5. After receiving a read operation, the storage module returns the read data to the condition execution status control module according to the read address.

[0163] 6. After a successful read operation, the conditional execution status control module compares the read data with the reference data. If the read data is 0x6, which is greater than the reference data 0x5, the instruction read / write module will continue to read instructions from the Ring Buffer in sequence and send them to the instruction status control module that matches the instruction type of the read instruction.

[0164] 7. After completing the current instruction, the conditional execution status control module sends the completion status to the first processor and returns to the idle state, waiting for the next conditional execution instruction.

[0165] The instruction scheduling method of this application embodiment has the following advantages: Performance improvement; it executes only a specified number of subsequent instructions after the conditional execution instruction is met, avoiding meaningless computation, reducing redundant work on the second processor, and lowering the burden on the second processor, thereby improving overall performance. Reduced first processor overhead; moving the conditional judgment to the second processor reduces the computational burden on the first processor; it also reduces the data transfer requirements between the first and second processors, resulting in higher overall system efficiency. Flexibility; based on conditional execution instructions, it can execute instructions without completely relying on the order of instructions issued to the Ring Buffer by the first processor, thereby implementing more complex algorithms and data processing logic. Simplified code structure; moving the conditional judgment logic to the second processor simplifies the application-level code, and the clear logical structure makes debugging and maintenance easier.

[0166] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0167] Based on the same inventive concept, this application also provides an instruction scheduling system. The solution provided by this system is similar to the solution described in the above method. Therefore, the specific limitations of one or more instruction scheduling systems provided below can be found in the limitations of the instruction scheduling method above, and will not be repeated here.

[0168] In one exemplary embodiment, the instruction scheduling system includes a heterogeneous chip, which includes a first processor and a second processor.

[0169] The first processor is configured to implement the steps of the method in any of the embodiments described above, where the first processor is the execution subject; the second processor is configured to implement the steps of the method in any of the embodiments described above, where the second processor is the execution subject.

[0170] Based on the same inventive concept, this application also provides an instruction scheduling apparatus for implementing the instruction scheduling method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more instruction scheduling apparatus embodiments provided below can be found in the limitations of the instruction scheduling method described above, and will not be repeated here.

[0171] In one exemplary embodiment, such as Figure 12 As shown, an instruction scheduling device 1 is provided, comprising: an instruction construction module 10 and an instruction sending module 20, wherein:

[0172] Instruction construction module 10 is used to construct conditional execution instructions based on conditional execution identifiers;

[0173] The instruction sending module 20 is used to send a conditional execution instruction to the second processor. The conditional execution instruction carries instruction parameter information, which is used to instruct the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0174] In one embodiment, the instruction construction module 10 is further configured to:

[0175] Obtain the instruction parameter information for the conditional execution instruction; the instruction parameter information includes the instruction opcode, read address, reference data, and number of conditional executions; combine the instruction parameter information according to the target instruction set architecture to obtain the conditional execution instruction.

[0176] In one embodiment, the instruction sending module 20 is further configured to:

[0177] Get the latest address pointed to by the write pointer in the circular buffer; write the conditional execution instruction into the circular buffer based on the latest address pointed to by the write pointer.

[0178] In one exemplary embodiment, such as Figure 13 As shown, an instruction scheduling device 2 is provided, comprising: an instruction receiving module 30, an instruction parsing module 40, a status detection module 50, and an instruction scheduling module 60, wherein:

[0179] The instruction receiving module 30 is used to receive conditional execution instructions sent by the first processor;

[0180] The instruction parsing module 40 is used to parse the conditional execution instruction to obtain the parameter information carried in the conditional execution instruction;

[0181] The status detection module 50 is used to detect the execution status of the associated instructions of the conditional execution instruction based on the parameter information carried in the conditional execution instruction.

[0182] The instruction scheduling module 60 is used to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0183] In one embodiment, the instruction parsing module 40 is further configured to:

[0184] Obtain the data read address from the parameter information; based on the data read address, read the corresponding data from the storage module to determine it as candidate data; based on the candidate data and the parameter information, detect the execution status of the associated instructions of the conditional execution instruction.

[0185] In one embodiment, the instruction parsing module 40 is further configured to:

[0186] Obtain reference data from the parameter information; if the candidate data is less than the reference data, determine that the execution status of the associated instruction is not executed; if the candidate data is greater than or equal to the reference data, determine that the execution status of the associated instruction is executed.

[0187] In one embodiment, the instruction scheduling module 60 is further configured to:

[0188] If the execution status of the associated instruction is "executed", the associated instruction is sent to the instruction status control module that matches the instruction type of the associated instruction through the instruction read / write module, and the associated instruction is executed; if the execution status of the associated instruction is "not executed", the associated instruction is sent to the no-operation instruction status control module through the instruction read / write module.

[0189] Each module in the aforementioned instruction scheduling device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0190] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 14As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores instruction scheduling data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements an instruction scheduling method.

[0191] Those skilled in the art will understand that Figure 14 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0192] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0193] Instructions are executed based on conditions constructed according to the target instruction set architecture.

[0194] A conditional execution instruction is sent to the second processor. The conditional execution instruction carries instruction parameter information, which instructs the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0195] The implementation principles and technical effects of each step in the processor implementation of this application embodiment are similar to those of the instruction scheduling method described above, and will not be repeated here.

[0196] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0197] Instructions are executed based on conditions constructed according to the target instruction set architecture.

[0198] A conditional execution instruction is sent to the second processor. The conditional execution instruction carries instruction parameter information, which instructs the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0199] The implementation principles and technical effects of each step when the computer program is executed by the processor in the embodiments of this application are similar to those of the instruction scheduling method described above, and will not be repeated here.

[0200] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0201] Instructions are executed based on conditions constructed according to the target instruction set architecture.

[0202] A conditional execution instruction is sent to the second processor. The conditional execution instruction carries instruction parameter information, which instructs the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

[0203] The implementation principles and technical effects of each step when the computer program is executed by the processor in the embodiments of this application are similar to those of the instruction scheduling method described above, and will not be repeated here.

[0204] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0205] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0206] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0207] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An instruction scheduling method, characterized in that, A first processor is applied in a heterogeneous chip; the heterogeneous chip further includes a second processor of a different type from the first processor; the method includes: Based on the conditional determination of the requirements, instructions are selected from the instruction set manual of the target instruction set, and combined according to the instruction format specified by the target instruction set architecture based on the instructions and set operands. The combined instructions are then encoded according to the encoding rules specified by the target instruction set architecture to construct conditional execution instructions. The conditional execution instruction is sent to the second processor. The conditional execution instruction carries instruction parameter information, which instructs the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions. The instruction parameter information includes instruction opcode, read address, reference data, and conditional execution quantity. The conditional execution quantity is used to characterize the number of associated instructions in the circular buffer whose execution status needs to be determined.

2. The method according to claim 1, characterized in that, The step of encoding the combined instructions according to the encoding rules specified in the target instruction set architecture to construct conditional execution instructions includes: The combined instructions are encoded according to the encoding rules specified in the target instruction set architecture to obtain candidate condition execution instructions; The candidate condition execution instructions are integrated into the test program and run in a simulator or actual hardware environment; If the test results do not meet expectations, the test program is modulated using debugging tools, and the candidate condition execution instructions are optimized to obtain the condition execution instructions.

3. The method according to claim 1 or 2, characterized in that, The second processor includes an instruction read / write module; the instruction read / write module includes a circular buffer; sending the conditional execution instruction to the second processor includes: Obtain the latest address pointed to by the write pointer in the circular buffer; The conditional execution instruction is written into the circular buffer based on the latest address pointed to by the write pointer.

4. An instruction scheduling method, characterized in that, A second processor is applied in a heterogeneous chip; the heterogeneous chip further includes a first processor of a different type from the second processor; the method includes: The first processor receives a conditional execution instruction sent by the first processor. The conditional execution instruction is obtained by the first processor selecting instructions from the instruction set manual of the target instruction set according to the conditional judgment requirements, and combining the instructions and set operands according to the instruction format specified by the target instruction set architecture, and encoding the combined instructions according to the encoding rules specified by the target instruction set architecture. The conditional execution instruction is parsed to obtain the instruction parameter information carried in the conditional execution instruction; the instruction parameter information includes the instruction opcode, read address, reference data and conditional execution count, the conditional execution count is used to characterize the number of associated instructions in the circular buffer that need to be judged in terms of execution status; Based on the instruction parameter information carried in the conditional execution instruction, detect the execution status of the associated instructions of the conditional execution instruction; The associated instructions of the conditional execution instructions are scheduled according to the execution status of the associated instructions.

5. The method according to claim 4, characterized in that, The second processor includes a storage module; the step of detecting the execution status of the associated instructions of the conditional execution instruction based on the instruction parameter information carried in the conditional execution instruction includes: Obtain the data read address from the instruction parameter information; Based on the data read address, the corresponding data is read from the storage module and determined as candidate data; Based on the candidate data and the parameter information, the execution status of the associated instructions of the conditional execution instruction is detected.

6. The method according to claim 5, characterized in that, The step of detecting the execution status of the associated instructions of the conditional execution instruction based on the candidate data and the parameter information includes: Obtain reference data from the parameter information; If the candidate data is smaller than the reference data, then the execution status of the associated instruction is determined to be non-execution; If the candidate data is greater than or equal to the reference data, then the execution status of the associated instruction is determined to be execution.

7. The method according to any one of claims 4-6, characterized in that, The second processor also includes an instruction read / write module and multiple instruction status control modules; the step of scheduling the associated instructions of the conditional execution instruction according to the execution status of the associated instructions includes: If the execution status of the associated instruction is "executed", then the associated instruction is sent to the instruction status control module that matches the instruction type of the associated instruction through the instruction read / write module, and the associated instruction is executed. If the execution status of the associated instruction is not executed, then the associated instruction is sent to the no-operation instruction status control module through the instruction read / write module.

8. The method according to claim 7, characterized in that, The instruction status control module further includes a conditional execution instruction status control module; the instruction read / write module includes a circular buffer. When the instruction read / write module receives the execution status of the associated instruction from the conditional execution instruction status control module, it reads the associated instruction from the circular buffer according to the number of conditional executions in the instruction parameter information, and sends the associated instruction to the corresponding instruction status control module according to the execution status.

9. An instruction scheduling system, characterized in that, The instruction scheduling system includes a heterogeneous chip, which includes a first processor and a second processor. The first processor is used to implement the steps of the method according to any one of claims 1 to 3; The second processor is used to implement the steps of the method according to any one of claims 4 to 8.

10. A command scheduling device, characterized in that, The device includes: The instruction construction module is used to determine the requirements based on conditions, select instructions from the instruction set manual of the target instruction set, and combine the instructions and set operands according to the instruction format specified by the target instruction set architecture. The module also encodes the combined instructions according to the encoding rules specified by the target instruction set architecture to construct conditional execution instructions. The instruction sending module is used to send the conditional execution instruction to the second processor. The conditional execution instruction carries instruction parameter information, which instructs the second processor to detect the execution status of the associated instructions of the conditional execution instruction according to the parameter information carried in the conditional execution instruction, and to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions. The instruction parameter information includes instruction opcode, read address, reference data, and conditional execution quantity. The conditional execution quantity is used to characterize the number of associated instructions in the circular buffer whose execution status needs to be determined.

11. A command scheduling device, characterized in that, The device includes: The instruction receiving module is used to receive conditional execution instructions sent by the first processor. The conditional execution instructions are obtained by the first processor selecting instructions from the instruction set manual of the target instruction set according to the conditional judgment requirements, and combining the instructions and set operands according to the instruction format specified by the target instruction set architecture, and encoding the combined instructions according to the encoding rules specified by the target instruction set architecture. The instruction parsing module is used to parse the conditional execution instruction to obtain the instruction parameter information carried in the conditional execution instruction; the instruction parameter information includes the instruction opcode, read address, reference data and conditional execution count, and the conditional execution count is used to characterize the number of associated instructions in the circular buffer that need to be judged in terms of execution status; The status detection module is used to detect the execution status of the associated instructions of the conditional execution instruction based on the instruction parameter information carried in the conditional execution instruction; The instruction scheduling module is used to schedule the associated instructions of the conditional execution instruction according to the execution status of the associated instructions.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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