Starting method, PCIe card, computing device and computer readable storage medium

Abstract

The invention provides a starting method which aims at meeting the starting requirement of a multi-chip PCIe card, according to the starting method, after a first chip is started, second chips are started in sequence, the situation that the second chips read second firmware in an external storage at the same time and possibly cause abnormities can be avoided, and through the starting process, the starting efficiency of the multi-chip PCIe card is improved. The multi-chip PCIe card can satisfy the orderly starting of the first chip and the plurality of second chips in the PCIe card, and guarantees the smooth starting of the multi-chip PCIe card.

Description

Technical Field

[0001] This specification relates to the field of computer technology, specifically to chip boot technology in the field of computer technology, and more specifically to a boot method, a PCIe card, a computing device, and a computer-readable storage medium. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that is widely used in computer systems.

[0003] A PCIe card refers to hardware with a PCIe interface (such as a network card, graphics card, or Neural Network Processing Unit (NPU)). PCIe cards can be inserted into the PCIe slots on the motherboard to expand the functionality of the computer system. With the continuous improvement of technology, the performance of PCIe cards has become increasingly powerful, and their structure has become increasingly complex. Therefore, it is necessary to provide a boot method to meet the boot requirements of multi-chip PCIe cards. Summary of the Invention

[0004] This specification provides a boot method, a PCIe card, a computing device, and a computer-readable storage medium to meet the boot requirements of a multi-chip PCIe card.

[0005] To achieve the above technical objectives, the embodiments described in this specification provide the following technical solutions:

[0006] Firstly, a boot method is provided, applied to a PCIe card. The PCIe card includes a PCIe interface, a first chip, and multiple second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process a target task. The first chip and the multiple second chips are connected to off-chip storage via a first communication bus. The off-chip storage is used to store first firmware and second firmware. The first firmware is the boot firmware of the first chip, and the second firmware is the boot firmware of the second chip. The first chip is connected to the second chips via a second communication bus. The boot method includes:

[0007] In response to the startup operation, the first chip reads the first firmware from the off-chip storage through the first communication bus, starts the first chip based on the first firmware, initializes the second communication bus, and notifies the second chip to start sequentially through the second communication bus;

[0008] The startup process of the second chip includes:

[0009] In response to the first notification message sent by the first chip, the second firmware is read from the off-chip storage via the first communication bus, and the device is started based on the second firmware. A first response message is then returned to the first chip. The first response message indicates that the second chip has finished starting and can notify the next second chip to start.

[0010] In a second aspect, a PCIe card is provided, comprising: a PCIe interface, a first chip, and a plurality of second chips, wherein the first chip is connected to the second chips, the first chip communicates with an external RC device through the PCIe interface, the second chips are used to process a target task, the first chip and the plurality of second chips are connected to off-chip storage through a first communication bus, the off-chip storage is used to store first firmware and second firmware, the first firmware is the boot firmware of the first chip, the second firmware is the boot firmware of the second chip, and the first chip is connected to the second chips through a second communication bus;

[0011] The first chip is configured to: in response to a boot operation, read the first firmware from the off-chip storage via the first communication bus, boot the first chip based on the first firmware, initialize the second communication bus, and notify the second chip to boot sequentially via the second communication bus;

[0012] The startup process of the second chip includes:

[0013] In response to the first notification message sent by the first chip, the second firmware is read from the off-chip storage via the first communication bus, and the device is started based on the second firmware. A first response message is then returned to the first chip. The first response message indicates that the second chip has finished starting and can notify the next second chip to start.

[0014] Thirdly, a computing device is provided, comprising: a motherboard, a processor disposed on the motherboard, and a PCIe card, wherein the PCIe card includes the PCIe card as described in any of the preceding claims.

[0015] Fourthly, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a PCIe card, implements the boot method described above.

[0016] Fifthly, a computer program product or computer program is provided, the computer program product including a computer program stored in a computer-readable storage medium; the PCIe card of the computer device reads the computer program from the computer-readable storage medium, and the PCIe card executes the computer program to implement the steps of the above-described startup method.

[0017] As can be seen from the above technical solution, the boot method provided in this specification is applied to a PCIe card including multiple chips (a first chip and multiple second chips). The PCIe card includes a PCIe interface, a first chip, and multiple second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process target tasks. The first chip and the multiple second chips are connected to off-chip storage via a first communication bus. The off-chip storage is used to store first firmware and second firmware. The first firmware is the boot firmware of the first chip, and the second firmware is the boot firmware of the second chip. The first chip is connected to the second chips via a second communication bus. In this PCIe card, the first chip can... As a communication medium between the external RC device and the second chip, the first chip can also meet the boot requirements of multiple second chips during the boot process. Specifically, during boot, the first chip reads the first firmware from the external storage via the first communication bus, boots the first chip based on the first firmware, initializes the second communication bus, and notifies the second chips to boot sequentially via the second communication bus. The boot process of the second chip includes: responding to a first notification message sent by the first chip, reading the second firmware from the external storage via the first communication bus, booting based on the second firmware, and returning a first response message to the first chip. The first response message indicates that the second chip has completed booting and can notify the next second chip to boot. In this way, after the first chip has booted, the second chips are booted sequentially, which can avoid the abnormalities that may be caused by multiple second chips reading the second firmware from the external storage at the same time. Through the above boot process, the orderly booting of the first chip and multiple second chips in the PCIe card can be satisfied, ensuring the smooth booting of the multi-chip PCIe card. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 A schematic diagram of the implementation environment that may be involved in the startup method provided in the embodiments of this specification;

[0020] Figure 2 A topology diagram of a PCIe bus system provided for embodiments of this specification;

[0021] Figure 3 A flowchart illustrating the startup method provided in the embodiments of this specification;

[0022] Figure 4 A schematic diagram of the structure of a PCIe card provided in the embodiments of this specification;

[0023] Figure 5 A schematic diagram of the structure of a PCIe card provided in the embodiments of this specification;

[0024] Figure 6 A schematic diagram illustrating a feasible process of the startup method provided in the embodiments of this specification;

[0025] Figure 7 A schematic diagram of the structure of the computing device provided for the embodiments of this specification. Detailed Implementation

[0026] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0027] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0028] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0029] First, it should be noted that spatial relation terms, such as "front" and "back," are intended to refer to the two opposing first and second surfaces of a device or element. The use of "front" and "back" here is for the purpose of conforming to the orientation of the accompanying drawings and facilitating description. When the orientation of the drawings changes, the spatial relation terms should also be interpreted accordingly; for example, if the device or element in the drawings is flipped, then "front" should be understood as "back."

[0030] Exemplary Implementation Environment

[0031] Please refer to Figure 1 , Figure 1 This diagram illustrates a possible implementation environment for the startup method provided in the embodiments of this specification. This implementation environment can be a computer system (or computing device), which can be a cloud server. The cloud server includes a host 20 and a PCIe card 10. The host 20 may include a motherboard and a PCIe slot, and the PCIe card 10 can be inserted into the PCIe slot. The PCIe card 10 can communicate with the host 20 via the PCIe bus system. The PCIe card 10 can offload some of the computations from the host 20 to itself, thereby reducing the computational load on the host 20 or enriching the computational types available to the host 20.

[0032] refer to Figure 2 , Figure 2 A topology diagram of a PCIe bus system, such as Figure 2 The PCIe bus system shown typically employs a tree topology. A PCIe bus system can include PCIe devices such as CPUs (processors), RC13 (Root Complex), switches, and EP12 (Endpoints). Additionally, it may include devices such as main memory and PCIe-PCI Bridges. Figure 1 In the implementation environment shown, RC13 and CPU11 can be integrated into host 20, and PCIe card 10 can communicate with host 20 as EP12 in the PCIe bus system. In some scenarios, to overcome the limitations of the server's structural design, an expansion card (riser card) can be set between PCIe card 10 and host 20. One end of the expansion card is inserted into a slot provided by host 20, and the other end provides one or more standard PCIe slots for PCIe card 10 to be inserted, thereby meeting the connection requirements of different types of PCIe cards 10 and host 20.

[0033] Overview

[0034] In related technologies, as PCIe cards become increasingly powerful, some PCIe cards can integrate multiple chips to meet the needs of specific scenarios. For example, an NPU can be used as a PCIe card plugged into the motherboard of a host computer. Some high-performance NPUs may integrate multiple NPU chips, which can perform computational tasks collaboratively or independently. In addition, an NPU may also include memory chips, I / O (INPUT / OUTPUT) chips, and other types of chips to meet the communication needs between the NPU chips and external RC devices. For PCIe cards integrating multiple chips, ensuring the orderly startup of each chip is a crucial issue that needs to be addressed.

[0035] To address this issue, the inventors designed an architecture for a PCIe card comprising multiple chips. Specifically, the PCIe card includes a PCIe interface, a first chip, and multiple second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process target tasks. The first chip and the multiple second chips are connected to off-chip storage via a first communication bus. The off-chip storage stores first firmware and second firmware. The first firmware is the boot firmware for the first chip, and the second firmware is the boot firmware for the second chip. The first chip is connected to the second chips via a second communication bus. In this PCIe card, the first chip can act as an external RC device and... The communication medium between the second chips, and the first chip can simultaneously meet the boot requirements of multiple second chips during the boot process. Specifically, during boot, the first chip reads the first firmware from the external storage via the first communication bus, boots the first chip based on the first firmware, initializes the second communication bus, and notifies the second chips to boot sequentially via the second communication bus. The boot process of the second chip includes: responding to a first notification message sent by the first chip, reading the second firmware from the external storage via the first communication bus, booting based on the second firmware, and returning a first response message to the first chip. The first response message indicates that the second chip has completed booting and can notify the next second chip to boot. In this way, after the first chip has booted, the second chips are booted sequentially, which can avoid the abnormalities that may be caused by multiple second chips simultaneously reading the second firmware from external storage. Through the above boot process, the orderly booting of the first chip and multiple second chips in the PCIe card can be satisfied, ensuring the smooth booting of multi-chip PCIe cards.

[0036] Based on the above concept, this specification provides a startup method. The startup method provided by this specification will be described exemplarily below with reference to the accompanying drawings.

[0037] Exemplary methods

[0038] Please refer to Figure 3 , Figure 3 This specification illustrates a flowchart of a boot method provided in one embodiment. The boot method is applied to a PCIe card, which includes a PCIe interface, a first chip, and multiple second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process a target task. The first chip and the multiple second chips are connected to off-chip storage via a first communication bus. The off-chip storage stores first firmware and second firmware. The first firmware is the boot firmware of the first chip, and the second firmware is the boot firmware of the second chip. The first chip is connected to the second chips via a second communication bus. The boot method includes:

[0039] S301: In response to the startup operation, the first chip reads the first firmware from the off-chip storage through the first communication bus, starts the first chip based on the first firmware, initializes the second communication bus, and notifies the second chip to start sequentially through the second communication bus;

[0040] The startup process of the second chip includes:

[0041] S302: In response to the first notification message sent by the first chip, the second firmware is read from the off-chip storage through the first communication bus, and the chip starts based on the second firmware. A first response message is returned to the first chip. The first response message is used to indicate that the second chip has finished starting and can notify the next second chip to start.

[0042] As mentioned earlier, a PCIe card can function as an EP (Extended Access Device) when communicating with an external RC (Remote Control) device in a computing device. Inside the PCIe card, a first chip can include a PCIe module, and the PCIe controller within this module can be in EP mode. When the PCIe controller is in EP mode, the first chip connects to the external RC device of the computing device via the PCIe slot. The entire PCIe card can then be scanned by the external RC device as a PCIe device. Subsequently, the computing device can communicate with the PCIe card through the external RC device. In this mode, the first chip can efficiently exchange data with the external RC device, meeting the bandwidth requirements of the PCIe card when processing large amounts of data and ensuring rapid data exchange between the first chip and the external RC device.

[0043] Regarding the connection relationship between the first and second chips inside the PCIe card, please refer to [link / reference needed]. Figure 3 and in conjunction with references Figure 4 and Figure 5 , Figures 3-5 A schematic diagram of a feasible connection method between the first chip and the second chip inside a PCIe card is provided.

[0044] exist Figure 3 The diagram primarily illustrates that the first and second chips in a PCIe card are each connected to external storage via a first communication bus. In some embodiments, the first communication bus can be a QSPI (Quad Serial Peripheral Interface) bus. QSPI is a high-speed serial bus used to connect chips (e.g., the first chip / second chip) to external storage (such as Flash memory), which can be located within the PCIe card. QSPI supports high-speed data transmission and can be used in embedded systems, particularly suitable for scenarios requiring rapid loading of boot code and firmware. QSPI can meet the requirement of the first and second chips to quickly read firmware from external storage during the boot process, thus ensuring high efficiency in the boot process.

[0045] exist Figure 3 The diagram also illustrates the connection between the first chip and the second chip. The second chips can be connected to each other via a fifth communication bus, and the first chip can also be connected to the second chip via the fifth communication bus. The fifth communication bus can be a bus used for inter-chip communication to meet the communication needs between the first chip and the second chip, as well as between the second chips. In some embodiments, the fifth communication bus can be a C2C (Chip to Chip) bus. A C2C bus is an interconnection form in integrated circuit design and packaging technology that can be used for inter-chip data communication.

[0046] exist Figure 4 The diagram illustrates that in some embodiments, the second chip can be connected to the second memory via a direct physical connection without requiring a special C2C bus connection. The second memory can be SRAM (Static Random-Access Memory) and can be used as a cache for the second chip to improve its data read speed. Similarly, in some embodiments, the first chip can also be connected to the first memory (not shown in the diagram) via a direct physical connection. The first memory can also be SRAM and can be used as a cache for the first chip to improve its data read speed.

[0047] exist Figure 5The image shows another communication connection method between the first chip and the second chip. The first chip sends data to the second chip through the second communication bus and the fourth communication bus, and the second chip sends data to the first chip through the third communication bus. In PCIe cards, since the initialization order of the second chip is usually later than that of the first chip, the fifth communication bus cannot be initialized before the second chip is initialized because the second chip has no clock. Therefore, the fifth communication bus cannot work before the second chip is initialized. To meet the communication needs between the first and second chips, a second, third, and fourth communication bus with an earlier initialization order is set between the first and second chips. The second, third, and fourth communication buses can all be buses with simple interfaces that are easy to implement and debug. In other words, the second, third, and fourth communication buses can all be buses whose initialization timing is before the second chip (i.e., the second, third, and fourth communication buses can work independently of the clock of the second chip). For example, in some implementations, the second, third, and fourth communication buses can all be GPIO (General-Purpose Input / Output) buses. GPIO buses can provide basic communication functions without the need for complex protocols and hardware support. Therefore, GPIO buses can work before the second chip is initialized, meeting the communication needs between the first and second chips before the second chip is initialized.

[0048] Understandable, Figures 3-5 To clarify the connections, portions of the buses and components within the PCIe card are shown. In some implementations, the PCIe card may include... Figures 3-5 The diagram shows all the communication buses and components; of course, in other embodiments, the PCIe card may also include, depending on requirements. Figures 3-5 The connections between all communication buses and components shown can be adjusted as needed, and this specification does not limit this; the specific arrangements depend on the actual situation.

[0049] The second chip can be a chip on the PCIe card used to execute the target task, and the first chip can be a chip that communicates with external computing devices such as RC devices as the second chip. The target task to be executed by the second chip varies depending on the type of PCIe card. For example, when the PCIe card is an NPU, the target task may include AI inference and training tasks, real-time data processing tasks, etc.; when the PCIe card is a graphics card, the target task may include graphics rendering tasks, scientific computing and large-scale data processing tasks, AI model training tasks, etc.

[0050] In the startup method provided in this embodiment, the first communication bus satisfies the requirement for the first chip and the second chip to read the first firmware and the second firmware respectively from external storage; the second communication bus satisfies the requirement for the first chip to send a first communication message to the second chip to instruct the second chip to start sequentially. In general, this method is applied to a PCIe card including multiple chips (a first chip and multiple second chips). The PCIe card includes a PCIe interface, a first chip, and multiple second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process target tasks. The first chip and the multiple second chips are connected to external storage through the first communication bus. The external storage is used to store the first firmware and the second firmware. The first firmware is the startup firmware of the first chip, and the second firmware is the startup firmware of the second chip. The first chip is connected to the second chip through the second communication bus. In this PCIe card, the first chip can act as an external RC device to communicate with the second chip. The communication medium between the two chips allows the first chip to meet the boot requirements of multiple second chips during the boot process. Specifically, during boot, the first chip reads the first firmware from the external storage via the first communication bus, boots the first chip based on the first firmware, initializes the second communication bus, and notifies the second chips to boot sequentially via the second communication bus. The boot process of the second chip includes: responding to a first notification message sent by the first chip, reading the second firmware from the external storage via the first communication bus, booting based on the second firmware, and returning a first response message to the first chip. The first response message indicates that the second chip has completed booting and can notify the next second chip to boot. In this way, after the first chip boots, the second chips boot sequentially. That is, after one second chip boots, the first chip receives the first response message before sending a second notification message to the next second chip. This avoids the anomalies that may be caused by multiple second chips simultaneously reading the second firmware from external storage. Through the above boot process, the orderly booting of the first chip and multiple second chips in the PCIe card can be satisfied, ensuring the smooth booting of multi-chip PCIe cards.

[0051] It should be noted that in a PCIe card, the first chip can be used to communicate with external RC devices. That is, the first chip's function can include communication between the PCIe card and external RC devices, and it can act as a communication bridge between the second chip and external RC devices. In some implementations, the first chip may not be used for the calculation of the target task; in this case, the first chip can focus solely on fulfilling the communication task, significantly reducing the hardware requirements for the first chip. Furthermore, to reduce the amount of data the first chip needs to process during startup and avoid increasing its data processing burden, after startup and initialization of the second communication bus, the first chip only needs to send a first notification message to the second chip, without performing the reading and distribution tasks of the second firmware. This means the first chip does not need to perform the reading and transmission of large amounts of data (multiple second firmware files), thus lowering the data processing capability requirements for the first chip and avoiding increasing its data processing capacity and hardware requirements, thereby preventing an increase in the overall cost of the PCIe card.

[0052] Still referencing Figure 5 To meet the communication requirements of the first chip and the second chip before the second chip is initialized, in some embodiments, the PCIe card may further include a third communication bus, which is used to connect the first chip and the second chip; the second communication bus and the third communication bus are of the same type (for example, they may both be GPIO buses);

[0053] The step of notifying the second chip to start sequentially via the second communication bus includes:

[0054] A first notification message is sent to the first second chip via the second communication bus. After receiving the first response message, the first notification message is sent to the next second chip until the plurality of second chips have completed startup.

[0055] The step of returning a first response message to the first chip includes:

[0056] The first response message is returned to the first chip via the third communication bus.

[0057] In this embodiment, the feasible methods for the first chip to notify the second chip to start sequentially via the second communication bus and the feasible methods for the second chip to return a first response message to the first chip are detailed. In this embodiment, the first notification message and the first response message are sent via the second communication bus and the third communication bus, respectively. This makes the method applicable to certain buses that typically transmit messages unidirectionally after initialization (such as the GPIO bus), and avoids mutual interference between the first notification message and the first response message during transmission, ensuring the integrity and reliability of the transmission of the first communication message and the first response message.

[0058] In one embodiment, to ensure the normal functioning of the first chip, the startup method further includes the following before the first chip reads the first firmware from the off-chip storage via the first communication bus:

[0059] The processor core of the first chip releases the clock reset of the PCIe module and C2C module of the first chip;

[0060] The PCIe controller of the PCIe module is initialized to EP mode so that the external RC device can scan the PCIe card.

[0061] In this embodiment, the first chip may include a PCIe module and a C2C module. The PCIe module can be used to meet the communication requirements of the PCIe system for the PCIe card, so that the entire PCIe card can be inserted into the computing device as a PCIe device. The first chip can serve to connect the second chip with other components of the computing device (such as external RC devices).

[0062] The C2C module can be used to enable communication between different chips or modules within a PCIe card, such as data transfer between the first chip and the second chip.

[0063] During firmware initialization, releasing the clock reset for the PCIe and C2C modules allows them to recover from the reset state and begin normal operation. Releasing the clock reset means that the clock signals of these modules begin operating normally, enabling them to receive and process data.

[0064] After the clock reset is complete, the PCIe controller of the PCIe module can be initialized to EP mode so that external RC devices can scan the PCIe card and establish a communication connection between the PCIe card and the motherboard of the computing device.

[0065] In one implementation, after the initialization process of the first and second chips is completed, the inter-chip communication bus can be initialized to meet the inter-chip communication requirements within the PCIe card. Specifically, refer to... Figures 3-5 The PCIe card further includes: a fourth communication bus and a fifth communication bus, wherein the fourth communication bus is connected between the first chip and each of the second chips; the fifth communication bus is connected between each of the second chips and between the first chip and the second chips; the fourth communication bus and the second communication bus have the same communication protocol; and the fifth communication bus is used for inter-chip communication.

[0066] After notifying the second chip to start sequentially via the second communication bus, the method further includes:

[0067] Initialize the fifth communication bus between the first chip and the second chip;

[0068] The second notification message is sent in parallel to the plurality of second chips via the fourth communication bus. The second notification message is used to instruct the second chips to initialize the fifth communication bus between each second chip.

[0069] In this embodiment, the initialization sequence of the fifth communication bus is placed after the second chip starts up, so that the fifth communication bus used for inter-chip communication has the initialization conditions (i.e., it can utilize the clock provided by the second chip).

[0070] Furthermore, in this embodiment, in order to improve the boot efficiency of the PCIe card, a second notification message is sent in parallel to the plurality of second chips through the fourth communication bus. This allows the second notification message to be transmitted to each second chip in parallel, instructing the plurality of second chips to initialize the fifth communication bus simultaneously, thereby improving boot efficiency.

[0071] In this embodiment, the second communication bus is not reused for sending the second notification message because the second communication bus needs to meet the requirement that the first chip sends the first communication message to the second chip sequentially, avoiding errors that may occur if multiple second chips read the second firmware from external storage at the same time. During the initialization of the fifth communication bus, there is no situation where the second chip needs to read data from external storage after receiving the second notification message. Therefore, the initialization process of the fifth communication bus can be executed in parallel. In order to meet the requirement of sending the second notification message to multiple second chips at the same time, a fourth notification bus can be set up to meet this requirement, thereby enabling multiple second chips to initialize the fifth communication bus at the same time and improving startup efficiency.

[0072] In one embodiment, in order for the first chip to confirm whether the entire boot process is complete, the second notification message is further used to instruct the second chip to return a second response message to the first chip via the third communication bus after completing the initialization of the fifth communication bus between the second chips; that is, after completing the initialization of the fifth communication bus, the second chip returns a second response message to the first chip via the third communication bus.

[0073] The startup method further includes:

[0074] After receiving the second response message returned by the plurality of second chips, the first chip completes the initialization of the PCIe card.

[0075] In this embodiment, since the first response message and the second response message are sent at different times (i.e., the first response message is sent after the second chip starts up, while the second response message is sent after the second chip completes the initialization of the fifth communication bus), the third communication bus can be time-division multiplexed to meet the sending requirements of the first response message and the second response message, thereby reducing the number of buses required inside the PCIe card and simplifying the internal structure of the PCIe card.

[0076] Optionally, to improve the speed at which each chip reads firmware data, as described above, in one embodiment, reference is made to... Figure 4 The first chip corresponds to the first memory, and the second chip corresponds to the second memory;

[0077] The step of starting the first chip based on the first firmware includes:

[0078] The first chip copies the first firmware it reads to the first memory and boots up based on the first firmware in the first memory;

[0079] The second chip boots based on the second firmware, including:

[0080] The second chip copies the read second firmware to the second memory and boots up based on the second firmware in the second memory.

[0081] In this embodiment, during the startup process, the firmware can be copied to a first memory and a second memory with a high data transfer rate. Then, each chip can be started based on the firmware copied to the first memory and the second memory, which helps to improve the speed at which each chip reads firmware data from the corresponding memory.

[0082] refer to Figure 6 , Figure 6 This specification illustrates a feasible startup process for a startup method provided in an embodiment of the present specification, the process including:

[0083] S1. First chip boot: The first chip can boot from external memory (e.g., Flash) via the QSPI bus.

[0084] The first firmware is taken from the middle;

[0085] S2, First firmware initialization:

[0086] (1) The processor core in the first chip releases the clock reset of the PCIe module and C2C module in the first chip;

[0087] (2) The first chip initializes the PCIe controller to EP mode;

[0088] (3) The first chip copies the first firmware from the external storage to the first memory inside the first chip, and jumps to the first memory to execute the first firmware.

[0089] S3. After the first chip completes its startup, it releases the second chip:

[0090] (1) The first chip sends a first notification message to the second chip through the second communication bus (which can be called the GPIOA bus) to notify the second chip to reset;

[0091] (2) Wait for the second chip to return the first response message.

[0092] S4, Second Chip Startup and Second Firmware Initialization:

[0093] (1) The processor core of the second chip releases the clock reset of the C2C module and the first sub-memory (e.g., SRAM (Static Random Access Memory));

[0094] (2) The second chip copies the second firmware from the external storage to the second memory and jumps to the second memory to execute the second firmware;

[0095] (3) The second chip is connected to the third communication bus (in order to distinguish it from the GPIOA bus, the third communication bus can be called the GPIOC bus).

[0096] Repeat steps S2 through S4 until all second chips are initialized.

[0097] S5. Initialization of the fifth communication bus (e.g., a C2C bus) of the first chip:

[0098] (1) The first chip sends a second notification message to all the second chips in the PCIe card through the fourth communication bus (in order to distinguish it from the GPIOA and GPIOC buses, the fourth communication bus can be called the GPIOB bus) to notify each second chip to initialize the fifth communication bus.

[0099] (2) The first chip initializes the fifth communication bus that connects to each of the second chips;

[0100] (3) Wait for each second chip to return the second response message.

[0101] S6. Initialization of the fifth communication bus and second memory of the second chip: Initialize the fifth communication bus connected to each second chip, initialize the second sub-memory corresponding to each second chip (e.g., HBM (High Bandwidth Memory) or DDR (Data Rate Synchronous Dynamic Random Access Memory)), and return a second notification message to the first chip through the third communication bus (e.g., GPIOC bus);

[0102] S7. Startup Complete: After receiving the second response messages returned by each of the second chips, the first chip determines that startup is complete. In this embodiment, the second memory corresponding to the second chip may include a first sub-memory and a second sub-memory, which can be initialized in steps S4 and S6 respectively.

[0103] Example PCIe card

[0104] Accordingly, this specification also provides a PCIe card, see reference. Figures 3-5 The PCIe card includes: a PCIe interface (not shown in the attached drawings), a first chip, and a plurality of second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process target tasks. The first chip and the plurality of second chips are connected to off-chip storage through a first communication bus. The off-chip storage is used to store first firmware and second firmware. The first firmware is the boot firmware of the first chip, and the second firmware is the boot firmware of the second chip. The first chip is connected to the second chips through a second communication bus.

[0105] The first chip is configured to: in response to a boot operation, read the first firmware from the off-chip storage via the first communication bus, boot the first chip based on the first firmware, initialize the second communication bus, and notify the second chip to boot sequentially via the second communication bus;

[0106] The startup process of the second chip includes:

[0107] In response to the first notification message sent by the first chip, the second firmware is read from the off-chip storage via the first communication bus, and the device is started based on the second firmware. A first response message is then returned to the first chip. The first response message indicates that the second chip has finished starting and can notify the next second chip to start.

[0108] Optionally, the PCIe card further includes a third communication bus for connecting the first chip and the second chip; the second communication bus is of the same type as the third communication bus.

[0109] The first chip notifies the second chip via the second communication bus to start up sequentially, specifically for:

[0110] A first notification message is sent to the first second chip via the second communication bus. After receiving the first response message, the first notification message is sent to the next second chip until the plurality of second chips have completed startup.

[0111] The second chip returns a first response message to the first chip specifically for:

[0112] The first response message is returned to the first chip via the third communication bus.

[0113] Optionally, before the first chip reads the first firmware from the off-chip storage via the first communication bus, it is further configured to:

[0114] The processor core of the first chip releases the clock reset of the PCIe module and C2C module of the first chip;

[0115] The PCIe controller of the PCIe module is initialized to EP mode so that the external RC device can scan the PCIe card.

[0116] Optionally, the PCIe card further includes: a fourth communication bus and a fifth communication bus, wherein the fourth communication bus is connected between the first chip and each of the second chips; the fifth communication bus is connected between each of the second chips and between the first chip and the second chips; the fourth communication bus and the second communication bus have the same communication protocol; and the fifth communication bus is used for inter-chip communication.

[0117] After the first chip notifies the second chip to start sequentially via the second communication bus, it is also used for:

[0118] Initialize the fifth communication bus between the first chip and the second chip;

[0119] The second notification message is sent in parallel to the plurality of second chips via the fourth communication bus. The second notification message is used to instruct the second chips to initialize the fifth communication bus between each second chip.

[0120] Optionally, the second notification message is further used to instruct the second chip to return a second response message to the first chip via the third communication bus after completing the initialization of the fifth communication bus between each of the second chips;

[0121] The first chip is also used to: complete the initialization of the PCIe card after receiving the second response message returned by the plurality of second chips.

[0122] Optionally, the first communication bus includes a QSPI bus;

[0123] The second communication bus and the fourth communication bus include GPIO buses;

[0124] The fifth communication bus includes a C2C bus.

[0125] Optionally, the first chip corresponds to a first memory, and the second chip corresponds to a second memory;

[0126] The specific steps of booting the first chip based on the first firmware include:

[0127] The first chip copies the first firmware it reads to the first memory and boots up based on the first firmware in the first memory;

[0128] The second chip boots based on the second firmware, including:

[0129] The second chip copies the read second firmware to the second memory and boots up based on the second firmware in the second memory.

[0130] For specific limitations regarding PCIe cards, please refer to the section on boot method limitations above; they will not be repeated here.

[0131] Exemplary computing device

[0132] Another embodiment of this specification also proposes a computing device, see [link to documentation]. Figure 7 As shown, an exemplary embodiment of this specification also provides a computing device, including: a motherboard, a processor disposed on the motherboard, and a PCIe card, the PCIe card including the PCIe card as described in any of the above embodiments, the PCIe card being used to perform the boot method described in any of the above embodiments.

[0133] The internal structure of the computing device can be as follows: Figure 7As shown, the computing device includes a processor, memory, network interface, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium, and may include the external storage described above. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by a PCIe card, it follows the steps of the boot methods according to various embodiments of this specification as described in the above embodiments.

[0134] The processor may include the main processor, as well as baseband chips, modems, etc.

[0135] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-described method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0136] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0137] Input devices may include devices that receive data and information input by the user, such as keyboards, mice, cameras, scanners, light pens, voice input devices, touch screens, pedometers, or gravity sensors.

[0138] Output devices may include devices that allow information to be output to a user, such as displays, printers, speakers, etc.

[0139] The communication interface may include any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0140] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display screen or an e-ink display screen. The input device of the computing device may be a touch layer covering the display component, or a button, trackball or touchpad set on the casing of the computing device, or an external keyboard, touchpad or mouse, etc.

[0141] Those skilled in the art will understand that Figure 7 The structures shown are merely block diagrams of some structures related to the solutions in this specification and do not constitute a limitation on the computing devices on which the solutions in this specification are applied. Specific computing devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0142] Exemplary computer program products and storage media

[0143] In addition to the methods and devices described above, the booting methods provided in the embodiments of this specification can also be computer program products, which include computer program instructions that, when run by a PCIe card, cause the PCIe card to perform the steps in the booting methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0144] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0145] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0146] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a PCIe card of the steps in the startup method according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0147] Those skilled in the art will understand that all or part of the processes in the above-described embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0148] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0149] The embodiments described above are merely illustrative of several implementations of this specification, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A startup method, characterized in that, This invention relates to a PCIe card, which includes a PCIe interface, a first chip, and multiple second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process target tasks. The first chip and the multiple second chips are connected to off-chip storage via a first communication bus. The off-chip storage is used to store first firmware and second firmware. The first firmware is the boot firmware of the first chip, and the second firmware is the boot firmware of the second chip. The first chip is connected to the second chips via a second communication bus. The boot method includes: In response to the startup operation, the first chip reads the first firmware from the off-chip storage through the first communication bus, starts the first chip based on the first firmware, initializes the second communication bus, and notifies the second chip to start sequentially through the second communication bus; The startup process of the second chip includes: In response to the first notification message sent by the first chip, the second firmware is read from the off-chip storage via the first communication bus, and the device is started based on the second firmware. A first response message is then returned to the first chip. The first response message indicates that the second chip has finished starting and can notify the next second chip to start.

2. The method according to claim 1, characterized in that, The PCIe card also includes a third communication bus, which is used to connect the first chip and the second chip; the second communication bus is of the same type as the third communication bus. The step of notifying the second chip to start sequentially via the second communication bus includes: A first notification message is sent to the first second chip via the second communication bus. After receiving the first response message, the first notification message is sent to the next second chip until the plurality of second chips have completed startup. The step of returning a first response message to the first chip includes: The first response message is returned to the first chip via the third communication bus.

3. The method according to claim 1, characterized in that, Before the first chip reads the first firmware from the off-chip storage via the first communication bus, it further includes: The processor core of the first chip releases the clock reset of the PCIe module and C2C module of the first chip; The PCIe controller of the PCIe module is initialized to EP mode so that the external RC device can scan the PCIe card.

4. The method according to any one of claims 1 to 3, characterized in that, The PCIe card further includes: a fourth communication bus and a fifth communication bus, wherein the fourth communication bus is connected between the first chip and each of the second chips; the fifth communication bus is connected between each of the second chips and between the first chip and the second chips; the fourth communication bus and the second communication bus have the same communication protocol; and the fifth communication bus is used for inter-chip communication. After notifying the second chip to start sequentially via the second communication bus, the method further includes: Initialize the fifth communication bus between the first chip and the second chip; The second notification message is sent in parallel to the plurality of second chips via the fourth communication bus. The second notification message is used to instruct the second chips to initialize the fifth communication bus between each second chip.

5. The method according to claim 4, characterized in that, The second notification message is also used to instruct the second chip to return a second response message to the first chip via the third communication bus after completing the initialization of the fifth communication bus between each second chip; The startup method further includes: After receiving the second response message returned by the plurality of second chips, the first chip completes the initialization of the PCIe card.

6. The method according to claim 4, characterized in that, The first communication bus includes a QSPI bus; The second communication bus and the fourth communication bus include GPIO buses; The fifth communication bus includes a C2C bus.

7. The method according to any one of claims 1 to 3, characterized in that, The first chip corresponds to a first memory, and the second chip corresponds to a second memory; The step of starting the first chip based on the first firmware includes: The first chip copies the first firmware it reads to the first memory and boots up based on the first firmware in the first memory; The second chip boots based on the second firmware, including: The second chip copies the read second firmware to the second memory and boots up based on the second firmware in the second memory.

8. A PCIe card, characterized in that, include: The system comprises a PCIe interface, a first chip, and multiple second chips. The first chip is connected to the second chips. The first chip communicates with an external RC device through the PCIe interface. The second chips are used to process target tasks. The first chip and the multiple second chips are connected to off-chip storage through a first communication bus. The off-chip storage is used to store first firmware and second firmware. The first firmware is the boot firmware of the first chip, and the second firmware is the boot firmware of the second chip. The first chip is connected to the second chips through a second communication bus. The first chip is configured to: in response to a boot operation, read the first firmware from the off-chip storage via the first communication bus, boot the first chip based on the first firmware, initialize the second communication bus, and notify the second chip to boot sequentially via the second communication bus; The startup process of the second chip includes: In response to the first notification message sent by the first chip, the second firmware is read from the off-chip storage through the first communication bus, the device is started based on the second firmware, and a first response message is returned to the first chip. The first response message is used to indicate that the second chip has completed its startup and can notify the second chip to start up next.

9. A computing device, characterized in that, include: A motherboard, a processor mounted on the motherboard, and a PCIe card, wherein the PCIe card includes the PCIe card as described in claim 8.

10. The computing device according to claim 9, characterized in that, The PCIe card includes a neural network processor.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the startup method according to any one of claims 1 to 9.

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