System real-time optimization method based on Loongson processor core

Abstract

The invention provides a system real-time performance optimization method based on a Loongson processor core, and relates to the field of chip processors, the system real-time performance optimization method based on the Loongson processor core comprises the following steps: S01, obtaining real-time performance demand information A of a chip processor in a Loongnix operating system environment; s02, determining a real-time optimized target parameter set B according to the real-time performance demand information A; according to the technical scheme, the process and thread switching time can be remarkably shortened, the task response delay is shortened so as to improve the real-time response capability of the system, and the method has the following beneficial effects that firstly, the system can interrupt the currently executed task at any time and then execute another task with a higher priority; and secondly, the system has the capability of completing task processing and making a response within a preset time, delay in task processing can be reduced by optimizing a scheduling algorithm and other related mechanisms, and jitter caused by task scheduling is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip processors, and in particular to a method for optimizing the real-time performance of a system based on the Loongson processor core. Background Technology

[0002] With the continuous development of industrial control, the real-time requirements for embedded systems are becoming increasingly stringent. The Loongson 2K1000 processor, a domestically produced high-performance processor, has been widely used in many fields. However, in certain industrial control scenarios with high real-time requirements, the pre-installed Loongnix operating system's real-time performance cannot fully meet the demands. Specifically, when the system needs to respond quickly to external events, the existing operating system's scheduling mechanism results in long process switching times, thread switching times, and task response delays, directly impacting the system's real-time responsiveness and reliability. Therefore, improving the real-time performance of systems based on the Loongson 2K1000 processor has become an urgent problem to solve, especially when multiple tasks are executed concurrently, where the extended system response time becomes a key bottleneck restricting its further application. Summary of the Invention

[0003] To address the shortcomings of the existing technologies, the technical problem to be solved by this invention is to provide a system real-time optimization method based on the Loongson processor core, which can significantly reduce process and thread switching time, shorten task response latency, and improve the real-time response capability of the system.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A system real-time performance optimization method based on the Loongson processor core includes the following steps:

[0006] S01. Obtain the real-time performance requirements of the chip processor under the Loongnix operating system environment;

[0007] S02. Determine the set of target parameters B for real-time performance optimization based on real-time performance requirement information A;

[0008] The target parameter set B includes at least the process switching time T. proc Thread switching time T thread and task response delay time T resp .

[0009] The preferred solution also includes the following steps:

[0010] S03. Obtain the process switching time information T from the target parameter set B. proc ;

[0011] S04, Based on process switching time information T proc It integrates the RT-Preempt patch and optimizes the scheduling strategy to reduce context switching overhead, improve interrupt handling and memory management, and reduce latency during process switching;

[0012] S05. Obtain thread switching time information T from the target parameter set B. thread ;

[0013] S06, Based on thread switching time information T thread Configure thread affinity, adjust thread priority, optimize locking mechanisms and thread-local storage to reduce thread switching latency;

[0014] S07. Obtain the task response delay time information T from the target parameter set B. resp ;

[0015] S08. Based on the task response delay time information T resp By adjusting the interrupt response mechanism, enhancing kernel preemption, optimizing memory management strategies, and adopting a real-time task scheduler, task response latency is reduced.

[0016] In the preferred scheme, the process switching time T proc The following formula is used to determine:

[0017] The optimized scheduling formula based on the integrated RT-Preempt patch is as follows:

[0018] T proc =T ctx_save +T ctx_restore +T sched (1);

[0019] Among them, T ctx_save To save the context time, T ctx_restore For context recovery time, T sched For scheduling time;

[0020] Based on context switching time T ctx_sw The formula is:

[0021] T ctx_sw =N ctx_sw ×(T ctx_save +T ctx_restore (2);

[0022] Among them, N ctx_sw For the number of context switches;

[0023] The optimization formula based on interrupt handling is:

[0024] T irq =Tirq_detect +T irq_handle (3);

[0025] Among them, T irq For interrupt response time, T irq_detect To interrupt the detection time, T irq_handle This is the interruption processing time.

[0026] In the preferred scheme, the thread switching time information T thread The following formula is used to determine:

[0027] The formula based on thread affinity is:

[0028] T thread =T migrate +T ctx_sw (4);

[0029] Among them, T thread T is the thread switching time. migrate T is the thread migration time. ctx_sw Context switching time;

[0030] The formula based on the locking mechanism is:

[0031] T lock =P lock ×T block (5);

[0032] Among them, T lock For delays caused by lock contention, P lock For the probability of lock contention, T block This represents the thread blocking time.

[0033] In the preferred scheme, the task response delay time T resp The following formula is used to determine:

[0034] T resp =T irq +T sched (6);

[0035] Among them, T resp Allow the task a corresponding delay time.

[0036] The preferred scheme also includes process switching time statistics R. proc Thread switching time statistics R thread ;

[0037] T proc_i T represents the time of the i-th process switch. thread_i Let i be the time of the i-th thread switch;

[0038] N procTo count the total number of process switches; N thread To count the total number of thread switches;

[0039] For N proc Secondary process switching time T proc_1 ,T proc_2 ,…,T proc_N Perform summation;

[0040] For N thread Secondary process switching time T thread_1 ,T thread_2 ,…,T thread_N Perform summation;

[0041] Furthermore, R proc For the Nth proc The average of the next process switching time;

[0042] Process switching time statistics R proc The formula is:

[0043]

[0044] Right now:

[0045]

[0046] Among them, R proc By N proc Sum the process switching times and then divide by N. proc The process of obtaining the average process switching time.

[0047] Furthermore, R thread For the Nth thread The average value of the thread switching time;

[0048] Thread switching time statistics R thread The formula is:

[0049]

[0050] Right now:

[0051]

[0052] Among them, R thread By analyzing N thread Sum the thread switching times and then divide by N. thread The process of obtaining the average thread switching time.

[0053] In the preferred solution, obtain the performance difference information D before and after optimization. perfand verification testing tools;

[0054] Based on the performance difference information before and after optimization, D perf And use verification testing tools to determine the performance of the optimized system;

[0055] Performance difference information before and after optimization D perf The following formula is used to determine:

[0056] D perf =T before -T after (9);

[0057] Among them, T before T represents the task response time before optimization. after This refers to the optimized task response time.

[0058] In a preferred embodiment, the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the steps of any of the above-described system real-time optimization methods based on the Loongson processor core.

[0059] In a preferred embodiment, the present invention provides a computer non-transitory readable storage medium storing a computer program / instruction thereon, characterized in that the computer program / instruction, when executed by a processor, implements the steps of the system real-time optimization method based on the Loongson processor core described above.

[0060] In a preferred embodiment, the present invention further provides a computer program product, including a computer program / instruction, characterized in that, when the computer program / instruction is executed by one or more processors, it implements the steps of the system real-time optimization method based on the Loongson processor core described above.

[0061] This invention provides a system real-time optimization method based on the Loongson processor core. Through the cooperation between the above structures, the process and thread switching time can be significantly reduced, and the task response latency can be shortened to improve the real-time response capability of the system. It has the following beneficial effects: First, the system can interrupt the currently executing task at any time and switch to another higher priority task; second, the system can complete task processing and respond within a predetermined time. By optimizing the scheduling algorithm and other related mechanisms, the latency in task processing can be reduced, and the jitter caused by task scheduling can be reduced, making the system run more smoothly. Attached Figure Description

[0062] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0063] Figure 1 This is a flowchart of the real-time optimization method of the present invention;

[0064] Figure 2 This is a flowchart of the process switching time statistics software of the present invention;

[0065] Figure 3 This is a flowchart of the thread switching time statistics software of the present invention;

[0066] Figure 4 This is the test software and hardware environment table for this invention;

[0067] Figure 5 This is a comparison table of the process switching times between real-time Loongnix and native Loongnix in this invention;

[0068] Figure 6 This is a comparison table of real-time Loongnix and native Loongnix line switching times in this invention;

[0069] Figure 7 This is a schematic diagram of the structure of the computer device of the present invention. Detailed Implementation

[0070] Example

[0071] like Figure 1 As shown, by integrating the RT-Preempt patch, optimizing the scheduling strategy, reducing context switching overhead, and improving interrupt handling and memory management, the preemptibility and real-time response capability of the Loongson processor under the Loongnix operating system environment can be improved. The technical solution is described in detail below:

[0072] A system real-time performance optimization method based on the Loongson processor core includes the following steps:

[0073] S01. Obtain the real-time performance requirements of the chip processor under the Loongnix operating system environment;

[0074] S02. Determine the set of target parameters B for real-time performance optimization based on real-time performance requirement information A;

[0075] The target parameter set B includes at least the process switching time T. proc Thread switching time T thread and task response delay time T resp ;

[0076] S03. Obtain the process switching time information T from the target parameter set B. proc ;

[0077] S04, Based on process switching time information T procIt integrates the RT-Preempt patch and optimizes the scheduling strategy to reduce context switching overhead, improve interrupt handling and memory management, and reduce latency during process switching;

[0078] S05. Obtain thread switching time information T from the target parameter set B. thread ;

[0079] S06, Based on thread switching time information T thread Configure thread affinity, adjust thread priority, optimize locking mechanisms and thread-local storage to reduce thread switching latency;

[0080] S07. Obtain the task response delay time information T from the target parameter set B. resp ;

[0081] S08. Based on the task response delay time information T resp By adjusting the interrupt response mechanism, enhancing kernel preemption, optimizing memory management strategies, and adopting a real-time task scheduler, task response latency is reduced.

[0082] Preferred solutions include Figure 2 , 3 To demonstrate in more detail how to optimize the real-time performance of the Loongson processor under the Loongnix operating system, an example is provided and the calculation process is further expanded:

[0083] The given numerical data is as follows:

[0084] Context save time T ctx_save =2μs;

[0085] Context recovery time T ctx_restore =2μs;

[0086] Scheduling time T sched =1μs;

[0087] Number of context switches N ctx_sw =1000;

[0088] Interruption detection time T irq_detect =1μs;

[0089] Interrupt handling time T irq_handle =2μs;

[0090] Thread migration time T migrate =1μs;

[0091] Lock contention probability P lock =0.1;

[0092] Thread blocking time T block =10μs;

[0093] Total number of process switches N proc =10000;

[0094] Count the total number of thread switches N thread =10000;

[0095] Optimized scheduling of process switching time T based on integrated RT-Preempt patch proc The following formula is used to determine:

[0096] T proc =T ctx_save +T ctx_restore +T sched (1);

[0097] Among them, T ctx_save Context saving time is used to save the current process's register state and stack pointer into memory;

[0098] Calculation method: Measure the time required to save all register states and stack pointers.

[0099] Substitute data: T ctx_save =2μs.

[0100] T ctx_restore This is for context recovery time, used to load the register state and stack pointer of the new process from memory.

[0101] Calculation method: Measure the time required to load the register states and stack pointer.

[0102] Substitute data: T ctx_restore =2μs.

[0103] T sched This is the scheduling time, used by the kernel to determine the next process to be executed.

[0104] Calculation method: Measure the time from decision to actual switchover.

[0105] Substitute the data: scheduling time T sched =1μs;

[0106] Example calculation:

[0107] T proc = 2μs + 2μs + 1μs = 5μs;

[0108] Calculation process:

[0109] Context save time T ctx_saveDuring process switching, the current process needs to save its context (such as register state, stack pointer, etc.) to memory so that this information can be reused upon resumption. This operation takes approximately 2μs.

[0110] Context recovery time T ctx_restore When a new process is scheduled to execute, it needs to restore its context information from memory, which also takes about 2μs.

[0111] Scheduling time T sched The kernel needs to make scheduling decisions and select the next process to be executed, which usually takes 1μs.

[0112] Based on context switching time T ctx_sw The formula is:

[0113] T ctx_sw =N ctx_sw ×(T ctx_save +T ctx_restore (2);

[0114] Among them, N ctx_sw This represents the number of context switches, specifically the number of context switches that occur within a given time period.

[0115] Calculation method: Count the number of context switches within a certain period of time.

[0116] Substitute the data: Number of context switches N ctx_sw =1000.

[0117] Single context switch time: The total time required for each context switch.

[0118] Calculation method: T ctx_save +T ctx_restore ;

[0119] Substitute data: T ctx_save +T ctx_restore =2μs + 2μs = 4μs;

[0120] Example calculation:

[0121] T ctx_sw =1000×(2μs+2μs)=1000×4μs=4000μs;

[0122] Calculation process:

[0123] Number of context switches N ctx_sw Suppose that 1000 context switches occur within a specific time window.

[0124] Time for each context switch: According to formula (1), the time for each context switch is 5μs, but since the total time is calculated here, T is used. ctx_save +T ctx_restore .

[0125] The optimization formula based on interrupt handling is:

[0126] T irq =T irq_detect +T irq_handle (3);

[0127] Among them, T irq Interruption response time;

[0128] T irq_detect This is the interrupt detection time, used by the system to detect interrupt signals sent by external devices.

[0129] Calculation method: Measure the time from when the hardware interrupt signal arrives at the kernel to when the detection is completed.

[0130] Substitute data: T irq_detect =1μs

[0131] T irq_handle This is the interrupt handling time, the processing time required to handle the interrupt.

[0132] Calculation method: Measure the time required for the interrupt handler function to execute.

[0133] Input data: Interrupt handling time T irq_handle =2μs;

[0134] Based on the above data, the following calculations can be made:

[0135] T irq =1μs + 2μs = 3μs;

[0136] Calculation process:

[0137] Interruption detection time T irq_detect The system detected an interrupt signal from an external device, which took 1μs.

[0138] Interrupt handling time T irq_handle The processing time required to handle this interrupt is 2μs.

[0139] Preferred solutions include Figure 1-3 In the middle, thread switching time information T thread The following formula is used to determine:

[0140] The formula based on thread affinity is:

[0141] T thread =Tmigrate +T ctx_sw (4);

[0142] Among them, T thread T is the thread switching time. migrate T is the thread migration time. ctx_save To save the context time, T ctx_restore For context recovery time;

[0143] The time for a single context switch is calculated as follows:

[0144] T thread = 1μs + 5μs = 6μs;

[0145] Calculation process:

[0146] Thread migration time T migrate When a thread migrates from one CPU core to another, the process takes 1μs.

[0147] The T here ctx_sw This likely refers to the time of a single context switch, not the total context switch time. The time of a single context switch, T... ctx_sw According to formula (1), the time for a single context switch is 5μs.

[0148] The formula based on the locking mechanism is:

[0149] T lock =P lock ×T block (5);

[0150] Among them, T lock For delays caused by lock contention, P lock For the probability of lock contention, T block This refers to the thread blocking time.

[0151] Calculation process:

[0152] Lock contention probability P lock In a multithreaded environment, threads need to acquire locks when accessing shared resources, and a thread may attempt to acquire the lock but fail.

[0153] Calculation method: Count the number of times you tried to acquire the lock but failed within a certain period of time, and divide the total number of attempts.

[0154] Substitute data: P lock =0.1.

[0155] Thread blocking time T block A thread enters a blocked state because it failed to acquire the lock, and remains blocked until the lock is released.

[0156] Calculation method: Measure the time a thread is blocked while waiting for a lock.

[0157] Substitute data: T block =10μs.

[0158] Based on the above values, an example calculation is performed:

[0159] T lock =0.1×10μs=1μs;

[0160] Preferred solutions include Figure 1-3 In the middle, the task response delay time T resp The following formula is used to determine:

[0161] T resp =T irq +T sched (6);

[0162] Among them, T resp Allow the task a corresponding delay time;

[0163] Calculation process:

[0164] Interrupt response time T irq According to formula (3), the time from detecting the interrupt and starting processing is the time from detecting the interrupt signal to completing the interrupt processing. The interrupt response time is: T irq =3μs.

[0165] Scheduling time T sched The time required for the kernel to perform scheduling, i.e., the time from when the kernel makes a scheduling decision to when the actual switch occurs, is denoted as T. sched = 1μs.

[0166] Based on the above values, an example calculation is performed:

[0167] T resp =3μs + 1μs = 4μs;

[0168] Preferred solutions include Figure 5 , 6 The data also includes process switching time statistics (R). proc Thread switching time statistics R thread ;

[0169] T proc_i T represents the time of the i-th process switch. thread_i Let i be the time of the i-th thread switch;

[0170] N proc To count the total number of process switches; N thread To count the total number of thread switches;

[0171] For N proc Secondary process switching time T proc_1 ,T proc_2 ,…,T proc_N Perform summation;

[0172] For N thread Secondary process switching time T thread_1 ,T thread_2 ,…,T thread_N Perform summation;

[0173] Furthermore, R proc For the Nth proc The average of the next process switching time;

[0174] Process switching time statistics R proc The formula is:

[0175]

[0176] Right now:

[0177]

[0178] Among them, R proc By N proc Sum the process switching times and then divide by N. proc The process of obtaining the average process switching time.

[0179] Furthermore, R thread For the Nth thread The average value of the thread switching time;

[0180] Total number of process switches N thread The number of process switches that occur within a certain period of time.

[0181] Calculation method: Count the number of process switches within a certain period of time.

[0182] Substitute the data: N thread =10000

[0183] The time T for each process switch proc_i : The actual time for each process switch.

[0184] Substitute data: T proc_i =5μs

[0185] Based on the aforementioned calculated values, the time for each process switch is set to T. proc ,but:

[0186]

[0187] Calculation process:

[0188] Total number of process switches N proc Within a specific time window, the system experienced 10,000 process switches.

[0189] The time T for each process switch proc According to formula (1), the time for each process switch is 5μs.

[0190] Thread switching time statistics R thread The formula is:

[0191]

[0192] Right now:

[0193]

[0194] Among them, R thread By analyzing N thread Sum the thread switching times and then divide by N. thread The process of obtaining the average thread switching time;

[0195] Based on the aforementioned calculated values, the thread switching time is set to T. thread ,but:

[0196]

[0197] Calculation process:

[0198] Count the total number of thread switches N thread Within a specific time window, the system experienced 10,000 thread switches.

[0199] The time T for each thread switch thread According to formula (4), the time for each thread switch is 6μs.

[0200] Preferred solutions include Figure 1 , 2 In the middle, obtain performance difference information before and after optimization D perf and verification testing tools;

[0201] Based on the performance difference information before and after optimization, D perf And use verification testing tools to determine the performance of the optimized system;

[0202] Performance difference information before and after optimization D perf The following formula is used to determine:

[0203] D pref =Tbefore -T after (9)

[0204] Among them, T before T represents the task response time before optimization. after This refers to the optimized task response time.

[0205] Calculation process:

[0206] Task response time T before optimization before Before any optimizations were performed, the system's task response time was 10 μs.

[0207] Optimized task response time T after After a series of optimization measures, the system's task response time was reduced to 4μs.

[0208] Based on the aforementioned calculations, the task response time before numerical optimization is T. before =10μs, the optimized task response time is T after =4μs, then:

[0209] D perf =10μs - 4μs = 6μs;

[0210] Through the detailed calculations and analyses in the above examples, it can be seen that by integrating the RTPreempt patch, optimizing the scheduling strategy, reducing context switching overhead, and improving interrupt handling and memory management, the real-time performance of the Loongson processor in the Loongnix operating system environment has been significantly improved.

[0211] In particular, the task response time has been reduced from 10μs to 4μs, showing a significant optimization effect. These calculation results provide valuable reference for the design and optimization of real-time systems.

[0212] Example 2

[0213] Further explanation in conjunction with Example 1, such as Figure 7 The structure shown. Figure 7 A schematic diagram of the structure of a computer device provided in an embodiment of this application. The computer device includes:

[0214] Processor, memory, communication bus, and computer programs stored in memory that can run on the processor.

[0215] The processor can call a computer program in memory to implement the system real-time optimization method based on the Loongson processor core provided in the above embodiments when executing the program. The method includes: S01, obtaining real-time performance requirement information A of the chip processor in the Loongnix operating system environment; S02, determining the target parameter set B for real-time optimization based on the real-time performance requirement information A; wherein, the target parameter set B includes at least process switching time T_proc, thread switching time T_thread, and task response delay time T_resp.

[0216] Furthermore, computer equipment also includes:

[0217] The Communications Interface (CI) is used for communication between the memory and the processor.

[0218] The memory may include high-speed RAM, and may also include non-volatile memory, such as at least one disk drive.

[0219] If the memory, processor, and communication interface are implemented independently, they can be interconnected via a bus to communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0220] Furthermore, when the logical instructions in the aforementioned memory can be implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0221] A processor may include one or more processing units, such as an application processor (AP), an application-specific integrated circuit (ASIC), a modem processor, a central processing unit (CPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors. The controller may serve as a central nervous system and command center. The controller generates operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution. The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has recently used or that is used repeatedly. If the processor needs to reuse the instruction or data, it can directly retrieve it from the memory. This avoids repeated access, reduces processor waiting time, and thus improves system efficiency.

[0222] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0223] Display devices are used to display images, videos, etc. Display devices may include display panels, which may employ liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), active-matrix organic light-emitting diodes (AMOLEDs), flexible light-emitting diodes (FLEDs), MiniLEDs, MicroLEDs, Micro-OLEDs, quantum dot light-emitting diodes (QLEDs), etc.

[0224] Alternatively, in a specific implementation, if the memory, processor, and communication interface are integrated on a single chip, then the memory, processor, and communication interface can communicate with each other through an internal interface.

[0225] On the other hand, embodiments of this application also provide a computer non-transitory readable storage medium storing a computer program thereon. When the program is executed by a processor, it implements the above-described system real-time optimization method based on the Loongnix processor core. The method includes: S01, obtaining real-time performance requirement information A of the chip processor under the Loongnix operating system environment; S02, determining a set of target parameters B for real-time optimization based on the real-time performance requirement information A; wherein the set of target parameters B includes at least process switching time T_proc, thread switching time T_thread, and task response delay time T_resp.

[0226] In another aspect, embodiments of this application also provide a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. The computer program can execute computer instructions. When the computer program is executed by a processor, the computer can execute the system real-time optimization method based on the Loongnix processor core provided by the above methods. The method includes: S01, obtaining real-time performance requirement information A of the chip processor under the Loongnix operating system environment; S02, determining the target parameter set B for real-time optimization based on the real-time performance requirement information A; wherein the target parameter set B includes at least process switching time T_proc, thread switching time T_thread, and task response delay time T_resp.

[0227] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0228] For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit a program for use in or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. Furthermore, a computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0229] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0230] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0231] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0232] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0233] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0234] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A system real-time performance optimization method based on the Loongson processor core, characterized in that, The following steps are involved: S01. Obtain the real-time performance requirements of the chip processor under the Loongnix operating system environment; S02. Determine the set of target parameters B for real-time performance optimization based on real-time performance requirement information A; The target parameter set B includes at least the process switching time T. proc Thread switching time T thread and task response delay time T resp .

2. The system real-time performance optimization method based on the Loongson processor core according to claim 1, characterized in that, It also includes the following steps: S03. Obtain the process switching time information T from the target parameter set B. proc ; S04, Based on process switching time information T proc It integrates the RT-Preempt patch and optimizes the scheduling strategy to reduce context switching overhead, improve interrupt handling and memory management, and reduce latency during process switching; S05. Obtain thread switching time information T from the target parameter set B. thread ; S06, Based on thread switching time information T thread Configure thread affinity, adjust thread priority, optimize locking mechanisms and thread-local storage to reduce thread switching latency; S07. Obtain the task response delay time information T from the target parameter set B. resp ; S08. Based on the task response delay time information T resp By adjusting the interrupt response mechanism, enhancing kernel preemption, optimizing memory management strategies, and adopting a real-time task scheduler, task response latency is reduced.

3. The system real-time performance optimization method based on the Loongson processor core according to claim 1, characterized in that, Process switching time T proc The following formula is used to determine: The optimized scheduling formula based on the integrated RT-Preempt patch is as follows: T proc =T ctx_save +T ctx_restore +T sched (1); Among them, T ctx_save To save the context time, T ctx_restore For context recovery time, T sched For scheduling time; Based on context switching time T ctx_sw The formula is: T ctx_sw =N ctx_sw ×(T ctx_save +T ctx_restore ) (2); Among them, N ctx_sw For the number of context switches; The optimization formula based on interrupt handling is: T irq =T irq_detect +f irq_handle (3); Among them, T irq For interrupt response time, T irq_detect To interrupt the detection time, T irq_handle This is the interruption processing time.

4. The system real-time performance optimization method based on the Loongson processor core according to claim 3, characterized in that, Thread switching time information T thread The following formula is used to determine: The formula based on thread affinity is: T thread =T migrate +T ctx_sw (4); Among them, T thread T is the thread switching time. migrate T is the thread migration time. ctx_sw Context switching time; The formula based on the locking mechanism is: T lock =P lock ×T block (5); Among them, T lock For delays caused by lock contention, P lock For the probability of lock contention, T block This represents the thread blocking time.

5. The system real-time performance optimization method based on the Loongson processor core according to claim 1 or 2, characterized in that, Task response delay time T resp The following formula is used to determine: T resp =T irq +T sched (6); Among them, T resp Allow the task a corresponding delay time.

6. The system real-time performance optimization method based on the Loongson processor core according to any one of claims 1 to 4, characterized in that, It also includes process switching time statistics R proc Thread switching time statistics R thread ; T proc_i Let i be the time of the i-th process switch; T thread_i Let i be the time of the i-th thread switch; N proc To count the total number of process switches; N thread To count the total number of thread switches; For N proc Secondary process switching time T proc_1 ,T proc_2 ,…,T proc_N Perform summation; For N thread Secondary process switching time T thread_1 ,T thread_2 ,…,T thread_N Perform summation; Furthermore, R proc For the Nth proc The average of the next process switching time; Process switching time statistics R proc The formula is: Right now: Among them, R proc By N proc Sum the process switching times and then divide by N. proc The process of obtaining the average process switching time. Furthermore, R thread For the Nth thread The average value of the thread switching time; Thread switching time statistics R thread The formula is: Right now: Among them, R thread By analyzing N thread Sum the thread switching times and then divide by N. thread The process of obtaining the average thread switching time.

7. The system real-time performance optimization method based on the Loongson processor core according to claim 1, characterized in that, Obtain performance difference information before and after optimization D perf and verification testing tools; Based on the performance difference information before and after optimization, D perf And use verification testing tools to determine the performance of the optimized system; Performance difference information before and after optimization D perf The following formula is used to determine: D perf =T before -T after (9); Among them, T before T represents the task response time before optimization. after This refers to the optimized task response time.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the system real-time optimization method based on the Loongson processor core as described in any one of claims 1-7.

9. A computer non-transitory readable storage medium storing computer programs / instructions thereon, characterized in that, When the computer program / instruction is executed by the processor, it implements the steps of the system real-time optimization method based on the Loongson processor core as described in any one of claims 1-7.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by one or more processors, it implements the steps of the system real-time optimization method based on the Loongson processor core as described in any one of claims 1-7.

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