Cache system and method based on three-dimensional dynamic random access memory

Abstract

The application provides a cache system and method based on three-dimensional dynamic random access memory, which comprises a plurality of dies, each of which has a plurality of processor units; a three-dimensional dynamic random access memory, a cache controller and a direct memory access engine are arranged on the processor unit; on the same processor unit, the direct memory access engine is connected with the three-dimensional dynamic random access memory and the cache controller respectively; the direct memory access engines on different processor units are connected; the direct memory access engine receives a cache request, determines a data block of a victim cache line and a position of the data block; if the victim cache line is in a modified state, the data block is removed and written into a data buffer of the direct memory access engine; the data to be stored in the cache request is written into the position of the data block; the data block is written back to a global memory, and the cache operation is completed; the cache system structure is reliable and can simultaneously meet the requirements of large capacity and low latency.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a high-speed cache system and method based on a three-dimensional dynamic random access memory. Background Technology

[0002] In recent years, with the development of deep learning, natural language processing and large-scale data mining technologies, the demand for artificial intelligence and big data computing has surged, placing unprecedented demands on computing platforms for high bandwidth and low latency.

[0003] Currently, common caching methods include: 1. A combination of on-chip static random access memory (SRAM) cache and external high-bandwidth memory; using high-speed SRAM as the L1 cache and high-bandwidth memory as the L2 or shared storage. 2. Traditional distributed three-dimensional dynamic random access memory (DRAM) storage method, which utilizes three-dimensional DRAM to construct large-capacity storage units, mainly relying on software control for data scheduling.

[0004] However, for the first caching method, traditional on-chip static random access memory (SRAM) is limited by area and cost, making it difficult to meet large-capacity requirements. External storage, such as high-bandwidth memory, while offering high bandwidth, is constrained by packaging and energy efficiency issues, resulting in limited overall system energy efficiency and latency. Neither method can simultaneously meet the requirements of capacity and low latency. For the second caching method, which relies on software control for data scheduling, there are issues with data transfer latency and high management complexity. Summary of the Invention

[0005] To address at least one problem in the prior art, this application proposes a cache system and method based on a three-dimensional dynamic random access memory. The cache system has a reliable structure and can simultaneously meet the requirements of large capacity and low latency.

[0006] To address the aforementioned technical problems, this application provides the following technical solution:

[0007] In a first aspect, this application provides a high-speed cache system based on three-dimensional dynamic random access memory, comprising: multiple dies, each die having multiple processor units; each processor unit having a three-dimensional dynamic random access memory, a cache controller, and a direct memory access engine;

[0008] On the same processor unit, the direct memory access engine is connected to the three-dimensional dynamic random access memory and the cache controller, respectively; direct memory access engines on different processing units are connected to each other;

[0009] The cache controller is used to send cache requests to the direct memory access engine on the same processor unit as the cache controller;

[0010] The direct memory access engine is configured to, based on the cache request, determine the data block of the victim cache line and its location from the three-dimensional dynamic random access memory (DRAM) on the same processor unit as the direct memory access engine; if the victim cache line is in a modified state, remove the data block and write it to the data buffer of the direct memory access engine; write the data to be stored in the cache request to the location of the data block; and write the data block in the data buffer back to the location of the victim cache line in global memory via the target direct memory access engine, thus completing the cache operation corresponding to the cache request. The target direct memory access engine and the location of the victim cache line in global memory are on the same processor unit.

[0011] In one embodiment, the cache controller is specifically configured to receive a data storage request containing a global memory address and data to be stored; if it is detected that the data blocks of each cache row in the three-dimensional dynamic random access memory on the same processing unit as the cache controller are full and there is no cache row corresponding to the global memory address in each cache row, then a distance parameter is obtained, and the distance value between each cache row and its corresponding position in the global memory is determined according to the distance parameter and a preset intelligent replacement strategy; based on each distance value, a victim cache row is determined from each cache row; and the cache request is sent to the direct memory access engine on the same processor unit as the cache controller.

[0012] The distance parameters include: single-hop latency, latency weighting coefficient, base number of hops between the cache line and its corresponding position in global memory, and number of cross-die operations; the cache request includes: the identifier of the victim cache line and the data to be stored.

[0013] In one embodiment, the direct memory access engine is further configured to, during the process of writing the data block into the data buffer, if the amount of data written exceeds a data amount threshold, send an early feedback alert to the cache controller on the same processor unit as the direct memory access engine; the cache controller then loads the data to be stored.

[0014] In one embodiment, the cache controller is specifically used for:

[0015] The distance D between cache line i and its corresponding location j in global memory is determined using the following formula. ij :

[0016] D ij =N ij ×T+w×M ij

[0017] Where, Nij Let T be the base hop count between cache line i and its corresponding location j in global memory, w be the single-hop latency, and M be the latency weighting factor. ij This represents the number of times cache line i crosses the raw disk between cache line i and its corresponding location j in global memory.

[0018] In one embodiment, the cache controller is specifically used for:

[0019] The cache lines whose corresponding distance values ​​are less than the distance threshold are identified as the victim cache lines.

[0020] In one embodiment, the cache controller is specifically used for:

[0021] Cache lines with a distance value less than the distance threshold are selected as cache lines to be filtered, and cache lines with an unmodified state are identified as the victim cache lines.

[0022] Correspondingly, the direct memory access engine is also used for:

[0023] The data block in the victim's cache line is replaced with the data to be stored in the cache request, thus completing the cache operation corresponding to the cache request.

[0024] Secondly, this application provides a high-speed caching method based on a three-dimensional dynamic random access memory, applied to the aforementioned high-speed caching system, the method comprising:

[0025] The cache controller sends cache requests to the direct memory access engine on the same processor unit as the cache controller.

[0026] According to the cache request, the Direct Memory Access Engine determines the data block of the victim cache line and its location from the 3D Dynamic Random Access Memory on the same processor unit as the Direct Memory Access Engine; if the state of the victim cache line is modified, the data block is removed and written to the data buffer of the Direct Memory Access Engine.

[0027] The direct memory access engine writes the data block in the data buffer back to the corresponding location of the victim cache line in global memory via the target direct memory access engine, thus completing the cache operation corresponding to the cache request. The target direct memory access engine and the location corresponding to the victim cache line in global memory are on the same processor unit.

[0028] In one embodiment, the cache controller sends cache requests to a direct memory access engine located on the same processor unit as the cache controller, including:

[0029] The cache controller receives a data storage request containing a global memory address and the data to be stored.

[0030] If it is detected that the data blocks of each cache line in the three-dimensional dynamic random access memory on the same processing unit as the cache controller are full and there is no cache line corresponding to the global memory address in each cache line, then the distance parameter is obtained, and the distance value between each cache line and its corresponding position in the global memory is determined according to the distance parameter and the preset intelligent replacement strategy.

[0031] The cache controller determines the victim cache line from each cache line based on various distance values; and sends the cache request to the direct memory access engine on the same processor unit as the cache controller.

[0032] The distance parameters include: single-hop latency, latency weighting coefficient, base number of hops between the cache line and its corresponding position in global memory, and number of cross-die operations; the cache request includes: the identifier of the victim cache line and the data to be stored.

[0033] In one embodiment, removing the data block and writing it to the data buffer of the direct memory access engine further includes:

[0034] During the process of writing the data block into the data buffer, if the amount of data written exceeds the data amount threshold, the direct memory access engine sends an early feedback alert to the cache controller located on the same processor unit; the cache controller then loads the data to be stored.

[0035] In one embodiment, determining the distance value between each cached line and its corresponding position in global memory based on the distance parameter and a preset intelligent replacement strategy includes:

[0036] The distance D between cache line i and its corresponding location j in global memory is determined using the following formula. ij :

[0037] D ij =N ij ×T+w×M ij

[0038] Where, N ij Let T be the base hop count between cache line i and its corresponding location j in global memory, w be the single-hop latency, and M be the latency weighting factor. ij This represents the number of times cache line i crosses the raw disk between cache line i and its corresponding location j in global memory.

[0039] In one embodiment, the cache controller determines the victim cache line from each of the cache lines based on various distance values, including:

[0040] The cache controller identifies cache lines whose corresponding distance values ​​are less than a distance threshold as the victim cache lines.

[0041] In one embodiment, the cache controller determines the victim cache line from each of the cache lines based on various distance values, including:

[0042] The cache controller will use cache lines whose corresponding distance values ​​are less than the distance threshold as cache lines to be filtered, and cache lines to be filtered that are not modified will be identified as the victim cache lines.

[0043] Correspondingly, after determining the data block of the victim cache line and its location in the three-dimensional dynamic random access memory on the same processor unit as the direct memory access engine, the process further includes:

[0044] The data block in the victim's cache line is replaced with the data to be stored in the cache request, thus completing the cache operation corresponding to the cache request.

[0045] Thirdly, this application provides an electronic device, including: the cache system based on the three-dimensional dynamic random access memory.

[0046] As can be seen from the above technical solution, this application provides a high-speed cache system and method based on three-dimensional dynamic random access memory (3D Dynamic Random Access Memory). The system includes: multiple dies, each die having multiple processor units; each processor unit having a 3D Dynamic Random Access Memory, a cache controller, and a direct memory access engine (DMI); on the same processor unit, the DMI is connected to both the 3D Dynamic Random Access Memory and the cache controller; DMIs on different processing units are interconnected; the cache controller sends cache requests to the DMI on the same processor unit as the cache controller; the DMI, based on the cache request, determines the data block of the victim cache line and its location from the 3D Dynamic Random Access Memory on the same processor unit as the DMI; if the victim cache line is in a modified state, the data block is removed and written into the data cache of the DMI. The process involves: 1) writing the data to be stored in the cache request to the location of the data block; 2) writing the data block in the data buffer back to the corresponding location of the victim cache line in global memory via the target direct memory access engine, thus completing the cache operation corresponding to the cache request. The target direct memory access engine and the corresponding location of the victim cache line in global memory are on the same processor unit. The cache system has a reliable structure and can simultaneously meet the requirements of large capacity and low latency. Specifically, large-capacity storage can be achieved through three-dimensional dynamic random access memory, and hardware control can be implemented through a cache controller and a direct memory access engine to reduce latency. Furthermore, the reuse of the data buffer in the direct memory access engine can avoid additional hardware overhead and improve cache efficiency. This allows for large-capacity storage, ensures access to large cache blocks, improves bandwidth utilization, and reduces unnecessary latency such as data replacement. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the structure of a cache system based on a three-dimensional dynamic random access memory in an embodiment of this application;

[0049] Figure 2 This is a schematic diagram of the first physical structure of a cache system based on a three-dimensional dynamic random access memory in an embodiment of this application;

[0050] Figure 3 This is a schematic diagram of the second physical structure of the cache system based on three-dimensional dynamic random access memory in the embodiments of this application;

[0051] Figure 4 This is a first structural schematic diagram of a cache system based on a three-dimensional dynamic random access memory in an application example of this application;

[0052] Figure 5 This is a schematic diagram of the second structure of a cache system based on a three-dimensional dynamic random access memory in an application example of this application;

[0053] Figure 6 This is a first flowchart illustrating the caching method based on a three-dimensional dynamic random access memory in an embodiment of this application.

[0054] Figure 7 This is a second flowchart illustrating the caching method based on a three-dimensional dynamic random access memory in an embodiment of this application.

[0055] Figure 8 This is a logical schematic diagram of the caching method based on three-dimensional dynamic random access memory in an application example of this application;

[0056] Figure 9 This is a schematic diagram illustrating the relationship between bare dies in an application example of this application. Detailed Implementation

[0057] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0058] To facilitate understanding of this solution, the technical terms related to this solution will be explained first.

[0059] 3D Dynamic Random Access Memory (3DDRAM): A memory technology that uses vertically stacked multilayer DRAM chips interconnected via through-silicon vias (TSVs). This technology can provide higher storage density and wider bandwidth per unit area while reducing power consumption.

[0060] High-bandwidth memory (HBM) enables high-speed data transfer with low power consumption and is widely used in computing and graphics processing fields that require high bandwidth support.

[0061] Static Random Access Memory (SRAM): Its storage cells are based on latches, which have fast access speeds but low integration density and are often used in caching applications.

[0062] Through-Silicon Via (TSV): A key technology that involves vertically drilling holes in a silicon wafer and filling them with conductive material to achieve interlayer interconnection, often used in 3D chip stacking.

[0063] Network on Chip (NoC): refers to a data communication network built inside a chip, used for high-speed data exchange between various functional units.

[0064] Direct Memory Access (DMA): Allows hardware modules to directly access main memory, reducing the CPU load and achieving higher data transfer efficiency.

[0065] Global Memory (Gmem) refers to a storage area accessible to all processors or cores throughout the system, used to store shared data or intermediate results.

[0066] Chip-to-chip interconnect (D2D): refers to the direct connection between multiple independent chips (or dies) to achieve high-speed data interaction.

[0067] Universal Chiplet Interconnect Express (UCIe) provides a standardized, high-speed interconnect solution between chips, promoting collaborative operation of multi-chip systems.

[0068] Least Recently Used (LRU) algorithm: It is a commonly used cache management strategy that keeps cache fresh by evicting data that has not been used for a long time.

[0069] Chiplets: These are the modular small units that make up the overall chip system. Chips are interconnected through standardized interfaces, which improves the flexibility of system design and manufacturing efficiency.

[0070] Artificial intelligence processor (AI Processor): A dedicated processor optimized for AI computing tasks (such as deep learning and neural network inference).

[0071] Cache line: The basic unit of data exchange between memory and cache, which determines the smallest granularity of data movement in the cache system.

[0072] 3D Cache: A caching system that utilizes three-dimensional stacking technology to improve performance and integration by vertically integrating multiple layers of cache.

[0073] Distance-aware technology optimizes scheduling by incorporating the actual physical or logical distance between components (such as communication latency) during the decision-making process.

[0074] The clean-first strategy prioritizes unmodified or "clean" data items during cache replacement to reduce write-back operations and lower latency.

[0075] A snoop filter is a hardware mechanism for cache consistency management that maintains data consistency in a multi-cache system by monitoring the transmission information on the data bus.

[0076] Early response mechanism refers to initiating subsequent processing procedures as soon as partial data arrives, providing early feedback that data preparation is complete, thereby reducing waiting time and improving system response speed.

[0077] Eviction buffer: A region that temporarily stores evicted data during cache replacement to ensure data consistency.

[0078] Processor unit (tile): A modular functional unit in chip design.

[0079] In existing technologies, the drawbacks of data caching include: high access latency: using simple cache replacement algorithms, such as the least recently used algorithm or a fixed priority replacement strategy, ignores the impact of internal chip physical distance and interconnect latency, easily leading to inefficient data scheduling across dies or processor units. That is, when data is transferred between different dies or processor units, high access latency and cache replacement delays often occur due to insufficient consideration of physical location factors.

[0080] High management complexity: Software-controlled 3D DRAM read and write operations increase the system scheduling burden, and traditional eviction buffer designs have hidden dangers in terms of area and power consumption.

[0081] Low resource utilization: Failure to fully reuse DMA engine resources leads to additional hardware overhead, and there is a lack of dynamic optimization mechanisms for the chip's internal topology.

[0082] Considering the development of 3D stacking technology, multilayer DRAM chips can achieve high-bandwidth interconnection through through-silicon vias (TSVs) while reducing package area; and the chiplet design enables high-speed D2D interconnection between different dies, with NoC interconnection within the die, breaking through the area and process limitations of traditional large chips. To address at least one of the problems existing in the above-mentioned prior art, this application provides a high-speed cache system and method based on three-dimensional dynamic random access memory (DMA). This system can systematically optimize data handling, cache replacement, and control strategies, reducing latency caused by physical distance. While ensuring the advantages of large capacity and high bandwidth, it significantly reduces the latency of data access across dies / processor units. Through hardware-coordinated DMA control and data buffer reuse, it reduces the dependence on software scheduling and simplifies the data interaction mechanism between 3D DRAM and chip logic.

[0083] A smart replacement algorithm is designed based on distance information and cache status (such as clean / dirty flags) to achieve dynamic calibration and optimization, adapting to actual latency conditions under different topologies. The collaborative working mechanism between the DMA engine and the cache controller is optimized to reuse existing hardware resources, reduce redundant design, and achieve multi-module collaborative optimization under the premise of limited system resources (such as chip area and power consumption). This solution is applicable to system-on-a-chip (SoC), server chips, AI processors, multi-core processors, and chiplet-based computing / storage chips.

[0084] The following examples illustrate this in detail.

[0085] like Figure 1 As shown, in order to simultaneously meet the requirements of large capacity and low latency, this embodiment provides a high-speed cache system based on three-dimensional dynamic random access memory, including: multiple dies, each die having multiple processor units; each processor unit having a three-dimensional dynamic random access memory, a cache controller, and a direct memory access engine; on the same processor unit, the direct memory access engine is connected to the three-dimensional dynamic random access memory and the cache controller respectively; direct memory access engines on different processing units are interconnected; the cache controller is used to send cache requests to the direct memory access engine on the same processor unit as the cache controller.

[0086] The direct memory access engine is configured to, based on the cache request, determine the data block of the victim cache line and its location from the three-dimensional dynamic random access memory (DRAM) on the same processor unit as the direct memory access engine; if the victim cache line is in a modified state, remove the data block and write it to the data buffer of the direct memory access engine; write the data to be stored in the cache request to the location of the data block; and write the data block in the data buffer back to the location of the victim cache line in global memory via the target direct memory access engine, thus completing the cache operation corresponding to the cache request. The target direct memory access engine and the location of the victim cache line in global memory are on the same processor unit.

[0087] Specifically, the modified state can represent a "dirty" state, requiring a write-back to global memory. Currently, the usual practice is to wait for the data block to be written directly back to global memory before writing the data to be stored to the location of the data block. In this embodiment, the data block can be written to the data buffer first. The time to write the data block to the data buffer is usually shorter than the time to write the data block directly back to global memory, thus reducing the waiting time for writing the data to be stored. The direct memory access engine can send the data block in the data buffer to the target direct memory access engine, and the target direct memory access engine writes the data block back to the location in global memory corresponding to the victim cache line. The cache system can be a cache system for a multi-core AI processor; the target direct memory access engine can refer to a direct memory access engine on the same processor unit as the location in global memory corresponding to the victim cache line. The direct memory access engine can receive cache requests sent by the cache controller on the same processor unit; a portion of each three-dimensional dynamic random access memory can be configured as global memory, and another portion can be configured as a cache region. The cache region includes: the data blocks of each of the multiple cache lines, and the global memory configured in each three-dimensional dynamic random access memory can jointly form a complete global memory. Cache lines and their corresponding locations in global memory may exist across dies and / or processing units. For example, the data block of cache line A is in the 3D DRAM of processor unit 1, and the corresponding location of cache line A in global memory is in the 3D DRAM of processor unit 2. Assuming that the victim cache line is cache line A and A is in the modified state, then DMA engine 1 in processor unit 1 can move the data block of cache line A to the data buffer of DMA engine 1, write the data to be stored to the position before the data block was moved out, and send the data block in the data buffer to DMA engine 2 in processor unit 2. DMA engine 2 writes the data block back to the global memory address corresponding to cache line A in the 3D DRAM of processor unit 2.

[0088] Specifically, the cache request may include: an identifier of the victim cache line and the data to be stored; the identifier of the victim cache line is used to distinguish different cache lines and may be the access address of the victim cache line. Based on the identifier of the victim cache line, the data block of the victim cache line and its location can be determined from the three-dimensional dynamic random access memory (DRAM) on the same processor unit as the direct memory access engine. The three-dimensional DRAM can serve as a data array containing data blocks from multiple cache lines; the tag array can be separate from the data array and configured on the chip logic die.

[0089] To avoid prolonged data replacement time due to the failure to consider the impact of internal physical distance and interconnect latency when determining the victim cache line, in one embodiment, the cache controller is specifically configured to receive a data storage request containing a global memory address and the data to be stored; if it is detected that the data blocks of each cache line in the three-dimensional dynamic random access memory on the same processing unit as the cache controller are full and there is no cache line corresponding to the global memory address in each cache line, then a distance parameter is obtained, and the distance value between each cache line and its corresponding position in the global memory is determined according to the distance parameter and a preset intelligent replacement strategy; the victim cache line is determined from each cache line according to the distance value; and the cache request is sent to the direct memory access engine on the same processor unit as the cache controller; wherein, the distance parameter includes: single-hop latency, latency weighting coefficient, base hop count between the cache line and its corresponding position in the global memory, and number of cross-die steps; the cache request includes: the identifier of the victim cache line and the data to be stored.

[0090] Specifically, the data storage request can be a write operation request; the global memory address in the data storage request can be the address location in global memory where the data to be stored will be written. In this embodiment, when determining the victim cache line, the situation across dies and / or across processing units can be considered, which can improve the efficiency of subsequent data transmission.

[0091] For example, the cache controller 1 on the processing unit 1 can receive a write operation request containing a global memory address and the data to be stored. If the data blocks of each cache line of the 3D DRAM on the processing unit 1 are full and there is no cache line corresponding to the global memory address in each cache line, then the victim cache line is determined, and a cache request containing the data to be stored and the identifier of the victim cache line is sent to the DMA engine on the processing unit 1.

[0092] To avoid time delays caused by waiting for all data blocks to be written to the data buffer before loading data in the cache controller, in one embodiment, the direct memory access engine is further configured to send an early feedback alert to the cache controller on the same processor unit as the direct memory access engine if the amount of data written exceeds a data amount threshold during the process of writing the data block to the data buffer; the cache controller then loads the data to be stored.

[0093] To further improve the reliability of determining the distance value, in one embodiment, the cache controller is specifically used for:

[0094] The distance D between cache line i and its corresponding location j in global memory is determined using the following formula. ij :

[0095] D ij =N ij ×T+w×M ij

[0096] Where, N ij Let T be the base hop count between cache line i and its corresponding location j in global memory, w be the single-hop latency, and M be the latency weighting factor. ij This represents the number of hops between cache line i and its corresponding location j in global memory. The base hop count between cache line i and its corresponding location j in global memory can represent the number of processor units traversed between the target cache line i and location j. The single-hop latency and latency weighting coefficient can be preset according to actual conditions.

[0097] To improve the reliability of identifying victim cache lines, in one embodiment, the cache controller is specifically configured to: identify cache lines whose corresponding distance values ​​are less than a distance threshold as victim cache lines.

[0098] Specifically, when all cached lines are in a modified state or in a non-latency-sensitive scenario, cached lines with a distance value less than a distance threshold can be identified as the victim cached lines.

[0099] Furthermore, to improve the accuracy and intelligence of identifying victim cache lines, the access frequency, bandwidth utilization, and data update status of each cache line can be obtained. Based on the access frequency, bandwidth utilization, data update status, distance value, and a preset classification model, the score of each cache line is determined, and the cache line with the highest score is identified as the victim cache line. The preset classification model can be obtained by pre-training a classification algorithm based on batch training samples and their respective scores. The training samples include: access frequency, bandwidth utilization, data update status, and distance value of historical cache lines. The data update status includes: modified status and unmodified status.

[0100] To reduce latency during data write-back and minimize system uncertainty caused by cache replacement, in one embodiment, the cache controller is specifically configured to: designate cache lines with a distance value less than a distance threshold as cache lines to be filtered, and identify cache lines in an unmodified state as the victim cache lines; correspondingly, the direct memory access engine is further configured to: replace the data blocks in the victim cache lines with the data to be stored in the cache request, thereby completing the cache operation corresponding to the cache request.

[0101] Specifically, the unmodified state can represent the "clean" state.

[0102] To further illustrate this solution, this application provides an application example of a high-speed cache system based on three-dimensional dynamic random access memory (3D DRAM). In this application example, a 3D DRAM cache for multi-core AI processors can be implemented. While leveraging the advantages of 3D DRAM's large capacity and high bandwidth (i.e., still ensuring large-block data access and improving bandwidth utilization), the complexity of software management of 3D DRAM is reduced, achieving hardware management. The data buffer of the direct memory access engine (DMA engine) is reused, eliminating the need for an additional controller buffer. This optimizes the cache replacement strategy without increasing the on-chip cache area, introduces location latency information, and utilizes the DMA engine to return information early, reducing the time introduced by cache line replacement. This solution can significantly reduce access latency, improve overall bandwidth utilization, better adapt to the high concurrency requirements of AI computing, reduce data waiting time, and improve energy efficiency. It is suitable for AI processors, suitable for chiplets, distributed storage, and many-core processors. Applicable scenarios: AI processors, many-core systems, dataflow architectures, and chips; Design goals: large capacity, high bandwidth (large cache blocks), and low latency (reducing unnecessary latency such as replacement).

[0103] like Figure 2As shown, the cache system based on three-dimensional dynamic random access memory includes: a dynamic random access memory die (DRAM die), a chip logic die, and a substrate arranged sequentially from top to bottom; the bottom of the substrate has solder balls, and a flip chip (bump) is provided between the logic die and the substrate; the dynamic random access memory die and the logic die are connected by hybrid bonding (HB); the highest layer of the logic die is the top metal layer, and the logic die includes through silicon vias.

[0104] like Figure 3 As shown, a dynamic random access memory (DRAM) die can contain multiple 3D DRAMs, which can be used as a data array for cache. The cache controller and tag array are located on the chip logic die and are packaged together. This tag-and-data separation structure offers greater flexibility. The 3D DRAM can be a multi-bank structure, where the memory array (such as DRAM / SRAM) is divided into multiple independent logical partitions (Banks) to support parallel access and improve efficiency. For example, DRAM uses a multi-bank structure to achieve bank interleaving for read and write operations.

[0105] like Figure 4 As shown, processor units can communicate with each other via NoC or D2D. Processor units on the same die are connected via NoC, while processor units on different dies are connected via D2D. A processor unit tile is a chip system with multiple similar processor units distributed on different dies. The dies are connected via D2D, and different processor units within a die are interconnected via NoC. Each chip logic die can be equivalent to one of the aforementioned dies.

[0106] Each processor unit can include: an AI core / processor, an inner cache, a cache controller (private), a direct memory access engine (DMAengine), a 3D DRAM controller, and 3D DRAM (data array). The DMAengine can be located above the cache controller. The cache controller can include: register in, register out, prefetch, replacement, and other misctrl logic units; the cache controller can include tags, store buffers, miss queues, and load buffers; the DMAengine can include a controller (ctrl) and a data buffer; the 3D DRAM has a multi-bank structure, meaning it contains multiple 3D memory banks. Each processor unit can communicate with global memory (distributed), main memory, and non-volatile memory.

[0107] The AI ​​kernel employs a multi-level cache, consisting of an internal conventional cache based on static random access memory (SRAM) and an external 3D cache based on 3D DRAM, providing greater capacity. To ensure bandwidth, access to dynamic random access memory (DRAM) needs optimization to guarantee access to large blocks of data and improve efficiency. Access to the 3D cache is assisted by reusing the direct memory access engine, supporting data transfer between the 3D DARRAY and global memory to perform cached data operations. The controller is implemented in the logic section of the processor unit. To reduce area, the data buffer of the direct memory access engine is reused to store large blocks of data. The 3D DRAM uses a multi-bank approach, which can increase bandwidth. Optimizing the cache controller reduces access latency, which is particularly effective for this dataflow / many-core processor architecture.

[0108] 1. The overall system architecture includes:

[0109] 1) 3D DRAM Data Array: The multi-layer stacked DRAM adopts a multi-bank design, where each bank can work independently and in parallel, ensuring large-capacity storage and high-bandwidth data transmission. Each bank can contain multiple cache lines.

[0110] 2) Cache controller and tag array: Located on the chip logic die, it adopts an architecture design that is separate from the 3D DRAM data array, which makes data access and cache management more flexible, while reducing the area occupied by the main logic.

[0111] 3) DMA Coordination Module: The Direct Memory Access Engine is not only responsible for regular data movement, but also works in conjunction with the cache controller to achieve data prefetching, early response, and dynamic scheduling of data movement through a shared data buffer.

[0112] 2. Smart cache replacement strategies include:

[0113] 1) Distance-aware replacement algorithm: Based on the NoC hop count, D2D transmission delay, and the physical mapping relationship inside the chip, a weight value is set for each cache line. The weight formula can be dynamically adjusted according to the actual test data.

[0114] 2) Clean-first strategy: For latency-sensitive scenarios, prioritize replacing cache lines that are in a clean state to reduce latency consumption during data write-back and reduce system uncertainty caused by cache replacement.

[0115] 3) Dynamic calibration mechanism:

[0116] The system monitors the latency of each path in real time during operation and dynamically updates the distance weight and replacement strategy parameters through a feedback mechanism to ensure that the replacement decision is always in the optimal state.

[0117] 3. Extended Functionality:

[0118] Shared 3D cache design: For multi-processor units and multi-core systems, a consistency management module can be introduced, for example, such as... Figure 5 As shown, based on the snooping filter, the cache of multiple processor units within the die can be managed to achieve data consistency and order management between different processing units and support cross-die data sharing.

[0119] Hybrid storage system: The system can use other high-speed storage media such as DDR in some nodes according to actual needs, and work together with 3D DRAM to achieve the optimization of overall data scheduling through topology optimization.

[0120] The structural components may include:

[0121] 3D DRAM memory module:

[0122] 1) Multilayer DRAM chips are used, and interlayer interconnection is achieved through silicon vias. Each layer or each memory bank has an independent address mapping.

[0123] 2) The corresponding physical layout diagram can show the arrangement and interconnection of different memory libraries.

[0124] Cache control unit:

[0125] 1) Integrates the tag array and replacement strategy logic, and is responsible for monitoring the cache status and scheduling replacement operations.

[0126] 2) Hardware logic is used to implement real-time processing of address mapping, status flags and replacement weight calculation.

[0127] DMA control module:

[0128] 1) Working in conjunction with the cache control unit via a dedicated channel, it is responsible for initiating victim cache line transfer requests, reading 3D DRAM data, and writing the data into the reused data buffer.

[0129] 2) Implement an early return mechanism to reduce the total latency from data reading to cache replacement completion.

[0130] Interconnection module:

[0131] The internal interconnect of the die uses NoC, and different dies use D2D high-speed channels (such as UCIe) for data transmission to ensure optimal path scheduling in the system topology.

[0132] Furthermore, adaptive scheduling based on machine learning can be implemented by introducing machine learning algorithms to analyze cache access patterns in real time through big data, automatically adjusting replacement strategies and DMA scheduling parameters to achieve intelligent optimization. Cross-platform and multi-protocol integration can be explored, allowing for the integration with emerging technologies such as optical interconnects, in-package memory, and even quantum interconnects to build higher-performance, lower-latency hybrid storage systems. Heterogeneous computing platform collaborative optimization involves designing a unified cache sharing and consistency management mechanism for the heterogeneous integration of future CPUs, GPUs, FPGAs, and AI-dedicated accelerators, enabling seamless data interaction between various computing units. Security and fault tolerance mechanisms can be introduced during high-concurrency data transmission to ensure data consistency and system stability, adapting to the application needs of mission-critical domains. Future-oriented modular design not only facilitates future system upgrades but also allows for flexible configuration for different application scenarios (such as edge computing, data centers, and high-performance servers), ensuring the long-term adaptability of the technology roadmap.

[0133] As described above, the high-speed cache system based on 3D dynamic random access memory provided in this application example combines hardware with DMA control and intelligent cache replacement (using methods such as distance and clean) to reduce data transfer latency across die / processor units and improve overall bandwidth utilization. Reusing the DMA data buffer and optimizing the replacement mechanism reduces chip area consumption and power consumption, improving system energy efficiency. The tag-and-data separation architecture, dynamically calibrated replacement strategy, and consistency management supporting shared 3D cache provide a highly scalable solution for future multi-core and heterogeneous systems. Dynamic feedback and adaptive tuning mechanisms enable the system to automatically optimize data scheduling and cache management based on actual operating conditions, adapting to different application scenarios and improving adaptability and intelligent management. The 3D cache design scheme / concept introduces new ideas in cache management and data flow control, and combined with the DMA engine, it can reduce storage overhead and reduce software management complexity through caching. Increasing cache capacity ensures bandwidth utilization while reducing latency introduced by replacement, and to a certain extent, minimizing it.

[0134] like Figure 6 As shown, in order to simultaneously meet the requirements of large capacity and low latency, this application provides a high-speed caching method based on a three-dimensional dynamic random access memory, applied to the aforementioned high-speed caching system. The method specifically includes the following:

[0135] Step 100: The cache controller sends the cache request to the direct memory access engine on the same processor unit as the cache controller.

[0136] Step 200: The direct memory access engine determines the data block of the victim cache line and its location from the three-dimensional dynamic random access memory on the same processor unit as the direct memory access engine, according to the cache request; if the state of the victim cache line is modified, the data block is removed and written to the data buffer of the direct memory access engine.

[0137] Step 300: The direct memory access engine writes the data block in the data buffer back to the location in global memory corresponding to the victim cache line via the target direct memory access engine, completing the cache operation corresponding to the cache request. The target direct memory access engine and the location in global memory corresponding to the victim cache line are on the same processor unit.

[0138] like Figure 7 As shown, in one embodiment, step 100 includes:

[0139] Step 001: The cache controller receives a data storage request containing a global memory address and the data to be stored.

[0140] Step 002: If it is detected that the data blocks of each cache line in the three-dimensional dynamic random access memory on the same processing unit as the cache controller are full and there is no cache line corresponding to the global memory address in each cache line, then obtain the distance parameter, and determine the distance value between each cache line and its corresponding position in the global memory according to the distance parameter and the preset intelligent replacement strategy.

[0141] Step 003: The cache controller determines the victim cache line from each cache line based on the distance values; and sends a cache request to the direct memory access engine on the same processor unit as the cache controller; wherein, the distance parameters include: single-hop latency, latency weighting coefficient, base number of hops between the cache line and its corresponding position in global memory, and number of cross-die times; the cache request includes: the identifier of the victim cache line and the data to be stored.

[0142] In one embodiment, step 200, which involves removing the data block and writing it to the data buffer of the direct memory access engine, further includes:

[0143] During the process of writing the data block into the data buffer, if the amount of data written exceeds the data amount threshold, the direct memory access engine sends an early feedback alert to the cache controller located on the same processor unit; the cache controller then loads the data to be stored.

[0144] In one embodiment, step 002, determining the distance value between each cache line and its corresponding position in global memory based on the distance parameter and a preset intelligent replacement strategy, includes:

[0145] The distance D between cache line i and its corresponding location j in global memory is determined using the following formula. ij :

[0146] D ij =N ij ×T+w×M ij

[0147] Where, N ij Let T be the base hop count between cache line i and its corresponding location j in global memory, w be the single-hop latency, and M be the latency weighting factor. ij This represents the number of times cache line i crosses the raw disk between cache line i and its corresponding location j in global memory.

[0148] In one embodiment, the cache controller in step 003 determines the victim cache line from each of the cache lines based on various distance values, including:

[0149] The cache controller identifies cache lines whose corresponding distance values ​​are less than a distance threshold as the victim cache lines.

[0150] In one embodiment, the cache controller in step 003 determines the victim cache line from each of the cache lines based on various distance values, including:

[0151] The cache controller will use cache lines whose corresponding distance values ​​are less than the distance threshold as cache lines to be filtered, and cache lines to be filtered that are not modified will be identified as the victim cache lines.

[0152] Correspondingly, after determining the data block of the victim cache line and its location from the three-dimensional dynamic random access memory on the same processor unit as the direct memory access engine in step 200, the method further includes:

[0153] The data block in the victim's cache line is replaced with the data to be stored in the cache request, thus completing the cache operation corresponding to the cache request.

[0154] The embodiments of the high-speed caching method based on three-dimensional dynamic random access memory provided in this specification can be specifically applied to the embodiments of the high-speed caching system based on three-dimensional dynamic random access memory described above. Its functions will not be repeated here, but can be referred to the detailed description of the embodiments of the high-speed caching system based on three-dimensional dynamic random access memory described above.

[0155] To further illustrate this solution, this application provides an application example of a high-speed caching method based on a three-dimensional dynamic random access memory, such as... Figure 8 As shown, this method includes: a complete data transfer process from caching requests, data reading, early response to write-back.

[0156] Step 1: The cache controller sends a request to the Direct Memory Access Engine (DMI) informing it of the victim cache line information; the main controller in the DMI can receive the request and select a channel controller from multiple channel controllers, sending the request to the selected channel controller. Step 2: The DMI reads the victim cache line from 3D DRAM; this can be done by the selected channel controller. Step 3: The victim cache line in 3D DRAM is written to the data buffer. Step 4: The data buffer informs the channel controller that the victim cache line has been moved to the data buffer, and new data can be written to 3D DRAM. Step 5: The DMI informs the cache controller (early return, reducing latency by hundreds of ns). Step 6: The DMI writes the victim cache line from the data buffer back to global memory via NoC, D2D, etc. Step 7: After receiving the victim cache line, global memory returns the actual write completion information to the DMI. Step 8: The DMI informs the cache controller of the actual completion. The scheme based on direct memory access engine transfer reuses its resources, reduces the area of ​​the cache controller (logical dies and memory dies are separated, and traditional evict buffers are large and resource-intensive), and supports early return.

[0157] 2. The data transfer and control process may specifically include:

[0158] Step 11: Request Initiation: After the cache controller detects a cache overflow or replacement request, it sends the victim cache line information through the direct memory access channel.

[0159] Specifically, the cache controller can receive data storage requests containing a global memory address and data to be stored. The data storage request includes a target address and the data to be stored, where the target address is the address of the target cache line. If the cache system is detected to be full, cache lines with a clean status are selected as cache lines to be filtered. Based on single-hop latency, latency weighting coefficients, the base hop count between the target cache line and each cache line to be filtered, and the number of cross-disk operations, an intelligent replacement strategy is applied to determine the distance between the target cache line and each cache line to be filtered. Cache lines with a distance value less than a distance threshold are identified as the victim cache lines. The victim cache line information can be a unique identifier for the victim cache line, such as an ID.

[0160] Step 12: Data Reading: The Direct Memory Access Engine reads the corresponding data block from the 3D DRAM according to the request and writes it to the reserved data buffer.

[0161] Step 13: Early Response: After receiving some data, the data buffer notifies the cache controller through an early feedback mechanism, allowing new data to be loaded in advance and reducing waiting latency.

[0162] Step 14: Data write-back: Write the victim's cached line data back to global memory via NoC or D2D channels to complete the entire replacement process.

[0163] Step 15: Dynamic calibration: The system continuously monitors the latency of each module and uses the feedback data to adjust the parameters of the direct memory access scheduling and cache replacement strategy.

[0164] Furthermore, during data transmission, actual latency can be measured (e.g., via a counter included with the packet). The measured data can be fed back to the configuration register (for calculating distance and updating scheduling strategy selection). Based on the new data, the replacement method can be automatically adjusted, reducing software requirements. This can be used for congestion control, controlling and judging traffic flow.

[0165] 3. Implementation details of the intelligent replacement strategy:

[0166] Distance calculation:

[0167] Each cache line records its physical location, and the distance value is calculated using a formula by combining NoC hop count and D2D latency information.

[0168] Example formula: Distance = Base number of hops * Single hop delay + Delay weighting coefficient (based on actual delay measurement) × Number of times across the die; Parameters can be optimized based on experimental data.

[0169] Replacement priority determined:

[0170] Among multiple candidate cache lines, the cache line with the smaller distance value and a clean status is prioritized for replacement. Simultaneously, the system can combine information such as access frequency and data update status for a comprehensive evaluation to ensure the optimal replacement decision.

[0171] Dynamic feedback mechanism: The system periodically performs performance evaluations and feeds back key indicators such as latency and bandwidth utilization to the cache controller, automatically adjusting and replacing algorithm parameters to achieve adaptive management.

[0172] Based on traditional replacement strategies such as priority and LRU, this paper introduces methods such as ① distance awareness and ② cleanliness priority strategy to reduce the latency of replacement. The decision-making process and dynamic adjustment process based on distance awareness and cleanliness priority strategy are described below:

[0173] Each node has distributed global memory, and some nodes have high-speed DDR storage media, which is also global memory. It is not limited by the NoC topology and distance information can be calibrated based on measured data. The transmission time varies depending on the location of the die / processor unit. The weight is configurable and can be configured based on different latency levels. XP nodes can be configured as processor units / cores / processing elements (PEs). Between processor units / cores / PEs, the hop count is based on the NoC (obtained from the address-location mapping). Between dies, D2D latency information is added. The PE is the smallest core unit in the chip that performs computational tasks.

[0174] like Figure 9 As shown in the example, the single-hop latency is assumed to be 1 unit of time. Assuming cache line A corresponds to one of the following locations in global memory: B to E, one DDR, and another DDR, the base hop count between A and B is 1, and the distance is 1; the base hop count between A and C is 4, and the distance is 4; the base hop count between A and D is 7, the number of times it crosses the die is 1, and the distance is 7 + weight; the base hop count between A and E is 10, the number of times it crosses the die is 2, and the distance is 10 + weight * 2; the distance between A and one of the DDRs is 5; and the distance between A and another DDR is 6 + weight. The smaller the distance between each cache line and its corresponding location in global memory, the higher the priority for replacement, all other things being equal.

[0175] As shown in Table 1 below, a cache line can contain: valid bit, dirty bit, replacement bit, distance information and tag parameters; it can also contain data blocks, etc.

[0176] Table 1

[0177] Valid bits Visceral Replacement bit Distance information Label

[0178] As described above, the cache system and method based on three-dimensional dynamic random access memory provided in this application have a reliable cache system structure that can simultaneously meet the requirements of large capacity and low latency. Specifically, large-capacity storage can be achieved through three-dimensional dynamic random access memory, and hardware control can be achieved through a cache controller and a direct memory access engine to reduce latency. Furthermore, the reuse of data buffers in the direct memory access engine can avoid additional hardware overhead and improve cache efficiency. Large-capacity storage can be achieved, large cache block access can be guaranteed, bandwidth utilization can be improved, and unnecessary latency such as data replacement can be reduced.

[0179] This application uses specific embodiments to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A high-speed cache system based on a three-dimensional dynamic random access memory, characterized in that, include: Multiple bare dies, each with multiple processor units; Each processor unit is equipped with a three-dimensional dynamic random access memory, a cache controller, and a direct memory access engine; On the same processor unit, the direct memory access engine is connected to the three-dimensional dynamic random access memory and the cache controller, respectively; direct memory access engines on different processing units are connected to each other; The cache controller is used to send cache requests to the direct memory access engine on the same processor unit as the cache controller; The direct memory access engine is configured to, based on the cache request, determine the data block of the victim cache line and its location from the three-dimensional dynamic random access memory (DRAM) on the same processor unit as the direct memory access engine; if the victim cache line is in a modified state, remove the data block and write it to the data buffer of the direct memory access engine; write the data to be stored in the cache request to the location of the data block; and write the data block in the data buffer back to the location of the victim cache line in global memory via the target direct memory access engine, thus completing the cache operation corresponding to the cache request. The target direct memory access engine and the location of the victim cache line in global memory are on the same processor unit. The cache controller is specifically used to receive a data storage request containing a global memory address and data to be stored; if it is detected that the data blocks of each cache row in the three-dimensional dynamic random access memory on the same processing unit as the cache controller are full and there is no cache row corresponding to the global memory address in each cache row, then a distance parameter is obtained, and the distance value between each cache row and its corresponding position in the global memory is determined according to the distance parameter and a preset intelligent replacement strategy. Based on each distance value, determine the victim cache line from the cache lines described in each row; Send the cache request to the direct memory access engine, which is on the same processor unit as the cache controller; The distance parameters include: single-hop latency, latency weighting coefficient, base number of hops between the cache line and its corresponding position in global memory, and number of cross-die operations; the cache request includes: the identifier of the victim cache line and the data to be stored.

2. The high-speed cache system based on three-dimensional dynamic random access memory according to claim 1, characterized in that, The direct memory access engine is further configured to, during the process of writing the data block into the data buffer, if the amount of data written exceeds a data amount threshold, send an early feedback alert to the cache controller on the same processor unit as the direct memory access engine; the cache controller then loads the data to be stored.

3. The high-speed cache system based on three-dimensional dynamic random access memory according to claim 1, characterized in that, The cache controller is specifically used for: The distance between cache line i and its corresponding location j in global memory is determined using the following formula. : in, Let be the base number of hops between cache line i and its corresponding position j in global memory. For single-hop delay, This is the delay weighting coefficient. This represents the number of times cache line i crosses the raw disk between cache line i and its corresponding location j in global memory.

4. The high-speed cache system based on three-dimensional dynamic random access memory according to claim 1, characterized in that, The cache controller is specifically used for: The cache lines whose corresponding distance values ​​are less than the distance threshold are identified as the victim cache lines.

5. The high-speed cache system based on three-dimensional dynamic random access memory according to claim 1, characterized in that, The cache controller is specifically used for: Cache lines with a distance value less than the distance threshold are selected as cache lines to be filtered, and cache lines with an unmodified state are identified as the victim cache lines. Correspondingly, the direct memory access engine is also used for: The data block in the victim's cache line is replaced with the data to be stored in the cache request, thus completing the cache operation corresponding to the cache request.

6. A high-speed caching method based on a three-dimensional dynamic random access memory, characterized in that, Applied to the cache system according to any one of claims 1 to 5, the method comprises: The cache controller sends cache requests to the direct memory access engine on the same processor unit as the cache controller. According to the cache request, the Direct Memory Access Engine determines the data block of the victim cache line and its location from the 3D Dynamic Random Access Memory on the same processor unit as the Direct Memory Access Engine; if the state of the victim cache line is modified, the data block is removed and written to the data buffer of the Direct Memory Access Engine. The direct memory access engine writes the data block in the data buffer back to the corresponding location of the victim cache line in global memory via the target direct memory access engine, thus completing the cache operation corresponding to the cache request. The target direct memory access engine and the location corresponding to the victim cache line in global memory are on the same processor unit.

7. The high-speed caching method based on three-dimensional dynamic random access memory according to claim 6, characterized in that, The cache controller sends cache requests to the direct memory access engine on the same processor unit as the cache controller, including: The cache controller receives a data storage request containing a global memory address and the data to be stored. If it is detected that the data blocks of each cache line in the three-dimensional dynamic random access memory on the same processing unit as the cache controller are full and there is no cache line corresponding to the global memory address in each cache line, then the distance parameter is obtained, and the distance value between each cache line and its corresponding position in the global memory is determined according to the distance parameter and the preset intelligent replacement strategy. The cache controller determines the victim cache line from each cache line based on various distance values; and sends the cache request to the direct memory access engine on the same processor unit as the cache controller. The distance parameters include: single-hop latency, latency weighting coefficient, base number of hops between the cache line and its corresponding position in global memory, and number of cross-die operations; the cache request includes: the identifier of the victim cache line and the data to be stored.

8. The high-speed caching method based on three-dimensional dynamic random access memory according to claim 6, characterized in that, The step of removing the data block and writing it to the data buffer of the direct memory access engine further includes: During the process of writing the data block into the data buffer, if the amount of data written exceeds the data amount threshold, the direct memory access engine sends an early feedback alert to the cache controller located on the same processor unit; the cache controller then loads the data to be stored.

9. The high-speed caching method based on a three-dimensional dynamic random access memory according to claim 7, characterized in that, The step of determining the distance value between each cache line and its corresponding position in global memory based on the distance parameter and a preset intelligent replacement strategy includes: The distance between cache line i and its corresponding location j in global memory is determined using the following formula. : in, Let be the base number of hops between cache line i and its corresponding position j in global memory. For single-hop delay, This is the delay weighting coefficient. This represents the number of times cache line i crosses the raw disk between cache line i and its corresponding location j in global memory.

10. The high-speed caching method based on a three-dimensional dynamic random access memory according to claim 7, characterized in that, The cache controller determines the victim cache line from each cache line based on various distance values, including: The cache controller identifies cache lines whose corresponding distance values ​​are less than a distance threshold as the victim cache lines.

11. The high-speed caching method based on a three-dimensional dynamic random access memory according to claim 7, characterized in that, The cache controller determines the victim cache line from each cache line based on various distance values, including: The cache controller will use cache lines whose corresponding distance values ​​are less than the distance threshold as cache lines to be filtered, and cache lines to be filtered that are not modified will be identified as the victim cache lines. Correspondingly, after determining the data block of the victim cache line and its location in the three-dimensional dynamic random access memory on the same processor unit as the direct memory access engine, the process further includes: The data block in the victim's cache line is replaced with the data to be stored in the cache request, thus completing the cache operation corresponding to the cache request.

12. An electronic device, characterized in that, include: The cache system based on a three-dimensional dynamic random access memory as described in any one of claims 1 to 5.

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