A method, device, medium and program product for plugging a PCIE device

Abstract

Embodiments of the present application provide a method, device, medium and program product for plugging and unplugging a PCIE device, the method comprising: a system on a chip (SOC) receiving first instruction information; wherein the first instruction information is used to indicate whether a PCIE device is inserted or unplugged on a second device; in the case that the first instruction information indicates that the PCIE device is inserted in a first insertion mode, the SOC sets a state value of a first flag bit in a first register to a first numerical value, and sends second instruction information to the second device, so that the second device adjusts a power indicator light of a PCIE slot based on the second instruction information; wherein the second instruction information at least contains an interrupt instruction of a physical connection state.

Description

Technical Field

[0001] This application relates to the fields of cloud computing, big data, and edge computing technologies, and in particular to a method, device, medium, and program product for plugging and unplugging PCIe devices. Background Technology

[0002] The computing power service foundation in cloud computing scenarios typically consists of servers and Data Processing Units (DPUs) with smart network interface cards (NICs). Through an integrated hardware and software computing architecture, the performance of bare metal, virtual machines, and containers can be elevated to a new level. DPU cards provide servers with network and storage processing capabilities. Leveraging the server platform, the DPU offers plug-and-play capabilities for Virtio-net Physical Function (PF) devices and Virtio-blk PF devices (i.e., Peripheral Component Interconnect Express (PCIE) devices). Currently, various application scenarios involving bare metal product instance ordering and cancellation, as well as the binding and unbinding of NICs and disk devices after instance activation, all rely on the underlying capability of PCIE device plug-and-play.

[0003] However, the current main method used for plugging and unplugging PCIe devices is the general notification-based plugging and unplugging mechanism, which is implemented using the standard PCIe device protocol. This mechanism relies on the operating system kernel driver to provide a 5-second delay to prevent accidental operation when plugging and unplugging PCIe devices. This delay can be quite long for some operating systems, resulting in a longer plugging and unplugging time for PCIe devices. Summary of the Invention

[0004] This application provides a method, apparatus, medium, and program product for plugging and unplugging PCIe devices, which can reduce the time spent plugging and unplugging PCIe devices and improve business efficiency.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] In a first aspect, embodiments of this application provide a method for plugging and unplugging a PCIe device, the method being applied to a first device, the first device comprising a System-on-a-Chip (SOC), the method comprising:

[0007] The SOC receives a first instruction message; wherein the first instruction message is used to indicate whether a PCIe device is inserted or removed from the second device;

[0008] When the first instruction indicates that the PCIe device is inserted in the first insertion mode, the SOC sets the status value of the first flag bit in the first register to a first value and sends a second instruction to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction; wherein...

[0009] The first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot.

[0010] Secondly, embodiments of this application provide a System-on-a-Chip (SOC), which includes: a receiving unit, a setting unit, and a transmitting unit; wherein...

[0011] The receiving unit is configured to receive first instruction information; wherein the first instruction information is configured to indicate whether a PCIe device is inserted or removed from a second device; the first device includes the PCIe device;

[0012] The setting unit is configured to set the status value of the first flag bit in the first register to a first value when the first instruction information indicates that the PCIe device is inserted in a first insertion mode;

[0013] The sending unit is configured to send a second instruction message to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction message; wherein...

[0014] The first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot.

[0015] Thirdly, embodiments of this application provide a first device, the first device comprising: a processor and a memory; wherein,

[0016] The memory is used to store computer programs that can run on the processor;

[0017] The processor is configured to perform the method of plugging and unplugging PCIe devices as described above when running the computer program.

[0018] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program code, which, when executed by a computer, implements the method for plugging and unplugging PCIe devices as described above.

[0019] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method for plugging and unplugging PCIe devices as described above.

[0020] This application provides a method, device, medium, and program product for inserting and removing a PCIe device. The method includes: a System-on-Chip (SOC) receiving first instruction information; wherein the first instruction information is used to indicate whether a PCIe device is inserted or removed from a second device; when the first instruction information indicates that the PCIe device is inserted in a first insertion mode, the SOC sets the status value of a first flag bit in a first register to a first value and sends second instruction information to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction information; wherein the first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot. Therefore, when the first instruction information indicates that a PCIe device is inserted in the first insertion method, the SOC can set the status value of the first flag bit in the first register to a first value to indicate that the physical connection status of the PCIe slot in the second device has changed, and send a second instruction information to the second device so that the second device can adjust the power indicator of the PCIe slot based on the second instruction information. The second instruction information includes at least an interrupt instruction for the physical connection status. That is, after the status value of the first flag bit in the first register is set to the first value in this embodiment, a physical connection status interrupt can be triggered to notify the second device that the insertion is complete, thereby ignoring the timeout waiting time of the operating system kernel, reducing the time spent inserting and removing PCIe devices, and thus improving business efficiency. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the method for plugging and unplugging PCIe devices according to an embodiment of this application. Figure 1 ;

[0022] Figure 2 This is a schematic diagram of the method for plugging and unplugging PCIe devices according to an embodiment of this application. Figure 2 ;

[0023] Figure 3 This is a schematic diagram of the architecture of the pluggable PCIe device proposed in the embodiments of this application;

[0024] Figure 4 This is a schematic diagram of the second register structure proposed in an embodiment of this application;

[0025] Figure 5This is a schematic diagram of the third register structure proposed in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the first register structure proposed in an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the hot-plug timing logic proposed in an embodiment of this application;

[0028] Figure 8 This is a schematic diagram of the hot-swappable timing logic proposed in an embodiment of this application;

[0029] Figure 9 This is a schematic diagram of the composition structure of the SOC proposed in the embodiments of this application;

[0030] Figure 10 This is a schematic diagram of the composition structure of the first device proposed in the embodiments of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant application and not for limiting the application. Furthermore, it should be noted that, for ease of description, only the parts related to the relevant application are shown in the accompanying drawings.

[0032] The computing power service platform in cloud computing scenarios typically consists of servers and DPU (Digital Processing Unit) smart network interface cards (NICs). Through an integrated hardware and software computing architecture, the performance of bare-metal products, virtual machines, and containers can be elevated to a new level. A DPU is a dedicated processor focused on accelerating network, storage, and security services. DPU cards provide servers with network and storage processing capabilities. Bare-metal products provide all physical computing resources to the user. DPUs, leveraging the server platform, offer pluggable / pluggable Virtio-net PF (Virtio-blk PF) devices.

[0033] For various scenarios involving elastic bare metal products, such as instance ordering and cancellation, as well as the binding and unbinding of network cards and disk devices after instance activation, the underlying capability of PCIe device plug-and-play is crucial. Therefore, it's essential to provide users with stability and the ability to quickly activate instance device resources across these scenarios. While current mainstream solutions support hot-swapping PCIe devices, they typically don't explicitly state support for cold-swapping. Since the host system of an elastic bare metal product is delivered to the customer, and there are system startup processes such as host shutdown or power on / off, as well as customer operations like binding and unbinding network cards and disk devices, ensuring stability and performance across these diverse scenarios is paramount.

[0034] However, the current mainstream notification-based plug-in / plug-out mechanism is implemented using the standard PCIe device protocol, which has a 5-second delay to prevent accidental operation when plugging in / out PCIe devices, depending on the operating system kernel driver. This delay can be significant for some operating systems, resulting in longer plugging / plugging times for PCIe devices. Furthermore, it is not compatible with cold plugging / plugging negotiations in business scenarios, as this mechanism only supports hot plugging / plugging.

[0035] To address the issue of long insertion / removal times for PCIe devices in current notification-based insertion / removal mechanisms, this application provides a method, device, medium, and program product for inserting / removing PCIe devices. The method includes: a System-on-Chip (SOC) receiving first instruction information; wherein the first instruction information indicates whether a PCIe device is inserted or removed from a second device; if the first instruction information indicates that a PCIe device is inserted in a first insertion mode, the SOC sets the status value of a first flag bit in a first register to a first value and sends second instruction information to the second device, causing the second device to adjust the power indicator light of the PCIe slot based on the second instruction information; wherein the first flag bit is at least used to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is at least used to characterize the physical state of the PCIe slot. Therefore, when the first instruction information indicates that a PCIe device is inserted in the first insertion method, the SOC can set the status value of the first flag bit in the first register to a first value to indicate that the physical connection status of the PCIe slot in the second device has changed, and send a second instruction information to the second device so that the second device can adjust the power indicator of the PCIe slot based on the second instruction information. The second instruction information includes at least an interrupt instruction for the physical connection status. That is, after the status value of the first flag bit in the first register is set to the first value in this embodiment, a physical connection status interrupt can be triggered to notify the second device that the insertion is complete, thereby ignoring the timeout waiting time of the operating system kernel, reducing the time spent inserting and removing PCIe devices, and thus improving business efficiency.

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0037] This application provides a method for plugging and unplugging a PCIe device. The method is applied to a first device, which includes a System-on-a-Chip (SoC). Figure 1 This is a schematic diagram of the method for plugging and unplugging PCIe devices according to an embodiment of this application. Figure 1 ,like Figure 1 As shown, the method for plugging and unplugging a PCIe device may include the following steps:

[0038] Step 101: The SOC receives the first instruction information; wherein the first instruction information is used to indicate whether the PCIe device is inserted or removed on the second device.

[0039] In the embodiments of this application, the SOC can receive first instruction information.

[0040] It should be noted that in the embodiments of this application, the first device may be a DPU device, and this application does not specifically limit the type of the first device.

[0041] It should be noted that, in the embodiments of this application, the first device may include a SOC, and this application does not specifically limit the number and type of modules included in the first device.

[0042] It should be noted that in the embodiments of this application, the second device may be a server device, and this application does not specifically limit the type of the second device.

[0043] It should be noted that, in the embodiments of this application, the first instruction information can be used to indicate whether a PCIe device is inserted or removed on the second device. The PCIe device may include the PF device in the DPU, such as a network card, storage controller, etc. This application does not specifically limit the type of PCIe device.

[0044] It should be noted that, in the embodiments of this application, the method of inserting a PCIe device may include a first insertion method and a second insertion method; wherein, the first insertion method may include a hot-plug method, and the second insertion method may include a cold-plug method, and this application does not specifically limit the type of the first insertion method.

[0045] It should be noted that, in the embodiments of this application, the method of unplugging the PCIe device may include a first unplugging method and a second unplugging method; wherein, the first unplugging method may include a hot-plugging method, and the second unplugging method may include a cold-plugging method, and this application does not specifically limit the type of the first unplugging method.

[0046] Step 102: When the first instruction information indicates that the PCIe device is inserted in the first insertion mode, the SOC sets the status value of the first flag bit in the first register to the first value and sends the second instruction information to the second device, so that the second device will adjust the power indicator of the PCIe slot based on the second instruction information; wherein, the first flag bit is used at least to indicate whether the physical connection status of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction of the physical connection status, and the first register is used at least to characterize the physical status of the PCIe slot.

[0047] In the embodiments of this application, after receiving the first instruction information, the SOC may, if the first instruction information indicates that a PCIe device is inserted in a first insertion mode, set the status value of the first flag bit in the first register to a first value and send the second instruction information to the second device.

[0048] It should be noted that, in the embodiments of this application, the first register can at least be used to characterize the physical state of the PCIe slot. The first register can be a Slot Status Register. This application does not specifically limit the type of the first register.

[0049] It should be noted that, in the embodiments of this application, the second instruction information may include physical connection status interruption instructions, and may also include link status interruption instructions. This application does not specifically limit the type and number of instructions included in the second instruction information.

[0050] It should be noted that, in the embodiments of this application, the first flag may include Data Link Layer State Changed, PresenceDetect State, and Presence Detect Changed in Slot StatusRegister. This application does not specifically limit the type of the first flag.

[0051] It should be noted that, in the embodiments of this application, the Data LinkLayer State Changed in the Slot Status Register can be used to indicate changes in the data link layer state, mainly for detecting hot-plug events or abnormal link states.

[0052] It should be noted that, in the embodiments of this application, the PresenceDetect State in the Slot Status Register can be used to detect whether a PCIe device is inserted or removed.

[0053] It should be noted that, in the embodiments of this application, PresenceDetect Changed in the Slot Status Register can be used to indicate whether the physical connection status of the PCIe slot has changed.

[0054] It should be noted that in the embodiments of this application, the first value can be 1, and this application does not make specific limitations on the setting of the first value.

[0055] For example, in an embodiment of this application, when the first instruction information indicates that a PCIe device is inserted in a hot-plug manner, the SOC can set the Data Link Layer StateChanged, Presence Detect State, and Presence Detect Changed flags in the Slot Status Register to 1; wherein, setting the Data Link Layer State Changed flag to 1 can be used to trigger a link state interruption, setting the Presence Detect State flag to 1 can confirm the insertion of the PCIe device, and setting the Presence Detect Changed flag to 1 can confirm that the physical connection state of the PCIe slot has changed, thereby triggering a Presence Detect Changed interrupt (i.e., a physical connection state interruption), and sending a second instruction information to the second device, so that after the second device receives the Presence Detect Changed interrupt, it can adjust the power indicator light of the PCIe slot.

[0056] Optionally, in the embodiments of this application, after the second device receives the Presence Detect Changed interrupt, the system driver in the second device can execute the interrupt handling function to enable the corresponding slot, which may include the slot in the PCIE Switch in the DPU, and load the device driver. After the driver initialization is completed, the Power Indicator Control flag in the Slot Control Register (i.e., the third register) will be set to a valid value, such as 01b (binary value 01), indicating that the power indicator is in the On state and the corresponding PCIE device has been successfully inserted, thereby completing the adjustment of the power indicator of the PCIE slot.

[0057] Optionally, in an embodiment of this application, after the second device adjusts the power indicator of the PCIe slot, the SOC can parse the Power IndicatorControl flag in the Slot Control Register (i.e., the third register). If the flag is 01b, it indicates that the hot-plugging of the PCIe device has been completed.

[0058] In other words, in the embodiments of this application, when the first instruction information indicates that the PCIe device is inserted in a hot-plug manner, the SOC can set the Data Link Layer StateChanged, Presence Detect State, and Presence Detect Changed flags in the Slot Status Register to 1; to trigger a link state interrupt (i.e., link interrupt) and a physical connection state interrupt (i.e., presence interrupt), notifying the second device that the hot-plugging is complete, so that the second device can adjust the power indicator light of the PCIe slot after receiving the interrupt; that is, in the embodiments of this application, the second device can be notified that the hot-plugging is complete by triggering a link interrupt and a presence interrupt. This fast plugging and unplugging method can ignore the timeout wait of the operating system kernel, thereby reducing the time spent plugging and unplugging PCIe devices and improving business efficiency.

[0059] It should be noted that, in the embodiments of this application, Figure 2 This is a schematic diagram of the method for plugging and unplugging PCIe devices according to an embodiment of this application. Figure 2 ,like Figure 2 As shown, before the SOC sets the status value of the first flag bit in the first register to the first value, i.e. before step 102, the following steps may also be included:

[0060] Step 103: The SOC sets the status value of the second flag bit in the second register to the second value, and determines whether the current value of the third flag bit in the third register is the first target value; wherein, the second register is used at least to monitor the current status of the PCIe link, the second flag bit is used to indicate whether the current data link layer of the PCIe link is active, the third register is used at least to control the power status of the PCIe slot, and the third flag bit is used to control the hot-plug interrupt function of the PCIe slot.

[0061] In other words, in the embodiments of this application, when the first instruction information indicates that the PCIe device is inserted in the first insertion mode, the SOC can first set the status value of the second flag bit in the second register to the second value, and determine whether the current value of the third flag bit in the third register is the first target value.

[0062] It should be noted that, in the embodiments of this application, the second register is used at least to monitor the current status of the PCIe link. The second register may include a Link Status Register. This application does not specifically limit the type of the second register.

[0063] It should be noted that, in the embodiments of this application, the second flag bit can be used to characterize whether the current data link layer of the PCIE link is active. The second flag bit can be the Data LinkLayer Link Active flag bit of the Link Status Register.

[0064] It should be noted that, in the embodiments of this application, the third register is used at least to control the power state of the PCIe slot. The third register may include a Slot Control Register. This application does not specifically limit the type of the third register.

[0065] It should be noted that, in the embodiments of this application, the third flag bit can be used to control the hot-plug interrupt function of the PCIe slot. The third flag bit can be hot-plug Interrupt Enable in the Slot Control Register.

[0066] For example, in an embodiment of this application, the SOC can set the Data LinkLayer Link Active in the Link Status Register to 1 (i.e., the second value) to activate the data link layer; and determine whether the current value of hot-plug Interrupt Enable in the Slot Control Register is 1 (i.e., the first target value). If the current value of hot-plug Interrupt Enable is 1, it means that the interruption notification function is enabled, which can enable the host (i.e., the second device) to sense the change in device status.

[0067] Step 104: If the current value of the third flag bit is the first target value, the SOC sets the fourth flag bit in the first register to the second target value; wherein, the fourth flag bit is used to indicate the device presence status of the PCIe slot, and the second target value indicates that the device in the PCIe slot is in place.

[0068] It should be noted that, in the embodiments of this application, if the current value of the third flag bit is not the first target value, the SOC prohibits setting the fourth flag bit in the first register to the second target value.

[0069] It should be noted that, in the embodiments of this application, the fourth flag bit can be the Presence Detect State (i.e., the presence detection state) in the Slot Status Register.

[0070] For example, in an embodiment of this application, when the current value of hot-plugInterrupt Enable in the Slot Control Register is 1, the SOC can set the Presence Detect State in the Slot Status Register to 1, indicating that the device in the PCIe slot is in place.

[0071] In other words, in the embodiments of this application, after the SOC receives the first instruction information, if the first instruction information indicates that a PCIe device is inserted in a hot-plug manner, the SOC can first set the Data LinkLayer Link Active in the Link Status Register to 1 (i.e., the second value) to activate the data link layer; and determine whether the current value of hot-plug Interrupt Enable in the Slot Control Register is 1 (i.e., the first target value). If the current value of hot-plug Interrupt Enable is 1, it indicates that the interrupt notification function is enabled, which can enable the host (i.e., the second device) to sense the device status change; if the current value of hot-plug Interrupt Enable in the Slot Control Register is 1, the SOC can set the Presence Detect State in the Slot Status Register to 1, indicating that the device in the PCIe slot is in place; and then set the Data Link Layer State Changed, Presence Detect State, and Presence Detect Changed flags in the Slot Status Register to 1; wherein, setting the Data Link Layer State Changed flag to 1 can be used to trigger a link status interruption, setting the Presence Detect State flag to 1 can confirm the insertion of the PCIe device, and setting the Presence Detect State flag to 1 can be used to trigger a link status interruption. Setting the DetectChanged flag to 1 confirms a change in the physical connection status of the PCIe slot, triggering a PresenceDetect Changed interrupt (i.e., a physical connection status interruption). This sends a second instruction to the second device, enabling the second device to adjust the power indicator light of the PCIe slot upon receiving the Presence Detect Changed interrupt.

[0072] Optionally, in embodiments of this application, when the first instruction information indicates that a PCIe device is inserted in the second insertion mode and the second device is not powered on, the SOC can set the status value of the second flag bit of the second register to the second value.

[0073] For example, in an embodiment of this application, when the first instruction information indicates that the PCIe device is inserted in a cold-plug manner and the second device is not powered on, the SOC can set the Data Link Layer LinkActive flag of the Link Status Register to 1. After the second device is powered on and the slot status is detected, the resources are automatically initialized to complete the cold-plug PCIe device process.

[0074] In other words, this application embodiment not only enables a fast hot-swap PCIe device mechanism, but also adds a cold-swap PCIe device business scenario, solving the problem that users cannot plug or unplug devices when the host (i.e., the second device) system is powered off, and the underlying system does not support cold-swap, thus greatly improving the user experience.

[0075] It should be noted that, in the embodiments of this application, when the first instruction information indicates that the PCIe device is removed in the first removal method, the SOC can set the status value of the second flag bit in the second register to a third value, and determine whether the current value of the third flag bit in the third register is the first target value; if the current value of the third flag bit is the first target value, the SOC sets the fourth flag bit in the first register to the third target value; wherein, the third target value indicates that the device in the PCIe slot is not in place; then the SOC can set the status value of the first flag bit in the first register to the first value, and send a third instruction information to the second device, so that the second device will adjust the power indicator light of the PCIe slot based on the third instruction information; wherein, the third instruction information is used to indicate that the status of the PCIe device is successfully removed.

[0076] It should be noted that, in the embodiments of this application, if the current value of the third flag bit is not the first target value, the SOC prohibits setting the fourth flag bit in the first register to the third target value.

[0077] It should be noted that in the embodiments of this application, the third value can be 0, and this application does not make specific limitations on the setting of the third value.

[0078] It should be noted that in the embodiments of this application, the third target value can be 0, and this application does not specifically limit the setting of the third target value.

[0079] For example, in an embodiment of this application, when the first instruction information indicates that the PCIe device is removed by hot-plugging, the SOC can set the Data Link Layer Link Active in the Link Status Register to 0 (i.e., the third value), indicating that the data link layer of the PCIe link is inactive; and determine whether the current value of hot-plug Interrupt Enable in the Slot Control Register is 1 (i.e., the first target value). If the current value of hot-plug Interrupt Enable is 1, it indicates that the interrupt notification function is enabled, which allows the host (i.e., the second device) to sense the change in device status; if the current value of hot-plug Interrupt Enable in the Slot Control Register is 1, the SOC can set the Presence Detect State in the Slot Status Register to 0 (i.e., the third target value), indicating that the device in the PCIe slot is not in place; then, the SOC can set the Data Link Layer State Changed, Presence Detect State, and Presence Detect Changed flags in the Slot Status Register to 1 to trigger a Presence Detect Changed interrupt (i.e., a physical connection state interruption), and send the third instruction information to the second device so that the second device receives the Presence Detect... After the Changed interruption, the power indicator light of the PCIe slot is adjusted.

[0080] Optionally, in the embodiments of this application, after the second device receives the third instruction information, the system driver in the second device can execute an interrupt handling function to enable the corresponding slot, which may include the slot in the PCIE switch in the DPU, and load the device driver. After the driver initialization is completed, the Power Indicator Control flag in the SlotControl Register (i.e., the third register) will be set to a valid value, such as 10b (binary value 10), indicating that the power indicator is in the off state and the corresponding PCIE device has been successfully removed, thereby completing the adjustment of the power indicator of the PCIE slot.

[0081] Optionally, in an embodiment of this application, after the second device adjusts the power indicator light of the PCIe slot, the SOC can parse the Power IndicatorControl flag bit of the Slot Control Register (i.e., the third register). If the flag bit is 10b, it indicates that the hot-plugging of the PCIe device has been completed.

[0082] It should be noted that, in the embodiments of this application, when the first instruction information indicates that the PCIe device is unplugged in the second unplugging method and the second device is not powered on, the SOC sets the status value of the second flag bit of the second register to the third value.

[0083] For example, in an embodiment of this application, when the first instruction information indicates that the PCIe device is removed by cold-swapping and the second device is not powered on, the SOC can set the Data Link Layer LinkActive flag of the Link Status Register to 0. After the second device is powered on and the slot status is detected, the resources are automatically initialized to complete the cold-swapping process of the PCIe device.

[0084] Optionally, in the embodiments of this application, the SOC can monitor the in-situ status of the PCIe device in real time through the second register; in the event of an abnormality in the PCIe device, the in-situ status of the PCIe device can be restored through a preset recovery strategy, thereby ensuring that in abnormal scenarios where the insertion or removal of the PCIe device fails, the PCIe device can be detected in time and a rollback operation can be performed, thereby avoiding the residual and device abnormalities caused by the failure to release resources during insertion or removal, and also ensuring the correctness and continuity of the overall hot and cold plugging / removing process.

[0085] For example, in the embodiments of this application, the preset recovery strategy may include one or more of the following: SOC restart, repeated plugging and unplugging operations, and second device shutdown and restart. This application does not specifically limit the type of strategy included in the preset recovery strategy.

[0086] In summary, when the first instruction indicates that a PCIe device is inserted via hot-plugging, the SOC can update the Data Link Layer State Changed, Presence DetectState, and Presence Detect in the Slot Status Register. The Changed flag is set to 1; a link state interrupt (i.e., link interrupt) and a physical connection state interrupt (i.e., presence interrupt) are triggered to notify the second device that hot-plugging is complete, so that the second device can adjust the power indicator light of the PCIe slot after receiving the interrupt. That is, in this embodiment, the second device can be notified that hot-plugging is complete by triggering link interrupt and presence interrupt. This fast plugging and unplugging method can ignore the timeout wait of the operating system kernel and is more friendly to cold plugging and unplugging operations, thereby reducing the time spent plugging and unplugging PCIe devices and improving business efficiency. In addition, this embodiment also adds the business scenario of cold plugging and unplugging PCIe devices, which solves the problem that users cannot plug and unplug devices when the host (i.e., the second device) system is powered off and the underlying layer does not support cold plugging and unplugging, which greatly improves the user experience. In the case of PCIe device abnormality, the in-situ state of the PCIe device can be restored by a preset recovery strategy, so as to ensure that in the abnormal scenario of PCIe device plugging and unplugging failure, the PCIe device can be detected in time and the PCIe device can be rolled back in time, thereby avoiding the resource release failure of plugging and unplugging causing residue and device abnormality, while also ensuring the correctness and continuity of the overall hot and cold plugging process.

[0087] This application provides a method for inserting and removing a PCIe device. The method includes: a System-on-Chip (SOC) receiving first instruction information; wherein the first instruction information is used to indicate whether a PCIe device is inserted or removed from a second device; when the first instruction information indicates that the PCIe device is inserted in a first insertion mode, the SOC sets the status value of a first flag bit in a first register to a first value and sends second instruction information to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction information; wherein the first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot. Therefore, when the first instruction information indicates that a PCIe device is inserted in the first insertion method, the SOC can set the status value of the first flag bit in the first register to a first value to indicate that the physical connection status of the PCIe slot in the second device has changed, and send a second instruction information to the second device so that the second device can adjust the power indicator of the PCIe slot based on the second instruction information. The second instruction information includes at least an interrupt instruction for the physical connection status. That is, after the status value of the first flag bit in the first register is set to the first value in this embodiment, a physical connection status interrupt can be triggered to notify the second device that the insertion is complete, thereby ignoring the timeout waiting time of the operating system kernel, reducing the time spent inserting and removing PCIe devices, and thus improving business efficiency.

[0088] Based on the above embodiments, another embodiment of this application provides a method for plugging and unplugging PCIe devices. This method can utilize the PCIe Switch function module of the DPU and the characteristics of the PCIe standard protocol to improve the notification-based hot-plugging PCIe device mechanism into a fast cold-hot-plugging PCIe device mechanism. This can reduce the time it takes for users to activate device resources and increase the business scenarios for cold plugging and unplugging. At the same time, it adds a monitoring mechanism for self-detection of device resource status characteristics and an adaptive device recovery strategy (i.e., a preset recovery strategy) to solve the instability problem caused by various abnormal scenarios leading to the failure of underlying cold-hot plugging and unplugging devices.

[0089] It should be noted that, in the embodiments of this application, Figure 3 This is a schematic diagram of the architecture of the pluggable PCIe device proposed in the embodiments of this application, such as... Figure 3As shown, the DPU can connect to the host (i.e., the second device) through a PCIe slot. This means the DPU can leverage the host's platform to provide hot-swap capabilities for Virtio-net and Virtio-blk PF devices. Within the DPU's PCIE switch, slots 0, 1, ..., 0n can accommodate multiple PF devices (such as network interface cards (NICs) and storage controllers). The driver in the second device (i.e., the PCIe driver) can mount different PF devices to the corresponding NET and BLK locations in the host. The NET can contain mounted NICs, and the BLK can contain mounted storage controllers. Furthermore, the DPU stores multiple registers, such as a first register, a second register, and a third register. The SOC in the DPU can access these registers through slot capabilities and implement the three mechanisms described in point 3 through the software layer (i.e., the application program (app)). These three mechanisms include a fast device plug-in / plug-out mechanism, a device status monitoring mechanism, and an adaptive device recovery mechanism.

[0090] It should be noted that in the embodiments of this application, the DPU, leveraging the server platform, can provide hot-plugging capabilities for Virtio-net PF and Virtio-blk PF devices. This capability is a general notification-based hot-plugging mechanism implemented based on the PCIe protocol. Notification-based hot-plugging negotiation heavily relies on a 5-second timeout from the operating system kernel. Combined with the time consumed by other negotiation enable bits and the limitation that the DPU only supports serial plugging, the native single-device plugging and unplugging process takes at least 5 seconds. The embodiments of this application can adjust the general notification-based plugging and unplugging mechanism into a fast cold-hot plugging and unplugging mechanism. Fast plugging and unplugging can ignore the operating system kernel timeout and is more friendly to cold-plugging operations. The time consumption of this fast single-device plugging and unplugging logic is typically within milliseconds (ms). The maximum timeout is set to 2 seconds based on experience, and the maximum timeout can be adjusted according to the characteristics of the DPU, the server (i.e., the second device), and the operating system.

[0091] It should be noted that in the embodiments of this application, the original notification interrupt is replaced by a presence detectchange interrupt. The fast process does not notify the driver to stop input / output (IO). If there is any incomplete IO processing, it will be handled by the Downstream Port Containment (DPC) feature in PCIe. The PCIe device protocol registers involved in fast plugging and unplugging include: Link Status Register (i.e., the second register), Slot Control Register (i.e., the third register), and Slot Status Register (i.e., the first register).

[0092] For example, in the embodiments of this application, Figure 4 This is a schematic diagram of the second register structure proposed in an embodiment of this application, as shown below. Figure 4 As shown, the Link Status Register may include one or more of the following flags: LinkAutonomous Bandwidth Status, Link Bandwidth Management Status, Data Link Layer Link Active, Slot Clock Configuration, Link Training, Undefined (reserved), Negotiated Link Width, and Current LinkSpeed; among which, Figure 4 The numbers marked in the text can represent the bit positions of each flag bit.

[0093] For example, in the embodiments of this application, Figure 5 This is a schematic diagram of the third register structure proposed in the embodiments of this application, as shown below. Figure 5As shown, the Slot Control Register may include one or more of the following flags: Attention Button Pressed Enable, Power Fault Detected Enable, MRL Sensor Changed Enable, Presence Detect Changed Enable, Command Completed Interrupt Enable, Hot-Plug Interrupt Enable, Attention Indicator Control, Power Indicator Control, Power Controller Control, Electromechanical Interlock Control, Data Link Layer StateChanged Enable, Auto Slot Power Limit Disable, and RsvdP (Power Management Reserved Bit). Figure 5 The numbers marked in the text can represent the bit positions of each flag bit.

[0094] For example, in the embodiments of this application, Figure 6 This is a schematic diagram of the first register structure proposed in an embodiment of this application, as shown below. Figure 6As shown, the Slot Status Register may include one or more of the following flags: DataLink Layer State Changed, Electromechanical Interlock Status, Presence Detect State, MRL Sensor State, Command Completed, Presence Detect Changed, MRL Sensor Changed, Power Fault Detected, and Attention Button Pressed. Figure 6 The numbers marked in the text can represent the bit positions of each flag bit.

[0095] It should be noted that, in the embodiments of this application, the process of hot-plugging a PCIe device may include the following steps: 1. When a device needs to be hot-plugged, the software layer (i.e., SOC) can set the Data Link Layer Link Active (i.e., the second flag bit) position in the Link Status Register (i.e., the second register) to 1 (DL_Down becomes DL_Active). This setting indicates that the data link layer is already in the DL_Active state; 2. After the host (i.e., the second device) senses the device status and powers on, the PCIe driver will set the hot-plug Interrupt Enable (i.e., the third flag bit) position in the Slot Control Register (i.e., the third register) to 1. The software layer (i.e., SOC) judges the change of this bit. The change of this bit indicates that the hot-plugged device needs to notify the host driver. After the software layer modifies the data link status bit, it needs to notify the host. At this time, the software layer needs to set the Presence Detect State (i.e., the first flag bit) in the Slot Status Register (i.e., the first register) to 1, indicating that there is a device in the slot. Then the software layer sets the Data Link Layer State in the SlotStatus Register (i.e., the first register) to 1. The Changed bit, PresenceDetect State, and Presence Detect Changed bit are set to 1 to trigger link interrupt and presence interrupt (i.e., the second instruction information) to notify the host that the device insertion is complete; 3. After the host (i.e. the second device) receives the interrupt, the system driver detects the interrupt and executes the interrupt handling function, enables the corresponding slot, and loads the device driver. After the driver initialization is completed, it will set the Power Indicator Control bit in the Slot Control Register (i.e., the third register) to a valid value. The software layer (i.e., SOC) parses the bit information to determine whether hot-plug has been completed.

[0096] In other words, in the embodiments of this application, when the first instruction information indicates that the PCIe device is inserted in a hot-plug manner, the SOC can set the Data Link Layer StateChanged, Presence Detect State, and Presence Detect Changed flags in the Slot Status Register to 1; to trigger a link state interrupt (i.e., link interrupt) and a physical connection state interrupt (i.e., presence interrupt), notifying the second device that the hot-plugging is complete, so that the second device can adjust the power indicator light of the PCIe slot after receiving the interrupt; that is, in the embodiments of this application, the second device can be notified that the hot-plugging is complete by triggering a link interrupt and a presence interrupt. This fast plugging and unplugging method can ignore the timeout wait of the operating system kernel and is more friendly to cold plugging and unplugging operations, thereby reducing the time spent plugging and unplugging PCIe devices and improving business efficiency.

[0097] For example, in the embodiments of this application, Figure 7 This is a schematic diagram of the hot-plug timing logic proposed in the embodiments of this application, such as... Figure 7As shown, HW can be used to represent DPU, and the second device can include the operating system (OS) and the basic input / output system (BIOS). The hot-plug timing logic flow can include the following steps: 1. The operating system initializes the slot; 2. The SOC pulls high the data link layer link active in the Link Status register (i.e., the link status register) to initiate a Data link layer status change interrupt (i.e., the data link layer status change interrupt); 3. After receiving the Data link layer status change interrupt, the DPU transmits the Data link layer status change interrupt to the OS / BIOS; 4. The SOC initiates a Presence detect change interrupt to the DPU (i.e., the physical connection status interrupt); 5. The DPU sends the Presence detect change interrupt to the OS / BIOS; 6. The OS / BIOS reads the normal operating status of the data link layer (i.e., Host read data link layer active); 7. The OS / BIOS loads the device driver, and after the driver initialization is complete, it will set the Power Indicator in the Slot Control Register (i.e., the third register) to... The Control (i.e., power indicator control) flag is set to a valid value, such as 01b (binary value 01), which indicates that the power indicator is on and the corresponding PCIe device has been successfully inserted; 8. The SOC reads the Power Indicator Control flag information from the Slot Control Register. If the flag is 01b, it means that the hot-plugging of the PCIe device has been completed.

[0098] It should be noted that, in the embodiments of this application, the process of cold-plugging a PCIe device may include the following: If the host (i.e., the second device) is not powered on, the software layer (i.e., the SOC) will only execute the hot-plugging step 1. When a cold-plugging device is required, the software layer (i.e., the SOC) can set the Data LinkLayer Link Active (i.e., the second flag bit) position in the Link Status Register (i.e., the second register) to 1 (DL_Down becomes DL_Active). This setting indicates that the data link layer is already in the DL_Active state. After the host is powered on, it detects the DL_Active state, automatically initializes resources, and the cold-plugging process will definitely succeed.

[0099] It should be noted that, in the embodiments of this application, the process of hot unplugging a PCIe device (3) may include the following steps: 1. When a device needs to be hot-plugged, the software layer (i.e., SOC) sets the Data Link Layer Link Active bit in the Link Status Register to 0 (DL_Active becomes DL_Down). This setting indicates that the data link layer is already in the DL_Down state; 2. After the host (i.e., the second device) senses the device power-on status, the PCIe driver sets the hot-plug Interrupt Enable bit in the Slot Control Register to 1. The software layer judges the change of this bit. The change of this bit indicates that the hot-plugged device needs to notify the host driver. After the software layer modifies the data link status bit, it needs to notify the host. At this point, the software layer needs to set the Presence Detect State in the Slot Status Register to 0, indicating that there is no device in the slot. Then, the software layer sets the Data Link LayerState Changed flag, Presence Detect State flag, and Presence Detect Changed flag in the Slot Status Register to 1 to trigger a link interrupt and a presence interrupt (i.e., the third instruction information) to notify the host that the device removal is complete. 3. After the host (i.e., the second device) receives the interrupt, the system driver detects the interrupt, executes the interrupt handling function, enables the corresponding slot, and loads the device driver. After the driver initialization is complete, it will set the Power Indicator Control bit in the Slot Control Register to a valid value. The software layer (i.e., SOC) parses this bit setting information to determine whether hot-unplug has been completed.

[0100] For example, in an embodiment of this application, after the second device receives the third instruction information, the system driver in the second device can execute an interrupt handling function to enable the corresponding slot, which may include the slot in the PCIE switch in the DPU, and load the device driver. After the driver initialization is completed, the Power Indicator Control flag in the SlotControl Register (i.e., the third register) will be set to a valid value, such as 10b (binary value 10), indicating that the power indicator is in the off state and the corresponding PCIE device has been successfully removed, thereby completing the adjustment of the power indicator of the PCIE slot.

[0101] For example, in an embodiment of this application, after the second device adjusts the power indicator of the PCIe slot, the SOC can parse the Power IndicatorControl flag in the Slot Control Register (i.e., the third register). If the flag is 10b, it indicates that the hot-plugging of the PCIe device has been completed.

[0102] For example, in the embodiments of this application, Figure 8 This is a schematic diagram of the hot-swappable timing logic proposed in an embodiment of this application, such as... Figure 8As shown, the hot unplug timing logic flow can include the following steps: 1. The operating system initializes the slot; 2. The SOC initiates a Presence Detect Change interrupt (i.e., a physical connection status interrupt); 3. The DPU transmits this Presence Detect Change interrupt to the OS / BIOS; 4. The OS / BIOS reads the normal operating status of the data link layer (Host read data link layer active); 5. The OS / BIOS loads the device driver. After the driver initialization is complete, it sets the Power Indicator Control flag in the Slot Control Register (i.e., the third register) to a valid value, such as 10b (binary value 10), indicating that the power indicator is in the off state and the corresponding PCIe device has been successfully unplugged; 6. The SOC reads the Power Indicator Control flag information in the Slot Control Register. If the flag is 10b, it indicates that the hot unplugging of the PCIe device has been completed; 7. The SOC checks whether the device driver in the slot is responding; 8. If it is responding, the DPU sends a Data Link Layer Status Change interrupt to the OS / BIOS; 9. OS / 10. The BIOS checks whether the device driver in the slot is responding and sends the response result to the DPU; 11. The DPU sends the response result to the SOC. If there is no response, the unplugging is not performed; 12. The data link layer link active of the Link Status reg (i.e., the link status register) is pulled low to initiate a Data link layer status change interrupt (i.e., the data link layer status change interrupt).

[0103] It should be noted that, in the embodiments of this application, the process of cold-plugging a PCIe device may include the following: If the host (i.e., the second device) is not powered on, the software layer will only execute the hot-plugging step 1. The software layer (i.e., SOC) sets the Data Link Layer Link Active bit of the Link Status Register to 0 (DL_Active becomes DL_Down). This setting indicates that the data link layer is already in the DL_Down state, and the cold-plugging process will definitely succeed.

[0104] It should be noted that, in the embodiments of this application, the above-described cold and hot plugging device mechanism implementation method inevitably suffers from repeated plugging and unplugging issues and inconsistencies between the device plugging / unplugging status and the service layer. This application embodiment adds a device status monitoring device, which records the service layer status through software and uses the device link status register to obtain the device's on-site status for real-time monitoring, enabling rapid fault detection and handling. This monitoring device is a necessary condition to ensure subsequent adaptive recovery from anomalies.

[0105] It should be noted that, in the embodiments of this application, based on the above mechanism of guaranteed success of cold plugging and unplugging and the device status monitoring device, the adaptive device recovery strategy (i.e. the preset recovery strategy) can recover the following abnormal scenarios: (1) DPU SOC restart: When the SOC restarts, the device status information on the DPU will be lost. Using the device status monitoring device, based on the recorded business layer status, the device behavior on the SOC is automatically recovered.

[0106] (2) Host not responding: During hot-plug or hot-swapping negotiation, high-concurrency business processing may occupy system driver kernel resources on the host side. At this time, the host cannot respond to the hot-plug or hot-swapping process. The process of repeatedly inserting or removing the host is used to solve the occasional abnormality of the system driver not responding. If there is no response, it can be determined that the host system or driver is abnormal. After the host driver recovers from the abnormality or the host is shut down and restarted, the software layer will adaptively restore the underlying device state.

[0107] It should be noted that, in the embodiments of this application, a fast plug-in / plug-out mechanism is first designed. Based on the DPU's general PCIe switch module capabilities, the mechanism is derived and adapted using the PCIe standard protocol combined with the DPU's capabilities. This mechanism optimizes the kernel timeout waiting time for hot-plugging PCIe devices and also supports the ability to cold-plug PCIe devices, fundamentally shortening the time consumption of instance ordering and device binding / unbinding scenarios, and solving the capability limitations of scenarios where users cannot bind / unbind devices when the host is shut down. Secondly, the embodiments of this application design a device status monitoring device. Based on the basic capabilities of the fast plug-in / plug-out mechanism, it can ensure that in abnormal scenarios where plugging / plugging PCIe devices fails, the device status monitoring device can detect it in a timely manner and perform a rollback operation on the PCIe device, thereby avoiding resource release failures during plugging / plugging that cause residue and device abnormalities, while also ensuring the correctness and consistency of the overall hot-plugging / cold-plugging process. The embodiments of this application also design an adaptive device recovery strategy (i.e., a preset recovery strategy) to avoid abnormalities such as repeated plugging / plugging or plugging in devices without unplugging them. By utilizing the diagnostic adaptive recovery guarantee mechanism, it can ensure that the device status remains consistent with the characteristics of business requirements.

[0108] In summary, when the first instruction indicates that a PCIe device is inserted via hot-plugging, the SOC can update the Data Link Layer State Changed, Presence DetectState, and Presence Detect in the Slot Status Register. The Changed flag is set to 1; a link state interrupt (i.e., link interrupt) and a physical connection state interrupt (i.e., presence interrupt) are triggered to notify the second device that hot-plugging is complete, so that the second device can adjust the power indicator light of the PCIe slot after receiving the interrupt. That is, in this embodiment, the second device can be notified that hot-plugging is complete by triggering link interrupt and presence interrupt. This fast plugging and unplugging method can ignore the timeout wait of the operating system kernel and is more friendly to cold plugging and unplugging operations, thereby reducing the time spent plugging and unplugging PCIe devices and improving business efficiency. In addition, this embodiment also adds the business scenario of cold plugging and unplugging PCIe devices, which solves the problem that users cannot plug and unplug devices when the host (i.e., the second device) system is powered off and the underlying layer does not support cold plugging and unplugging, which greatly improves the user experience. In the case of PCIe device abnormality, the in-situ state of the PCIe device can be restored by a preset recovery strategy, so as to ensure that in the abnormal scenario of PCIe device plugging and unplugging failure, the PCIe device can be detected in time and the PCIe device can be rolled back in time, thereby avoiding the resource release failure of plugging and unplugging causing residue and device abnormality, while also ensuring the correctness and continuity of the overall hot and cold plugging process.

[0109] This application provides a method for inserting and removing a PCIe device. The method includes: a System-on-Chip (SOC) receiving first instruction information; wherein the first instruction information is used to indicate whether a PCIe device is inserted or removed from a second device; when the first instruction information indicates that the PCIe device is inserted in a first insertion mode, the SOC sets the status value of a first flag bit in a first register to a first value and sends second instruction information to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction information; wherein the first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot. Therefore, when the first instruction information indicates that a PCIe device is inserted in the first insertion method, the SOC can set the status value of the first flag bit in the first register to a first value to indicate that the physical connection status of the PCIe slot in the second device has changed, and send a second instruction information to the second device so that the second device can adjust the power indicator of the PCIe slot based on the second instruction information. The second instruction information includes at least an interrupt instruction for the physical connection status. That is, after the status value of the first flag bit in the first register is set to the first value in this embodiment, a physical connection status interrupt can be triggered to notify the second device that the insertion is complete, thereby ignoring the timeout waiting time of the operating system kernel, reducing the time spent inserting and removing PCIe devices, and thus improving business efficiency.

[0110] Based on the above embodiments, this application provides a SOC. Figure 9 This is a schematic diagram of the composition structure of a SOC, as shown below. Figure 9 As shown, the SOC10 includes: a receiving unit 11, a setting unit 12, and a transmitting unit 13; wherein,

[0111] The receiving unit 11 is configured to receive first instruction information; wherein, the first instruction information is configured to indicate whether a PCIe device is inserted or removed from the second device; the first device includes the PCIe device;

[0112] The setting unit 12 is used to set the status value of the first flag bit in the first register to a first value when the first instruction information indicates that the PCIE device is inserted in a first insertion mode.

[0113] The sending unit 13 is used to send a second instruction message to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction message; wherein...

[0114] The first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot.

[0115] In the embodiments of this application, further, Figure 10 This is a schematic diagram of the composition of the first device, such as... Figure 10 As shown, the first device 20 proposed in this application embodiment may further include a processor 14, a memory 15 storing instructions executable by the processor 14, and further, the first device 20 may further include a communication interface 16 and a bus 17 for connecting the processor 14, the memory 15 and the communication interface 16.

[0116] In the embodiments of this application, the processor 14 can be at least one of the following: Application-Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field-Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that for different devices, the electronic device used to implement the above-mentioned processor function can also be other types, and this application embodiment does not specifically limit the specific types. The first device 20 may further include a memory 15, which can be connected to the processor 14. The memory 15 is used to store executable program code, which includes computer operation instructions. The memory 15 may include high-speed RAM memory and may also include non-volatile memory, such as at least two disk drives.

[0117] In embodiments of this application, bus 17 is used to connect communication interface 16, processor 14, and memory 15, as well as the mutual communication between these devices.

[0118] In embodiments of this application, memory 15 is used to store instructions and data.

[0119] Furthermore, in an embodiment of this application, the processor 14 is configured to receive first instruction information; wherein, the first instruction information is configured to indicate whether a PCIe device is inserted or removed from the second device;

[0120] When the first instruction information indicates that the PCIe device is inserted in the first insertion mode, the SOC sets the status value of the first flag bit in the first register to a first value and sends a second instruction information to the second device, so that the second device adjusts the power indicator of the PCIe slot based on the second instruction information; wherein, the first flag bit is used at least to indicate whether the physical connection status of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection status, and the first register is used at least to characterize the physical status of the PCIe slot.

[0121] In practical applications, the aforementioned memory 15 can be volatile memory, such as random-access memory (RAM); or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); or a combination of the above types of memory, and provide instructions and data to the processor 14.

[0122] This application provides a System-on-Chip (SOC) that receives first instruction information. The first instruction information indicates whether a PCIe device is inserted or removed from a second device. When the first instruction information indicates that a PCIe device is inserted in a first insertion mode, the SOC sets the status value of a first flag bit in a first register to a first value and sends second instruction information to the second device, causing the second device to adjust the power indicator light of the PCIe slot based on the second instruction information. The first flag bit is at least used to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is at least used to characterize the physical state of the PCIe slot. Therefore, when the first instruction information indicates that a PCIe device is inserted in the first insertion method, the SOC can set the status value of the first flag bit in the first register to a first value to indicate that the physical connection status of the PCIe slot in the second device has changed, and send a second instruction information to the second device so that the second device can adjust the power indicator of the PCIe slot based on the second instruction information. The second instruction information includes at least an interrupt instruction for the physical connection status. That is, after the status value of the first flag bit in the first register is set to the first value in this embodiment, a physical connection status interrupt can be triggered to notify the second device that the insertion is complete, thereby ignoring the timeout waiting time of the operating system kernel, reducing the time spent inserting and removing PCIe devices, and thus improving business efficiency.

[0123] This application provides a computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the method of plugging and unplugging a PCIe device as described above.

[0124] Specifically, the program instructions corresponding to a method for plugging and unplugging a PCIe device in this embodiment can be stored on storage media such as optical discs, hard disks, and USB flash drives. When the program instructions corresponding to a method for plugging and unplugging a PCIe device in the storage media are read or executed by an electronic device, the following steps are included:

[0125] The SOC receives a first instruction message; wherein the first instruction message is used to indicate whether a PCIe device is inserted or removed from the second device;

[0126] When the first instruction indicates that the PCIe device is inserted in the first insertion mode, the SOC sets the status value of the first flag bit in the first register to a first value and sends a second instruction to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction; wherein...

[0127] The first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot.

[0128] This application also provides a computer program product, including a computer program that can be executed by the processor 14 of the first device 20 to perform the steps described in any of the foregoing methods.

[0129] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0130] This application is described with reference to schematic and / or block diagrams of implementations of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the schematic and / or block diagrams can be implemented by computer program instructions, and combinations of blocks in the schematic and / or block diagrams can be implemented. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the schematic and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0131] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the implementation flow diagram. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0132] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1The steps of the function specified in one or more boxes.

[0133] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A method for plugging and unplugging a PCIe device, characterized in that, The method is applied to a first device, the first device comprising a System-on-a-Chip (SOC), the method comprising: The SOC receives a first instruction message; wherein the first instruction message is used to indicate whether a PCIe device is inserted or removed from the second device; When the first instruction indicates that the PCIe device is inserted in the first insertion mode, the SOC sets the status value of the first flag bit in the first register to a first value and sends a second instruction to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction; wherein... The first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, the first register is used at least to characterize the physical state of the PCIe slot, and the first insertion method includes hot-plugging. When the first instruction information indicates that the PCIe device is inserted in the second insertion mode and the second device is not powered on, the SOC sets the status value of the second flag bit of the second register to the second value; wherein, the second insertion mode includes the cold insertion mode.

2. The method according to claim 1, characterized in that, Before the SOC sets the status value of the first flag bit in the first register to the first value, the method further includes: The SOC sets the status value of the second flag bit in the second register to the second value, and determines whether the current value of the third flag bit in the third register is the first target value. The second register is used at least to monitor the current status of the PCIe link, the second flag bit is used to indicate whether the current data link layer of the PCIe link is active, the third register is used at least to control the power status of the PCIe slot, and the third flag bit is used to control the hot-plug interrupt function of the PCIe slot. When the current value of the third flag bit is the first target value, the SOC sets the fourth flag bit in the first register to the second target value; wherein the fourth flag bit is used to characterize the device presence status of the PCIe slot, and the second target value characterizes that the device in the PCIe slot is in place.

3. The method according to claim 2, characterized in that, The method further includes: If the current value of the third flag bit is not the first target value, the SOC prohibits setting the fourth flag bit in the first register to the second target value.

4. The method according to claim 1, characterized in that, The method further includes: When the first instruction information indicates that the PCIe device is unplugged in the first unplugging method, the SOC sets the status value of the second flag bit in the second register to a third value, and determines whether the current value of the third flag bit in the third register is the first target value. If the current value of the third flag bit is the first target value, the SOC sets the fourth flag bit in the first register to the third target value; wherein the third target value indicates that the device in the PCIe slot is not present. The SOC sets the status value of the first flag bit in the first register to the first value and sends a third instruction message to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the third instruction message; wherein, the third instruction message is used to indicate that the PCIe device is successfully removed.

5. The method according to claim 4, characterized in that, The method further includes: If the current value of the third flag bit is not the first target value, the SOC prohibits setting the fourth flag bit in the first register to the third target value.

6. The method according to claim 1, characterized in that, The method further includes: When the first instruction information indicates that the PCIe device is unplugged in the second unplugging method and the second device is not powered on, the SOC sets the status value of the second flag bit of the second register to the third value.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: The SOC monitors the in-situ status of the PCIe device in real time through the second register. In the event of an anomaly in the PCIe device, the in-situ state of the PCIe device is restored using a preset recovery strategy.

8. A SOC, characterized in that, The SOC includes: a receiving unit, a setting unit, and a transmitting unit; wherein... The receiving unit is configured to receive first instruction information; wherein the first instruction information is configured to indicate whether a PCIe device is inserted or removed from a second device; the first device includes the PCIe device; The setting unit is configured to, when the first instruction information indicates that the PCIe device is inserted in a first insertion mode, set the status value of the first flag bit in the first register to a first value; and when the first instruction information indicates that the PCIe device is inserted in a second insertion mode and the second device is not powered on, set the status value of the second flag bit in the second register to a second value; wherein the second insertion mode includes a cold insertion mode and the first insertion mode includes a hot insertion mode; The sending unit is configured to send a second instruction message to the second device, so that the second device adjusts the power indicator light of the PCIe slot based on the second instruction message; wherein... The first flag bit is used at least to indicate whether the physical connection state of the PCIe slot has changed, the second instruction information includes at least an interrupt instruction for the physical connection state, and the first register is used at least to characterize the physical state of the PCIe slot.

9. A first device, characterized in that, The first device includes: a processor and a memory; wherein, The memory is used to store computer programs that can run on the processor; The processor is configured to perform the method as described in any one of claims 1-7 when running the computer program.

10. A computer-readable storage medium, characterized in that, The storage medium stores computer program code, which, when executed by a computer, performs the method described in any one of claims 1-7.

11. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the method according to any one of claims 1-7.

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