Method for realizing TDLAS-WMS gas signal enhancement by FPGA based on period average algorithm

Abstract

The invention discloses a method for realizing TDLAS-WMS gas signal enhancement by an FPGA based on a period average algorithm, and belongs to the technical field of gas detection. In order to solve the problems that in trace gas detection, due to the fact that the concentration of target gas is extremely low, second harmonic signals obtained through demodulation are prone to being submerged by random noise, signal recognition is difficult, and the accuracy and stability of a detection system are affected, the invention provides a signal enhancement method based on a period average algorithm. By averaging the corresponding sampling points in a plurality of periods, random noise is effectively suppressed, the signal-to-noise ratio of weak signals is remarkably improved, and the method is particularly suitable for a TDLAS-WMS trace gas detection system realized by an FPGA (Field Programmable Gate Array). According to the method, cycle alignment, average operation and real-time output are rapidly completed after complete cycle data are stored in the BRAM by utilizing the multiple relation of the read-write clock frequency, and the system signal quality and the processing efficiency are improved.

Description

Technical Field

[0001] This invention belongs to the field of gas detection technology, specifically relating to an FPGA-based method for enhancing TDLAS-WMS gas signals based on a periodic averaging algorithm. Background Technology

[0002] Tunable Diode Laser Absorption Spectroscopy (TDLAS) is a highly sensitive and selective gas detection technique. This technique utilizes a tunable laser to scan the characteristic absorption lines of a target gas, measuring the absorption intensity as the laser passes through the gaseous medium, and then using Beer-Lambert's law to invert the gas concentration. TDLAS offers significant advantages such as fast response, non-contact operation, high resolution, and suitability for online monitoring, and is widely used in environmental monitoring, industrial process control, and trace gas detection.

[0003] To further improve detection sensitivity, TDLAS is often combined with Wavelength Modulation Spectroscopy (WMS). WMS technology superimposes a high-frequency sinusoidal modulation signal onto a laser sawtooth wave scan, extracts the second harmonic component of the modulation signal using a lock-in amplifier to invert the gas concentration, significantly improving the system's signal-to-noise ratio (SNR) and measurement accuracy, and enhancing its trace gas detection capabilities. However, when the gas concentration decreases further, the SNR of the demodulated second harmonic signal drops significantly, often becoming submerged in random noise, making it difficult for conventional single-cycle filtering methods to effectively extract the useful signal. Existing second harmonic signal enhancement methods include Kalman filtering, averaging filtering, and wavelet transform filtering. These filtering methods can suppress noise and improve the SNR to some extent; acquiring multiple periodic signals and processing them by computer is commonly used for experimental data analysis. However, when the gas concentration is extremely low, the amplitude of the second harmonic signal is close to or below the noise level, making it difficult for traditional filters to further improve the SNR, and potentially even causing further loss of the useful signal. The method of acquiring multiple periodic signals and averaging them by computer suffers from insufficient real-time performance. Summary of the Invention

[0004] In trace gas detection, due to the extremely low concentration of the target gas, the demodulated second harmonic signal is easily submerged by random noise, leading to difficulties in signal identification and affecting the accuracy and stability of the detection system. This invention provides a signal enhancement method based on a periodic averaging algorithm. By averaging corresponding sampling points within multiple periods, random noise is effectively suppressed, and the signal-to-noise ratio of weak signals is significantly improved. This method is particularly suitable for the TDLAS-WMS trace gas detection system implemented in FPGA.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm includes the following steps:

[0007] Step 1: Write the second harmonic signal, which has consecutive period_cnt cycles and contains point sampling points per cycle, into the block memory (BRAM) inside the Field-Programmable Gate Array (FPGA) in sequence.

[0008] Step 2: Control the write operation through the periodic synchronous trigger signal to make the BRAM write address increment sequentially;

[0009] Step 3: When the accumulated write address reaches (period_cnt - 1) × point, initiate the read operation;

[0010] Step 4: The read address is generated by a two-level counter, using the formula addrb = inner_cnt × point + outer_cnt;

[0011] Step 5: Through a non-linear address mapping mechanism, data at the same sampling position in multiple cycles are read in an interleaved manner to ensure that the sampling points across cycles correspond one-to-one.

[0012] Step 6: Sum the data from period_cnt sampling points at the same position in each group, and then calculate the average by right shifting.

[0013] Step 7: The final output is a periodic average signal containing points.

[0014] This method utilizes the multiple relationship between read and write clock frequencies to quickly complete cycle alignment, averaging calculation, and real-time output after storing complete cycle data in BRAM, thereby improving system signal quality and processing efficiency.

[0015] Furthermore, in step 1, the clock frequency is written to be consistent with the signal sampling rate.

[0016] Furthermore, the read operation in step 3 uses a read clock frequency that is period_cnt times the write clock frequency to achieve fast read processing.

[0017] Furthermore, the block memory (BRAM) is an asynchronous dual-port RAM structure.

[0018] A second harmonic detection system based on lock-in amplification includes: a high-speed analog-to-digital converter, a periodic averaging module, a lock-in amplification module, a cascaded integrator comb filter (CIC filter), a processing module, and a block memory module.

[0019] The high-speed analog-to-digital converter (ADC) is used to sample the analog signal output by the photodetector in real time;

[0020] The periodic averaging module is used to average multiple periodic signals to improve the signal-to-noise ratio of the signal;

[0021] The lock-in amplifier module is used to extract weak signal components with the same frequency as the reference signal to suppress noise;

[0022] The cascaded integrator comb filter achieves downsampling of the sampled signal to reduce the computational complexity of subsequent filters;

[0023] The processing module is used to perform periodic averaging of the second harmonic signal in gas detection to improve the signal-to-noise ratio and reduce the detection limit.

[0024] After the signal is acquired by the high-speed analog-to-digital converter (ADC), the signal is demodulated by the lock-in amplifier module to extract the second harmonic signal (2f signal) containing the absorption information of the target gas. Then, it is processed by the cascaded integrator comb filter (CIC filter) to effectively downsample the data rate from 25 MSPS to 10 kSPS to adapt to the computing power and data bandwidth requirements of the processing module.

[0025] Furthermore, the second harmonic detection system uses a sawtooth wave to modulate the laser frequency, with the modulation period of the sawtooth wave set to 10 Hz. At the start of each sawtooth wave cycle update, the second harmonic detection system generates a synchronous high-level control signal with a duration of 100 microseconds to trigger the block memory (BRAM) module to start a write operation, ensuring cycle synchronization and data consistency.

[0026] Furthermore, the period averaging module includes a reset signal interface, an input signal interface, a period signal point count interface, a BRAM read clock interface, a BRAM write clock interface, a period start signal interface, an output signal interface, a BRAM read enable signal interface, a BRAM write enable signal interface, a BRAM read address interface, a BRAM write address interface, and an averaging completion signal interface.

[0027] Furthermore, the high-speed analog-to-digital converter (ADC) has a sampling rate of 25 megasamples per second (25 MSPS), ensuring sufficient accuracy in acquiring high-frequency signals.

[0028] Furthermore, the block memory (BRAM) module uses a 10 kHz clock for the write port and a 20 kHz clock for the read port to implement a slow write and fast read data processing architecture.

[0029] Furthermore, the BRAM read address mapping strategy is as follows: at each time step, the sampling point at the same position is taken from two different cycles, and a zero-complement cycle is added to achieve cross-cycle point-to-point data alignment and subsequent processing; the calculation formula is expressed as: addrb = N + k × 1000; where k = 0, 1; N = 0 ~ 999.

[0030] Compared with the prior art, the present invention has the following advantages:

[0031] This invention improves the signal-to-noise ratio by introducing a multi-cycle averaging mechanism: Compared to traditional lock-in amplifier systems that typically only collect harmonic signals from a single cycle, which are susceptible to noise interference and result in large fluctuations in detection results, this invention writes the second harmonic signals from multiple consecutive cycles into the block RAM (BRAM) inside the FPGA and performs a weighted average at corresponding points in each cycle during the readout phase (the data from four cycles is accumulated and then shifted two bits to the right), which significantly suppresses random noise and improves signal stability and system repeatability.

[0032] Meanwhile, this application employs an asynchronous dual-port BRAM design and a non-linear address mapping strategy: using an asynchronous dual-port BRAM, the write port maintains a consistent 10kHz rate with sampling, while the read port operates at a higher 40kHz rate, achieving separation and parallel operation of write and read operations. During reading, the innovative address mapping formula addrb = N + k × 1000 is used to achieve interleaved reading of data from the same sampling point across multiple cycles, facilitating averaging in subsequent cycles. This "cross-cycle point-to-point pairing" reading method represents an improvement over existing averaging strategies. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a flowchart of the periodic averaging method.

[0035] Figure 2 This is a schematic diagram of the periodic averaging module interface.

[0036] Figure 3 It is a module timing diagram. Detailed Implementation

[0037] To gain a deeper understanding of this invention, we will provide a comprehensive and detailed description. However, this invention has various implementations and is not limited to the specific examples listed herein. These examples are presented to enhance a full understanding of the disclosure of this invention.

[0038] Example 1

[0039] A method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm, such as... Figure 1 As shown,

[0040] Step 1: Write the second harmonic signal with consecutive period_cnt cycles, each cycle containing point sampling points, into the block memory (BRAM) inside the field programmable gate array (FPGA) in sequence; the writing clock frequency is consistent with the signal sampling rate.

[0041] Step 2: Control the write operation through the periodic synchronous trigger signal to make the BRAM write address increment sequentially;

[0042] Step 3: When the write address accumulates to (period_cnt - 1) × point, the read operation is started; the read clock frequency is a multiple of the write clock frequency of period_cnt to achieve fast read processing;

[0043] Step 4: The read address is generated by a two-level counter, using the formula addrb = inner_cnt × point + outer_cnt;

[0044] Step 5: Through a non-linear address mapping mechanism, data at the same sampling position in multiple cycles are read in an interleaved manner to ensure that the sampling points across cycles correspond one-to-one.

[0045] Step 6: Sum the data from period_cnt sampling points at the same position in each group, and then calculate the average by right shifting.

[0046] Step 7: The final output is a periodic average signal containing points.

[0047] By utilizing the multiple relationship between the read and write clock frequencies, after storing complete cycle data in the BRAM, cycle alignment, averaging calculation, and real-time output can be completed quickly, improving system signal quality and processing efficiency.

[0048] Example 2

[0049] A second harmonic detection system based on lock-in amplification includes: a high-speed analog-to-digital converter, a periodic averaging module, a lock-in amplification module, a cascaded integrator comb filter (CIC filter), and a processing module;

[0050] The high-speed analog-to-digital converter (ADC) is used to sample the analog signal output by the photodetector in real time;

[0051] The periodic averaging module is used to average multiple periodic signals to improve the signal-to-noise ratio of the signal;

[0052] The lock-in amplifier module is used to extract weak signal components with the same frequency as the reference signal to suppress noise;

[0053] The cascaded integrator comb filter achieves downsampling of the sampled signal to reduce the computational complexity of subsequent filters;

[0054] The processing module is used to perform periodic averaging of the second harmonic signal in gas detection to improve the signal-to-noise ratio and reduce the detection limit.

[0055] After the signal is acquired by the high-speed analog-to-digital converter (ADC), the signal is demodulated by the lock-in amplifier module to extract the second harmonic signal (2f signal) containing the absorption information of the target gas. Then, it is processed by the cascaded integrator comb filter (CIC filter) to effectively downsample the data rate from 25 MSPS to 10 kSPS to adapt to the computing power and data bandwidth requirements of the processing module. Figure 2 This is the input / output interface for the periodic averaging module.

[0056] Since the system uses a sawtooth wave to modulate the laser frequency, with a modulation period set to 10Hz, each cycle consists of 100ms. Corresponding to a 10 kSPS sampling rate, each cycle will collect 1000 points of second harmonic data. To ensure cycle synchronization and data consistency, at the start of each sawtooth wave cycle update, the system generates a 100-microsecond high-level synchronization control signal to trigger the Block RAM (BRAM) module to begin write operations.

[0057] The BRAM is configured as an asynchronous dual-port RAM structure, with an average cycle count of 2. The write port uses a 10kHz clock, and the read port uses a 20kHz clock to achieve a "slow write, fast read" data processing architecture. Upon receiving a write trigger signal, the BRAM's write address is initialized to 0 and incremented by 1 on each rising edge of the write clock until the write address reaches 1999. During this process, two consecutive complete cycles (i.e., 2000 points) of the second harmonic signal are written, stored in the address ranges [0, 999] and [1000, 1999], respectively.

[0058] After two cycles of data have been written, the system automatically switches to read mode and initiates read operations on the BRAM. To achieve rapid averaging of corresponding points in each cycle, the read address is generated using a special mapping strategy. Specifically, the read address is accessed sequentially as follows: 0, 1000, 1, 1001, 2, 1002, ..., which is generated using the following formula:

[0059] addrb =N+k×1000(k=0,1; N=0∼999)

[0060] This address generation method ensures that at each moment, the same sampling point (e.g., the Nth sampling point) is retrieved from two different cycles, along with a zero-padding cycle (address 1000+N), thereby achieving cross-cycle point-to-point data alignment and subsequent processing.

[0061] Subsequently, the data from the sampling points corresponding to the four adjacent cycles are accumulated, and the mean is calculated by logically shifting one bit to the right (equivalent to dividing by 2), thus outputting the result after averaging for one cycle. The module timing diagram is as follows. Figure 3 As shown.

[0062] This processing method not only significantly reduces the impact of random fluctuations within the period on signal stability, but also effectively improves the signal-to-noise ratio and data repeatability, which helps to improve the stability of gas concentration inversion.

[0063] Furthermore, by implementing the cumulative averaging logic of corresponding points across multiple cycles in an FPGA, and with the help of an efficient clock control and address mapping mechanism, this design can complete complex data fusion processing without relying on an external processor. It has high integration and real-time performance, making it particularly suitable for high-precision gas detection and laser absorption spectroscopy systems.

[0064] Contents not described in detail in this specification are prior art known to those skilled in the art. Although illustrative specific embodiments of the invention have been described above to facilitate understanding by those skilled in the art, it should be understood that the invention is not limited to the scope of the specific embodiments. Various modifications are readily apparent to those skilled in the art as long as they fall within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of this invention are protected.

Claims

1. A method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm, characterized in that: Includes the following steps: Step 1: Write the second harmonic signal with consecutive period_cnt cycles and each cycle containing point sampling points into the block memory (BRAM) inside the field programmable gate array (FPGA) in sequence. Step 2: Control the write operation through the periodic synchronous trigger signal to make the BRAM write address increment sequentially; Step 3: When the accumulated write address reaches (period_cnt - 1) × point, initiate the read operation; Step 4: The read address is generated by a two-level counter, using the formula addrb = inner_cnt × point + outer_cnt; Step 5: Through a non-linear address mapping mechanism, data at the same sampling position in multiple cycles are read in an interleaved manner to ensure that the sampling points across cycles correspond one-to-one. Step 6: Sum the data from period_cnt sampling points at the same position in each group, and then calculate the average by right shifting. Step 7: The final output is a periodic average signal containing points.

2. The method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm according to claim 1, characterized in that: In step 1, the clock frequency is written to be consistent with the signal sampling rate.

3. The method for enhancing TDLAS-WMS gas signals using an FPGA based on a periodic averaging algorithm according to claim 1, characterized in that: The read operation in step 3 uses a read clock frequency that is period_cnt times the write clock frequency to achieve fast read processing.

4. The FPGA-based TDLAS-WMS gas signal enhancement method based on a periodic averaging algorithm according to claim 1, characterized in that: The block memory (BRAM) is an asynchronous dual-port RAM structure.

5. A second harmonic detection system based on lock-in amplification, characterized in that, The method for implementing the method of claims 1 to 4 specifically includes: a high-speed analog-to-digital converter, a periodic averaging module, a phase-locked amplifier module, a cascaded integrator-comb filter, a processing module, and a block memory module. The high-speed analog-to-digital converter is used to sample the analog signal output by the photodetector in real time. The periodic averaging module is used to average multiple periodic signals to improve the signal-to-noise ratio of the signal; The lock-in amplifier module is used to extract weak signal components with the same frequency as the reference signal to suppress noise; The cascaded integrator comb filter achieves downsampling of the sampled signal to reduce the computational complexity of subsequent filters; The processing module is used to perform periodic averaging of the second harmonic signal in gas detection to improve the signal-to-noise ratio and reduce the detection limit. After the signal is acquired by the high-speed analog-to-digital converter, the signal is demodulated by the lock-in amplifier module to extract the second harmonic signal containing the absorption information of the target gas. Then, it is processed by the cascaded integrator comb filter to effectively downsample the data rate from 25 MSPS to 10 kSPS to match the computing power and data bandwidth requirements of the processing module.

6. The second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The second harmonic detection system uses a sawtooth wave to modulate the laser frequency, with the modulation period of the sawtooth wave set to 10 Hz. At the start of each sawtooth wave cycle update, the second harmonic detection system generates a 100-microsecond synchronous high-level control signal to trigger the block memory module to begin write operations, ensuring cycle synchronization and data consistency.

7. The second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The period averaging module includes a reset signal interface, an input signal interface, a period signal point count interface, a BRAM read clock interface, a BRAM write clock interface, a period start signal interface, an output signal interface, a BRAM read enable signal interface, a BRAM write enable signal interface, a BRAM read address interface, a BRAM write address interface, and an averaging completion signal interface.

8. The second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The high-speed analog-to-digital converter has a sampling rate of 25 megasamples per second.

9. A second harmonic detection system based on lock-in amplification according to claim 5, characterized in that: The block memory module uses a 10 kHz clock for the write port and a 20 kHz clock for the read port to implement a slow write and fast read data processing architecture.

10. A second harmonic detection system based on lock-in amplification according to claim 7, characterized in that: The mapping strategy adopted by BRAM read address is as follows: at each time step, the sampling point at the same position is taken from two different cycles, and a zero-padding cycle is added to realize cross-cycle point-to-point data alignment and subsequent processing; the calculation formula is expressed as: addrb =N+k×1000; where k=0,1; N=0~999.

Images