Processor circuit generation method, system and related devices

Abstract

The application relates to a processor circuit generation method, system and related equipment, which comprises the following steps: acquiring all computing unit parameters of all computing unit modules in a processor; acquiring preset product parameters used for determining the logic size of the processor; calculating control component parameters corresponding to different control components in the processor according to the preset product parameters and taking the computing unit parameters as the basis; and based on the control component parameters, performing instantiation of the control components to obtain a corresponding processor circuit of the processor. The application completely decouples the calculation process of the parameters of the computing unit modules and the control components in the processor from the logic of circuit generation, so that the flexibility and configurability of the circuit generation process are maximally reserved, meanwhile, the parameter description of the modules and components can also maintain high maintainability and readability, which is beneficial to the design and maintenance of the processor circuit.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of processor integrated design technology, and particularly relates to a processor circuit generation method and system and related equipment. BACKGROUND

[0002] Chisel is based on Scala language, and is a circuit description language for processor design. The Chisel language can use high-level language mechanisms such as object-oriented and high-order functions to quickly and efficiently generate Verilog code for describing circuit logic according to parameters set by the developer. In the process of circuit development, the code of the Chisel language can be run by passing in specific parameters to generate the corresponding circuit structure according to the parameters, so that the circuit development process based on this language can greatly reduce the repetitive labor of the developer and improve the work efficiency of the designer.

[0003] However, due to the high configurability of the Chisel language and the Scala language in circuit design, as the design complexity gradually increases, how to ensure the correctness of parameters and wiring between modules in a large out-of-order central processing unit (CPU) IP core has become an important problem that hinders the development and design space optimization exploration of large core processor projects.

[0004] The existing method uses a scheme of mixing in parameter traits to ensure parameter alignment. This scheme specifically includes two objects in use, one is the circuit module itself, and the other is the parameter trait carrying the parameters required for generating the circuit. This method obtains the parameters required for generating the circuit by mixing the parameter trait into the circuit module waiting to run, and the mixed-in circuit module executes to obtain the circuit corresponding to the parameters. For example, a method using a commercial integrated framework includes parameters passed through the framework in the parameters waiting to be calculated and transmitted, and these parameters are integrated into the circuit code.

[0005] However, in the above method, the description of the circuit topology is integrated into the code itself, and once the topology of the circuit needs to be highly configured, the code for generating the circuit needs to be rewritten constantly. Under the condition of requiring highly configurable and complex system design requirements, this code maintenance is difficult. For a central processing unit with a specific structure, the existing design method is not applicable. SUMMARY

[0006] The present application provides a processor circuit method, system and related equipment, which aims to solve the technical problem that the existing method cannot decouple the circuit structure and the circuit code, resulting in difficulty in processor circuit design and maintenance.

[0007] To solve the above technical problems, in a first aspect, the application provides a processor circuit generation method, comprising the following steps:

[0008] Obtaining computing unit parameters of all computing unit modules in the processor;

[0009] Obtaining preset product parameters for determining the logic size of the processor;

[0010] According to the preset product parameters, control component parameters corresponding to different control components in the processor are calculated based on the computing unit parameters;

[0011] Based on the control component parameters, instantiation of the control components is performed to obtain a processor circuit corresponding to the processor.

[0012] Further, in the step of calculating control component parameters corresponding to different control components in the processor based on the computing unit parameters according to the preset product parameters, the following sub-steps are included:

[0013] According to the preset product parameters, a set of control components contained in the processor is determined;

[0014] Taking the computing unit modules as sub-nodes, a hierarchical connection relationship between each control component and the remaining control components and between each computing unit module is determined in the set of control components to obtain a hierarchical connection relationship list;

[0015] According to the hierarchical connection relationship list, the control component parameters corresponding to different control components are calculated based on the computing unit parameters.

[0016] Further, in the step of calculating control component parameters corresponding to different control components based on the hierarchical connection relationship list and the computing unit parameters, the following steps are further included:

[0017] Obtaining preset resource parameters for determining the computing resource size of the processor, and using the preset resource parameters in the calculation process of the control component parameters.

[0018] Further, different computing unit modules can have a reuse relationship in the hierarchical connection relationship list corresponding to different control components.

[0019] Further, the control components include at least one of an operation pipeline, a register read port, a launch queue, a dispatch distribution component, a renaming component, and a decoding component according to the logical order of instruction calculation to instruction decoding in the processor.

[0020] Further, based on the control component parameters, the step of instantiating the control component is performed in reverse order of calculation of the control component parameters.

[0021] Further, the preset product parameters are used to define the number of the computing unit modules and the memory access pipeline required by the core of the processor, and the preset resource parameters are used to define the number of the cache capacity and the register heap required by the control component.

[0022] In a second aspect, the present application further provides a processor circuit generation system, comprising:

[0023] a computing parameter acquisition module, configured to acquire computing unit parameters of all computing unit modules in the processor;

[0024] an input module, configured to acquire preset product parameters used to determine the logic size of the processor;

[0025] a parameter passing module, configured to calculate control component parameters corresponding to different control components in the processor based on the preset product parameters and the computing unit parameters;

[0026] an instantiation generation module, configured to perform instantiation of the control components based on the control component parameters, to obtain a processor circuit corresponding to the processor.

[0027] In a third aspect, the present application further provides a computer device, comprising a memory, a processor, and a processor circuit generation program stored in the memory and executable on the processor, wherein the processor implements the steps of the processor circuit generation method according to any one of the above embodiments when executing the processor circuit generation program.

[0028] In a fourth aspect, the present application further provides a computer readable storage medium, wherein the computer readable storage medium stores a processor circuit generation program, and the processor circuit generation program implements the steps of the processor circuit generation method according to any one of the above embodiments when executed by a processor.

[0029] The present application has the advantages that a processor circuit generation method based on computing unit parameters is provided, which describes the structure and corresponding relationship of each control component in the processor circuit by using the parameters of the basic structure of the computing unit, and instantiates the circuit modules according to the corresponding relationship and the component topology relationship. In this process, the calculation process of the parameters of the modules and components can be completely decoupled from the logic of the circuit generation, so that the flexibility and configurability of the circuit generation process are maximally reserved. At the same time, the parameter description of the modules and components can also maintain high maintainability and readability, which is beneficial to the design and maintenance of the processor circuit. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a step flow block diagram of a processor circuit generation method provided by an embodiment of the present application;

[0031] Figure 2 is a processor parameter level and instantiation schematic diagram in the processor circuit generation method provided by an embodiment of the present application;

[0032] Figure 3 is a structural schematic diagram of a processor circuit generation system provided by an embodiment of the present application;

[0033] Figure 4 is a structural schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0035] Please refer to Figure 1 , Figure 1 is a step flow block diagram of a processor circuit generation method provided by an embodiment of the present application, and the processor circuit generation method comprises the following steps:

[0036] S101, obtaining computing unit parameters of all computing unit modules in a processor.

[0037] Specifically, the computing unit module in the embodiment of the present application refers to a module (FU) in a processor system that performs arithmetic operation, memory access control and the like. As described in the background, the existing processor circuit design is based on a coded language to perform structural description and circuit generation, and in the processor circuit design, in order to realize perfect parameterized design to guide the circuit generation and connection at the processor level and ensure the width and number of the connection between the modules correct, it is necessary to determine the propagation starting point and mixing step of the circuit parameters, and strictly follow the DRY (Don't Repeat Yourself) principle in the parameter calculation and transmission process, and the related parameters guiding the connection between two modules are not allowed to be initialized respectively when the two modules are instantiated. Therefore, in order to realize this requirement, it is necessary to generate parameters from a higher perspective, starting from a certain structure in the processor as a starting point to gradually calculate, and these information gradually becomes complete through multi-layer calculation and mixing, and needs to be informed to other related modules through a reasonable way, and finally can guide the instantiation of all sub-modules in the processor.

[0038] The inventors have noticed that in the design of an out-of-order processor core, there are obvious data flow directions and natural topological logical relationships, for example:

[0039] All compute unit modules need to read data as raw materials from the register file or the front-end network;

[0040] All compute unit modules will report to the reorder buffer and write back the corresponding register file after the end of instruction execution;

[0041] All instructions need to be uniformly and globally decoded and register renamed before being dispatched to the corresponding compute unit module;

[0042] All compute unit modules and related control components will receive redirection-related information for correct maintenance of resource usage and flushing of instructions that are flushed.

[0043] Therefore, in the design of an out-of-order processor core, all control components coordinate the workload of compute unit modules, put in the correct raw materials, take back and record the correct calculation results, that is, the control components serve the compute units, and the compute units are actually the starting point of parameter diffusion of the out-of-order processor. Therefore, the processor circuit generation method provided in the embodiment of the present application determines to take the respective compute unit parameters of the compute unit modules as the starting point for parameter calculation.

[0044] In the implementation process, the compute unit parameters can be represented based on a certain circuit description language, and the compute unit parameters are basic language structures. In step S101, a special parameter class is constructed for each specific type of compute unit parameter. Instantiation of these parameters is called parameter objects. These parameter classes contain on-chip resource information required by the compute unit, such as the number of register file read-write port requirements and the number of submission ports of the reorder buffer. In subsequent steps, the compute unit parameters are called by the circuit description language of other control components.

[0045] S102, obtaining preset product parameters for determining the logic size of the processor.

[0046] The preset product parameters are determined by user input data. In the processor circuit design, the use scenario of the processor and the functions implemented by the processor need to be determined. The preset product parameters can be used to limit the number of computing unit modules and memory access pipelines required by the core of the processor. These parameters determine the size and capacity of the processor core. For example, a small core of a processor supports a maximum of two instructions for simultaneous decoding, which includes two integer arithmetic logic units (ALUs), one multiplication division unit (MDU), and one memory access pipeline. Or a large core supports a maximum of four instructions for simultaneous decoding, six integer arithmetic logic units (ALUs), two multiplication division units (MDUs), and two memory access pipelines. It should be noted that different processor core configuration parameters are described by different preset product parameters in the implementation process.

[0047] S103, according to the preset product parameters, the control component parameters corresponding to different control components in the processor are calculated based on the computing unit parameters.

[0048] Specifically, please refer to Figure 2 , Figure 2 is a processor parameter level and instantiation diagram provided by the embodiment of the application. The control component is according to the logical order of instruction computing (based on the computing unit module FU, Figure 2 including FUA, FUB, FUC, and other types of computing unit modules) to instruction decoding stage, including at least one of the operation pipeline (Pipe), the register read port (Read Port), the emission queue (Issue), the dispatch distribution component (Dispatch), the renaming component (Rename), and the decoding component (Decode). The components involved before the dispatch distribution logic can be considered as included in a register heap port (White Port), wherein, Figure 2 the same type of different components are labeled as A, B, C, etc.

[0049] As described in step S101, different types of computing unit modules have different requirements for register heap read-write ports and other resources. Due to the objective limitation of register heap port resources, all computing unit modules cannot freely access the register heap in the actual processor circuit. In some cases, one or more computing unit modules need to share the register heap read-write port. The inventor also noticed that this limitation can be naturally coupled with the task of the emission unit. For example, instructions with all operands ready are arranged by the emission unit to read the register heap, and after obtaining the data, they are sent to the corresponding computing unit for execution.

[0050] Therefore, in the embodiment of the present application, the different computing unit modules can exist in a multiplexing relationship in the hierarchical connection relationship list corresponding to the different control components. In the implementation process, the number of various types of computing unit modules and the shared register stack read-write port resources are arranged and combined (which several units share a set of register read or write ports, etc.), and based on the obtained computing unit parameters, the parameters and interface numbers of other related control components can be obtained through calculation.

[0051] Step S103 includes the following sub-steps:

[0052] S1031, determining a set of control components contained in the processor according to the preset product parameters;

[0053] S1032, determining the hierarchical connection relationship between each control component and the remaining control components in the set of control components and between each computing unit module, and obtaining a hierarchical connection relationship list, by taking the computing unit module as a sub-node.

[0054] S1033, according to the hierarchical connection relationship list, calculating the control component parameters corresponding to the different control components based on the computing unit parameters.

[0055] Specifically, as shown in Figure 2 , the parameter calculation process of the control component takes the computing unit parameter as the bottom layer, and then corresponding, the first operation pipeline (PipeA) has a direct calling hierarchical connection relationship with the first type of computing unit (FUA) and the second type of computing unit (FUB), and the first, second, and third operation pipelines (PipeA, PipeB, PipeC) are at the same level and are directly called by the first register read port (Read PortA), forming a second-level hierarchical connection relationship. In addition, it can be seen from Figure 2 that the same type of computing unit (for example, FUC, FUD) is called by different operation pipelines, and there is a multiplexing situation in the entire hierarchical connection relationship. By analogy, after step S103 is executed, the control component parameters corresponding to all control components in the processor can be easily obtained through the calling of the computing unit parameters.

[0056] Step S1033 further includes obtaining a preset resource parameter for determining the computing resource size of the processor, and using the preset resource parameter in the calculation process of the control component parameters. The preset resource parameter is used to limit the cache capacity and the number of register stacks required by the control component. This parameter can be manually input or determined according to the actual function of the control component.

[0057] The mixing in of the resource parameters in this step is necessary for the calculation of the control component parameters, and in the parameter configuration process of each control component, the use of the internal related resources of each control component also needs to be reflected, therefore, the control component parameters obtained through the processing of step S103 can also reflect the circuit performance of the processor, such as circuit area and time delay, etc.

[0058] S104, based on the control component parameters, instantiation of the control component is performed to obtain the corresponding processor circuit of the processor.

[0059] As shown in Figure 2 , the circuit instantiation is performed in reverse according to the calculation order of the control component parameters, so that the circuit structure obtained through the processing can clearly show the connection relationship between each control component in the processor circuit. It can be understood that the entire circuit generation process and the parameter calculation process are completely decoupled, and all modules are instantiated and connected after the mixing in and calculation of all parameters are completed, therefore, the processor circuit generation method provided by the embodiment of the present application will not exist the case that a large number of parameters (or description language codes) are modified due to the change of the module, so that the flexibility and configurability are retained.

[0060] On the other hand, in the parameter calculation process of each module, the parameters of the calculation resources are also mixed in, so that the final circuit of the processor generated in this way can calculate the total amount of global resources according to these topologies, such processing not only can directly show the calculation performance based on the bottom calculation unit module, but also can facilitate the developer to intuitively analyze the actual circuit of each control component in the processor in terms of area and use of calculation resources, so as to perform time delay analysis and other work.

[0061] The beneficial effects achieved by the present application are that a processor circuit generation method based on calculation unit parameters is proposed, which describes the structure and corresponding relationship of each control component in the processor circuit by using the parameters of the calculation unit as the basic structure, and instantiates and generates the circuit module according to the corresponding relationship and component topology relationship, in this process, the calculation process of the parameters of the module and the component and the logic of the circuit generation can be completely decoupled, so that the flexibility and configurability of the circuit generation process are maximally retained, at the same time, the parameter description of the module and the component can also maintain high maintainability and readability, which is beneficial to the design and maintenance of the processor circuit.

[0062] The embodiment of the present application also provides a processor circuit generation system 200, please refer to Figure 3 , Figure 3 is a structure diagram of the processor circuit generation system provided by the embodiment of the present application, which comprises:

[0063] The computing parameter obtaining module 201 is configured to obtain computing unit parameters of all computing unit modules in the processor.

[0064] The input module 202 is configured to obtain preset product parameters used to determine the logic size of the processor.

[0065] The parameter passing module 203 is configured to calculate control component parameters corresponding to different control components in the processor based on the preset product parameters and the computing unit parameters.

[0066] The instantiation generation module 204 is configured to perform instantiation of the control components based on the control component parameters, to obtain the processor circuit corresponding to the processor.

[0067] The processor circuit generation system 200 can implement the steps in the processor circuit generation method in the above-described embodiments, and achieve the same technical effects. For details, refer to the description in the above-described embodiments, which will not be described here again.

[0068] The embodiment of the present application also provides a computer device, please refer to Figure 4 , Figure 4 is a structural schematic diagram of the computer device provided by the embodiment of the present application, the computer device 300 comprises a memory 302, a processor 301 and a processor circuit generation program stored in the memory 302 and capable of running on the processor 301.

[0069] The processor 301 invokes the processor circuit generation program stored in the memory 302 to execute the steps in the processor circuit generation method provided by the embodiment of the present application, please combine Figure 1 , specifically comprising the following steps:

[0070] S101, obtaining computing unit parameters of all computing unit modules in the processor;

[0071] S102, obtaining preset product parameters used to determine the logic size of the processor;

[0072] S103, calculating control component parameters corresponding to different control components in the processor based on the preset product parameters and the computing unit parameters;

[0073] S104, performing instantiation of the control components based on the control component parameters, to obtain the processor circuit corresponding to the processor.

[0074] Step S103 comprises the following sub-steps:

[0075] S1031, determining the set of control components contained in the processor based on the preset product parameters;

[0076] S1032, determining a hierarchical connection relationship between each of the control components and the rest of the control components and between each of the computing unit modules in the set of control components with the computing unit module as a sub-node, to obtain a hierarchical connection relationship list;

[0077] S1033, calculating the control component parameters corresponding to different control components according to the hierarchical connection relationship list and taking the computing unit parameters as a reference.

[0078] In step S1033, further comprising:

[0079] obtaining a preset resource parameter for determining the computing resource size of the processor, and using the preset resource parameter in the calculation process of the control component parameters.

[0080] Different computing unit modules can exist in a multiplexing relationship in the hierarchical connection relationship list corresponding to different control components.

[0081] The control component includes at least one of an operation pipeline, a register read port, a transmission queue, a dispatch distribution component, a renaming component, and a decoding component according to the logical order of instruction calculation to instruction decoding in the processor.

[0082] In the step of instantiating the control component based on the control component parameters, circuit instantiation is performed in reverse according to the calculation order of the control component parameters.

[0083] The preset product parameter is used to limit the number of computing unit modules and memory pipelines required by the core of the processor, and the preset resource parameter is used to limit the cache capacity and the number of register stacks required by the control component.

[0084] The computer device 300 provided by the embodiment of the present application can realize the steps in the processor circuit generation method of the processor circuit generation method in the above-mentioned embodiment, and can realize the same technical effects. For the description in the above-mentioned embodiment, details are not repeated here.

[0085] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores a processor circuit generation program. When the processor circuit generation program is executed by a processor, each process and step in the processor circuit generation method provided by the embodiment of the present application is realized, and the same technical effects can be realized. To avoid repetition, details are not repeated here.

[0086] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a processor circuit generating a program to instruct relevant hardware (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to complete. The program can be stored in a computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiments of the methods can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc.

[0087] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0088] The embodiments of the present application are described above in conjunction with the drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are only illustrative, but not restrictive, and those skilled in the art can make many equivalent changes under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

Claims

1. A processor circuit generation method, characterized by, The method comprises the following steps: obtaining the computing unit parameters of all computing unit modules in a processor; obtaining preset product parameters for determining the logic size of the processor; calculating the control component parameters corresponding to different control components in the processor based on the computing unit parameters according to the preset product parameters; based on the control component parameters, instantiating the control components to obtain the processor circuit corresponding to the processor; wherein, in the step of calculating the control component parameters corresponding to different control components in the processor based on the computing unit parameters according to the preset product parameters, the following sub-steps are included: determining the set of control components contained in the processor according to the preset product parameters; determining the hierarchical connection relationship between each control component and the remaining control components in the set of control components and between each computing unit module based on the computing unit modules as child nodes to obtain a hierarchical connection relationship list; calculating the control component parameters corresponding to different control components based on the computing unit parameters according to the hierarchical connection relationship list.

2. The processor circuit generation method of claim 1, wherein, In the step of calculating the control component parameters corresponding to different control components based on the computing unit parameters according to the hierarchical connection relationship list, the following is also included: obtaining preset resource parameters for determining the computing resource size of the processor, and using the preset resource parameters in the calculation process of the control component parameters.

3. The processor circuit generation method of claim 1, wherein, Different computing unit modules can have a reuse relationship in the hierarchical connection relationship list corresponding to different control components.

4. The processor circuit generation method of claim 1, wherein, The control components include at least one of an operation pipeline, a register read port, a transmission queue, a dispatch distribution component, a renaming component, and a decoding component according to the logical order of instruction calculation to instruction decoding in the processor.

5. The processor circuit generation method of claim 1, wherein, In the step of instantiating the control components based on the control component parameters, the circuit instantiation is performed in reverse according to the calculation order of the control component parameters.

6. The processor circuit generation method of claim 2, wherein, The preset product parameters are used to limit the number of computing unit modules and memory pipelines required by the core of the processor, and the preset resource parameters are used to limit the cache capacity and the number of register stacks required by the control components.

7. A processor circuit generation system, characterized by, It comprises: a computing parameter obtaining module for obtaining the computing unit parameters of all computing unit modules in a processor; an input module for obtaining preset product parameters for determining the logic size of the processor; a parameter passing module for calculating the control component parameters corresponding to different control components in the processor based on the computing unit parameters according to the preset product parameters; an instantiation generation module for instantiating the control components based on the control component parameters to obtain the processor circuit corresponding to the processor; wherein, the parameter passing module is specifically used for: determining the set of control components contained in the processor according to the preset product parameters; Determine a hierarchical connection relationship between each of the control components and the rest of the control components and between each of the computing unit modules in the set of control components, taking the computing unit modules as sub-nodes, to obtain a hierarchical connection relationship list; According to the hierarchical connection relationship list, calculate the control component parameters corresponding to different control components based on the computing unit parameters.

8. A computer device, comprising: Comprise: A memory, a processor, and a processor circuit generation program stored on the memory and executable on the processor, wherein the processor implements the steps in the processor circuit generation method as claimed in any one of claims 1-6 when executing the processor circuit generation program.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium has a processor circuit generation program stored thereon, and the processor circuit generation program implements the steps in the processor circuit generation method as claimed in any one of claims 1-6 when executed by a processor.

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