Method for implementing reconfigurable nonlinear activation function by semiconductor device and application

Abstract

The application relates to the technical field of semiconductor device application, and provides a method for realizing a reconfigurable nonlinear activation function of a semiconductor device and application, which comprises the following steps: adjusting the doping degree of a channel through a local field regulation mode, so as to induce a bipolar semiconductor channel to form an in-plane p-n junction; the size and direction of the local field are adjusted, the barrier height of the in-plane p-n junction and the built-in electric field intensity are induced to change, the rectification characteristics of the bipolar semiconductor channel are further regulated to change, and the nonlinear activation function is simulated. The activation module constructed based on the method can complete the ReLU or Sigmoid nonlinear activation function at the hardware level, reduces data carrying, reduces regulation and control and the complexity of neural network deployment training, and is helpful to construct an embedded visual system with simple structure, high integration and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device application technology, and in particular to a method and application for realizing reconfigurable nonlinear activation function in a semiconductor device. Background Technology

[0002] Neural networks consist of a set of neurons connected in layers by synaptic weights. Inputs to the neural network are multiplied by their respective weights, and the computation results accumulate within the neurons. However, modern deep neural networks (DNNs) consist of hundreds of layers, and the output of each layer requires a multiplication and accumulation (MAC) result to be passed to a nonlinear activation function for computation. Memory-based computing maps these neural network operations onto an array of non-volatile memory devices, where weights are stored and weighted sums are calculated using Kirchhoff's current law. While in-memory computation allows for local storage of weights in compact and energy-efficient synaptic devices, activation function computation still relies on general-purpose processors or large and complex peripheral circuitry for neurons. Fan-in and fan-out of in-memory activations can dominate the power consumption of memory-based computing accelerators, significantly reducing the system's energy and area efficiency. Furthermore, the energy consumed to compute a single activation element using an analog-to-digital converter (ADC) is comparable to the energy consumed by the entire synaptic array for MAC operations. Since DNNs require a large number of activations to achieve high accuracy, low-power devices for implementing activation functions are essential for efficient, all-hardware implementations of deep neural networks. Implementing reconfigurable nonlinear activation (NAF) directly in physical devices presents significant challenges. Currently reported memristors, ferroelectrics, and floating-gate memories primarily focus on storage or linear computation functions, failing to achieve NAF within a single device. In recent research, only one experimental study has demonstrated ReLU (Rectified Linear Unit) activation using a Mott transistor; the lack of hardware-level reconfigurable NAF remains a key obstacle to constructing monolithic neuromorphic systems. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the related art. Therefore, this invention provides a method and application for realizing reconfigurable nonlinear activation function in a semiconductor device. The method involves adjusting the doping level of the channel through local field modulation, thereby inducing the formation of an in-plane pn junction in the bipolar semiconductor channel. By adjusting the magnitude and direction of the local field, changes in the barrier height and built-in electric field strength of the in-plane pn junction are induced, thereby controlling the rectification characteristics of the bipolar semiconductor channel and simulating the nonlinear activation function. When the barrier height of the in-plane pn junction is small, corresponding to a small built-in electric field strength, the positive voltage segment (V>0 V) of the channel output characteristic shows a near-linear change with increasing voltage. When the barrier height of the in-plane pn junction is large, corresponding to a large built-in electric field strength, the positive voltage segment (V>0 V) of the channel output characteristic shows a near-nonlinear change with increasing voltage. The linear and nonlinear changes in the positive voltage segment of the in-plane pn junction output characteristic correspond to the ReLU and Sigmoid activation functions, respectively, thus realizing reconfigurable ReLU and Sigmoid activation functions. This invention performs ReLU or Sigmoid nonlinear activation at the hardware level, reducing data handling and the complexity of control and neural network deployment and training, which helps to build a simple, highly integrated, and low-power embedded vision system.

[0004] This invention provides a method for implementing reconfigurable nonlinear activation functionality in a semiconductor device, comprising:

[0005] The doping level of the channel is adjusted by local field modulation to induce the formation of an in-plane pn junction in the bipolar semiconductor channel.

[0006] By adjusting the magnitude and direction of the local field, changes in the in-plane pn junction barrier height and built-in electric field strength are induced, thereby altering the rectification characteristics of the bipolar semiconductor channel to simulate the function of nonlinear activation.

[0007] Furthermore, the doping level of the channel is adjusted through local field modulation to induce the formation of an in-plane pn junction in the bipolar semiconductor channel, including:

[0008] By controlling the polarization states of the two sides of the two-dimensional ferroelectric layer to be oriented upward and downward, and utilizing the residual polarization retention function of the two-dimensional ferroelectric layer, ferroelectric residual polarization local fields with opposite directions are generated on the left and right sides of the two-dimensional ferroelectric layer. The ferroelectric residual polarization local fields induce the formation of an in-plane pn junction in the bipolar semiconductor channel.

[0009] Furthermore, the barrier height of the in-plane pn junction corresponds to the built-in electric field strength of the in-plane pn junction, and the positive voltage segment of the channel output characteristics tends to change linearly or nonlinearly as the voltage increases.

[0010] Furthermore, the linear change of the positive voltage segment of the output characteristic of the in-plane pn junction corresponds to the ReLU activation function, and the nonlinear change of the positive voltage segment of the output characteristic of the in-plane pn junction corresponds to the Sigmoid activation function.

[0011] Furthermore, by adjusting the amplitude of the voltage pulse to control the magnitude of the local field and by adjusting the polarity of the voltage pulse to control the direction of the local field, the barrier height of the pn junction and the magnitude of the built-in electric field can be controlled, thereby adjusting the operating range of the ReLU and Sigmoid curves, as well as the linearity and nonlinearity of the positive voltage segment of the output characteristics of the in-plane pn junction, in order to adapt to different degrees of nonlinear activation requirements.

[0012] Furthermore, as the barrier height changes from small to large, the ReLU activation function gradually transitions to the Sigmoid activation function.

[0013] An application of a semiconductor device to realize reconfigurable nonlinear activation function is disclosed. By adjusting the barrier height and built-in electric field strength of the in-plane pn junction, hardware-based reconfigurable ReLU and Sigmoid nonlinear activation functions are realized through the aforementioned method of realizing reconfigurable nonlinear activation function using a semiconductor device.

[0014] Furthermore, a single semiconductor device constitutes a nonlinear activation module.

[0015] Furthermore, the nonlinear activation module is applied to the hidden layer and output layer of the neural network, and the nonlinear activation module implements ReLU or Sigmoid nonlinear activation functions.

[0016] Furthermore, the nonlinear activation module adjusts the physical characteristics of the pn junction, regulates the pn junction barrier height and the magnitude of the built-in electric field, and precisely controls the linearity and nonlinearity of the output signal to flexibly adapt to the activation requirements of different application scenarios.

[0017] The present invention also provides a semiconductor device, and a method for implementing the reconfigurable nonlinear activation function of the semiconductor device described above, comprising:

[0018] A bottom insulating substrate is provided, on which two separate graphene electrodes are disposed. A first slit is formed between the first separate graphene electrode and the second separate graphene electrode. A first bottom parallel double grid electrode is disposed on the left end of the first separate graphene electrode, and a second bottom parallel double grid electrode is disposed on the right end of the second separate graphene electrode.

[0019] A two-dimensional ferroelectric layer covers the first and second discrete graphene electrodes. The left end of the two-dimensional ferroelectric layer does not contact the first bottom parallel double gate electrode, and the right end of the two-dimensional ferroelectric layer does not contact the second bottom parallel double gate electrode.

[0020] The split parallel double floating gate charge storage layer is disposed on the two-dimensional ferroelectric layer, and the split parallel double floating gate charge storage layer is cut to form a second slit, which is located directly above the first slit;

[0021] An upper dielectric layer is disposed on the discrete parallel double floating gate charge storage layer, and the upper dielectric layer completely covers the discrete parallel double floating gate charge storage layer and the two-dimensional ferroelectric layer;

[0022] A bipolar semiconductor channel layer is disposed on the upper dielectric layer, and the edge of the bipolar semiconductor channel layer does not extend beyond the upper dielectric layer;

[0023] The bipolar semiconductor channel layer has a source electrode at one end and a drain electrode at the other end.

[0024] Furthermore, the thickness of the first discrete graphene electrode and the second discrete graphene electrode is 2nm~7nm;

[0025] The thickness of the two-dimensional ferroelectric layer is 60nm~200nm;

[0026] The thickness of the upper dielectric layer is 10nm~20nm;

[0027] The thickness of the split parallel dual floating gate charge storage layer is 2nm~4nm;

[0028] The thickness of the bipolar semiconductor channel layer is 3nm~5nm;

[0029] The thicknesses of the first bottom parallel double gate electrode, the second bottom parallel double gate electrode, the source electrode, and the drain electrode are all 50 nm.

[0030] Furthermore, the material of the two-dimensional ferroelectric layer includes copper indium phosphorus sulfide or polyvinylidene fluoride;

[0031] The material of the split parallel dual floating gate charge storage layer is graphene;

[0032] The material of the upper dielectric layer includes any one of boron nitride, aluminum oxide, and hafnium oxide;

[0033] The material of the bipolar semiconductor channel layer includes tungsten selenide or black phosphorus;

[0034] The bottom parallel dual-gate electrode, the source electrode, and the drain electrode are made of any one or two of chromium, indium, palladium, silver, and gold.

[0035] The bottom insulating substrate is made of any one of silicon / silicon dioxide, sapphire, polyethylene terephthalate film and / or polyimide film.

[0036] Furthermore, the semiconductor device includes, but is not limited to, any one of the following: ferroelectric double floating gate device, charge direct injection mechanism double floating gate device, charge tunneling mechanism double floating gate device, ion migration mechanism double floating gate device, and atomic vacancy induced mechanism double floating gate device.

[0037] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:

[0038] This invention adjusts the doping level of the channel through local field manipulation, thereby inducing the formation of an in-plane pn junction in the bipolar semiconductor channel. By adjusting the magnitude and direction of the local field, changes in the barrier height and built-in electric field strength of the in-plane pn junction are induced, thus altering the rectification characteristics of the bipolar semiconductor channel and simulating the function of nonlinear activation. A nonlinear activation module is constructed using a single semiconductor device and applied to the activation of the hidden and output layers of a neural network. ReLU or Sigmoid nonlinear activation is performed at the hardware level. At the sensor end, this device performs nonlinear activation of the analog signal data obtained from the sensor, reducing data handling and lowering the complexity of control and neural network deployment and training. This contributes to building a simple, highly integrated, and low-power embedded vision system.

[0039] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the structure of a semiconductor device that implements a reconfigurable nonlinear activation function, as provided by the present invention.

[0042] Figure 2 This is a schematic diagram illustrating the working mechanism of a semiconductor device that enables reconfigurable nonlinear activation, as provided by the present invention.

[0043] Figure 3 This is an IV curve diagram of a semiconductor device that implements reconfigurable nonlinear activation function, as provided by the present invention.

[0044] Figure 4 This invention provides a method for implementing reconfigurable nonlinear activation functions in semiconductor devices, which is applied in convolutional neural networks.

[0045] Figure label:

[0046] 1. Bottom insulating substrate; 2. First bottom parallel dual gate electrode; 3. First discrete graphene electrode; 4. Second discrete graphene electrode; 5. Two-dimensional ferroelectric layer; 6. Discrete parallel dual floating gate charge storage layer; 7. Upper dielectric layer; 8. Bipolar semiconductor channel layer; 9. Source electrode; 10. Drain electrode; 11. Second bottom parallel dual gate electrode. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The following embodiments are used to illustrate this invention but cannot be used to limit the scope of this invention.

[0048] In the description of the embodiments of the present invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance, unless otherwise expressly specified and limited. "Above" or "below" a second feature can mean that the first and second features are in direct contact, or that they are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of a second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" a second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0050] In the following embodiments, unless otherwise specified, the experimental methods used are conventional methods, and the materials and reagents used are commercially available, unless otherwise specified, and are carried out in accordance with the techniques or conditions described in the literature in this field or in accordance with the product instructions.

[0051] The following is combined Figures 1 to 4 This invention describes a method and application for implementing reconfigurable nonlinear activation functionality in a semiconductor device.

[0052] like Figure 1 As shown, a semiconductor device for implementing reconfigurable nonlinear activation functionality includes:

[0053] Two separate graphene electrodes are disposed on the bottom insulating substrate 1. A first slit is formed between the first separate graphene electrode 3 and the second separate graphene electrode 4. A first bottom parallel double grid electrode 2 is disposed on the upper left end of the first separate graphene electrode 3, and a second bottom parallel double grid electrode 11 is disposed on the upper right end of the second separate graphene electrode 4.

[0054] Two-dimensional ferroelectric layer 5 covers the first discrete graphene electrode 3 and the second discrete graphene electrode 4. The left end of the two-dimensional ferroelectric layer 5 does not contact the first bottom parallel double gate electrode 2, and the right end of the two-dimensional ferroelectric layer 5 does not contact the second bottom parallel double gate electrode 11.

[0055] A separate parallel double floating gate charge storage layer 6 is disposed on the two-dimensional ferroelectric layer 5. The separate parallel double floating gate charge storage layer 6 is cut to form a second slit, which is located directly above the first slit.

[0056] An upper dielectric layer 7 is disposed on the split parallel double floating gate charge storage layer 6, and the upper dielectric layer 7 completely covers the split parallel double floating gate charge storage layer 6 and the two-dimensional ferroelectric layer 5.

[0057] A bipolar semiconductor channel layer 8 is disposed on the upper dielectric layer 7, and the edge of the bipolar semiconductor channel layer 8 does not extend beyond the upper dielectric layer 7.

[0058] A source electrode 9 is disposed at one end of the bipolar semiconductor channel layer 8, and a drain electrode 10 is disposed at the other end.

[0059] The thickness of the first discrete graphene electrode 3 and the second discrete graphene electrode 4 is 2nm~7nm; it can be selected as 2nm, 3nm, 5nm, or 7nm.

[0060] The thickness of the two-dimensional ferroelectric layer 5 is 60nm~200nm; it can be selected as 60nm, 100nm, 150nm, or 200nm.

[0061] The thickness of the upper dielectric layer 7 is 10nm~20nm; it can be selected as 10nm, 13nm, 16nm, or 20nm.

[0062] The thickness of the split parallel dual floating gate charge storage layer 6 is 2nm~4nm; it can be selected as 2nm, 3nm, or 4nm.

[0063] The thickness of the bipolar semiconductor channel layer 8 is 3nm~5nm; it can be selected as 3nm, 4nm, or 5nm.

[0064] The thicknesses of the first bottom parallel double gate electrode 2, the second bottom parallel double gate electrode 11, the source electrode 9, and the drain electrode 10 are all 50 nm.

[0065] The material of the two-dimensional ferroelectric layer 5 includes copper indium phosphorus sulfide (CuInP2S6) or polyvinylidene fluoride (PVDF).

[0066] The material of the split parallel dual floating gate charge storage layer 6 is graphene;

[0067] The material of the upper dielectric layer 7 includes any one of boron nitride (BN), aluminum oxide (Al2O3), and hafnium oxide (HfO2);

[0068] The material of the bipolar semiconductor channel layer 8 includes tungsten selenide (WSe2) or black phosphorus (BP).

[0069] The first bottom parallel double gate electrode 2, the second bottom parallel double gate electrode 11, the source electrode 9, and the drain electrode 10 are made of any one or two of chromium, indium, palladium, silver, and gold.

[0070] The bottom insulating substrate 1 is made of any one of silicon / silicon dioxide (Si / SiO2), sapphire, polyethylene terephthalate film (PET) and / or polyimide film (PI).

[0071] A method for fabricating a semiconductor device that realizes a reconfigurable nonlinear activation function, comprising the following steps:

[0072] S1: A first discrete graphene electrode and a second discrete graphene electrode are fabricated on a bottom insulating substrate. The first discrete graphene electrode and the second discrete graphene electrode are sequentially cut by mechanical peeling, dry transfer, fixed-point stacking and focused ion beam processing technology to form a first slit.

[0073] S2: Chromium and gold metal electrodes are deposited by photolithography and thermal evaporation through laser direct writing process. A first bottom parallel double gate electrode is prepared on the left end of the first split graphene electrode, and a second bottom parallel double gate electrode is prepared on the right end of the second split graphene electrode.

[0074] S3: Two-dimensional ferroelectric layers are prepared on the first and second split graphene electrodes sequentially using mechanical exfoliation, dry transfer and fixed-point stacking techniques.

[0075] S4: A split parallel double floating gate charge storage layer is prepared on a two-dimensional ferroelectric layer by in-situ cutting of slits using mechanical stripping, dry transfer and fixed-point stacking techniques and focused ion beam processing techniques.

[0076] S5: The upper dielectric layer is prepared on the discrete parallel double floating gate charge storage layer by mechanical stripping, dry transfer and fixed-point stacking techniques in sequence;

[0077] S6: Bipolar semiconductor channels are fabricated on the upper dielectric layer sequentially using mechanical stripping, dry transfer, and fixed-point stacking techniques;

[0078] S7: By depositing chromium and gold metal electrodes through laser direct writing lithography and thermal evaporation process, a source electrode is prepared at one end of a two-dimensional semiconductor channel and a drain electrode is prepared at the other end.

[0079] A method for implementing reconfigurable nonlinear activation functionality in a semiconductor device, comprising:

[0080] The doping level of the channel can be adjusted by local field modulation, thereby inducing the formation of an in-plane pn junction in the bipolar semiconductor channel;

[0081] By adjusting the magnitude and direction of the local field, the barrier height and built-in electric field strength of the in-plane pn junction are induced to change, thereby modulating the rectification characteristics of the bipolar semiconductor channel and simulating the function of nonlinear activation.

[0082] The barrier height of the in-plane pn junction corresponds to the built-in electric field strength of the in-plane pn junction, and the positive voltage segment of the channel output characteristics tends to change linearly or nonlinearly as the voltage increases.

[0083] When the barrier height of the in-plane pn junction is small, the built-in electric field strength of the in-plane pn junction is also small. The positive voltage segment (V>0V) of the channel output characteristics shows a near-linear change with increasing voltage.

[0084] When the barrier height of the in-plane pn junction is large, the built-in electric field strength of the in-plane pn junction is also large. The positive voltage segment (V>0 V) of the channel output characteristics shows a near nonlinear change as the voltage increases.

[0085] The linear and nonlinear changes in the positive voltage segment of the output characteristic of the in-plane pn junction can be respectively associated with the ReLU and Sigmoid activation functions, thereby realizing reconfigurable ReLU and Sigmoid activation functions.

[0086] Adjusting the doping level of the channel through local field modulation to induce the formation of an in-plane pn junction in a bipolar semiconductor channel includes:

[0087] By controlling the polarization states of the two sides of the two-dimensional ferroelectric layer to be oriented upward and downward, and utilizing the residual polarization retention function of the two-dimensional ferroelectric layer, ferroelectric residual polarization local fields with opposite directions are generated on the left and right sides of the two-dimensional ferroelectric layer. The ferroelectric residual polarization local fields induce the formation of an in-plane pn junction in the bipolar semiconductor channel.

[0088] In some specific embodiments of the present invention, paired voltage pulses of opposite polarity are applied to two discrete graphene electrodes via bottom parallel double-gate electrodes. Specifically, a -5V, 100 ns voltage pulse is applied to the first discrete graphene electrode via the first bottom parallel double-gate electrode, and a +5V, 100 ns voltage pulse is applied to the second discrete graphene electrode via the second bottom parallel double-gate electrode. The dipoles in the left and right halves of the two-dimensional ferroelectric layer exhibit upward and downward oriented polarization states, respectively, under the influence of the electrostatic field generated by the paired voltage pulses. Figure 2 As shown, Cu (copper), In (indium), P (phosphorus), and S (sulfur) form the lattice of a two-dimensional ferroelectric layer. The dipoles within the lattice rearrange, exhibiting upward and downward oriented polarization states. After the paired voltage pulse ends, due to the retention of the polarization of the two-dimensional ferroelectric layer itself, downward and upward residual polarization fields are generated on the left and right sides, respectively.

[0089] The residual polarization field induces the formation of an in-plane pn junction in the bipolar semiconductor channel. By adjusting the magnitude and direction of the residual polarization field, the barrier height and built-in electric field strength of the in-plane pn junction are induced to change, thereby modulating the rectification characteristics of the bipolar semiconductor channel and changing the linearity of the IV curve. This makes the ReLU and Sigmoid functions highly tunable, which can meet the needs of ReLU and Sigmoid activation functions in convolutional neural networks, simple neural networks and deep neural networks.

[0090] By adjusting the amplitude of the voltage pulse to control the magnitude of the local field and by adjusting the polarity of the voltage pulse to control the direction of the local field, the barrier height of the pn junction and the magnitude of the built-in electric field can be controlled. This allows for adjustment of the operating range of the ReLU and Sigmoid curves, as well as the linearity and nonlinearity of the positive voltage segment of the output characteristics of the in-plane pn junction, in order to adapt to different levels of nonlinear activation requirements.

[0091] As the barrier height changes from small to large, the ReLU activation function gradually transitions to the Sigmoid activation function. By adjusting the barrier height and built-in electric field strength of the in-plane pn junction, hardware-reconfigurable ReLU and Sigmoid nonlinear activation functions are realized.

[0092] like Figure 3 As shown, the implementation process of the activation function in this embodiment of the invention is as follows: Figure 3 As shown in Figure (a), when the junction strength of the in-plane pn junction formed by the bipolar semiconductor channel is weak, resulting in a low pn junction barrier height, the output curve exhibits strong linearity in the 0V~1V range and almost maintains the off-state current in the -1V~0V range, similar to the ReLU activation function output curve. Figure 3 As shown in Figure (b), when the junction strength of the pn junction is strong, the barrier height of the pn junction will increase, and the output curve will show weak linearity in the 0V~1V range. By setting the compliant current in the 0V~1V range, the output curve can be made similar to the output curve of the Sigmoid activation function.

[0093] This similarity to the output curves of ReLU and Sigmoid activation functions gives it the potential for direct activation in hardware applications. Specifically, after the front-end in-memory computing device or sensor identifies and preprocesses the stimulus signal, it is input as a voltage signal to this ReLU-type nonlinear activation device. Negative voltage signals are cut off, while positive voltage signals are retained, thus achieving the ReLU activation effect and introducing nonlinearity into the neural network. Furthermore, at the back end of the in-memory computing device, the output voltage signal is used as the input signal to this Sigmoid-type nonlinear activation device, causing the output signal to approach two extreme values, thus achieving the Sigmoid activation effect, which is helpful for classification tasks.

[0094] Therefore, the semiconductor device of the present invention can integrate ReLU and Sigmoid functions on a single device. The above-mentioned ReLU and Sigmoid nonlinear activation can be completed simply by inputting the voltage signal to be processed at the device input terminal, which helps to simplify circuit configuration and fills the gap in ReLU and Sigmoid activation that relies on computers.

[0095] An application of a semiconductor device to implement reconfigurable nonlinear activation function is disclosed. The method of implementing reconfigurable nonlinear activation function using a semiconductor device is described. A single semiconductor device constitutes a nonlinear activation module, which is applied to the activation of the hidden layer and output layer of a convolutional neural network. The nonlinear activation module implements the ReLU activation function and the Sigmoid activation function.

[0096] The nonlinear activation module adjusts the physical characteristics of the pn junction, regulates the pn junction barrier height and the magnitude of the built-in electric field, and precisely controls the linearity and nonlinearity of the output signal to flexibly adapt to the activation requirements of different application scenarios.

[0097] To verify the practicality and applicability of this invention, a convolutional neural network (CNN) hardware was constructed using ferroelectric double-floating gate devices to realize the recognition and classification of handwritten digits. The CNN network consists of convolutional layers, fully connected layers, and an output layer. Ferroelectric double-floating gate devices are used for activation of the hidden layers and the output layer, respectively performing ReLU and Sigmoid activation.

[0098] Specifically, such as Figure 4 As shown, a 28×28 pixel handwritten digit image is input into three 3×3 convolutional kernels for convolution operations. Then, it is fed into a 3×1 array for ReLU activation. The activated image is a 3-channel, 26×26 pixel image. The activation result is then input into a fully connected layer for computation, resulting in a 1×10 matrix. Finally, a sigmoid activation is applied for binary classification, yielding the output corresponding to the input image, thus achieving image classification.

[0099] like Figure 4 The effects of hardware ReLU activation and software ReLU activation are basically the same, as are the effects of hardware Sigmoid activation and software Sigmoid activation.

[0100] This invention adjusts the doping level of the channel through local field manipulation, thereby inducing the formation of an in-plane pn junction in the bipolar semiconductor channel. By adjusting the magnitude and direction of the local field, changes in the barrier height and built-in electric field strength of the in-plane pn junction are induced, thus altering the rectification characteristics of the bipolar semiconductor channel. The linear and nonlinear changes in the positive voltage segment of the in-plane pn junction output characteristics correspond to ReLU and Sigmoid activation functions, respectively, thereby achieving reconfigurable ReLU and Sigmoid activation functions. A nonlinear activation module is constructed using a single semiconductor device and applied to the activation of the hidden and output layers of a neural network. ReLU or Sigmoid nonlinear activation functions are performed at the hardware level. At the sensor end, this device performs nonlinear activation of the analog signal data obtained from the sensor, reducing data handling and lowering the complexity of control and neural network deployment and training. This contributes to building a simple, highly integrated, and low-power embedded vision system.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for implementing reconfigurable nonlinear activation functionality in a semiconductor device, characterized in that, include: The doping level of the channel is adjusted by local field modulation to induce the formation of an in-plane pn junction in the bipolar semiconductor channel. By adjusting the magnitude and direction of the local field, the barrier height and built-in electric field strength of the in-plane pn junction are induced to change, thereby controlling the rectification characteristics of the bipolar semiconductor channel to simulate the function of nonlinear activation. The linear change of the positive voltage segment of the output characteristic of the in-plane pn junction corresponds to the ReLU activation function, and the nonlinear change of the positive voltage segment of the output characteristic of the in-plane pn junction corresponds to the Sigmoid activation function. By adjusting the amplitude of the voltage pulse to control the magnitude of the local field and by adjusting the polarity of the voltage pulse to control the direction of the local field, the barrier height of the pn junction and the magnitude of the built-in electric field can be controlled. This allows for adjustment of the operating range of the ReLU and Sigmoid curves, as well as the linearity and nonlinearity of the positive voltage segment of the output characteristics of the in-plane pn junction, in order to adapt to different levels of nonlinear activation requirements.

2. The method for implementing reconfigurable nonlinear activation function in a semiconductor device according to claim 1, characterized in that, By controlling the polarization states of the two sides of the two-dimensional ferroelectric layer to be oriented upward and downward, and utilizing the residual polarization retention function of the two-dimensional ferroelectric layer, ferroelectric residual polarization local fields with opposite directions are generated on the left and right sides of the two-dimensional ferroelectric layer. The ferroelectric residual polarization local fields induce the formation of an in-plane pn junction in the bipolar semiconductor channel.

3. The method for implementing reconfigurable nonlinear activation function in a semiconductor device according to claim 1, characterized in that, The barrier height of the in-plane pn junction corresponds to the built-in electric field strength of the in-plane pn junction, and the positive voltage segment of the channel output characteristics tends to change linearly or nonlinearly as the voltage increases.

4. The method for implementing reconfigurable nonlinear activation function in a semiconductor device according to claim 1, characterized in that, As the barrier height changes from small to large, the ReLU activation function gradually transitions to the Sigmoid activation function.

5. An application of a semiconductor device to implement a reconfigurable nonlinear activation function, implemented by a method for implementing a reconfigurable nonlinear activation function using a semiconductor device as described in any one of claims 1 to 4, characterized in that, By adjusting the barrier height and built-in electric field strength of the in-plane pn junction, hardware-reconfigurable ReLU and Sigmoid nonlinear activation functions are achieved.

6. The application of a semiconductor device according to claim 5 to realize a reconfigurable nonlinear activation function, characterized in that, A single semiconductor device constitutes a nonlinear activation module.

7. The application of a semiconductor device according to claim 6 to realize a reconfigurable nonlinear activation function, characterized in that, The nonlinear activation module is applied to the hidden layer and output layer of the neural network, and the nonlinear activation module implements ReLU or Sigmoid nonlinear activation functions.

8. The application of a semiconductor device according to claim 6 to realize a reconfigurable nonlinear activation function, characterized in that, The nonlinear activation module adjusts the physical characteristics of the pn junction, regulates the pn junction barrier height and the magnitude of the built-in electric field, and precisely controls the linearity and nonlinearity of the output signal to flexibly adapt to the activation requirements of different application scenarios.

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