Digital in-memory computing architecture compiling and simulating method and tool chain

Abstract

The invention discloses a digital in-memory computing architecture compiling and simulating method and a tool chain, and belongs to the technical field of in-memory computing. The method comprises the following steps: acquiring a target deep neural network model and a target in-memory computing architecture configuration parameter adapted to the target deep neural network model, the target in-memory computing architecture configuration parameters comprise at least one of the following parameters: the number of cores, the on-chip communication bandwidth between the cores, the size, the number and the bit width of a storage unit of each core, and the scale of a computing unit of each core; configuring a digital in-memory computing accelerator according to the target in-memory computing architecture configuration parameters; compiling the target deep neural network model into a target optimization instruction sequence based on a digital in-memory calculation accelerator; simulating and executing the target optimization instruction sequence, and performing performance evaluation according to performance indexes in the process of executing the target optimization instruction sequence.

Description

Technical Field

[0001] This application relates to the field of in-memory computing technology, and in particular to a method and toolchain for compiling and simulating digital in-memory computing architectures. Background Technology

[0002] In recent years, with the widespread application of deep neural networks (DNNs) in fields such as computer vision and natural language processing, the scale and complexity of models have been continuously increasing, posing unprecedented challenges to the performance and efficiency of computing platforms. Because the computation of deep learning models involves the frequent flow of large amounts of data between computing and storage units, the traditional von Neumann architecture often encounters severe "memory wall" and "power wall" problems when handling related operations, falling far short of meeting the urgent demands of artificial intelligence technology for computing power and efficiency.

[0003] Compute-in-Memory (CIM), as an emerging computing paradigm, effectively reduces data movement and significantly improves system performance and energy efficiency by performing computations directly within storage units. CIM architectures can be broadly categorized into analog CIM and digital CIM. Analog CIM accelerators utilize the physical characteristics of storage devices to perform multiplication and addition operations directly in the current and voltage domains. While offering high energy efficiency, their accuracy is limited and they are susceptible to variations in manufacturing processes and the environment. Digital CIM accelerators, on the other hand, embed digital logic circuits within storage units, implementing computational functions through bit-level operations. This results in better computational accuracy and stability, making them more suitable for applications with high precision requirements.

[0004] In-memory computing architecture compilation and simulation toolchains are tools for understanding the circuit behavior within in-memory computing architecture chips. While existing toolchains can perform hardware simulation, performance evaluation, energy efficiency analysis, algorithm verification, parametric simulation, and custom hardware configuration, the hardware performance of the in-memory computing architecture and the deployment of software algorithms on the in-memory computing system are separated during simulation, leading to a lack of realism in the simulation results. Existing in-memory computing architecture compilation and simulation toolchains suffer from limited configurability, can only simulate limited use cases, struggle to handle complex DNNs, and produce inaccurate simulation results. Summary of the Invention

[0005] This application provides a method and toolchain for compiling and simulating digital in-memory computing architectures, which can solve the problems of existing in-memory computing architecture compilation and simulation toolchains having limited configurable items, being able to simulate only limited use cases, being unable to cope with complex DNNs, and having inaccurate simulation results.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows: In a first aspect, a method for compiling and simulating a digital in-memory computing architecture is provided, comprising: acquiring a target deep neural network model and target in-memory computing architecture configuration parameters adapted to the target neural network model, wherein the target in-memory computing architecture configuration parameters include at least one of the following: the number of cores, the on-chip communication bandwidth between cores, the size, quantity, and bit width of the memory units of each core, and the scale of the computing units of each core; configuring a digital in-memory computing accelerator according to the target in-memory computing architecture configuration parameters; compiling the target deep neural network model into a target optimized instruction sequence based on the digital in-memory computing accelerator; simulating the execution of the target optimized instruction sequence, and performing performance evaluation based on performance indicators during the execution of the target optimized instruction sequence.

[0007] Secondly, a digital in-memory computing architecture compilation and simulation toolchain is provided, comprising: an acquisition module for acquiring a target deep neural network model and target in-memory computing architecture configuration parameters adapted to the target neural network model, wherein the target in-memory computing architecture configuration parameters include at least one of the following: the number of cores, the on-chip communication bandwidth between cores, the size, quantity, and bit width of the storage unit of each core, the size of the storage unit of each core, and the scale of the computing unit; a configuration module for configuring a digital in-memory computing accelerator according to the target in-memory computing architecture configuration parameters; a compiler for compiling the target deep neural network model into a target optimized instruction sequence based on the digital in-memory computing accelerator; and a simulator for simulating the execution of the target optimized instruction sequence and performing performance evaluation based on performance indicators during the execution of the target optimized instruction sequence.

[0008] This application provides a method and toolchain for compiling and simulating a digital in-memory computing architecture. Based on the hierarchical hardware structure of the hardware modules of a digital in-memory computing accelerator and a unified instruction set, it utilizes computation graph-level optimization and operator-level optimization to compile user-input deep neural network models into a target-optimized instruction sequence suitable for execution by the digital in-memory computing architecture. This expands the configurable items of the in-memory computing architecture compilation and simulation toolchain, enabling the simulation of more usage scenarios and simplifying complex DNNs, thereby improving the accuracy of simulation results. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0010] Figure 1 A flowchart illustrating a compilation and simulation method for a digital in-memory computing architecture provided in an exemplary embodiment of this application is shown. Figure 2This invention provides a schematic diagram of the structure of a chip-level module for a digital in-memory computing accelerator according to an exemplary embodiment of the present application. Figure 3 This invention provides a schematic diagram of the core module of a digital in-memory computing accelerator according to an exemplary embodiment of the present application. Figure 4 This invention provides a schematic diagram of the structure of a unit-level module of a digital in-memory computing accelerator according to an exemplary embodiment of the present application. Figure 5 A flowchart illustrating a compilation and simulation method for a digital in-memory computing architecture provided in an exemplary embodiment of this application is shown. Figure 6 A flowchart illustrating a compilation and simulation method for a digital in-memory computing architecture provided in an exemplary embodiment of this application is shown. Figure 7 This invention illustrates a structural block diagram of an in-memory computing architecture compilation and simulation toolchain provided in an exemplary embodiment of this application; Figure 8 A structural block diagram of an electronic device provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0011] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0012] To address the limitations of existing in-memory computing architecture compilation and simulation toolchains, such as limited configurable options, the ability to simulate only a limited number of use cases, difficulty in handling complex DNNs, and inaccurate simulation results, this application provides a digital in-memory computing architecture compilation and simulation method and an in-memory computing architecture compilation and simulation toolchain.

[0013] The core idea of ​​this application is to use a standard interface for software and hardware interaction based on digital in-memory computing accelerators, including chip-level abstraction, core-level abstraction, unit-level abstraction and instruction design, to compile the input target deep neural network model into an executable target optimized instruction sequence, thereby simplifying complex deep neural networks and solving the problems of limited configurable items, limited simulation scenarios, and inaccurate simulation results in existing in-memory computing architecture compilation and simulation toolchains.

[0014] First, the terms used in this application will be explained.

[0015] Deep Neural Networks (DNNs) are a type of artificial neural network with a multi-layered structure. They use deep, non-linear transformations to progressively abstract and represent input data, enabling the learning and recognition of complex patterns. DNNs have achieved significant success in fields such as computer vision and natural language processing. However, their complex structure and massive number of parameters also bring huge computational and storage requirements, making them one of the main application scenarios for in-memory computing technology.

[0016] Compute-In-Memory (CIM): CIM is a novel computing paradigm that reduces or eliminates latency and energy consumption caused by frequent data movement between the processor and memory in traditional von Neumann architectures by performing computational operations directly within memory cells. This technology is particularly well-suited for data-intensive applications such as deep neural networks, effectively overcoming the "memory wall" and "power wall" problems.

[0017] Digital in-memory computing architecture: Digital in-memory computing architecture is an implementation of in-memory computing. It achieves digital computing functions within the storage cells of Static Random Access Memory (SRAM). Compared to analog in-memory computing, digital in-memory computing offers higher computational accuracy and stability, making it more suitable for applications with high precision requirements.

[0018] Analog in-memory computing architecture: Analog in-memory computing architecture is an in-memory computing scheme implemented in the analog domain (such as the current, voltage, or time domain). It directly performs analog multiplication and addition operations by utilizing the physical characteristics of the storage medium (such as impedance, conductance, etc.) to replace traditional digital operations, thereby improving energy efficiency. However, its accuracy is usually affected by material properties and environmental factors.

[0019] Static Random Access Memory (SRAM): SRAM is a common semiconductor memory that uses bistable circuitry (typically six transistors) to store each bit. As long as power is maintained, the data remains unchanged without the need for refresh operations. SRAM is relatively mature in integrated circuit technology, has high integration density, and fast read / write speeds, but its bit density is relatively low, resulting in higher cost per unit area compared to other storage media such as DRAM.

[0020] In-memory compute macrocells (CIM Macros): In-memory compute macrocells are the basic building blocks of in-memory compute architectures, typically consisting of a memory array (such as SRAM) and dedicated compute logic. Multiple macrocells can be combined and configured into larger-scale in-memory compute units or architectures, effectively solving the "memory wall" problem in traditional compute architectures.

[0021] Computation graph: A directed graph structure that represents the computation process of a deep learning model. Nodes represent computational operations, and edges represent data flow relationships. It is an important intermediate representation in the deep learning compilation process.

[0022] Deep learning compilation: The process of compiling high-level neural network models into a sequence of low-level instructions that can be executed efficiently on the target hardware architecture. It includes key steps such as computation graph optimization, operator mapping, and resource allocation, and serves as a bridge connecting application development and hardware execution.

[0023] Architecture simulation: A technique that simulates the behavior of hardware architecture through software. It is used to evaluate the performance, power consumption and resource utilization of in-memory computing architecture, and supports design space exploration and performance prediction before actual hardware implementation.

[0024] Full-stack toolchain: A full-stack toolchain refers to a complete collection of software tools covering everything from application development to hardware implementation, including compilers, simulators, performance analysis tools, etc. In the field of in-memory computing, the full-stack toolchain is responsible for mapping high-level neural network models to low-level in-memory computing hardware architectures, enabling software and hardware co-optimization, and improving the overall system performance and efficiency.

[0025] Instruction Set Architecture (ISA): An instruction set architecture is a specification that defines how a processor executes instructions, including instruction format, opcode, and addressing mode. For in-memory computing architectures, dedicated instruction set designs can fully leverage their unique hardware capabilities to improve computational efficiency. General-purpose and scalable instruction set architecture designs can support different types of in-memory computing hardware platforms and diverse computing tasks.

[0026] Matrix-Vector Multiplication (MVM): Matrix-vector multiplication is one of the core computational operations in deep neural networks, especially prevalent in convolutional neural networks and fully connected layers. In in-memory computing architectures, MVM operations can be efficiently executed directly within memory units without moving data out to separate computation units, thus significantly improving computational efficiency and energy efficiency.

[0027] MLIR (Multi-Level Intermediate Representation): A compiler infrastructure designed to support cross-platform, multi-domain, and deep learning-specific optimizations for general intermediate representations (IRs). Its goal is to provide a flexible and scalable framework that allows developers to build high-performance computing libraries, particularly well-suited for machine learning and artificial intelligence applications.

[0028] Intermediate Representation (IR) is an abstract representation used between the source language and the target machine code during the compilation process. Similar to translating an article, the original text is first converted into a general intermediate form, and then translated from this intermediate form into the target language. This reduces the complexity of the compilation process and improves the maintainability and portability of the compiler.

[0029] Figure 1 A flowchart illustrating a method for compiling and simulating a digital in-memory computing architecture, as shown in an exemplary embodiment of this application, is provided. This method can be executed by a digital in-memory computing architecture compilation and simulation toolchain. Figure 1 As shown, the compilation and simulation method of this digital in-memory computing architecture mainly includes the following steps (S101-S104): S101. Obtain the target deep neural network model and the target in-memory computing architecture configuration parameters adapted to the target neural network model, wherein the target in-memory computing architecture configuration parameters include at least one of the following: the number of cores, the on-chip communication bandwidth between cores, the size, number and bit width of the storage unit of each core, and the scale of the computing unit of each core. In this embodiment, as an optional approach, the target deep neural network module includes one of the following: Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), and Long Short-Term Memory (LSTM). CNN is specifically designed for processing data with a grid structure (such as images and audio). RNN is mainly used for processing sequential data, such as text and speech. LSTM is a special RNN architecture that solves the problem of traditional RNNs' difficulty in handling long sequence dependencies through a gating mechanism.

[0030] The target in-memory computing architecture configuration parameters are obtained by analyzing the target deep neural network model. Using these parameters, the hardware modules of the digital in-memory computing accelerator are configured in step S102. Based on the hierarchical hardware structure of the accelerator's hardware modules, the configurable items of the in-memory computing architecture compilation and simulation toolchain are expanded, enabling the simulation of more usage scenarios, simplifying complex DNNs, and improving the accuracy of simulation results.

[0031] S102. Configure the digital in-memory computing accelerator according to the target in-memory computing architecture configuration parameters; In this embodiment, the digital in-memory computing accelerator serves as a bridge connecting the compiler and simulator in the in-memory computing architecture compilation and simulation toolchain. It defines a standard interface for software and hardware interaction. The digital in-memory computing accelerator includes a hardware module and an instruction set adapted to the hardware module. Based on the hardware structure of the digital in-memory computing accelerator package and the adapted instruction set, the compiler can map the upper-layer target deep neural network model to the lower-layer instructions to be executed. The simulator simulates the execution of the instructions to be executed, thereby mapping the complex deep neural network model to the lower-layer target optimized instruction sequence.

[0032] The hardware modules and instruction set of the digital in-memory computing accelerator are described in detail below.

[0033] In this embodiment, the hardware module of the digital in-memory computing accelerator adopts a three-level module structure, including: chip-level modules, core-level modules, and unit-level modules. Chip-level modules define on-chip resources and configuration parameters, such as... Figure 2 As shown, the chip-level module includes: multiple cores connected via an on-chip network and a global storage unit, supporting synchronous communication between cores and global memory access. The cores are composed of core-level modules. The core-level modules define the organization of hardware resources, such as... Figure 3 As shown, the core-level modules include: instruction memory, various computing units, register file, and local memory. To achieve efficient memory management and architectural scalability, in this embodiment, instructions access hardware resources in the digital in-memory computing accelerator through virtual addresses. Specifically, all addressable storage resources in the digital in-memory computing accelerator are mapped to the same contiguous virtual address space, and a preset address mapping mechanism converts the virtual address in the instruction into the physical address of the hardware resource in the digital in-memory computing accelerator. This virtual address mapping method achieves a unified address space across global and local memory. Furthermore, the address space of the local memory is divided into multiple segments to efficiently process the input and output data of the DNN layer. The register file consists of general-purpose registers for instruction-level access and special-purpose registers for specific operational functions. Computation units are composed of unit-level modules. Unit-level modules define the functional information of the computing unit. For example... Figure 4 As shown, the unit-level modules include: in-memory computation units, vector computation units, and scalar computation units. The in-memory computation unit contains multiple macrogroups (MGs), supporting weight replication and flexible spatial mapping strategies. Within each macrogroup, weights are typically organized along the output channel, enabling efficient broadcasting of input data between macrogroups for parallel in-memory MVM operations. The vector computation unit handles DNN operations such as activation functions, pooling, and quantization. The scalar computation unit performs control flow operations through scalar arithmetic calculations.

[0034] In this embodiment, the instruction set of the digital in-memory computing accelerator provides a dedicated instruction set for in-memory computing characteristics. The instruction set adopts a unified 32-bit instruction format and provides dedicated instruction designs for different operation types. Instructions can be divided into several categories: computation instructions, communication instructions, and control flow instructions. Among them, computation instructions are further subdivided into in-memory computing instructions, vector computing instructions, and scalar computing instructions. Each instruction contains a 6-bit opcode and several 5-bit operand fields. Some instruction types may also include supplementary fields such as a 6-bit function specifier, execution flags, or 10-bit or 16-bit immediate values. Depending on the operation type, the instruction format supports up to four operands, providing flexibility for complex operations while maintaining coding efficiency.

[0035] The digital in-memory computing accelerator in this embodiment can adapt to different types of digital in-memory computing architecture configurations. Based on the target in-memory computing architecture configuration parameters obtained in step S101, the hardware structure of the digital in-memory computing accelerator is configured; for example, the number of cores included in the chip-level module is configured according to the number of cores. Figure 2 As shown, this chip-level module includes 16 cores. Furthermore, the appropriate instruction memory, register file, and local memory are selected based on the size of the memory units, and various computing units are configured according to the scale of the computing units. Thus, the hierarchical hardware structure of the hardware module based on the digital in-memory computing accelerator expands the configurable items of the in-memory computing architecture compilation and simulation toolchain, enabling the simulation of more usage scenarios, simplifying complex DNNs, and improving the accuracy of simulation results.

[0036] S103. Compile the target deep neural network model into a target-optimized instruction sequence based on a digital in-memory computing accelerator; In this embodiment, the compiler is responsible for compiling the user-input deep neural network model into a target optimized instruction sequence suitable for execution by a digital in-memory computing accelerator. Specifically, this includes two key stages: computation graph-level optimization and operator-level optimization.

[0037] As an optional implementation method in the embodiments of this application, the implementation method of step S103 will be described below.

[0038] like Figure 5 As shown, in another method for compiling and simulating a digital in-memory computing architecture provided by this embodiment of the invention, compiling the target deep neural network model into a target optimized instruction sequence based on a digital in-memory computing accelerator may specifically include the following steps: S201. Based on the computation graph optimization strategy, compile the target deep neural network model into a core-level intermediate representation suitable for the core-level module; S202. Perform operator-level optimization on the core-level intermediate representation according to the operator optimization strategy to generate a target optimized instruction sequence that conforms to the instruction set.

[0039] In this embodiment, step S201 is the computation graph-level optimization stage, and step S202 is the operator-level optimization stage. Computation graph-level optimization processes the computation graph of the entire target deep neural network model from a macroscopic perspective, including computation graph analysis, segmentation, and inter-core scheduling, adapting the model as a whole to the underlying in-memory computing architecture. Operator-level optimization, based on computation graph-level optimization, focuses on individual operators at the microscopic level, further optimizing the computation process of operators to better execute them at the unit-level module level. In this embodiment, computation graph-level optimization provides the overall framework and task allocation for operator-level optimization. For example, computation graph-level optimization determines the task modules executed on different cores, while operator-level optimization performs fine-grained mapping and instruction generation for the specific operators allocated to the cores.

[0040] As an optional implementation method in the embodiments of this application, the implementation method of step S201 will be described below.

[0041] like Figure 6 As shown, in another method for compiling and simulating a digital in-memory computing architecture provided by this embodiment of the invention, the target deep neural network model is compiled into a core-level intermediate representation suitable for core-level modules according to a computation graph optimization strategy. Specifically, this may include the following steps (S301-S304): S301. Parse the file of the target deep neural network model and generate the target computation graph; In this embodiment, an ONNX format DNN model file is received as input data, the model structure and parameters are parsed, and the target computation graph is constructed. This step completes the model format conversion and basic semantic understanding, preparing for subsequent analysis.

[0042] For example, a ResNet-50 model for image classification is stored in ONNX format. The parsing process identifies different types of layers in the model, such as convolutional layers, pooling layers, and fully connected layers, as well as the parameters of each layer, such as kernel size and stride. This information is then organized into an initial form of a directed acyclic graph (DAG), i.e., generating the target computation graph.

[0043] S302. Reorder the operators in the target computation graph according to the operator dependencies in the target computation graph to generate a linear operator sequence; In this embodiment, the target computation graph constructed from the input DNN model includes operation nodes such as convolution (Conv) and activation functions (ReLU), i.e., operators. Each operator has dependencies on the others. For example, in the ResNet-50 model, the output of a convolutional layer is often the input to a subsequent pooling or activation layer. Analysis can determine the order and dependencies between these layers. Furthermore, it can identify which layers can be executed in parallel, such as convolution operations in different branches. Based on these operator dependencies in the target computation graph, the operators are then reordered to generate a linear operator sequence.

[0044] As an optional implementation method in this embodiment, the operators in the target computation graph are reordered according to the operator dependencies in the target computation graph to generate a linear operator sequence, including: extracting MVM-based operators in the target computation graph; grouping and merging the MVM-based operators with adjacent auxiliary operators as target operators, and rearranging the target operators according to the operator dependencies to generate a linear operator sequence.

[0045] MVM-based operators account for a major portion of the computation in neural networks and are the core of in-memory computation optimization. Therefore, in this embodiment, it is preferable to identify and extract MVM-based operators in the target computation graph as the main target for in-memory computation acceleration. By extracting these MVM-based operators, specific optimizations can be performed on them to improve computational efficiency. For example, in the grouped ResNet-50 computation graph, according to the dependencies between operators, each operator group and individual operator is arranged into a linear sequence. For example, the operators of the input layer are executed first, and then the operator groups composed of each convolutional layer and pooling layer are executed sequentially.

[0046] In this embodiment, adjacent auxiliary operators (such as activation functions, normalization, etc.) are grouped and merged with MVM-based operators, which can reduce the number of processing nodes, further simplify the structure of the target computation graph, and maintain functional integrity.

[0047] S303. Use dynamic programming partitioning algorithm to divide the linear operator sequence into multiple partitions, and map the multiple partitions to different cores; In this embodiment, by identifying all dependent closures in the simplified target computation graph and encoding them into bitmasks, the dependent closures are used as partitioning units for dynamic partitioning and as input to the dynamic programming partitioning algorithm. Each dependent closure represents a set of self-contained operators, whose dependencies are completely enclosed within the set.

[0048] In this embodiment, a dynamic programming partitioning algorithm is executed, which recursively constructs the optimal partitioning scheme. A detailed cost evaluation is performed on each candidate partition (the aforementioned dependency closure), including computational cost, memory usage, and data transfer overhead. The partition quality is determined by considering multiple factors, and the evaluation results are fed back, thereby recursively determining the optimal partitioning scheme.

[0049] For example, for linear sequences and dependency closures in ResNet-50, the dynamic programming partitioning algorithm considers factors such as the computational cost and memory usage of each dependency closure and recursively searches for the optimal partitioning method so that each partition has the highest execution efficiency on different computing cores.

[0050] S304. Schedule partitions between different cores, exchange data through global storage, and generate corresponding partitions for each core. The intermediate representation information sequence is adapted to the core-level module of the digital in-memory computing accelerator. The core-level intermediate representation includes: intermediate representation information sequences corresponding to multiple cores.

[0051] In this embodiment, a core mapping strategy is designed for each partition to determine how to allocate workloads among available computing cores, balancing computational parallelism and communication overhead. For example, in an in-memory computing architecture with multiple computing cores, the partitioning scheme for ResNet-50 assigns different partitions to different cores. For instance, partitions with high computational demands are assigned to multiple cores to collaboratively execute computational tasks.

[0052] As an optional implementation in this embodiment, the core mapping strategy further includes: cross-core replication operator weights. In this embodiment, since the same weight needs to be calculated with several inputs, cross-core replication operator weights allow these calculations to be executed in parallel, thereby improving the parallelism of the computation.

[0053] As an optional implementation method in this embodiment, the core mapping strategy further includes: planning the data transmission paths and timings between the cores. In this embodiment, an inter-core data transmission plan can also be designed, which orchestrates data movement paths and timings through on-chip network interconnection, thereby minimizing communication latency and power consumption.

[0054] As an optional implementation in this embodiment, the core mapping strategy further includes: coordinating the parallel execution strategy among multiple cores, with each core executing according to a pipelined execution mode. The pipelined execution mode includes: instruction fetch (IF), instruction decode (ID), and instruction execute (IE) stages. The parallel execution strategy among multiple cores enables parallel computation and communication between them, improving the overall system throughput.

[0055] Finally, an optimized computation sequence is generated for each computational core, containing complete partitioning and mapping information, and a structured intermediate representation is created as input for operator-level optimization. The intermediate representation sequence for each core contains detailed computation steps and data transmission instructions generated based on the partitioning, mapping, and core mapping strategies described in the preceding steps.

[0056] In this embodiment, the core of computation graph-level optimization lies in effectively dividing and scheduling large-scale neural network models onto distributed in-memory computing cores for execution, thereby solving the hardware capacity constraint problem of digital in-memory computing accelerators.

[0057] As an optional implementation method in the embodiments of this application, the implementation method of step S202 will be described below.

[0058] like Figure 6 As shown, in another method for compiling and simulating a digital in-memory computing architecture provided by this embodiment of the invention, a compiler optimization process is provided. Operator-level optimization is performed on the core-level intermediate representation according to the operator optimization strategy to generate a target optimized instruction sequence that conforms to the instruction set. Specifically, this may include the following steps (S401-S405): S401. Obtain the operator description information and core module parameter information of the target operator based on the core-level intermediate representation. The operator description information includes: weight dimension, input feature dimension, and loop structure corresponding to the weight dimension and input feature dimension. In this embodiment, the intermediate representation information sequence of the computation graph-level optimization output is used as the input to the operator-level optimization. A detailed dimensional structure analysis is performed on each operator in the computation graph-level optimization output to identify its nested loop pattern, weight dimensions, data dependencies, and computational characteristics.

[0059] For example, for a convolution operator, we analyze information such as the size of its input feature map, the size of the convolution kernel, and the stride. Taking a... Convolution kernel acts on Taking the input feature map as an example, determining its nested loops may involve traversing the rows, columns, and elements of the convolution kernel of the input feature map.

[0060] S402. Match the weight dimensions with the dimensions of the hardware modules to establish a virtual mapping; During the virtual mapping phase, the compiler first establishes an initial mapping scheme in an ideal environment that does not consider physical resource constraints. This abstraction allows the compiler to explore a wider optimization space and find the theoretically optimal solution.

[0061] For example, based on the dimensional structure analysis results of the operators, the operations of the operators are mapped to a virtual computational space. For example, the dimensions of a hardware module are... This maps the computation of the convolution operator to a two-dimensional virtual matrix multiplication space. .

[0062] S403. Based on virtual mapping, the loop structure is correlated with the dimensions of the hardware module. The loop structure is split and rearranged according to the resource capacity constraints of the hardware module to obtain intermediate representation optimization information for the target operator and the hardware module. The intermediate representation optimization information includes: splitting dimension and memory access operation annotation. In this embodiment, the resource capacity constraints of the hardware module include macrocell size, available storage, and the number of computing units. To ensure that the mapping scheme can be effectively executed on the actual hardware, the loop structure is segmented in this embodiment. Loop segmentation involves dividing a large loop structure into multiple smaller loops according to preset rules. In operator-level optimization, based on the resource capacity constraints of the hardware module, the originally continuously executed loop operations are separated, thereby allowing the loop iteration to better adapt to hardware resources and improve execution efficiency. For example, when the hardware has multiple storage levels, loop segmentation ensures that the data accessed in each loop can be hit in fast storage (such as cache) as much as possible, reducing the overhead of reading data from slow storage (such as main memory). The compiler calculates the optimal segmentation method to ensure that it can be efficiently mapped to hardware resources.

[0063] Before segmenting the loop structure, the method provided in this application embodiment further includes: analyzing redundant calculations and unnecessary nesting in the loop structure, merging and simplifying them, corresponding the loop structure to the dimensions of the hardware module, and preparing for efficient mapping to the hardware module of the digital in-memory computing accelerator. The in-memory computing array has its specific computing mode, and simplifying the loop structure can better utilize hardware resources.

[0064] In practical implementation, aligning the loop structure with the dimensions of the hardware modules includes: adjusting the weight dimensions at the software level (such as input / output channels, convolution kernel size, etc.) according to the physical structure of the CIM array. For example, adjusting the weights of the three-dimensional convolution kernels in the software according to the two-dimensional structure of the CIM array. The storage method is rearranged. Specifically, the organization of weighted data includes techniques such as image-to-column transformation (im2col) to adapt to the computation mode of the in-memory computing array. The correspondence between the algorithm description and the hardware architecture is a key step in efficient hardware execution; only with dimensional alignment can the correct execution of the software algorithm on the hardware be ensured. Furthermore, in the physical mapping phase, the idealized virtual mapping scheme is combined with the resource capacity constraints of the actual hardware modules, and the mapping strategy is gradually adjusted through a series of optimization processes implemented by the MLIR infrastructure.

[0065] Loop rearrangement changes the execution order of loops. In code, the execution order of loops affects data access patterns and computational locality. By rearranging the nesting or iteration order of loops, the order in which data is accessed in memory can be optimized, making the data accessed by adjacent loop iterations more contiguous in memory. This improves cache hit rate, reduces memory access latency, and enhances program efficiency.

[0066] As an optional implementation method in this embodiment, the loop structure is segmented and rearranged according to the resource capacity constraints of the hardware module to obtain intermediate representation optimization information that adapts the target operator to the hardware module. This includes: segmenting the loop structure into multiple sub-loops according to the resource capacity constraints of the hardware module to obtain the segmentation dimension; rearranging the nesting order in the loop structure according to the data dependencies in the loop structure; and inserting memory access operations at preset positions in the loop structure to obtain memory access operation annotations.

[0067] Specifically, MVM operations are identified and extracted from the loop structure. MVM operations are the core computing mode of the CIM architecture and will be converted into dedicated CIM instructions in the future.

[0068] In this embodiment, the nesting order of loops is adjusted by analyzing data dependencies and memory access patterns within the loop structure. For example, in a double-nested loop, if the inner loop accesses data more frequently, it can be placed in the outer loop to reduce the number of data loads. The optimal loop nesting order is determined to maximize computational efficiency and data reuse. This step improves computational density while respecting the resource limitations of each memory level through automated analysis.

[0069] In this embodiment, memory access operations are inserted at predetermined positions within the loop structure. Obtaining memory access operation annotations includes analyzing data access patterns within the loop structure and inserting memory access instructions at appropriate locations. For example, data is pre-loaded into the cache before the loop begins and the results are stored back into memory after the loop ends. This clarifies the timing and path of data loading and storage, minimizes data transfer overhead, and improves storage efficiency.

[0070] In this embodiment, based on the resource capacity constraints of the hardware module, the loop structure is split and rearranged, and the compiler calculates the optimal splitting method to ensure that it can be efficiently mapped to hardware resources.

[0071] S404. Based on the intermediate representation optimization information as the target operator, the hardware module's register allocation and scheduling are performed for computational operations. In this embodiment, the intermediate representation optimization information also includes: further optimization operations on the intermediate representation, including traditional compilation techniques such as constant propagation, common subexpression elimination, and dead code elimination, to further improve code quality.

[0072] Building upon intermediate representation optimization, register resources are allocated for the computational operations of the target operator. Register usage strategies are optimized to reduce register overflows and unnecessary memory accesses, thereby improving instruction execution efficiency. Specifically, appropriate registers are allocated for each operation based on the computational operations in the intermediate representation. For example, a graph coloring algorithm is used to allocate registers, avoiding register conflicts.

[0073] S405. Based on the intermediate representation optimization information and the results of register allocation and scheduling of the hardware module, generate the target optimized instruction sequence.

[0074] According to the instruction set specification, based on intermediate representation optimization information and the results of register allocation and scheduling of hardware modules, the operations in the intermediate representation are converted into specific instruction sequences. For example, the matrix-vector multiplication operation is converted into a dedicated matrix-vector multiplication instruction for the CIM architecture.

[0075] Finally, the instruction sequence, data layout, and execution control information are integrated to generate executable code, ready for deployment and execution on simulators or actual hardware, completing the entire process of transformation from high-level model to low-level hardware.

[0076] In this embodiment, through Figure 6 The compiler optimization process shown achieves efficient mapping from deep neural network models to digital in-memory computing accelerator hardware. Based on the hierarchical hardware structure of the digital in-memory computing accelerator hardware modules, it expands the configurable items of the in-memory computing architecture compilation and simulation toolchain, enabling the simulation of more usage scenarios, simplifying complex DNNs, and thus improving the accuracy of simulation results.

[0077] S104. Simulate the execution of the target optimization instruction sequence and evaluate the performance based on the performance indicators during the execution of the target optimization instruction sequence.

[0078] In this embodiment, the simulator is implemented based on SystemC, providing detailed hardware behavior modeling and accurate performance evaluation. The simulator provides simulation support for the optimized instruction sequence of the execution target based on three levels of the hardware module structure of the digital in-memory computing accelerator: chip-level modules, core-level modules, and unit-level modules.

[0079] (1) Chip-level: The simulator implements a complete on-chip network interconnection model, supports synchronous communication and global memory access between multiple cores, and can simulate data transmission latency and bandwidth between cores. This layer also includes global resource management and task scheduling functions, supporting dynamic allocation of workloads among multiple cores.

[0080] (2) Core level: The simulator adopts a three-stage pipeline architecture, including instruction fetching, instruction decoding and instruction execution. The instruction execution process is precisely time-controlled, and the execution process and delay of each instruction are modeled in detail.

[0081] (3) Unit-level: For different computing units, including in-memory computing units, vector computing units, and scalar computing units, each unit executes according to a three-stage pipeline architecture. Instruction-level parallelism is supported between units. In particular, for in-memory computing units, the simulator provides an accurate macrocell array model to capture their unique computational characteristics and timing behavior. The simulator also performs detailed modeling of the storage hierarchy, including global memory, local memory, and various register files, accurately reflecting data access latency and bandwidth limitations.

[0082] In this embodiment, the simulator performs performance evaluation based on performance metrics during the instruction sequence optimization process. Specifically, these performance metrics include key parameters such as power consumption, execution latency, and hardware utilization. The simulator provides comprehensive performance metric tracking and statistical functions. It records these performance metrics at different granularities, from the execution of a single instruction to the execution of the entire network. The simulator also generates visual performance analysis reports to help designers identify potential performance bottlenecks and optimization opportunities. These performance evaluation results not only support the evaluation of configurable items in compilation and simulation toolchains for different in-memory computing architectures but also provide verification of the accuracy of compiler-optimized simulation results.

[0083] The digital in-memory computing architecture compilation and simulation method provided in this application, based on the hierarchical hardware structure of the hardware modules of the digital in-memory computing accelerator and the unified instruction set, utilizes computation graph-level optimization and operator-level optimization to compile the user-input deep neural network model into a target optimized instruction sequence suitable for execution by the digital in-memory computing architecture. This expands the configurable items of the in-memory computing architecture compilation and simulation toolchain, enabling the simulation of more usage scenarios and simplifying complex DNNs, thereby improving the accuracy of simulation results.

[0084] An exemplary embodiment of this application provides a compilation and simulation toolchain 10 for digital in-memory computing architectures. Figure 7 This illustration shows a structural block diagram of a digital in-memory computing architecture compilation and simulation toolchain 10 provided in an exemplary embodiment of this application. The aforementioned digital in-memory computing architecture compilation and simulation toolchain 10 can achieve the following: Figures 1-6 All or part of the contents of any of the illustrated embodiments. The following is only a brief description of the structure and function of the digital in-memory computing architecture compilation and simulation toolchain 10. For other matters not covered herein, please refer to the relevant descriptions in the aforementioned digital in-memory computing architecture compilation and simulation method. The embodiments of this digital in-memory computing architecture compilation and simulation toolchain 10 correspond to the embodiments of the aforementioned digital in-memory computing architecture compilation and simulation method. All implementation processes and methods of the aforementioned method embodiments can be applied to the embodiments of this digital in-memory computing architecture compilation and simulation toolchain, and can achieve the same technical effects.

[0085] like Figure 7 As shown, the digital in-memory computing architecture compilation and simulation toolchain 10 includes: an acquisition module 100, a configuration module 200, a compiler 300, and a simulator 400, wherein: The acquisition module 100 is used to acquire the target deep neural network model and the target in-memory computing architecture configuration parameters adapted to the target neural network model. The target in-memory computing architecture configuration parameters include at least one of the following: the number of cores, the on-chip communication bandwidth between cores, the size, number and bit width of the storage unit of each core, and the scale of the computing unit of each core. Configuration module 200 is used to configure the digital in-memory computing accelerator according to the target in-memory computing architecture configuration parameters; Compiler 300 is used to compile target deep neural network models into a target-optimized instruction sequence based on a digital in-memory computing accelerator. Simulator 400 is used to simulate the execution of target-optimized instruction sequences and to evaluate performance based on performance metrics during the execution of the target-optimized instruction sequences.

[0086] In this embodiment, as an optional approach, the target deep neural network module includes one of the following: Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), and Long Short-Term Memory (LSTM). CNN is specifically designed for processing data with a grid structure (such as images and audio). RNN is mainly used for processing sequential data, such as text and speech. LSTM is a special RNN architecture that solves the problem of traditional RNNs' difficulty in handling long sequence dependencies through a gating mechanism.

[0087] The configuration module 200 configures the hardware module of the digital in-memory computing accelerator using the target in-memory computing architecture configuration parameters. Based on the hierarchical hardware structure of the hardware module of the digital in-memory computing accelerator, it expands the configurable items of the in-memory computing architecture compilation and simulation toolchain, enabling the simulation of more usage scenarios, simplifying complex DNNs, and improving the accuracy of simulation results.

[0088] In this embodiment, the digital in-memory computing accelerator serves as a bridge between the compiler and simulator in the digital in-memory computing architecture compilation and simulation toolchain, defining a standard interface for hardware-software interaction. The digital in-memory computing accelerator includes a hardware module and an instruction set adapted to the hardware module. Based on the hardware structure of the digital in-memory computing accelerator package and the adapted instruction set, the compiler can map the upper-layer target deep neural network model to the lower-layer instructions to be executed, and the simulator simulates the execution of the instructions to be executed, thereby mapping the complex deep neural network model to the lower-layer target optimized instruction sequence. For a detailed description of the hardware module and instruction set of the digital in-memory computing accelerator, please refer to the relevant descriptions in the above embodiment of the digital in-memory computing architecture compilation and simulation method; they will not be repeated here.

[0089] In this embodiment, compiler 300 is responsible for compiling the user-input deep neural network model into a target optimized instruction sequence suitable for execution by a digital in-memory computing accelerator. Specifically, this includes two key stages: computation graph-level optimization and operator-level optimization.

[0090] As an optional implementation in this application, the compiler 300 compiles the target deep neural network model into a target optimized instruction sequence based on a digital in-memory computing accelerator in the following manner: compiling the target deep neural network model into a core-level intermediate representation suitable for core-level modules according to a computation graph optimization strategy; performing operator-level optimization on the core-level intermediate representation according to an operator optimization strategy to generate a target optimized instruction sequence that conforms to the instruction set.

[0091] Computation graph-level optimization processes the computation graph of the entire target deep neural network model from a macroscopic perspective. This includes computation graph analysis, partitioning, and inter-core scheduling, adapting the model to the underlying in-memory computing architecture. Operator-level optimization, building upon computation graph-level optimization, focuses on individual operators at the microscopic level, further optimizing their computation processes to ensure better execution at the unit-level module level. In this embodiment, computation graph-level optimization provides the overall framework and task allocation for operator-level optimization. For example, computation graph-level optimization determines the task modules executed on different cores, while operator-level optimization performs fine-grained mapping and instruction generation for the specific operators allocated to the cores.

[0092] As an optional implementation in this application, the compiler 300 compiles the target deep neural network model into a core-level intermediate representation suitable for the core-level module according to the computation graph optimization strategy in the following manner: parsing the file of the target deep neural network model to generate a target computation graph; reordering the operators in the target computation graph according to the operator dependencies in the target computation graph to generate a linear operator sequence; The linear operator sequence is divided into multiple partitions using a dynamic programming partitioning algorithm. These partitions are then mapped to different cores. The partitions between different cores are scheduled, and data interaction is performed through global storage to generate intermediate representation information sequences corresponding to each core. These intermediate representation information sequences are adapted to the core-level modules of the digital in-memory computing accelerator. The core-level intermediate representation includes intermediate representation information sequences corresponding to multiple cores.

[0093] As an optional implementation in this application, the compiler 300 reorders the operators in the target computation graph according to the operator dependencies in the target computation graph to generate a linear operator sequence in the following manner: extracting MVM-based operators from the target computation graph; grouping and merging the MVM-based operators with adjacent auxiliary operators as target operators, and rearranging the target operators according to the operator dependencies to generate a linear operator sequence.

[0094] In this embodiment, the core of computation graph-level optimization lies in effectively dividing and scheduling large-scale neural network models onto distributed in-memory computing cores for execution, thereby solving the hardware capacity constraint problem of digital in-memory computing accelerators.

[0095] As an optional implementation in this application, the compiler 300 performs operator-level optimization on the core-level intermediate representation according to the operator optimization strategy in the following manner to generate a target optimized instruction sequence that conforms to the instruction set: It obtains the operator description information of the target operator and the core-level module parameter information based on the core-level intermediate representation. The operator description information includes: weight dimension, input feature dimension, and loop structure corresponding to the weight dimension and input feature dimension; it matches the weight dimension with the dimensions of the hardware module to establish a virtual mapping; based on the virtual mapping, it corresponds the loop structure with the dimensions of the hardware module, and segments and rearranges the loop structure according to the resource capacity constraints of the hardware module to obtain intermediate representation optimization information that adapts the target operator to the hardware module. The intermediate representation optimization information includes: segmentation dimension and memory access operation comments; it performs register allocation and scheduling of the hardware module for the computational operations of the target operator based on the intermediate representation optimization information; and it generates the target optimized instruction sequence based on the intermediate representation optimization information and the results of register allocation and scheduling of the hardware module.

[0096] As an optional implementation in this application, the compiler 300 segments and rearranges the loop structure according to the resource capacity constraints of the hardware module in the following way to obtain intermediate representation optimization information that adapts the target operator to the hardware module: the loop structure is segmented into multiple sub-loops according to the resource capacity constraints of the hardware module to obtain the segmentation dimension; the nesting order in the loop structure is rearranged according to the data dependency relationship in the loop structure, and memory access operations are inserted at preset positions in the loop structure to obtain memory access operation comments.

[0097] In this embodiment, the resource capacity constraints of the hardware module include macrocell size, available storage, and the number of computing units. To ensure that the mapping scheme can be effectively executed on the actual hardware, the loop structure is segmented in this embodiment. Loop segmentation involves dividing a large loop structure into multiple smaller loops according to preset rules. In operator-level optimization, based on the resource capacity constraints of the hardware module, the originally continuously executed loop operations are separated, thereby allowing the loop iteration to better adapt to hardware resources and improve execution efficiency. For example, when the hardware has multiple storage levels, loop segmentation ensures that the data accessed in each loop can be hit in fast storage (such as cache) as much as possible, reducing the overhead of reading data from slow storage (such as main memory). The compiler calculates the optimal segmentation method to ensure that it can be efficiently mapped to hardware resources.

[0098] In this embodiment, the compiler's compilation optimization process achieves efficient mapping from deep neural network models to digital in-memory computing accelerator hardware. Based on the hierarchical hardware structure of the digital in-memory computing accelerator hardware modules, the configurable items of the in-memory computing architecture compilation and simulation toolchain are expanded, enabling the simulation of more usage scenarios, simplifying complex DNNs, and thus improving the accuracy of simulation results.

[0099] In this embodiment, the simulator 400 is implemented based on System C, providing detailed hardware behavior modeling and accurate performance evaluation. The simulator 400 provides simulation support for the optimized instruction sequence of the execution target based on three levels of the hardware module structure of the digital in-memory computing accelerator: chip-level modules, core-level modules, and unit-level modules.

[0100] (1) Chip-level: The simulator 400 implements a complete on-chip network interconnection model, supports synchronous communication and global memory access between multiple cores, and can simulate data transmission latency and bandwidth between cores. This layer also includes global resource management and task scheduling functions, supporting dynamic allocation of workloads among multiple cores.

[0101] (2) Core level: The simulator 400 adopts a three-stage pipeline architecture, including instruction fetching, instruction decoding and instruction execution stages. The instruction execution process is precisely time-controlled, and the execution process and latency of each instruction are modeled in detail.

[0102] (3) Unit-level: For different computing units, including in-memory computing units, vector computing units, and scalar computing units, each unit executes according to a three-stage pipeline architecture. Instruction-level parallelism is supported between units. In particular, for in-memory computing units, the simulator 400 provides an accurate macrocell array model to capture their unique computing characteristics and timing behavior. The simulator 400 also provides a detailed model of the storage hierarchy, including global memory, local memory, and various register files, accurately reflecting data access latency and bandwidth limitations.

[0103] In this embodiment, the simulator 400 performs performance evaluation based on performance metrics during the execution of the target optimized instruction sequence. Specifically, these performance metrics include key parameters such as energy consumption, execution latency, and hardware utilization. The simulator 400 provides comprehensive performance metric tracking and statistical functions. It records these performance metrics at different granularities, from the execution of a single instruction to the execution of the entire network. The simulator 400 also generates visualized performance analysis reports to help designers identify potential performance bottlenecks and optimization opportunities. These performance evaluation results not only support the evaluation of configurable items in compilation and simulation toolchains for different in-memory computing architectures but also provide verification of the accuracy of compiler-optimized simulation results.

[0104] The digital in-memory computing architecture compilation and simulation toolchain provided in this application, based on the hierarchical hardware structure of the hardware modules of the digital in-memory computing accelerator and the unified instruction set, utilizes computation graph-level optimization and operator-level optimization to compile the user-input deep neural network model into a target optimized instruction sequence suitable for execution by the digital in-memory computing architecture. This expands the configurable items of the in-memory computing architecture compilation and simulation toolchain, enabling the simulation of more usage scenarios and simplifying complex DNNs, thereby improving the accuracy of simulation results.

[0105] Figure 8 A structural block diagram of an electronic device 1000 illustrating an exemplary embodiment of this application is shown. The electronic device 1000 can be implemented as the aforementioned digital in-memory computing architecture compilation and simulation toolchain, which can be configured in electronic devices such as smartphones, tablets, laptops, desktop computers, smartwatches, televisions, or servers.

[0106] Typically, electronic device 1000 includes a processor 1001 and a memory 1002.

[0107] Processor 1001 may include one or more processors, such as a quad-core processor, a deca-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1001 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0108] Memory 1002 may include one or more computer-readable storage media, which may be non-transitory. Memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in memory 1002 is used to store at least one instruction, which is executed by processor 1001 to implement all or part of the steps in the digital in-memory computing architecture compilation and simulation method shown in the method embodiments of this application.

[0109] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on the electronic device 1000, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0110] In one exemplary embodiment, a readable storage medium is also provided, which stores a program or instructions that, when executed by a processor, implement all or part of the steps in the above-described digital in-memory computing architecture compilation and simulation method. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0111] In one exemplary embodiment, a computer program product is also provided, comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform the aforementioned... Figures 1 to 6 All or part of the steps of the compilation and simulation method for the digital in-memory computing architecture shown in any embodiment.

[0112] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0113] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for compiling and simulating a digital in-memory computing architecture, characterized in that, include: Obtain the target deep neural network model and the target in-memory computing architecture configuration parameters adapted to the target neural network model, wherein the target in-memory computing architecture configuration parameters include at least one of the following: the number of cores, the on-chip communication bandwidth between cores, the size, number and bit width of the storage unit of each core, and the scale of the computing unit of each core. Configure the digital in-memory computing accelerator according to the target in-memory computing architecture configuration parameters; The target deep neural network model is compiled into a target optimized instruction sequence based on the digital in-memory computing accelerator; The target optimized instruction sequence is simulated and executed, and the performance is evaluated based on the performance metrics during the execution of the target optimized instruction sequence.

2. The method according to claim 1, characterized in that, The step of compiling the target deep neural network model into a target optimized instruction sequence based on the digital in-memory computing accelerator includes: The target deep neural network model is compiled into a core-level intermediate representation suitable for the core-level module according to the computation graph optimization strategy. The core-level intermediate representation is optimized at the operator level according to the operator optimization strategy to generate the target optimized instruction sequence that conforms to the instruction set.

3. The method according to claim 2, characterized in that, The step of compiling the target deep neural network model into a core-level intermediate representation suitable for the core-level module according to the computation graph optimization strategy includes: The file of the target deep neural network model is parsed to generate the target computation graph; The operators in the target computation graph are reordered according to the operator dependencies in the target computation graph to generate a linear operator sequence; The linear operator sequence is divided using a dynamic programming partitioning algorithm to obtain multiple partitions, and these multiple partitions are mapped to different cores. The partitions between different cores are scheduled, data interaction is performed through global storage, and intermediate representation information sequences corresponding to each core are generated. The intermediate representation information sequences are adapted to the core-level modules of the digital in-memory computing accelerator, and the core-level intermediate representation includes: multiple intermediate representation information sequences corresponding to the cores.

4. The method according to claim 3, characterized in that, The step of reordering the operators in the target computation graph according to the operator dependencies in the target computation graph to generate a linear operator sequence includes: Extract the operators based on matrix-vector multiplication (MVM) from the target computation graph; The operator based on matrix-vector multiplication (MVM) is grouped and merged with adjacent auxiliary operators to form the target operator, and the target operator is rearranged based on the operator dependency relationship to generate the linear operator sequence.

5. The method according to claim 2, characterized in that, The step of performing operator-level optimization on the core-level intermediate representation according to the operator optimization strategy to generate the target optimized instruction sequence that conforms to the instruction set includes: The operator description information of the target operator and the parameter information of the core-level module are obtained according to the core-level intermediate representation, wherein the operator description information includes: weight dimension, input feature dimension and loop structure corresponding to the weight dimension and the input feature dimension; The weight dimensions are matched with the dimensions of the hardware modules to establish a virtual mapping; Based on the virtual mapping, the loop structure is mapped to the dimension of the hardware module. The loop structure is then segmented and rearranged according to the resource capacity constraints of the hardware module to obtain intermediate representation optimization information that adapts the target operator to the hardware module. The intermediate representation optimization information includes: segmentation dimension and memory access operation annotation. Based on the intermediate representation optimization information, the hardware module's register allocation and scheduling are performed for the computational operations of the target operator; Based on the intermediate representation optimization information and the register allocation and scheduling results of the hardware module, the target optimized instruction sequence is generated.

6. The method according to claim 5, characterized in that, The step of segmenting and rearranging the loop structure according to the resource capacity constraints of the hardware module to obtain intermediate representation optimization information that adapts the target operator to the hardware module includes: The loop structure is divided into multiple sub-loops based on the resource capacity constraints of the hardware module to obtain the segmentation dimension; The nesting order in the loop structure is rearranged according to the data dependencies in the loop structure, and memory access operations are inserted at preset positions in the loop structure to obtain the memory access operation annotations.

7. A compilation and simulation toolchain for a digital in-memory computing architecture, characterized in that, include: The acquisition module is used to acquire the target deep neural network model and the target in-memory computing architecture configuration parameters adapted to the target neural network model. The target in-memory computing architecture configuration parameters include at least one of the following: the number of cores, the on-chip communication bandwidth between cores, the size, number and bit width of the storage unit of each core, and the scale of the computing unit of each core. The configuration module is used to configure the digital in-memory computing accelerator according to the target in-memory computing architecture configuration parameters; A compiler for compiling the target deep neural network model into a target optimized instruction sequence based on the digital in-memory computing accelerator; A simulator is used to simulate the execution of the target optimized instruction sequence and to evaluate performance based on performance metrics during the execution of the target optimized instruction sequence.

8. The toolchain according to claim 7, characterized in that, The compiler compiles the target deep neural network model into a target optimized instruction sequence based on the digital in-memory computing accelerator in the following manner: The target deep neural network model is compiled into a core-level intermediate representation suitable for the core-level module according to the computation graph optimization strategy. The core-level intermediate representation is optimized at the operator level according to the operator optimization strategy to generate the target optimized instruction sequence that conforms to the instruction set.

9. The toolchain according to claim 8, characterized in that, The compiler compiles the target deep neural network model into a core-level intermediate representation suitable for the core-level module based on a computation graph optimization strategy in the following manner: The file of the target deep neural network model is parsed to generate the target computation graph; The operators in the target computation graph are reordered according to the operator dependencies in the target computation graph to generate a linear operator sequence; The linear operator sequence is divided using a dynamic programming partitioning algorithm to obtain multiple partitions, and these multiple partitions are mapped to different cores. The partitions between different cores are scheduled, data interaction is performed through global storage, and intermediate representation information sequences corresponding to each core are generated. The intermediate representation information sequences are adapted to the core-level modules of the digital in-memory computing accelerator, and the core-level intermediate representation includes: multiple intermediate representation information sequences corresponding to the cores.

10. The toolchain according to claim 8, characterized in that, The compiler performs operator-level optimization on the core-level intermediate representation according to the operator optimization strategy in the following manner to generate the target optimized instruction sequence that conforms to the instruction set: The operator description information of the target operator and the parameter information of the core-level module are obtained according to the core-level intermediate representation, wherein the operator description information includes: weight dimension, input feature dimension and loop structure corresponding to the weight dimension and the input feature dimension; The weight dimensions are matched with the dimensions of the hardware modules to establish a virtual mapping; Based on the virtual mapping, the loop structure is mapped to the dimension of the hardware module. The loop structure is then segmented and rearranged according to the resource capacity constraints of the hardware module to obtain intermediate representation optimization information that adapts the target operator to the hardware module. The intermediate representation optimization information includes: segmentation dimension and memory access operation annotation. Based on the intermediate representation optimization information, the hardware module's register allocation and scheduling are performed for the computational operations of the target operator; Based on the intermediate representation optimization information and the register allocation and scheduling results of the hardware module, the target optimized instruction sequence is generated.

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