Technological method for reducing damage of undeveloped photoresist layer
By forming a carbon polymer protective layer with adjustable thickness on the photoresist layer, the problem of photoresist layer damage caused by over-etching is solved, the integrity of the photoresist layer boundary is maintained, the process yield is improved, and the process difficulty and impurity introduction are reduced.
Patent Information
- Application Number
- CN202410514360.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-26
- Publication Date
- 2025-10-28
AI Technical Summary
In the semiconductor device manufacturing process, over-etching can damage the undeveloped photoresist layer, especially under the load effect in dense and sparse areas. This results in rough exposure boundaries of the photoresist layer, and may even expose the underlying circuit pattern, affecting the process yield.
A carbon polymer protective layer is formed on the photoresist layer, and its thickness is adjusted according to the different regional densities. First, the bottom anti-reflection layer is etched in the dense area to protect the photoresist layer in the sparse area. The carbon polymer protective layer is formed by plasma deposition, and its thickness is controlled to avoid the consumption of the photoresist layer.
Maintaining the integrity of the photoresist layer boundary avoids defects, improves process yield, reduces process difficulty, minimizes impurity introduction, and enhances process efficiency.
Smart Images
Figure CN120854263A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor etching processes, and in particular to a process method for reducing damage to undeveloped photoresist layers. Background Technology
[0002] In the manufacturing process of semiconductor devices, as technology nodes continue to advance, the critical dimension (CD) continues to shrink, the number of patterns that can be accommodated per unit area continues to increase, and the sparse and dense regions within the wafer increase dramatically, ultimately exacerbating the loading effect, which is particularly pronounced in structures with high aspect ratios. Specifically, for example... Figure 1 As shown, in the dense region 100 of the semiconductor device 10, due to the numerous channels 102, their density is higher than that of the channels 102 in the sparse region 101. When the bottom anti-reflective layer 103 (BARC) with fluidity is coated during the process, more BARC flows into the channels 102 in the high aspect ratio structure. This results in the BARC thickness D1 remaining on the top surface of the dense region 100 being significantly lower than the BARC thickness D2 remaining on the top surface of the sparse region 101, producing a loading effect; as Figure 2 As shown, after the subsequent etching process, the BARC in the dense region 100 has been completely etched, while the BARC in the sparse region still has BARC residue 104, which affects the process.
[0003] Regarding the loading effect of BARC in the sparse region 101 and dense region 100, the traditional solution is to use over-etch (OE) to mitigate the impact. While OE completely etches away the BARC in the sparse region 101, it introduces a new problem, such as... Figure 3 As shown, after prolonged etching, the photoresist layer 105 that has not been exposed and developed will be consumed, resulting in a rough exposure boundary for the photoresist layer 105. Figure 3 The B in the image even reveals the circuit pattern beneath the photoresist layer 105, affecting subsequent processes. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a process method to reduce damage to the undeveloped photoresist layer, which solves the problem that in the prior art, when using an etching process to remove the BARC in dense and sparse areas, the unexposed and undeveloped photoresist layer is consumed, resulting in rough exposure boundaries of the photoresist layer, or even exposing the pattern under the photoresist layer, affecting subsequent processes and reducing process yield.
[0005] To achieve the above and other related objectives, the present invention provides a process method for reducing damage to undeveloped photoresist layers, the process method comprising:
[0006] A substrate is provided comprising a first region and a second region having adjacent regions, wherein each of the first region and the second region has a desired circuit pattern formed thereon, and the first region includes a pattern-dense region and a pattern-sparse region depending on the density of the circuit pattern.
[0007] A bottom anti-reflective layer and a photoresist layer are sequentially coated on the surface of the substrate;
[0008] The photoresist layer is patterned to remove the photoresist layer on the first region;
[0009] A carbon-containing polymer protective layer is formed on the surface of the obtained structure, and the thickness of the carbon-containing polymer protective layer located in the second region is greater than the thickness of the carbon-containing polymer protective layer located in the first region;
[0010] The carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer on the second region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
[0011] Optionally, the second region may also include densely patterned areas and sparsely patterned areas depending on the density of the circuit pattern; after sequentially etching the carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region using an etching process, it further includes:
[0012] Remove the photoresist layer and the bottom anti-reflective layer from the second region;
[0013] The bottom anti-reflective layer and the photoresist layer are sequentially coated on the surface of the substrate;
[0014] The photoresist layer is patterned to remove the photoresist layer on the second region;
[0015] The carbon-containing polymer protective layer is formed on the surface of the resulting structure, and the thickness of the carbon-containing polymer protective layer located in the first region is greater than the thickness of the carbon-containing polymer protective layer located in the second region;
[0016] The carbon-containing polymer protective layer and the bottom anti-reflective layer on the second region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer located on the first region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
[0017] Furthermore, the first region is of type NMOS or PMOS, the second region is of type NMOS or PMOS, and the first region and the second region are of different types.
[0018] Optionally, the dense and sparse regions of the graphic have circuit patterns with high aspect ratios.
[0019] The present invention also provides a process method for reducing damage to undeveloped photoresist layers, the process method comprising:
[0020] A substrate is provided comprising a first region and a second region having adjacent regions, wherein each of the first region and the second region has a desired circuit pattern formed thereon, and the first region includes a pattern-dense region and a pattern-sparse region depending on the density of the circuit pattern.
[0021] A bottom anti-reflective layer and a photoresist layer are sequentially coated on the surface of the substrate;
[0022] The photoresist layer is patterned to remove the photoresist layer on the first region;
[0023] A carbon-containing polymer protective layer is formed on the surface of the obtained structure; wherein, the gas source for forming the carbon-containing polymer protective layer is a gas including C and F elements, and the gas source is ignited by an RF ignition power supply to form plasma. Charged particles in the plasma move to the substrate and combine with dangling bonds on the substrate to form the carbon-containing polymer protective layer, and no RF bias power supply is required to guide the plasma to move towards the substrate.
[0024] The carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer on the second region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
[0025] Optionally, the bottom anti-reflective layer on the first region is etched using an over-etching process.
[0026] Optionally, the second region may also include densely patterned areas and sparsely patterned areas depending on the density of the circuit pattern; after sequentially etching the carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region using an etching process, it further includes:
[0027] Remove the photoresist layer and the bottom anti-reflective layer from the second region;
[0028] The bottom anti-reflective layer and the photoresist layer are sequentially coated on the surface of the substrate;
[0029] The photoresist layer is patterned to remove the photoresist layer on the second region;
[0030] The carbon-containing polymer protective layer is formed on the surface of the obtained structure; wherein, the gas source for forming the carbon-containing polymer protective layer is a gas including C and F elements, and the gas source is ignited by an RF ignition power supply to form plasma. Charged particles in the plasma move to the substrate and combine with dangling bonds on the substrate to form the carbon-containing polymer protective layer, and no RF bias power supply is required to guide the plasma to move towards the substrate.
[0031] The carbon-containing polymer protective layer and the bottom anti-reflective layer on the second region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer located on the first region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
[0032] Furthermore, the carbon-containing polymer protective layer is formed in the etching cavity.
[0033] Furthermore, the first region is of type NMOS or PMOS, the second region is of type NMOS or PMOS, and the first region and the second region are of different types.
[0034] Furthermore, the gas source is CH3F.
[0035] Furthermore, the power of the radio frequency ignition power supply is greater than 800W.
[0036] Furthermore, when igniting the gas source to form the plasma, the process also includes an excitation gas and a dilution gas; the excitation gas is argon, and the dilution gas is helium.
[0037] Optionally, the dense and sparse regions of the graphic have circuit patterns with high aspect ratios.
[0038] As described above, the process method of the present invention for reducing damage to the undeveloped photoresist layer involves etching the bottom anti-reflective layer of a first region having densely patterned and sparsely patterned areas. After patterning the photoresist layer to expose the bottom anti-reflective layer of the first region and protect the second region, a carbon-containing polymer protective layer is first formed on the entire surface of the first and second regions, with the thickness of the carbon-containing polymer protective layer on the second region being greater than the thickness of the carbon-containing polymer protective layer on the first region. Then, based on this carbon-containing polymer protective layer, the bottom anti-reflective layer on the first region is etched. During the etching process, the bottom anti-reflective layer is simultaneously consumed. The first and second regions have carbon-containing polymer protective layers. However, since the carbon-containing polymer protective layer in the second region is thicker, it will only come into contact with the photoresist layer in the second region after the carbon-containing polymer protective layer in the second region is completely etched. Therefore, the photoresist layer in the second region is less likely to be consumed, thus better maintaining the integrity of the boundary of the photoresist layer in the second region, avoiding the occurrence of defects, and improving the process yield. In addition, the carbon-containing polymer is easy to deposit on the surface of the photoresist layer and the bottom anti-reflection layer during the deposition process, reducing the process difficulty, and will not introduce too many impurities other than the elements required in the semiconductor device fabrication process during etching removal. Attached Figure Description
[0039] Figure 1 The diagram shows a cross-sectional structure of a semiconductor device as an example, with a bottom anti-reflective layer coated on the surface of the device.
[0040] Figure 2 Displayed as will Figure 1 A schematic diagram of the cross-sectional structure of the bottom anti-reflective layer on a semiconductor device after etching.
[0041] Figure 3 Displayed as will Figure 1 A top view of the structure of the bottom anti-reflective layer on a semiconductor device after etching.
[0042] Figure 4 The diagram shown is a top view of the substrate in the process method for mitigating damage to the undeveloped photoresist layer of the present invention.
[0043] Figure 5 Displayed as along Figure 4 A schematic diagram of the cross-sectional structure along the AA direction.
[0044] Figure 6 The diagram shown is a top view of the substrate surface after the bottom anti-reflection layer and the photoresist layer are sequentially coated on the substrate surface in the process method of the present invention to reduce damage to the undeveloped photoresist layer.
[0045] Figure 7The process method for mitigating damage to the undeveloped photoresist layer shown in this invention involves sequentially coating a bottom anti-reflective layer and a photoresist layer onto the substrate surface, followed by... Figure 6 A schematic diagram of the cross-sectional structure along the AA direction.
[0046] Figure 8 The diagram shown is a top view of the photoresist layer after it has been patterned, as part of the process for reducing damage to the undeveloped photoresist layer according to the present invention.
[0047] Figure 9 Displayed as along Figure 8 Schematic diagram of the cross-sectional structure in the BB direction.
[0048] Figure 10 The diagram shown is a top view of the structure after a carbon-containing polymer protective layer is formed on the substrate in the process method for mitigating damage to the undeveloped photoresist layer of the present invention.
[0049] Figure 11 Displayed as along Figure 10 A schematic diagram of the cross-sectional structure in the CC direction.
[0050] Figure 12 The diagram shown is a top view of the structure after the carbon-containing polymer protective layer and the bottom anti-reflective layer on the second region are sequentially etched using an etching process in the process method of the present invention to reduce damage to the undeveloped photoresist layer.
[0051] Component designation explanation
[0052] 10 Semiconductor Devices
[0053] 100 dense area
[0054] 101 Sparse Region
[0055] 102 Ditch
[0056] 103 Bottom Anti-reflective Layer
[0057] 104 BARC Residue
[0058] 105 Photoresist Layer
[0059] 20 substrates
[0060] 201 First District
[0061] 202 Second Zone
[0062] 203 Circuit Pattern
[0063] 204 Dense Graphic Area
[0064] 205 Sparse Regions in Graphics
[0065] 206 gate
[0066] 207 Barrier Layer
[0067] 208 trench
[0068] 209 base
[0069] 210 Source / Drain
[0070] 21 Bottom anti-reflective layer
[0071] 22 Photoresist layer
[0072] 23 Carbon-containing polymer protective layer Detailed Implementation
[0073] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0074] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0075] As described in the background section, during semiconductor device manufacturing, dense and sparse regions exist due to varying circuit pattern densities. Dense regions have more trenches, so when the same amount of barcodes (BARC) is applied to dense regions, the thickness of the BARC residue on the surface is thinner compared to sparse regions (e.g., ...). Figure 1 (As shown). To completely etch the thicker BARC in the sparse region, an over-etching process is generally used. Furthermore, in the semiconductor device manufacturing process, after the photoresist layer is exposed and developed, the areas to be etched are exposed, while the areas that do not need to be etched are covered and protected by the photoresist layer. Therefore, when using an over-etching process to remove the BARC in the areas to be etched, the photoresist layer in the areas that do not need to be etched is consumed, resulting in rough edges on those photoresist layers (e.g., ...). Figure 3(B) In this case, the underlying circuit pattern may even be exposed, affecting subsequent processes. The most typical example is when NMOS and PMOS are fabricated together on the wafer, forming their respective source / drain. When fabricating the source / drain of NMOS, the PMOS region needs to be protected with a photoresist layer, and when fabricating the source / drain of PMOS, the NMOS region needs to be protected with a photoresist layer. Because this consumes the photoresist layer, it can cause various problems such as the fusion of NMOS and PMOS regions, the loss of NMOS and / or PMOS regions, and damage to the hard mask layer.
[0076] Based on this, this embodiment provides a process method for reducing damage to the undeveloped photoresist layer, the process method comprising:
[0077] S1. A substrate is provided including a first region and a second region that are adjacent to each other, wherein the first region and the second region are respectively formed with their respective desired circuit patterns, and the first region includes a pattern-dense region and a pattern-sparse region depending on the density of the circuit pattern.
[0078] S2. A bottom anti-reflection layer and a photoresist layer are sequentially coated on the surface of the substrate;
[0079] S3. Pattern the photoresist layer to remove the photoresist layer on the first region;
[0080] S4. A carbon-containing polymer protective layer is formed on the surface of the obtained structure, and the thickness of the carbon-containing polymer protective layer located in the second region is greater than the thickness of the carbon-containing polymer protective layer located in the first region.
[0081] S5. The carbon-containing polymer protective layer and the bottom anti-reflection layer on the first region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer on the second region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
[0082] In this embodiment, when etching the bottom anti-reflective layer of a first region with both dense and sparse patterned areas, after patterning the photoresist layer to expose the bottom anti-reflective layer of the first region and protect the second region, a carbon-containing polymer protective layer is first formed on the entire surface of both the first and second regions. The thickness of the carbon-containing polymer protective layer on the second region is greater than the thickness of the carbon-containing polymer protective layer on the first region. Then, based on this carbon-containing polymer protective layer, the bottom anti-reflective layer on the first region is etched. During the etching process, both the first and second regions are simultaneously consumed. The carbon-containing polymer protective layer in the second region is thicker, and it will only come into contact with the photoresist layer in the second region after the carbon-containing polymer protective layer in the second region is completely etched. Therefore, the photoresist layer in the second region is less likely to be consumed, thus better maintaining the integrity of the photoresist layer boundary in the second region, avoiding the occurrence of defects, and improving the process yield. In addition, the carbon-containing polymer is easy to deposit on the surface of the photoresist layer and the bottom anti-reflection layer during the deposition process, reducing the process difficulty, and will not introduce too many impurities other than the elements required in the semiconductor device fabrication process during etching removal.
[0083] The process method of this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0084] like Figure 4 and Figure 5 As shown, step S1 is performed first, providing a substrate 20 including a first region 201 and a second region 202 that are adjacent to each other. The first region 201 and the second region 202 are respectively formed with their respective desired circuit patterns 203, and the first region 201 includes a pattern-dense region 204 and a pattern-sparse region 205 according to the different densities of the circuit patterns 203.
[0085] It should be noted that the circuit patterns in the first region 201 and the second region 202 of the substrate 20 are set according to actual needs, as long as the first region 201 includes a densely patterned region 204 and a sparsely patterned region 205. The main difference between the densely patterned region 204 and the sparsely patterned region 205 is that the densely patterned region 204 has more trenches than the sparsely patterned region 205. In addition, the terms "first" and "second" in the first region 201 and the second region 202 are only used to describe two different types of regions and do not specifically limit the relative importance of the two types of regions.
[0086] As an example, the second region 202 may also include densely patterned regions and sparsely patterned regions depending on the density of the circuit pattern.
[0087] like Figure 4As shown, as an example, the first region 201 can be of type NMOS or PMOS, and the second region 202 can be of type NMOS or PMOS, satisfying that the types of the first region 201 and the second region 202 are different. For example, when the first region 201 is of type NMOS, the second region 202 is of type PMOS; when the first region 201 is of type PMOS, the second region 202 is of type NMOS. It should be noted here that... Figure 4 This is just an illustration. Figure 4 The text does not indicate the connection to the previous sentence. Figure 5 The corresponding features of the dense region 204 and the sparse region 205 can be found in the following reference. Figure 5 The illustration is shown in the image.
[0088] like Figure 5 As shown, as an example, when the first region 201 and the second region 202 are in the source / drain of forming NMOS and PMOS transistors, the substrate 20 may include a base 209, a gate 206 and a barrier layer 207 from bottom to top, and the materials used for these structures are not overly restricted, as long as they are suitable for fabricating MOS transistors.
[0089] like Figure 5 As shown, as an example, the graphic dense region 204 and the graphic sparse region 205 of the first region 201 are circuit patterns 203 with a high aspect ratio, that is, both the graphic dense region 204 and the graphic sparse region 205 have deep trenches 208, and the number of trenches in the graphic dense region 204 is greater than the number of trenches in the graphic sparse region 205.
[0090] like Figure 6 and Figure 7 As shown, then step S2 is performed, in which a bottom anti-reflection layer 21 and a photoresist layer 22 are sequentially coated on the surface of the substrate 20.
[0091] Because the first region 201 has a densely patterned region 204 and a sparsely patterned region 205, when the bottom anti-reflective layer 21 and the photoresist layer 22 are coated in this step, a pattern such as... will be formed. Figure 7 The shape shown indicates that the thickness of the bottom anti-reflective layer 21 of the dense pattern region 204 on the top surface is significantly lower than the thickness of the bottom anti-reflective layer 21 of the sparse pattern region 205 on the top surface.
[0092] It should be noted that the materials used for the bottom anti-reflective layer 21 and the photoresist layer 22 are BARC materials and photoresist materials commonly used in the art, and their thickness is set according to the process stage. The thickness may be the same or different in different process stages, and no excessive restrictions are imposed here.
[0093] like Figure 8 and Figure 9 As shown, step S3 is then performed to pattern the photoresist layer 22 to remove the photoresist layer 22 on the first region 201 and expose the bottom anti-reflective layer 21 on the first region 201.
[0094] like Figure 9 As shown, as an example, when the first region 201 and the second region 202 are located at the source / drain 210 forming the NMOS and PMOS transistors, Figure 9 For along Figure 8 A schematic diagram of the cross-sectional structure along the BB direction, which is a schematic diagram of the cross-sectional structure along the region where the source / drain 210 of the NMOS and PMOS transistors are located.
[0095] Generally, patterning is achieved by exposing and developing the photoresist layer 22. After this step, the photoresist layer 22 covers the second region 202, exposing the bottom anti-reflective layer 21 on the first region 201, so as to lay the foundation for the subsequent process of the first region 201.
[0096] like Figure 10 and Figure 11 As shown, step S4 is then performed, forming a carbon-containing polymer protective layer 23 (e.g., ...) on the surface of the structure obtained after step S3. Figure 10 As shown), and the thickness of the carbon polymer protective layer 23 located in the second region 202 is greater than the thickness of the carbon polymer protective layer 23 located in the first region 201.
[0097] like Figure 11 As shown, as an example, when the first region 201 and the second region 202 are located at the source / drain 210 forming the NMOS and PMOS transistors, Figure 11 For along Figure 10 A schematic diagram of the cross-sectional structure along the CC direction, which is a schematic diagram of the cross-sectional structure along the region where the source / drain 210 of the NMOS and PMOS transistors are located.
[0098] Regarding the function of the carbon-containing polymer protective layer 23, there is no excessive limitation on the process used to form it; for example, CVD or ALD processes can be used. As a preferred example, the carbon-containing polymer protective layer 23 can be formed by plasma deposition of a gas source. Specifically, a gas source for forming the carbon-containing polymer protective layer 23 is introduced into the process chamber. This gas source is a gas containing carbon and fluorine elements. Preferably, a gas source with a high carbon-to-fluorine ratio (i.e., a gas source with a higher carbon content than fluorine content) is selected. The gas source is ignited by an RF ignition power supply to form plasma. To reduce damage to the photoresist layer 22 on the second region 202 caused by the formed plasma, it is not necessary for the RF bias power supply to guide the plasma towards the substrate 20. Only the RF ignition power supply is needed to ignite the gas source to form plasma. The formed plasma moves freely to the substrate 20 (i.e., the surface of the photoresist layer 22 and the bottom anti-reflection layer 21) and interacts with the plasma. The carbon polymer protective layer 23 is formed by dangling bonds on the substrate 20. During this process, a gas source containing C and F elements is ionized into plasma. The C bonds easily form saturated bonds, such as H and O bonds, on the surfaces of the photoresist layer 22 and the bottom anti-reflection layer 21, thereby forming the carbon polymer protective layer 23. The F bonds formed by the F element can further reduce the consumption of the photoresist layer 22 on the second region 202 by the formed plasma. On the other hand, after the plasma is formed, since the plasma is in a free motion state and its motion law basically follows free fall, the carbon polymer protective layer 23 is more likely to accumulate on the surface of the obviously raised second region 202. Thus, the thickness of the carbon polymer protective layer 23 naturally formed on the raised second region 202 is greater than the thickness of the carbon polymer protective layer 23 on the recessed first region 201. Since the formation of the carbon-containing polymer protective layer 23 is a step followed by etching the bottom anti-reflective layer 23 on the first region 201, the carbon-containing polymer protective layer 23 can be formed in the etching chamber, effectively improving process efficiency. Furthermore, the gas source including C and F elements will not introduce more excess impurity elements into the etching chamber, ensuring the required etching environment quality.
[0099] As a specific example, when the carbon-containing polymer protective layer 23 is formed in the etching chamber, the gas source for forming the carbon-containing polymer protective layer 23 is selected as CH3F (fluoromethane). Preferably, when igniting CH3F to form plasma, the power of the radio frequency ignition power supply is generally greater than 800W. More preferably, when igniting the CH3F gas source to form plasma, an excitation gas and a dilution gas are also included. The excitation gas assists in plasma formation, and the dilution gas adjusts the plasma density. The excitation gas is generally selected as argon, and the dilution gas is generally selected as helium.
[0100] like Figure 12 As shown, in step S5, the carbon polymer protective layer 23 and the bottom anti-reflective layer 21 on the first region 201 are etched sequentially using an etching process. The thickness of the carbon polymer protective layer 23 on the second region 202 is selected to ensure that the photoresist layer 22 below it is not consumed or that the photoresist layer 22 below it is consumed within a preset range during the etching step. Here, the preset range is set according to the actual process requirements.
[0101] contrast Figure 8 and Figure 12 Due to the presence of the carbon-containing polymer protective layer 23, the boundary of the photoresist layer 22 on the second region 202 is effectively maintained after this step, avoiding issues such as... Figure 3 The appearance of rough boundaries.
[0102] As an example, in order to completely remove the bottom anti-reflective layer 21 of the pattern-dense region 204 and the pattern-sparse region 205 on the first region 201, the bottom anti-reflective layer 21 on the first region 201 is etched using an over-etching (OE) process.
[0103] As an example, this step also includes the step of removing the photoresist layer 22 and the bottom anti-reflective layer 21 on the second region 202 after this step is completed.
[0104] As illustrated in the example of step S1 above, the second region 202 may also include densely patterned areas and sparsely patterned areas depending on the density of the circuit pattern. Therefore, when the first region 201 needs to be protected by a photoresist layer during the fabrication process of the second region 202, any of the above-described process methods can be used to protect the photoresist layer on the first region 201, specifically including the following steps:
[0105] The bottom anti-reflective layer and the photoresist layer are sequentially coated on the surface of the substrate;
[0106] The photoresist layer is patterned to remove the photoresist layer on the second region;
[0107] The carbon-containing polymer protective layer is formed on the surface of the resulting structure, and the thickness of the carbon-containing polymer protective layer located in the first region is greater than the thickness of the carbon-containing polymer protective layer located in the second region;
[0108] The carbon-containing polymer protective layer and the bottom anti-reflective layer on the second region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer located on the first region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
[0109] As an example, a method can also be used to plasma-entrain a gas source and freely deposit the carbon-containing polymer protective layer. The gas source, which includes C and F elements, is ignited by an RF ignition power supply to form plasma. Charged particles in the plasma move to the substrate and combine with dangling bonds on the substrate to form the carbon-containing polymer protective layer. This method does not require an RF bias power supply to guide the movement of the formed plasma toward the substrate.
[0110] In summary, this invention provides a process method to reduce damage to undeveloped photoresist layers. When etching the bottom anti-reflective layer of a first region having densely patterned and sparsely patterned areas, after patterning the photoresist layer to expose the bottom anti-reflective layer of the first region and protect the second region, a carbon-containing polymer protective layer is first formed on the entire surface of the first and second regions, with the thickness of the carbon-containing polymer protective layer on the second region being greater than the thickness of the carbon-containing polymer protective layer on the first region. Then, based on this carbon-containing polymer protective layer, the bottom anti-reflective layer on the first region is etched. During the etching process, simultaneously... The carbon-containing polymer protective layers in the first and second regions are consumed. However, because the carbon-containing polymer protective layer in the second region is thicker, it will only come into contact with the photoresist layer in the second region after the carbon-containing polymer protective layer in the second region is completely etched. Therefore, the photoresist layer in the second region is less likely to be consumed, thus better maintaining the integrity of the photoresist layer boundary, avoiding defects, and improving process yield. In addition, the carbon-containing polymer is easy to deposit on the surface of the photoresist layer and the bottom anti-reflective layer during the deposition process, reducing the process difficulty, and will not introduce excessive impurities other than those required for semiconductor device fabrication during etching removal. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A process for reducing damage to undeveloped photoresist layers, characterized in that, The process includes: A substrate is provided comprising a first region and a second region having adjacent regions, wherein each of the first region and the second region has a desired circuit pattern formed thereon, and the first region includes a pattern-dense region and a pattern-sparse region depending on the density of the circuit pattern. A bottom anti-reflective layer and a photoresist layer are sequentially coated on the surface of the substrate; The photoresist layer is patterned to remove the photoresist layer on the first region; A carbon-containing polymer protective layer is formed on the surface of the obtained structure, and the thickness of the carbon-containing polymer protective layer located in the second region is greater than the thickness of the carbon-containing polymer protective layer located in the first region; The carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer on the second region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
2. The process method for reducing damage to the undeveloped photoresist layer according to claim 1, characterized in that, The second region also includes densely patterned areas and sparsely patterned areas depending on the density of the circuit pattern; After sequentially etching the carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region using an etching process, the process further includes: Remove the photoresist layer and the bottom anti-reflective layer from the second region; The bottom anti-reflective layer and the photoresist layer are sequentially coated on the surface of the substrate; The photoresist layer is patterned to remove the photoresist layer on the second region; The carbon-containing polymer protective layer is formed on the surface of the resulting structure, and the thickness of the carbon-containing polymer protective layer located in the first region is greater than the thickness of the carbon-containing polymer protective layer located in the second region; The carbon-containing polymer protective layer and the bottom anti-reflective layer on the second region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer located on the first region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
3. The process method for reducing damage to the undeveloped photoresist layer according to claim 2, characterized in that: The first region is of type NMOS or PMOS, the second region is of type NMOS or PMOS, and the first region and the second region are of different types.
4. The process method for reducing damage to the undeveloped photoresist layer according to any one of claims 1 to 3, characterized in that: The dense and sparse regions of the graphic have circuit patterns with high aspect ratios.
5. A process for reducing damage to undeveloped photoresist layers, characterized in that, The process includes: A substrate is provided comprising a first region and a second region having adjacent regions, wherein each of the first region and the second region has a desired circuit pattern formed thereon, and the first region includes a pattern-dense region and a pattern-sparse region depending on the density of the circuit pattern. A bottom anti-reflective layer and a photoresist layer are sequentially coated on the surface of the substrate; The photoresist layer is patterned to remove the photoresist layer on the first region; A carbon-containing polymer protective layer is formed on the surface of the obtained structure; wherein, the gas source for forming the carbon-containing polymer protective layer is a gas including C and F elements, and the gas source is ignited by an RF ignition power supply to form plasma. Charged particles in the plasma move to the substrate and combine with dangling bonds on the substrate to form the carbon-containing polymer protective layer, and no RF bias power supply is required to guide the plasma to move towards the substrate. The carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer on the second region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
6. The process method for reducing damage to the undeveloped photoresist layer according to claim 1 or 5, characterized in that: The bottom anti-reflective layer on the first region is etched using an over-etching process.
7. The process method for reducing damage to the undeveloped photoresist layer according to claim 5, characterized in that, The second region also includes densely patterned areas and sparsely patterned areas depending on the density of the circuit pattern; After sequentially etching the carbon-containing polymer protective layer and the bottom anti-reflective layer on the first region using an etching process, the process further includes: Remove the photoresist layer and the bottom anti-reflective layer from the second region; The bottom anti-reflective layer and the photoresist layer are sequentially coated on the surface of the substrate; The photoresist layer is patterned to remove the photoresist layer on the second region; The carbon-containing polymer protective layer is formed on the surface of the obtained structure; wherein, the gas source for forming the carbon-containing polymer protective layer is a gas including C and F elements, and the gas source is ignited by an RF ignition power supply to form plasma. Charged particles in the plasma move to the substrate and combine with dangling bonds on the substrate to form the carbon-containing polymer protective layer, and no RF bias power supply is required to guide the plasma to move towards the substrate. The carbon-containing polymer protective layer and the bottom anti-reflective layer on the second region are sequentially etched using an etching process; wherein, the thickness of the carbon-containing polymer protective layer located on the first region is selected to ensure that the photoresist layer below it is not consumed or that the photoresist layer below it is consumed within a preset range during the etching step.
8. The process method for reducing damage to the undeveloped photoresist layer according to claim 5 or 7, characterized in that: The carbon-containing polymer protective layer is formed in the etching cavity.
9. The process method for reducing damage to the undeveloped photoresist layer according to claim 7, characterized in that: The first region is of type NMOS or PMOS, the second region is of type NMOS or PMOS, and the first region and the second region are of different types.
10. The process method for reducing damage to the undeveloped photoresist layer according to claim 5 or 7, characterized in that: The gas source is CH3F.
11. The process method for reducing damage to the undeveloped photoresist layer according to claim 10, characterized in that: The power of the radio frequency ignition power supply is greater than 800W.
12. The process method for reducing damage to the undeveloped photoresist layer according to claim 11, characterized in that: When the gas source is ignited to form the plasma, an excitation gas and a dilution gas are also included; the excitation gas is argon and the dilution gas is helium.
13. The process method for reducing damage to the undeveloped photoresist layer according to claim 5 or 7, characterized in that: The dense and sparse regions of the graphic have circuit patterns with high aspect ratios.