Semiconductor device and method for forming the same

Abstract

One aspect of the disclosure relates to a semiconductor device. The semiconductor device includes a source / drain (S / D) contact over the S / D feature; a gate structure over the channel region, where the channel region is adjacent to the S / D feature; a first interlayer dielectric (ILD) layer over the gate structure and surrounding the S / D contact; an etch stop layer over the first ILD layer and the S / D contact, where the etch stop layer includes a first portion and a second portion, and the second portion is chemically different from the first portion; a second ILD layer over the etch stop layer; and a gate via over the gate structure, where the gate via is surrounded by a second portion of the etch stop layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Background Technology

[0002] The electronics industry's demand for smaller and faster electronic devices, capable of supporting increasingly complex and sophisticated functions, is constantly growing. To meet these demands, the integrated circuit (IC) industry is increasingly focused on manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC dimensions (e.g., the smallest IC feature size), thereby increasing production efficiency and reducing associated costs. However, such scaling down also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require similar progress in IC manufacturing processes and technologies.

[0003] As technology nodes shrink, the risk of unwanted coupling between semiconductor device components increases. For example, gate-to-source / drain leakage can occur due to over-etching during gate via formation, causing the via to be too close to the source / drain contacts. Gate vias are formed by creating gate via trenches and filling them with conductive material. However, gate via trenches require deeper etching than source / drain via trenches, and this deeper etching involves etching through multiple dielectric layers of different materials. For these reasons, over-etching effects such as unintended lateral etching can lead to bending and damage to the trench sidewalls. Thus, when gate vias are filled in gate via trenches, they may be too close to the source / drain contacts, resulting in undesirable leakage effects.

[0004] Therefore, although existing methods and structures for forming gate vias are generally sufficient to meet their intended purpose, they are not entirely satisfactory in every case. Summary of the Invention

[0005] One aspect disclosed herein relates to a semiconductor device. The semiconductor device includes source / drain (S / D) contacts above the S / D features; a gate structure above a channel region adjacent to the S / D features; a first interlayer dielectric (ILD) layer above the gate structure and surrounding the S / D contacts; an etch-stop layer above the first ILD layer and the S / D contacts, wherein the etch-stop layer includes a first portion and a second portion, and the second portion is chemically different from the first portion; a second ILD layer above the etch-stop layer; and a gate via above the gate structure, wherein the gate via is surrounded by the second portion of the etch-stop layer.

[0006] Another aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a gate structure above a channel region of a substrate; a source / drain (S / D) feature adjacent to the channel region; a first interlayer dielectric (ILD) layer above the gate structure and the S / D feature; an S / D contact penetrating the first ILD layer to land on the S / D feature; an etch-stop layer above the first ILD layer and the S / D contact, wherein the etch-stop layer includes a first portion and a second portion, and the second portion is chemically different from the first portion; a second ILD layer above the etch-stop layer; an S / D via penetrating the second ILD layer and the first portion of the etch-stop layer to land on the S / D contact; and a gate via penetrating the second ILD layer, the second portion of the etch-stop layer, and the first ILD layer to land on the gate structure.

[0007] Another aspect disclosed herein relates to a method for forming a semiconductor device. The method includes receiving a workpiece having a gate structure above a channel region, a source / drain (S / D) feature adjacent to the channel region, and a first interlayer dielectric directly above the S / D feature. The process includes: forming a dielectric (ILD) layer and a second ILD layer directly above the first ILD layer and directly above the gate structure; forming an S / D contact that passes through the first and second ILD layers to land on the top surface of the S / D feature; forming an etch stop layer above the second ILD layer and above the S / D contact; forming a third ILD layer above the etch stop layer; forming a hard mask layer above the third ILD layer; patterning a photoresist structure to form an etch mask above the hard mask layer; performing a first etching using the etch mask to form a first trench that passes through the hard mask layer, the third ILD layer, and the etch stop layer to expose the top surface of the second ILD layer; performing plasma treatment on the exposed side surface of the etch stop layer in the first trench to form a modified layer; performing a second etching to deepen the first trench to form a second trench that further penetrates the second ILD layer to expose the top surface of the gate structure; and forming a gate via in the second trench. Attached Figure Description

[0008] The state of this disclosure is in relation to the accompanying items. Figure 1 The best understanding of this text comes from the following detailed description. It should be emphasized that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. It should also be emphasized that the accompanying figures illustrate only typical embodiments of this disclosure and should not be considered limiting in scope, as this disclosure is equally applicable to other embodiments. Furthermore, the accompanying figures may implicitly depict features not explicitly described in the embodiments.

[0009] Figure 1 The illustration shows a semiconductor device having a gate via surrounded by a modified etch-stop layer according to an embodiment of the present disclosure.

[0010] Figure 2 The illustration is a flowchart of a method for forming a semiconductor device having a gate via partially or wholly surrounded by a modified etch-stop layer, according to an embodiment of the present disclosure.

[0011] Figures 3 to 11 The illustration shows an embodiment according to the present disclosure. Figure 2 A cross-sectional view of a semiconductor device at an intermediate stage of the manufacturing and processing method;

[0012] Figure 12 The illustration shows a semiconductor device having a modified etch-stop layer surrounding (a plurality of) gate vias and (a plurality of) abutment points according to an embodiment of the present disclosure;

[0013] Figure 13 The figure shows a top view of a semiconductor device having an improved etch-stop layer surrounding a gate via and abutment points according to an embodiment of the present disclosure.

[0014] Figure 14 The illustration is a flowchart of a method for forming a semiconductor device having a modified etch-stop layer partially or completely surrounding (a plurality of) gate vias and surrounding (a plurality of) abutment contacts according to an embodiment of the present disclosure;

[0015] Figures 15 to 24 The illustration is based on an embodiment of the present disclosure. Figure 14 Cross-sectional and top views of a semiconductor device at an intermediate stage of the manufacturing and processing method.

[0016]

Explanation of symbols

[0017] 100: Semiconductor devices

[0018] 101:Substrate

[0019] 105: Internal spacers

[0020] 106: Active Zone

[0021] 106a: Channel

[0022] 106b:S / D epitaxial characteristics

[0023] 108: Gate Structure

[0024] 108a: Bottom section

[0025] 108b: Top section

[0026] 109: Gate spacer

[0027] 110: ILD layer

[0028] 113: Barrier Layer

[0029] 115:CESL

[0030] 116: S / D Contact

[0031] 117: Conformal seed layer

[0032] 118: Gate via

[0033] 120: ILD layer

[0034] 125:CESL

[0035] 127: Improved Etching Termination Layer / Improved Layer / Improved Etching Termination Sidewall Layer

[0036] 130: ILD layer

[0037] 137: Conformal seed layer

[0038] 138: Point of contact

[0039] 150: Hard mask layer

[0040] 155: S / D Through-hole Groove

[0041] 160: Photoresist structure

[0042] 160a: Top layer

[0043] 160b: Intermediate layer

[0044] 160c: Bottom layer

[0045] 161: Opening

[0046] 163: First trench

[0047] 165: Second trench

[0048] 175: Contact point groove

[0049] 200: Semiconductor devices

[0050] 300: Plasma treatment process

[0051] 1000: Method

[0052] 1002, 1004, 1006, 1008, 1010, 1012, 1014, 1016, 1018, 1020: Operations

[0053] 2000: Method

[0054] 2002, 2004, 2006, 2008, 2010, 2012, 2014, 2016: Operations

[0055] t1, t2, t3, t4, t5: Thickness

[0056] d1, d2, d3, d4, d5: Width / Distance

[0057] X, Y, Z: Direction

[0058] θ: angle

[0059] F-F': Line Detailed Implementation

[0060] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0061] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0062] Furthermore, when using "about," "approximately," "substantially," and similar terms to describe a number or range of numbers, the terms are intended to cover numbers within a reasonable range including the described number, such as within + / - 10% of the described number or other values ​​understood by one skilled in the art. For example, the term "about 5 nm" may cover a dimensional range of 4.5 nm to 5.5 nm, where the manufacturing tolerance associated with a deposited material layer is known to be + / - 10% by one of the art. And when comparing the dimension or size of a feature with another feature, the phrases "substantially identical," "basically the same," "similar in size," and similar terms may be understood to be within + / - 10% between the compared features. Moreover, the dimensionality of the different features disclosed may implicitly reveal the dimensionality ratio between the different features.

[0063] This disclosure relates to a semiconductor device having a gate via surrounded by a modified etch-stop layer. The modified etch-stop layer acts as a sidewall buffer, preventing over-etching effects, such as unintended lateral etching, during the formation of the gate via trench. Without a modified etch-stop layer, the sidewalls of the gate via trench may be damaged or laterally over-etched. If lateral over-etching occurs, the gate via formed laterally will be too close to adjacent contacts, such as source / drain contacts. Thus, the gate via may cause short-circuit or leakage effects to the source / drain features. To address such short-circuit and leakage effects, this disclosure provides a method for forming a modified etch-stop layer and a semiconductor device having a modified etch-stop layer.

[0064] Modified etch-stop layers prevent lateral over-etching during gate via formation. These modified etch-stop layers can be selectively formed for gate vias but not for source / drain vias. This is because there are fewer lateral over-etching issues when forming source / drain vias compared to gate vias. Source / drain vias require smaller etch depths and etch through less dielectric layer compared to gate vias. Thus, source / drain vias may not require modified etch-stop layers. For semiconductor devices with butted contacts, modified etch-stop layers can be formed only on a portion of the butted contact. The butted contact (also known as the gate-to-drain contact) is configured as a combination of a gate via and a source / drain via. In these cases, the modified etch-stop layer may only be necessary for the gate via portion of the butted contact (not the source / drain via portion). By selectively forming modified etch-stop layers targeted at gate vias or portions of gate vias, leakage problems are addressed while avoiding the additional cost of forming unwanted layers.

[0065] To illustrate the various aspects of this disclosure, methods for forming semiconductor devices are described below. The embodiments shown in this disclosure are implemented using Gate-All-Around (GAA) field-effect transistors (FETs), but this disclosure is not limited to this. A GAA FET refers to a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding the transistor channel, such as a vertically stacked Gate-All-Around horizontal nanowire or nanosheet MOSFET device. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. For example, this disclosure can also be implemented using a finned FET.

[0066] In the following description, a semiconductor device may also be referred to as a semiconductor structure corresponding to a semiconductor device. Furthermore, the modified etch-stop layers(s) described herein may also be simply referred to as modified layers, modified dielectric layers, modification layers, buffer layers, modified etch-stop sidewall layers, or similar. Although described as modified “etch-stop layers,” this disclosure also contemplates that this layer may be merely a dielectric layer, and is not limited to being an “etch-stop layer.”

[0067] Figure 1The illustration shows a semiconductor device 100 having a gate via 118 surrounded by a modified etch-stop layer 127, according to an embodiment of the present disclosure. The semiconductor device 100 may be part of an integrated circuit (IC) wafer, a system-on-chip (SoC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device includes non-volatile memory, such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof.

[0068] Semiconductor device 100 includes a substrate 101 and an active region 106 above and projecting from the substrate 101. The substrate 101 may be a silicon (Si) substrate or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), or diamond. The active region 106 extends longitudinally along the X direction and may project over an isolation structure (not shown) also disposed above the substrate 101. The isolation structure may be a shallow trench isolation (STI) layer and provides isolation (not shown) between adjacent active regions 106 spaced apart along the Y direction. The dielectric material used for the isolation structure may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0069] The active region 106 includes a channel region between the source / drain (S / D) regions. The channel region may include vertically stacked channels 106a, and the S / D region may include S / D epitaxial features 106b, with the channels 106a extending laterally along the X direction between the S / D epitaxial features 106b. The S / D epitaxial features 106b may include n-type S / D features corresponding to n-type GAA transistor regions or p-type source / drain features corresponding to p-type GAA transistor regions. The S / D epitaxial features 106b can be formed using epitaxial processes employing CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S / D epitaxial features 106b are doped with n-type dopants and / or p-type dopants. In some embodiments, for an n-type GAA transistor, the S / D epitaxial feature 106b comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or Si:C:P epitaxial source / drain features). In some embodiments, for a p-type GAA transistor, the S / D epitaxial feature 106b comprises silicon-germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source / drain features).

[0070] Still refer to Figure 1The semiconductor device 100 includes a gate structure 108 (or gate stack) disposed above a channel region of an active region 106. The gate structure 108 meshes with and surrounds each of the channels 106a. The gate structure 108 includes a gate dielectric layer (not explicitly shown) and a gate electrode (not explicitly shown) disposed on the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer and a high-k dielectric layer disposed on the interface layer. The gate electrode may include one or more conductive materials, such as a capping layer, a work function metal layer, a barrier layer, a metal fill layer, and / or other suitable conductive material layers. The work function layers (if present) may be the same or different, and may be an n-type work function layer or a p-type work function layer, depending on the type of the corresponding GAA transistor. The gate dielectric layer includes a high-k dielectric material, such as a material with a dielectric constant greater than silicon oxide (k≈3.9). The metal fill layer includes a suitable conductive material, such as Al, W, and / or Cu. The metal filler layer may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof.

[0071] Still refer to Figure 1 The gate structure 108 includes a bottom portion 108a disposed below the topmost channel 106a and a top portion 108b disposed above the topmost channel 106a. Internal spacers 105 are disposed along the sidewall of the bottom portion 108a of the gate structure 108, and gate spacers 109 are disposed along the sidewall of the top portion 108b of the gate structure 108. The internal spacers are vertically disposed between the channels 106a and laterally disposed between the S / D epitaxial feature 106b and the gate structure 108. The gate spacers 109 fall on the topmost channel 106a and can be directly disposed above the internal spacers 105. In some embodiments, the internal spacer 105 comprises a dielectric material, including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), or silicon oxycarbonitride (SiOCN). In some embodiments, the internal spacer 105 comprises a low-k dielectric material. In some embodiments, the gate spacer 109 may be made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxycarbonitride (SiOC), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), metal nitride, or a suitable dielectric material. In some embodiments, the internal spacer 105 may comprise a material different from that of the gate spacer 109 to achieve desired etch selectivity or different isolation effects.

[0072] Still refer to Figure 1The semiconductor device 100 includes an interlayer dielectric (ILD) layer 110 above an S / D epitaxial feature 106b. The ILD layer 110 also laterally surrounds the top portion 108b of the gate structure 108. As shown, a gate spacer 109 is laterally disposed between the ILD layer 110 and the top portion 108b of the gate structure 108. In this embodiment, the ILD layer 110 includes an oxide-based dielectric material, such as silicon oxide (SiO2). However, the ILD layer 110 may include a multilayer structure having multiple dielectric materials. In some embodiments, a contact etch stop layer (CESL) (not shown) is vertically disposed between the S / D epitaxial feature 106b and the ILD layer 110, and laterally disposed between the gate spacer 109 and the ILD layer 110. The CESL includes a material different from that of the ILD layer 110, such as a dielectric material different from the dielectric material of the ILD layer 110. For example, the ILD layer 110 includes a dielectric material based on a low-k oxide, and the CESL includes silicon and nitrogen, such as silicon nitride (SiN) or silicon oxynitride (SiON).

[0073] Still refer to Figure 1The semiconductor device 100 includes a CESL 115 disposed above an ILD layer 110 and a gate structure 108, an ILD layer 120 disposed above the CESL 115, a CESL 125 disposed above the ILD layer 120, an ILD layer 130 disposed above the CESL 125, and a hard mask layer 150 disposed above the ILD layer 130. Furthermore, the CESL 125 includes a modified etch stop layer 127 surrounding a gate via 118. As explained in more detail below, the modified etch stop layer 127 has a higher oxygen concentration than the remainder of the CESL 125 to act as a protective layer preventing lateral over-etching during the formation of the gate via 118. The modified etch stop layer 127 is a buffer layer laterally disposed along the X direction between the gate via 118 and the remainder of the CESL 125. As shown, the remaining portion of CESL 125 is laterally spaced from the gate via 118 by the width of the modified etch stop layer 127 along the X direction. Furthermore, the modified etch stop layer 127 and the remaining portion of CESL 125 may share a common top surface and a common bottom surface. In one embodiment, the top surfaces of the modified etch stop layer 127 and the remaining portion of CESL 125 are substantially coplanar. In another embodiment, the bottom surfaces of the modified etch stop layer 127 and the remaining portion of CESL 125 are substantially coplanar. In this embodiment, ILD layers 110, 120, and 130 comprise dielectric materials different from those of CESL 115 and 125. For example, ILD layers 110, 120, and 130 are made of oxide-based dielectrics (such as silicon oxide), while CESL 115 and 125 are made of nitride-based dielectrics (such as silicon nitride). This allows for selection of etchants when forming various conductive sockets, vias, and contacts through the different ILD and CESL layers.

[0074] Still refer to Figure 1 The hard mask layer 150 is made of a different material than the ILD layers 110, 120, and 130. For example, the hard mask layer 150 may be made of a material comprising silicon (Si), silicon nitride (SiN), silicon carbide (SiC), tungsten carbide (WC), or a metal nitride. As described in further detail below, the hard mask layer 150 provides masking protection during plasma processing 300 to improve CESL 125 and remove the photoresist layer. This disclosure envisions that the hard mask layer 150 may be present in the final structure or may be removed by a planarization process, which also removes a portion of the gate via 118. If present in the final structure, the hard mask layer 150 is a dielectric layer such as silicon nitride. If not present in the final structure, the hard mask layer may be a dielectric layer or a metal-containing layer such as tungsten carbide (WC) or a metal nitride.

[0075] Still refer to Figure 1The semiconductor device 100 includes an S / D contact 116 that penetrates the ILD layer 120, CESL 115, and ILD layer 110 to land on an S / D epitaxial feature 106b. The S / D contact 116 may include a silicide feature and a metal filler layer above the silicide feature. The silicide feature may include titanium silicon (TiSi), nickel silicon (NiSi), tungsten silicon (WSi), nickel platinum silicon (NiPtSi), nickel platinum germanium silicon (NiPtGeSi), nickel germanium silicon (NiGeSi), ytterbium silicon (YbSi), platinum silicon (PtSi), iridium silicon (IrSi), erbium silicon (ErSi), cobalt silicon (CoSi), or other suitable compounds. The metal filler layer above the silicide feature may include titanium (Ti), titanium nitride (TiN), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), or molybdenum (Mo). In this embodiment, the S / D contact 116 includes tungsten (W). Furthermore, the S / D contact 116 may be lined with a barrier layer 113 to prevent metal from diffusing into the surrounding environment. The barrier layer 113 may include Ti / TiN, SiN, or W. In this embodiment, the barrier layer 113 includes SiN.

[0076] Still refer to Figure 1 Semiconductor device 100 includes a gate via 118 penetrating a hard mask layer 150, an ILD layer 130, a CESL 125 (or a modified portion thereof), an ILD layer 120, and a CESL 115 to land on a gate structure 108. The gate via 118 may include a conductive material such as W, Ti / TiN, or Ru. In this embodiment, the gate via 118 includes tungsten (W). Furthermore, the gate via 118 may be lined with a conformal seed layer 117 surrounding the gate via 118. The conformal seed layer 117 acts as an adhesion layer to promote better gate filling during the formation of the gate via 118. The conformal seed layer 117 also prevents metal diffusion into the surrounding environment. The conformal seed layer 117 may include Ti / TiN or W. In this embodiment, the conformal seed layer 117 includes TiN or W. As shown, the gate via 118 penetrates a modified etch stop layer 127 of the CESL 125.

[0077] although Figure 1 Not shown in the text, but as Figure 12 As shown, the semiconductor device 100 may further include S / D vias 126 that penetrate the hard mask layer 150, the ILD layer 130, and the CESL 125 to land on the S / D contacts 116. These S / D vias 126 comprise a material similar to that of the gate vias 118. However, as explained in more detail below, these S / D vias 126 do not penetrate any modified etch-stop layer 127, and may also not have any conformal seed layer.

[0078] Figure 2The illustration shows a flowchart of a method 1000 for forming a semiconductor device 100 having a gate via 118 partially or entirely surrounded by a modified etch-stop layer 127, according to an embodiment of the present disclosure. Figures 3 to 11 The diagram is based on Figure 2 A cross-sectional view of the semiconductor device 100 at an intermediate stage of manufacturing and processing according to method 1000. The following references... Figures 3 to 11 To describe method 1000. (Already referenced) Figure 1 The described features can correspond to Figures 3 to 11 The features cited in the text. However, some of the same or similar features will be described in further detail, while for the sake of brevity, some of the same or similar features will not be described again.

[0079] Now for reference Figure 3 In method 1000, at operation 1002, a workpiece is received having a gate structure 108 above a channel 106a in a channel region. The workpiece further includes a source / drain (S / D) feature (e.g., S / D epitaxial feature 106b) adjacent to the channel region, an S / D contact 116 above the S / D feature, and a first interlayer dielectric (ILD) layer (e.g., ILD layer 120) above the gate structure 108. The first ILD layer may refer to ILD layer 120, or may collectively refer to CESL 115 and ILD layer 120.

[0080] Still refer to Figure 3 In method 1000, at operation 1004, an etch stop layer (e.g., CESL 125) is formed over the first ILD layer (e.g., ILD layer 120) and the S / D contact (e.g., S / D epitaxial feature 106b). The etch stop layer can be formed by any suitable deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof). In this embodiment, the etch stop layer is a silicon nitride (SiN) layer or a silicon carbonitride (SiCN) layer. In some embodiments, the etch stop layer is a low-density dielectric layer. For example, due to the presence of carbon, the etch stop layer (e.g., CESL 125) may have a lower density than CESL 115 and the hard mask layer 150. A lower density layer with carbon and / or an etch stop layer can better facilitate a subsequent plasma treatment process 300 for an oxidized etch stop layer, which then forms an improved etch stop layer 127.

[0081] Still refer to Figure 3In method 1000, at operation 1006, a second ILD layer (e.g., ILD layer 130) is formed over an etch-stop layer (e.g., CESL 125). The second ILD layer can be formed by any suitable deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof). The second ILD layer comprises a material similar to the first ILD layer (e.g., both ILD layers comprise silicon oxide).

[0082] Now for reference Figure 4 In method 1000, at operation 1008, a hard mask layer 150 is formed over a second ILD layer (e.g., ILD layer 130). The hard mask layer 150 can be formed by any suitable deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof). In some embodiments, the hard mask layer 150 is a high-density dielectric or metallic layer. In an embodiment, the hard mask layer 150 comprises silicon nitride, and the etch stop layer (e.g., CESL 125) also comprises silicon nitride. However, the hard mask layer 150 has a higher density than the etch stop layer. The higher density layer can better facilitate subsequent plasma processing 300 by selectively blocking oxygen plasma during the oxidation of the etch stop layer. In an embodiment, both the hard mask layer 150 and the etch stop layer comprise silicon nitride, but the etch stop layer comprises carbon, while the hard mask layer does not. In this embodiment, the hard mask layer also includes carbon, but at a lower concentration than that of the etch stop layer. For example, the hard mask layer has less than 5% carbon atoms, while the etch stop layer has about 20% or more carbon atoms.

[0083] Now for reference Figure 5 In method 1000, at operation 1010, a photoresist structure 160 is formed over a hard mask layer 150. In the illustrated embodiment, the photoresist structure 160 is a three-layer photoresist stack having a top layer 160a, an intermediate layer 160b, and a bottom layer 160c. The top layer 160a may be a photoresist (PR) layer that is sensitive to light exposure. The intermediate layer 160b may be an anti-reflective layer to aid exposure and focusing when the top layer 160a is patterned. The intermediate layer 160b may be a silicon-containing intermediate layer (e.g., spin-coated glass). In an embodiment, the intermediate layer 160b includes silicon and oxygen. The bottom layer 160c may be an organic thin film underlayer to provide further anti-reflective properties, but may also provide etch durability when using the later-formed patterned top layer 160a as an etch mask. The bottom layer 160c may include carbon, nitrogen, hydrogen, and / or oxygen, but does not contain silicon.

[0084] Now for reference Figure 6 In method 1000, at operation 1012, the photoresist structure 160 is patterned to form an etch mask over a hard mask layer. To form the etch mask, the top layer 160a is patterned by first exposing the top layer 160a to radiation such as light or an excimer laser through a photomask defining the opening 161. Next, a baking or curing operation is performed to harden the resist in the top layer 160a. Then, depending on whether a positive or negative resist is used, exposed or unexposed portions of the resist are removed using a developer to form a pattern in the top layer 160a. As a result, the opening 161 is formed in the top layer 160a.

[0085] Now for reference Figure 7 In method 1000, at operation 1014, a first etch is performed using an etch mask to form a first trench 163 through a hard mask layer 150, a second ILD layer (e.g., ILD layer 130), and an etch stop layer (e.g., CESL 125) to expose the top surface of the first ILD layer (e.g., ILD layer 120). During this first etch, the photoresist structure 160 may also be etched. In the illustrated embodiment, after the first etch, both the top layer 160a and the intermediate layer 160b are completely removed, while only the bottom layer 160c is partially removed. This is because the bottom layer 160c configuration has etch-resistant properties and can also be formed as a thicker layer than the top layer 160a and the intermediate layer 160b. Thus, although the top layer 160a and the middle layer 160b can be etched away during the first etching, the bottom layer 160c continues to serve as an etching mask for patterning the underlying layers (i.e., the hard mask layer 150, the ILD layer 130, and the CESL 125).

[0086] Notably, the first etch is used to etch through the etch stop layer (e.g., CESL 125) to expose the side surfaces of the etch stop layer. The exposed side surfaces will later be processed by plasma treatment process 300. Note that the first etch is designed to completely etch through the etch stop layer to maximize the exposed side surface area of ​​the etch stop layer. However, the first etch is also designed not to over-etch into the first ILD layer (e.g., ILD layer 120). Over-etching into the first ILD layer can result in undesirable lateral etching or bending effects on the etch stop layer due to the different materials of the etch stop layer and the first ILD layer. For example, the first etch may etch the etch stop layer at a faster rate than the first and second ILD layers, resulting in undesirable lateral etching. If this occurs, the metal vias later filled in the first trench 163 may cause leakage effects with the surrounding metal. Thus, the first etch can sometimes be slightly under-etched, provided that sufficient side surface of the etch stop layer is exposed. In embodiments, the first etch penetrates 90% to 100% of the thickness of the etch stop layer.

[0087] Now for reference Figure 8 In method 1000, at operation 1016, a plasma treatment 300 (or plasma treatment process 300) is performed on the exposed side surface of the etch stop layer (e.g., CESL 125) in the first trench 163 to form a modified etch stop layer 127 (also referred to herein as modified layer 127). The plasma treatment 300 includes a plasma ashing process that applies oxygen plasma, wherein the plasma ashing process modifies the exposed side surface of the etch stop layer to form modified layer 127. Furthermore, the plasma ashing process simultaneously etches away the remaining portion of the etch mask (i.e., the bottom layer 160c). For example, oxygen plasma can remove all trace amounts of organic matter, thereby removing any remaining portion of the photoresist structure 160, while simultaneously introducing oxygen onto the exposed surface of the first trench 163. After plasma treatment 300, the exposed sidewall portions of the etch stop layer are oxidized to form modified layer 127. In embodiments where the etch stop layer is made of silicon nitride (SiN), the formed modified layer 127 is now formed of silicon oxynitride (SiON). In embodiments where the etch stop layer is made of silicon carbonitride (SiCN), the formed modified layer 127 is now formed of silicon oxycarbonitride (SiOCN). In any case, the modified layer 127 includes a greater oxygen concentration than the remainder of the etch stop layer (e.g., the unmodified portion of CESL 125). The modified layer 127 provides buffer protection in preparation for a second etch to be performed later. Specifically, the increased oxygen concentration in the modified layer 127 prevents lateral etching in the etch stop layer. In embodiments, the oxygen concentration in the modified layer 127 is 3 to 5 times greater than in the remainder of the etch stop layer. If it is less than 3 times, there may not be enough oxygen to provide protection against lateral over-etching. However, if it is greater than 5 times, there is no additional benefit; furthermore, there is a risk of oxidation of other unintended layers (e.g., ILD layer 130, hard mask layer 150, or other surrounding features). It should be noted that since the second ILD layer (e.g., ILD layer 130) can be an oxide-based dielectric, the risk of any unintended oxidation of the second ILD layer is relatively low. It should also be noted that since the hard mask layer 150 can be a high-density layer (e.g., due to the absence or minimal carbon), the risk of unintended oxidation is also reduced. Therefore, as long as the introduced oxygen level is not excessive, only the sidewalls of the etch-stop layer (e.g., CESL 125) are improved, without affecting the hard mask layer 150 and / or the second ILD layer (e.g., ILD layer 130). Furthermore, in some embodiments, due to the lower density of the etch-stop layer (e.g., CESL 125), more oxygen can be absorbed into its sidewalls. For example, in embodiments where the etch-stop layer includes SiCN, plasma treatment 300 can remove some of the carbon in the etch-stop layer and replace it with oxygen.

[0088] Optionally, the plasma ashing process may further apply hydrogen plasma to introduce hydrogen into the modified layer 127. The hydrogen plasma further prevents the hard mask layer 150 from undergoing unwanted oxidation. It should be noted that hydrogen does not prevent oxidation in the etch-stop layer, as the etch-stop layer is a lower-density layer, while the hard mask layer 150 is a higher-density layer (although both may comprise similar materials, such as silicon nitride). In an embodiment, the plasma treatment 300 is performed at a chamber pressure of 1 Torr, wherein oxygen is introduced at a gas flow rate of approximately 6150 sccm (standard cubic centimeters per minute), and optionally hydrogen is introduced at a gas flow rate of approximately 1850 sccm. Because the plasma ashing process is designed to introduce oxygen, carrier gases typically used to prevent oxidation (such as argon or other inert gases) are not used. In an embodiment, the plasma ashing process also does not introduce nitrogen plasma.

[0089] Now for reference Figure 9 In method 1000, a second etching is performed at operation 1018 to deepen the first trench 163, thereby forming a second trench 165 that further penetrates the first ILD layer (e.g., ILD layer 120, or ILD layer 120 together with CESL 115). The second etching exposes the top surface of the gate structure 108. It should be noted that since the bottom layer 160c, which previously served as an etch mask, was removed during plasma processing 300, the hard mask layer 150 now acts as a second etch mask when forming the second trench 165. Due to the now-formed modified layer 127, the etch stop layer (e.g., CESL 125) will not be damaged or laterally over-etched when the second etching is performed to deepen the first trench 163. Furthermore, since ILD layers 120 and 130 plus modified layer 127 are all oxygen-containing (e.g., SiO2 of ILD layers 120 and 130 and SiON of modified layer 127), a more consistent etch profile is produced.

[0090] Now for reference Figures 10 and 11 In method 1000, at operation 1020, a gate via 118 is formed in the second trench 165. In the illustrated embodiment, forming the gate via 118 includes first forming the second trench 165 (… Figure 10 A conformal seed layer 117 is formed in the trench, and then the remainder of the trench is filled with a metal filler. The gate via 118 can be formed by any suitable deposition process described herein.

[0091] Additional operations may be provided before, during, and after method 1000, and some of these operations may be moved, replaced, or eliminated for additional embodiments of method 1000. For example, method 1000 may further include forming an S / D via 126 penetrating a hard mask layer 150, a second ILD layer (e.g., ILD layer 130), and an etch stop layer (e.g., CESL 125) to fall on an S / D contact 116 (see...). Figure 12It should be noted that no modification layer 127 is formed when preparing to form the S / D via 126. In other words, the modification layer 127 is selectively formed when preparing to form the gate via 118 (but not for the S / D via 126). As explained herein, the modification layer 127 may not be necessary for the S / D via 126.

[0092] Furthermore, in some embodiments, method 1000 may further include a planarization process that planarizes the workpiece until the hard mask layer 150 is removed. Then, additional metallic features and / or dielectric layers may be formed over the workpiece to complete the semiconductor device 100. In other embodiments, the hard mask layer 150 remains unchanged, and method 1000 includes forming additional metallic features and / or dielectric layers over the hard mask layer 150 to complete the semiconductor device 100.

[0093] Figure 12 The illustration shows a semiconductor device 200 according to an embodiment of the present disclosure, having a modified etch-stop layer 127 surrounding a plurality of gate vias 118 and a plurality of contact points 138. The semiconductor device 200 includes components related to... Figure 1 The semiconductor device 100 described has similar features. As shown, the semiconductor device 200 may substantially surround the previously described semiconductor device 100. Thus, for the sake of brevity, some of the same or similar features will not be described again, but some of the same or similar features will be described in further detail.

[0094] The difference between semiconductor device 200 and semiconductor device 100 lies in the extension of the active region 106 to further include abutment contact points 138 above different transistor regions, and to include S / D vias 126 above S / D contacts 116. Although Figure 12 A certain number of S / D contacts 116, S / D vias 126, gate vias 118, and contact points 138 are displayed above a certain number of gate structures 108 and active regions 106; however, the number of these features is not limited to... Figure 12 As shown. These features are possible in greater or lesser extent without departing from the spirit and scope of this disclosure.

[0095] like Figure 12As shown, the semiconductor device 200 includes the various dielectric layers previously described. ILD layer 110 has a thickness t1, CESL 115 plus ILD layer 120 have a total thickness t2, CESL 125 has a thickness t3, ILD layer 130 has a thickness t4, and hard mask layer 150 has a thickness t5. In an embodiment, the thickness t1 can range from about 5 to about 30 nm, corresponding to the height of the top portion 108b of the gate structure 108. In an embodiment, the thickness t2 can range from about 10 nm to about 25 nm, wherein the thickness of ILD layer 120 is greater than the thickness of CESL 115. In an embodiment, the thickness t3 of CESL 125 can range from about 2 to about 12 nm. In an embodiment, CESL 115 also has a thickness t3. In an embodiment, the thickness t4 of ILD layer 130 can range from about 0 to about 20 nm. In an embodiment, ILD layer 120 also has a thickness t4. In an embodiment, the thickness t5 of the hard mask layer 150 can range from about 1 to about 40 nm.

[0096] Still refer to Figure 12 S / D contact 116 penetrates ILD layer 120, CESL 115, and ILD layer 110 to land on S / D epitaxial feature 106b. S / D contact 116 has a height equal to the sum of thicknesses t1 and t2. S / D via 126 penetrates hard mask layer 150, ILD layer 130, and CESL 125 to land on S / D contact 116. S / D via 126 has a height equal to the sum of thicknesses t3, t4, and t5. S / D via 126 may not have any conformal seed layer. Gate via 118 penetrates hard mask layer 150, ILD layer 130, CESL 125, ILD layer 120, and CESL 115 to land on gate structure 108. Gate via 118 has a height equal to the sum of thicknesses t2, t3, t4, and t5. The gate via 118 may include a conformal seed layer 117. The abutment contact 138 penetrates the hard mask layer 150, ILD layer 130, CESL 125, ILD layer 120, and CESL 115 to have a gate via portion falling on the gate structure 108 and an S / D via portion falling on the S / D contact 116. The abutment contact 138 has a height equal to the sum of thicknesses t2, t3, t4, and t5 for the gate via portion and a height equal to the sum of thicknesses t3, t4, and t5 for the S / D via portion. The abutment contact 138 may also have a sloped portion between the gate via portion and the S / D via portion, which partially penetrates the ILD layer 120. The abutment contact 138 may include a conformal seed layer 137. Note that in the embodiment where the hard mask layer 150 is removed, the thickness t5 is subtracted from the individual heights of the S / D via 126, the gate via 118, and the contact point 138.

[0097] Still refer to Figure 12 CESL 125 includes a modified layer 127 surrounding the gate via 118, and directly contacts the two sidewalls of the gate via 118 when viewed along the X and Y directions (e.g., Figure 13 (As shown). CESL 125 may further include a modified layer 127 that surrounds and directly contacts the sidewall of the gate via portion (but not the S / D via portion) of the contact point 138. Modified layer 127 may selectively form the gate via 118 and the gate via portion for the contact point 138, but not for the S / D via 126 and the S / D via portion of the contact point. This is because there is less lateral over-etching when forming the S / D via 126 and the S / D via portion compared to forming the gate via 118 and the gate via portion, as the S / D via 126 and the S / D via portion require a smaller etch depth and do not need to etch through the ILD layer 120 and CESL 115. Thus, modified etch-stop layer 127 may not be necessary for the S / D via 126 and the S / D via portion. By selectively forming an improved etch stop layer 127 to target the gate via or gate via portion, leakage problems are resolved while avoiding the additional cost of forming unwanted layers.

[0098] Still refer to Figure 12 The modified layer 127 for the gate via 118 has a width d1 extending from the sidewall of the gate via 118. In embodiments, the width d1 ranges from about 0.1 nm to about 15 nm in the X or Y direction. In embodiments, the width d1 should be greater than about 4 nm to achieve a barrier effect during etching. The oxygen concentration of the modified layer 127 is stronger near the gate via 118 than radially outward from the gate via 118. The oxygen concentration may decrease radially by 0.1% to 20% per nm starting from a distance of about 0.1 nm to about 0.5 nm from the gate via 118. The modified layer 127 may have a chamfer or rounded corner, forming an angle θ between the horizontal surface and the chamfer of the modified layer 127. In embodiments, the angle θ ranges from about 5 to about 45 degrees.

[0099] Still refer to Figure 12 The S / D via 126 is surrounded by the unmodified portion of CESL 125, which directly contacts the two sidewalls of the S / D via 126 when viewed along the X and Y directions (e.g., Figure 13(As shown). In an embodiment, the distance d2 of the unmodified portion of the CESL 125 located laterally between the modified layer 127 and the S / D via 126 (or S / D contact 116) ranges from about 27 nm to about 200 nm. In an embodiment, the vertical distance d3 between the modified layer 127 and the gate structure 108 is equal to the thickness t2. In an embodiment, the horizontal distance d4 between adjacent gate vias 118 is between about 35 nm and about 800 nm, and the lateral distance d5 between the gate via 118 and the adjacent contact 138 is between about 35 nm and about 200 nm.

[0100] Figure 13 The figure shows a top view of a semiconductor device 200 having an improved etch-stop layer 127 (also referred to as improved layer 127) surrounding a gate via 118 and an abutment contact 138. Figure 13 An S / D via 126, a gate via 118, and an abutment contact 138 are shown, but more or less of these features are possible without departing from the spirit and scope of this disclosure. Figure 13 Corresponding to Figure 12 , Figure 13 Top view along CESL 125 and along Figure 12 The line F-F' shown is cut off. As shown, the S / D via 126 is completely surrounded by the unmodified portion of CESL 125 and directly contacts the unmodified portion of CESL 125 along the X and Y directions. The gate via 118 is completely surrounded by the modified layer 127 and directly contacts the modified layer 127 along the X and Y directions. The contact point 138 is only partially surrounded by the modified layer 127 and directly contacts the modified layer 127 along the X and Y directions. As shown, the modified layer 127 for the contact point 138 only directly contacts and surrounds the three sides of the gate via portion of the contact point 138, while the S / D via portion of the contact point 138 is surrounded by and directly contacts the unmodified portion of CESL 125. In this view, the modified layer 127 for the gate via 118 has an "O" shape, while the modified layer 127 for the contact point 138 has a "C" shape. Furthermore, in this view, the individual conformal seed layers 117 and 137 can directly interface with the unmodified portion and / or modified layer 127 of CESL 125.

[0101] Figure 14 The figure shows a flowchart of a method 2000 for forming a semiconductor device 200 according to an embodiment of the present disclosure. The semiconductor device 200 has a modified etch stop layer 127 partially or entirely surrounding one or more gate vias 118 and surrounding one or more contact points 138. Figures 15 to 24 The diagram is based on Figure 14 Cross-sectional and top views of semiconductor device 200 at an intermediate stage of manufacturing and processing according to method 2000. The following references... Figures 15 to 24 Description Method 2000. About Figure 12 and Figure 13 The described features can correspond to the reference. Figures 15 to 24 The characteristics described. However, some of the same or similar characteristics will be described in further detail, while for the sake of brevity, some of the same or similar characteristics will not be described again. Furthermore, for simplicity, [the following is a list of related characteristics]. Figure 12 and Figure 13 compared to, Figures 15 to 24 Some features and / or labels may be omitted.

[0102] Now for reference Figure 15 In method 2000, at operation 2002, a workpiece is received having a gate structure 108 over a channel 106a in a channel region. The workpiece further includes an S / D epitaxial feature 106b adjacent to the channel region, an S / D contact 116 over the S / D epitaxial feature 106b, and a first interlayer dielectric (ILD) layer (e.g., ILD layer 120) over the gate structure. The first ILD layer may refer to ILD layer 120, or may collectively refer to CESL 115 and ILD layer 120. For illustrative purposes, Figure 15 Two S / D contacts 116 are displayed. It is also possible to use other numbers of S / D contacts 116. Operation 2002 is similar to the previously described operation 1002. Therefore, for simplicity, operation 2002 will not be described again.

[0103] Still refer to Figure 15 In method 2000, at operation 2004, an etch stop layer (e.g., CESL 125) is formed over the S / D contact 116 and the first ILD layer (e.g., ILD layer 120). Operation 2004 is similar to operation 1004 previously described. Therefore, for simplicity, operation 2004 will not be described again.

[0104] Still refer to Figure 15 In method 2000, a second ILD layer (e.g., ILD layer 130) is formed above the etch stop layer (e.g., CESL 125) in operation 2006. Operation 2006 is similar to operation 1006 previously described. Therefore, for simplicity, operation 2006 will not be described again.

[0105] Still refer to Figure 15 In method 2000, a hard mask layer 150 is formed above the second ILD layer (e.g., ILD layer 130) in operation 2008. Operation 2008 is similar to operation 1008 previously described. Therefore, for simplicity, operation 2008 will not be described again.

[0106] Now for reference Figures 16 and 17In method 2000, an S / D via 126 is formed at operation 2010, which passes through a hard mask layer 150, a second ILD layer (e.g., ILD layer 130), and an etch stop layer (e.g., CESL 125) to fall on the S / D contact 116. Operation 2010 may include first forming the S / D via trench 155 by a patterning process (see...). Figure 16 The patterning process may include photolithography and etching, wherein a patterned mask layer is formed over the workpiece, and an S / D via trench 155 is formed by etching through an opening defined by the patterned mask layer. It should be noted that the patterning process does not form the S / D via trench 155 over some of the S / D contacts 116. These S / D contacts 116 will later have abutment contacts 138 formed thereon. After forming the S / D via trench 155, operation 2010 may then include forming S / D vias 126 in the S / D via trench 155. In this embodiment, the S / D via 126 is formed by bottom-up metal growth without first depositing any conformal seed layer. For example, a metal filler layer is deposited directly in the S / D via trench 155, wherein the metal filler is grown directly from the top surface of the S / D contact 116. The metal filler then forms the S / D via 126. Because the S / D via trench 155 has a lower aspect ratio (e.g., compared to the gate via trench), and the metal material used for the S / D contact 116 and the S / D via 126 can be the same material to promote good interface contact during bottom-up growth, a conformal seed layer may not be necessary. In this embodiment, both the S / D contact 116 and the S / D via 126 comprise tungsten.

[0107] Now for reference Figures 18 and 19 In method 2000, at operation 2012, a portion of the etch stop layer (e.g., CESL 125) is modified to form a modified etch stop sidewall layer 127. The modified etch stop sidewall layer 127 is formed during preparation of the gate via portion for forming the gate via 118 and / or abutment point 138. Thus, operation 2012 may also include forming a gate via trench (e.g., the previously described second trench 165) to be filled later. Operation 2012 can be performed via operations 1010 to 1018 previously described in method 1000. Therefore, for simplicity, operation 2012 will not be described further. Briefly proceed to... Figure 19 It shows Figure 18A top view along line F-F' and across the etch stop layer (e.g., CESL 125). In this operation step, the unmodified portion of the etch stop layer (e.g., CESL 125) directly contacts and completely surrounds the S / D via 126, and the modified portion of the etch stop layer (i.e., the modified etch stop sidewall layer 127) directly contacts and completely surrounds the gate via trench (e.g., the second trench 165).

[0108] Jump to Figures 22 to 24 In method 2000, a gate via 118 is formed at operation 2014, passing through a hard mask layer 150, a second ILD layer (e.g., ILD layer 130), an etch stop layer (e.g., CESL 125), and a first ILD layer (e.g., ILD layer 120 or ILD layer 120 plus CESL 115) to fall on the gate structure 108, wherein a modified etch stop sidewall layer 127 completely surrounds the gate via 118. Operation 2014 is similar to operation 1020 previously described. Therefore, for simplicity, operation 2014 will not be described further. It should be noted that in this embodiment, the gate via 118 includes a conformal seed layer 117 to improve the gate metal fill, because the gate via has a high aspect ratio, and the gate metal fill may include a material different from the gate structure 108 on which it falls. In an embodiment, the gate structure 108 may have a top width ranging from about 9 nm to about 100 nm, and the gate via 118 may have a bottom width ranging from about 8.5 nm to about 18 nm.

[0109] Return to reference Figures 20 to 21 And refer to other Figures 22 to 24 In method 2000, an abutment contact 138 is formed at operation 2016, extending through a hard mask layer 150, a second ILD layer (e.g., ILD layer 130), an etch stop layer (e.g., CESL 125), and a first ILD layer (e.g., ILD layer 120 or ILD layer 120 plus CESL 115) to land on the gate structure 108 and the S / D contact 116, wherein the modified etch stop sidewall layer 127 only partially surrounds the abutment contact 138. Reference Figure 20Operation 2016 includes first widening one or more of the previously formed gate via trenches (e.g., second trench 165) to form an abutment contact trench 175. The abutment contact trench 175 can be formed by a patterning process including lithography and etching, wherein a patterned masking layer is formed over a workpiece to define the S / D via portion opening adjacent to the gate via trench (e.g., second trench 165), and the abutment contact trench 175 is formed by etching through the S / D via portion opening defined by the patterned masking layer. As a result, the abutment contact trench 175 is formed with a gate via trench portion exposing the gate structure 108 and an S / D via trench portion exposing the S / D contact 116. Furthermore, since the etching laterally extends the gate via trench portion, a trench inclined into the ILD layer 120 may exist between the gate via trench portion and the S / D via trench portion. In addition, when the contact point trench 175 is formed, the sidewall portion of the improved etch termination sidewall layer 127 is removed.

[0110] Briefly redirect to Figure 21 It shows Figure 20 The top view shows the contact trench 175 formed along line F-F' and across the etch stop layer (e.g., CESL 125). In this operational step, the formed contact trench 175 extends and penetrates one sidewall of the modified etch stop sidewall layer 127. As a result, the remaining modified etch stop sidewall layer 127 holds the gate via portion of the contact trench 175 against the other three sides.

[0111] Next, now refer to Figures 22 to 24 A metal filler is formed in the contact trench 175 using a suitable deposition process to form the contact 138. In this embodiment, the contact 138 and the gate via 118 are formed simultaneously. For example, the conformal seed layer 117 for the gate via 118 is formed together with the conformal seed layer 137 for the contact, and the metal filler filling the gate trench (e.g., the second trench 165) is filled together with the metal filler filling the contact trench 175. In this way, the same materials and processes can be used to form both features, saving costs. It should be noted that, like the gate via 118, the contact 138 also includes a seed layer for similar reasons. For example, these seed layers exist at least because the contact 138 has a gate via portion extending to fall on the gate structure 108, even if the seed layer may not be necessary for the S / D via portion of the contact 138.

[0112] In this embodiment, the gate via 118 and the contact point 138 are formed after the S / D via 126 is formed, but this disclosure is not limited thereto. The gate via 118 and the contact point 138 may be formed together first, followed by the formation of the S / D via 126.

[0113] Additional operations may be provided before, during, and after method 2000, and some of these operations may be moved, replaced, or eliminated in additional embodiments of method 1000. For example, method 2000 may further include a planarization process that planarizes the workpiece until the hard mask layer 150 is removed. Subsequently, additional metallic features and / or dielectric layers may be formed over the workpiece to complete the semiconductor device 200. In other embodiments, the hard mask layer 150 remains unchanged, and method 2000 includes forming additional metallic features and / or dielectric layers over the hard mask layer 150 to complete the semiconductor device 200.

[0114] While not intended to be limiting, this disclosure provides advantages regarding the formation of gate vias in semiconductor devices. One example advantage is the formation of an improved etch-stop layer as a protective layer during the formation of the gate via trench. These improved etch-stop layers prevent lateral over-etching that could lead to gate-to-S / D leakage. Another example advantage is the formation of the improved etch-stop layer via a plasma processing process that simultaneously processes the sidewalls of the etch-stop layer and removes the photoresist structure. Another example advantage is the selective formation of improved etch-stop layers for both the gate via and its portions to save costs. Yet another example advantage is the selective formation of conformal seed layers for both the gate via and its portions.

[0115] One aspect disclosed herein relates to a semiconductor device. The semiconductor device includes source / drain (S / D) contacts above the S / D features; a gate structure above a channel region adjacent to the S / D features; a first interlayer dielectric (ILD) layer above the gate structure and surrounding the S / D contacts; an etch-stop layer above the first ILD layer and the S / D contacts, wherein the etch-stop layer includes a first portion and a second portion, and the second portion is chemically different from the first portion; a second ILD layer above the etch-stop layer; and a gate via above the gate structure, wherein the gate via is surrounded by the second portion of the etch-stop layer.

[0116] In the embodiment, both the first and second portions of the etch stop layer comprise silicon nitride, but the second portion of the etch stop layer has a higher oxygen concentration than the first portion of the etch stop layer.

[0117] In one embodiment, a second portion of the etch stop layer is disposed between the gate via and the S / D contact.

[0118] In the embodiment, the first portion and the second portion of the etch termination layer share a common top surface and a common bottom surface.

[0119] In one embodiment, the semiconductor device further includes a hard mask layer above the second ILD layer, wherein both the etch stop layer and the hard mask layer comprise silicon nitride, but the hard mask layer has a higher density than the etch stop layer. In a further embodiment, a gate via penetrates the hard mask layer, the second ILD layer, the etch stop layer, and the first ILD layer to land on the gate structure.

[0120] In an embodiment, the etch stop layer is a first etch stop layer, and the semiconductor device further includes a second etch stop layer between the gate structure and the first ILD layer, wherein the gate via further penetrates the second etch stop layer to fall on the gate structure.

[0121] In one embodiment, the semiconductor further includes an S / D via above the S / D contacts, wherein the S / D via is surrounded by a first portion of an etch-stop layer. In a further embodiment, the gate via includes a conductive seed layer surrounding a gate via filling layer, and the conductive seed layer directly contacts a second portion of the etch-stop layer. In a further embodiment, the S / D via includes an S / D via metal filling layer, and the S / D via metal filling layer directly contacts a first portion of the etch-stop layer.

[0122] Another aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a gate structure above a channel region of a substrate; a source / drain (S / D) feature adjacent to the channel region; a first interlayer dielectric (ILD) layer above the gate structure and the S / D feature; an S / D contact penetrating the first ILD layer to land on the S / D feature; an etch-stop layer above the first ILD layer and the S / D contact, wherein the etch-stop layer includes a first portion and a second portion, and the second portion is chemically different from the first portion; a second ILD layer above the etch-stop layer; an S / D via penetrating the second ILD layer and the first portion of the etch-stop layer to land on the S / D contact; and a gate via penetrating the second ILD layer, the second portion of the etch-stop layer, and the first ILD layer to land on the gate structure.

[0123] In one embodiment, the second portion of the etch stop layer has a higher oxygen concentration than the first portion of the etch stop layer.

[0124] In an embodiment, the semiconductor device further includes a hard mask layer above the second ILD layer, wherein the hard mask layer comprises a material different from the second ILD layer, and wherein each of the S / D via and the gate via further penetrates the hard mask layer.

[0125] In one embodiment, the S / D via directly contacts and is completely surrounded by the first portion of the etch-terminated layer.

[0126] In one embodiment, the gate via directly contacts and is completely surrounded by the second portion of the etch-stop layer.

[0127] In an embodiment, the S / D via falls on the first S / D contact of the S / D contact, the gate via falls on the first gate structure of the gate structure, and the semiconductor device further includes: abutment contacts that penetrate the first and second portions of the second ILD layer, the etch stop layer, and the first ILD layer, wherein each of the abutment contacts falls on the second S / D contact of the S / D contact and the second gate structure of the gate structure.

[0128] In a further embodiment, the contact point directly contacts and is partially surrounded by the first portion of the etch termination layer, and the contact point directly contacts and is partially surrounded by the second portion of the etch termination layer.

[0129] Another aspect disclosed herein relates to a method for forming a semiconductor device. The method includes receiving a workpiece having a gate structure above a channel region, a source / drain (S / D) feature adjacent to the channel region, and a first interlayer dielectric directly above the S / D feature. The process includes: forming a dielectric (ILD) layer and a second ILD layer directly above the first ILD layer and directly above the gate structure; forming an S / D contact that passes through the first and second ILD layers to land on the top surface of the S / D feature; forming an etch stop layer above the second ILD layer and above the S / D contact; forming a third ILD layer above the etch stop layer; forming a hard mask layer above the third ILD layer; patterning a photoresist structure to form an etch mask above the hard mask layer; performing a first etching using the etch mask to form a first trench that passes through the hard mask layer, the third ILD layer, and the etch stop layer to expose the top surface of the second ILD layer; performing plasma treatment on the exposed side surface of the etch stop layer in the first trench to form a modified layer; performing a second etching to deepen the first trench to form a second trench that further penetrates the second ILD layer to expose the top surface of the gate structure; and forming a gate via in the second trench.

[0130] In one embodiment, the plasma treatment includes a plasma ashing process that applies oxygen plasma, wherein performing the plasma ashing process simultaneously etches away the etch mask and improves the exposed side surface of the etch termination layer to form an improved layer.

[0131] In the embodiments, the plasma ashing process further applies hydrogen plasma.

[0132] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the following implementation methods. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A source / drain contact is located above a source / drain feature; A gate structure is located above a channel region, wherein the channel region is adjacent to the source / drain feature; A first interlayer dielectric layer is placed above the gate structure and surrounds the source / drain contacts; An etch stop layer is provided above the first interlayer dielectric layer and the source / drain contact, wherein the etch stop layer includes a first portion and a second portion, and the second portion is different from the first portion in chemical composition. A second interlayer dielectric layer above the etch stop layer; and A gate via is located above the gate structure, wherein the gate via is surrounded by the second portion of the etch stop layer.

2. The semiconductor device as claimed in claim 1, characterized in that, Both the first and second portions of the etch stop layer comprise silicon nitride, but the second portion of the etch stop layer has a higher oxygen concentration than the first portion of the etch stop layer.

3. The semiconductor device as claimed in claim 1, characterized in that, The second portion of the etch stop layer is disposed between the gate via and the source / drain contact.

4. The semiconductor device as claimed in claim 1, characterized in that, The first part and the second part of the etch termination layer share a common top surface and a common bottom surface.

5. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A hard mask layer is provided above the second interlayer dielectric layer, wherein both the etch stop layer and the hard mask layer comprise silicon nitride, but the hard mask layer has a higher density than the etch stop layer.

6. The semiconductor device as claimed in claim 1, characterized in that, The etch stop layer is a first etch stop layer, and the semiconductor device further includes: A second etch-stop layer is provided between the gate structure and the first interlayer dielectric layer, wherein the gate via further penetrates the second etch-stop layer to fall onto the gate structure.

7. A semiconductor device, characterized in that, Include: Multiple gate structures are located above multiple channel regions on a substrate; Multiple source / drain features are located adjacent to the multiple channel regions; A first interlayer dielectric layer is disposed above the plurality of gate structures and the plurality of source / drain features; Multiple source / drain contacts penetrate the first interlayer dielectric layer to land on the multiple source / drain features; An etch stop layer is provided above the first interlayer dielectric layer and the plurality of source / drain contacts, wherein the etch stop layer includes a first portion and a second portion, and the second portion is different from the first portion in chemical composition. A second interlayer dielectric layer is placed above the etch stop layer; Multiple source / drain vias penetrate the first portion of the second interlayer dielectric layer and the etch stop layer to land on the multiple source / drain contacts; and Multiple gate vias penetrate the second interlayer dielectric layer, the second portion of the etch stop layer, and the first interlayer dielectric layer to land on the gate structure.

8. A method for forming a semiconductor device, characterized in that, The method includes the following steps: A workpiece is received having a gate structure above a channel region, a source / drain feature adjacent to the channel region, a first interlayer dielectric layer directly above the source / drain feature, and a second interlayer dielectric layer directly above the first interlayer dielectric layer and directly above the gate structure. A source / drain contact is formed, passing through the first interlayer dielectric layer and the second interlayer dielectric layer, to land on a top surface of the source / drain feature; An etch stop layer is formed above the second interlayer dielectric layer and above the source / drain contact; A third interlayer dielectric layer is formed above the etch stop layer; A hard shielding layer is formed above the third interlayer dielectric layer; A photoresist structure is patterned to form an etch mask over the hard mask layer; An etch mask is used to perform a first etch to form a first trench that passes through the hard mask layer, the third interlayer dielectric layer, and the etch stop layer to expose a top surface of the second interlayer dielectric layer. A plasma treatment is performed on multiple exposed side surfaces of the etch termination layer in the first trench to form an improved layer; A second etching is performed to deepen the first trench, thereby forming a second trench that further penetrates the second interlayer dielectric layer to expose a top surface of the gate structure. and A gate via is formed in the second trench.

9. The method as described in claim 8, characterized in that, The plasma treatment includes a plasma ashing process that applies oxygen plasma, wherein performing the plasma ashing process simultaneously etches away the etch mask and improves the plurality of exposed side surfaces of the etch termination layer to form the improved layer.

10. The method as described in claim 9, characterized in that, The plasma ashing process further applies hydrogen plasma.

Images