Synchronous rectification control method, device and equipment based on CLLLC converter and medium

Abstract

The invention discloses a synchronous rectification control method, device and equipment of a CLLLC converter and a medium. The method comprises the following steps: controlling the CLLLC converter according to a preset closed-loop control strategy, and obtaining a phase shift value of an input side switching tube of the CLLLC converter through the closed-loop control strategy; determining the duty ratio of an output side switching tube of the CLLLC converter according to the phase shift value and a preset switching period count value; and generating a variable duty ratio driving signal of the output side switching tube according to the rising edge of the driving signal of the input side switching tube and the duty ratio so as to control the conduction state of the output side switching tube. The phase shift value is dynamically obtained based on the closed-loop control strategy, and the variable duty ratio driving signal of the output side switch tube is calculated, so that the conduction time sequence of the synchronous rectifier tube can be accurately controlled without an additional detection circuit, the conduction loss of the switch tube is effectively reduced, the risk of output short circuit caused by overlong driving signal is avoided, and the service life of the synchronous rectifier tube is prolonged. Meanwhile, the hardware design is simplified, and the efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of electronic circuit technology, and in particular to a synchronous rectification control method, apparatus, device and medium based on a CLLLC converter. Background Technology

[0002] CLLLC converters, as high-efficiency power conversion systems, are widely used in energy-intensive applications such as switching power supplies, electric vehicle charging systems, industrial power supplies, data center server power supplies, communication equipment power modules, on-board chargers, and industrial automation equipment. In these converters, when the output-side switching transistors are not driven, the current is rectified through the parasitic diodes of the switching transistors. However, due to the large voltage drop of the parasitic diodes, this leads to excessive rectifier bridge current and significant conduction losses. To effectively reduce these losses, synchronous rectification technology is required. The core principle is to control the conduction pulse of the switching transistor (such as a MOSFET / IGBT) during the conduction period of the rectifier diodes, causing the current to flow through the switching transistor with lower on-resistance instead of the diode, thereby reducing energy loss. However, because CLLLC converters have multiple operating states, the conduction characteristics of the rectifier transistors vary in different states, making it difficult to accurately generate synchronous rectification drive signals. If the conduction time of the drive signal exceeds the duration of the actual rectified current, it may also cause an output short circuit, threatening system safety. While traditional voltage-source or current-source synchronous rectification techniques can partially address the aforementioned issues, their control accuracy is highly dependent on the detection circuit. This not only increases hardware complexity and cost but also means that detection errors can affect overall performance. Therefore, there is an urgent need for a high-precision synchronous rectification control method that requires no complex hardware detection and can adapt to multiple operating states. Summary of the Invention

[0003] This invention provides a synchronous rectification control method, apparatus, device, and medium based on a CLLLC converter, aiming to solve the problem of losses in parasitic diode rectification in the undriven state of the output-side switching transistors of existing CLLLC converters.

[0004] In a first aspect, embodiments of the present invention provide a synchronous rectification control method based on a CLLLC converter, the method comprising:

[0005] The CLLLC converter is controlled according to a preset closed-loop control strategy, and the phase shift value of the input-side switching transistor of the CLLLC converter is obtained through the closed-loop control strategy.

[0006] The duty cycle of the output-side switching transistor of the CLLLC converter is determined based on the phase shift value and the preset switching cycle count value.

[0007] A variable duty cycle drive signal for the output switch is generated based on the rising edge of the drive signal of the input switch and the duty cycle to control the conduction state of the output switch.

[0008] Secondly, the present invention also provides a synchronous rectification control device based on a CLLLC converter, including a unit for performing the above-described method.

[0009] Thirdly, embodiments of the present invention also provide a computer device, the computer device including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the above-described method.

[0010] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described method.

[0011] This invention provides a synchronous rectification control method, apparatus, device, and medium based on a CLLLC converter. The method includes: controlling the CLLLC converter according to a preset closed-loop control strategy, and obtaining the phase shift value of the input-side switch of the CLLLC converter through the closed-loop control strategy; determining the duty cycle of the output-side switch of the CLLLC converter based on the phase shift value and a preset switching cycle count value; and generating a variable duty cycle drive signal for the output-side switch based on the rising edge of the drive signal of the input-side switch and the duty cycle to control the conduction state of the output-side switch. This invention achieves precise control of the synchronous rectifier's conduction timing without additional detection circuitry by dynamically obtaining the phase shift value and calculating the variable duty cycle drive signal for the output-side switch based on a closed-loop control strategy. This effectively reduces the conduction loss of the switch, avoids the risk of output short circuit due to excessively long drive signals, simplifies hardware design, and improves system efficiency. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating the steps of the synchronous rectification control method based on a CLLLC converter according to an embodiment of the present invention.

[0014] Figure 2 for Figure 1 A flowchart illustrating the sub-steps of step S110;

[0015] Figure 3 This is a block diagram of the phase-shifting synchronous rectification control method based on a CLLLC converter according to an embodiment of the present invention.

[0016] Figure 4 for Figure 1 A flowchart illustrating another sub-step of step S110;

[0017] Figure 5 for Figure 1 A flowchart illustrating the sub-steps of step S130;

[0018] Figure 6 This is the circuit topology diagram of a CLLLC converter;

[0019] Figure 7 A schematic block diagram of a synchronous rectification control device based on a CLLLC converter provided in an embodiment of the present invention;

[0020] Figure 8 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0026] CLLLC resonant converters, as a high-efficiency DC-DC converter topology, are widely used in electric vehicle charging, data center power supplies, and other applications due to their advantages such as soft-switching characteristics and high power density. However, in practical applications, when no drive signal is applied to the output-side switching transistors, the current is forced to flow through the parasitic diodes inside the switching transistors for rectification. Because the on-state voltage drop of the parasitic diodes is large, significant conduction losses occur under high-current output conditions, severely limiting system efficiency. While traditional synchronous rectification schemes using voltage-type or current-type sensing can alleviate this problem, they suffer from technical bottlenecks such as strong dependence on the accuracy of the sensing circuit, high hardware costs, and the risk of short circuits due to drive signal mismatch during current direction switching. Therefore, there is an urgent need to develop a synchronous rectification control method that does not rely on hardware sensing to solve these problems.

[0027] Therefore, this invention proposes a synchronous rectification control method, apparatus, device, and medium based on a CLLLC converter. It eliminates the need for additional detection circuits, reducing hardware costs. Without hardware detection circuits, it achieves more precise driving and effectively improves system efficiency. Details are as follows:

[0028] Please see Figure 1 , Figure 1 The flowchart of the synchronous rectification control method based on a CLLLC converter provided in the embodiment of the present invention is shown. The method includes steps S110-S130.

[0029] S110. Control the CLLLC converter according to the preset closed-loop control strategy, and obtain the phase shift value of the input-side switching transistor of the CLLLC converter through the closed-loop control strategy.

[0030] In this embodiment, the preset closed-loop control strategy is a strategy for closed-loop control of the output of the CLLLC converter. It can be a dual closed-loop control architecture based on voltage and current loops. Through real-time monitoring and feedback adjustment of the output voltage and bus current, precise control of the CLLLC converter is achieved. The CLLLC converter is a resonant DC-DC converter containing two resonant inductors, two resonant capacitors, and one magnetizing inductor. It has advantages such as high efficiency and low EMI over a wide load range. The input-side switching transistors refer to the power switching devices located on the primary side of the CLLLC converter, typically MOSFETs or IGBTs, used to achieve high-frequency switching. The phase shift value refers to the digital control quantity used to adjust the phase difference of the drive signals of the upper and lower bridge arm switching transistors on the input side. It is calculated based on a 0-180° phase shift angle, and its range is 0-60°. Specifically, the preset closed-loop control strategy in this embodiment acquires the output parameters of the CLLLC converter (such as voltage and current) in real time, compares them with preset target values, and then outputs a phase shift control quantity through a control algorithm. This control quantity is digitally processed to generate the phase shift value (phase) of the input-side switching transistors. In practice, the control system periodically samples the output voltage, calculates the required phase adjustment amount using a preset control algorithm (such as a PID algorithm), and converts this adjustment amount (phase shift angle) into a phase shift value that the PWM module can process. This value is then output to the drive circuit of the input-side switching transistors. Efficient control of the converter is achieved by dynamically adjusting the conduction phase difference between the upper and lower bridge arm switching transistors. The preset closed-loop control strategy enables the CLLLC converter to maintain a stable output voltage under different load conditions, while also providing accurate reference parameters for the variable duty cycle control of the subsequent output-side synchronous rectification.

[0031] In one embodiment, step S110 specifically involves performing dual closed-loop control on the CLLLC converter based on the voltage loop and the current loop.

[0032] In this embodiment, the voltage loop refers to a feedback regulation loop that controls the output voltage, and the current loop refers to a feedback regulation loop that controls the input current. Specifically, the voltage loop collects the output voltage of the CLLLC converter in real time through a voltage sensor, compares it with a preset reference voltage, and then inputs it to a PI controller to generate a current reference value. The current loop collects the input bus current through a current sensor, compares it with the current reference value output by the voltage loop, and then inputs it to another PI controller, ultimately outputting a control signal for regulating the drive of the switching transistors. The advantage of this dual closed-loop control strategy is that the voltage loop ensures the stability and accuracy of the output voltage, while the current loop provides overload protection by limiting the maximum input current. The two work together to achieve a fast dynamic response and avoid the current surge that a single voltage loop might cause during load changes, thereby optimizing the overall efficiency of the converter while ensuring system stability.

[0033] In one embodiment, such as Figure 2 As shown, step S110 includes: S111-S112.

[0034] S111. Obtain the output voltage of the CLLLC converter, compare the output voltage with a preset reference voltage, and input the voltage loop PI controller to generate a current reference value.

[0035] S112. Obtain the bus current, compare the bus current with the current reference value, input the current loop PI controller to output the phase shift angle, and perform mapping conversion on the phase shift angle to obtain the phase shift value of the input-side switch.

[0036] like Figure 3 As shown, in this embodiment, the output voltage refers to the DC voltage U_fb at the output terminal of the CLLLC converter; the preset reference voltage Vref is a target voltage value set according to load requirements; the voltage loop PI controller is a proportional-integral controller used to adjust the output voltage deviation; the current reference value is the output of the voltage loop PI controller, which serves as the input setting value of the current loop; the bus current I_in is the current flowing through the primary bus of the CLLLC converter; the current loop PI controller is a proportional-integral controller used to adjust the bus current deviation; and the phase shift angle refers to the phase difference between the drive signals of the upper and lower bridge arm switching transistors on the input side. Specifically, during system initialization, the proportional coefficient Kp_v and integral coefficient Ki_v of the voltage loop PI controller, and the proportional coefficient Kp_i and integral coefficient Ki_i of the current loop PI controller are pre-configured. During operation, the output voltage U_fb of the CLLLC converter is collected in real time through a voltage sensor, and the difference is calculated with the preset reference voltage U_ref before being input to the voltage loop PI controller for error amplification, outputting a current reference value I_g. At the same time, the input bus current I_in is collected through a current sensor, compared with I_g, and input to the current loop PI controller. After proportional-integral calculation, a 0-180° phase shift angle is output. This phase shift angle is mapped to a 0-600° phase shift value by the PWM module of the digital signal processor to obtain the phase shift value of the input side switch. For example, when the output voltage is 40V (the preset reference voltage is 48V), the voltage error is -8V, and the voltage loop PI controller output current reference value is 5A; if the bus current is 3A at this time, the current error is 2A, the current loop PI controller outputs a phase shift angle of 30°, and after mapping conversion, the count value corresponding to the phase shift value is 100.

[0037] In one embodiment, as shown in Figure 4, step S110 includes: S113.

[0038] S113. The drive signal of the upper bridge arm switch on the input side of the CLLLC converter is phase-shifted according to the phase shift angle to obtain the drive signal of the lower bridge arm switch on the input side so as to drive it to conduct.

[0039] In this embodiment, the upper bridge arm switches refer to the two switches (Q1 and Q3) connected to the positive bus in the full-bridge circuit on the input side of the CLLLC converter, and the lower bridge arm switches refer to the two switches (Q2 and Q4) connected to the negative bus. Specifically, after obtaining the phase shift angle output by the current loop PI controller, the drive signal of the upper bridge arm switch (e.g., Q1) on the input side is used as a reference. The reference signal is phase-shifted according to the phase shift angle θ to generate the corresponding drive signal of the lower bridge arm switch (e.g., Q4), where the phase shift angle θ directly determines the phase difference between the two bridge arm drive signals. For example, when the phase shift angle θ = 90° (corresponding to phase = 30°), the drive signal of the lower bridge arm switch Q4 will be turned on 1 / 4 of a switching cycle later than that of the upper bridge arm Q1. This phase shift control is used to adjust the output voltage by changing the phase difference of the switching devices without adjusting the duty cycle, thereby adjusting the magnitude of the resonant current. This phase difference determines the conduction time. This control method helps to smoothly adjust the output voltage while maintaining a constant switching frequency. For example, when the output voltage needs to be increased, the conduction time is extended; conversely, the conduction time is shortened.

[0040] S120. Determine the duty cycle of the output-side switching transistor of the CLLLC converter based on the phase shift value and the preset switching cycle count value;

[0041] In this embodiment, the preset switching cycle count value TBPRD refers to the PWM timer cycle count value configured in the digital controller, for example, 1200, used to set the control cycle of the switching transistor; the output-side switching transistor refers to the MOSFET constituting the full-bridge rectifier circuit, used to implement the rectification function; the duty cycle D represents the proportion of the switching transistor's on-time in each switching cycle. In specific implementation, the phase shift value and the preset switching cycle count value determine the duty cycle of the output-side switching transistor of the CLLLC converter according to the following formula.

[0042] D = phase / TBPRD

[0043] Where D is the duty cycle of the output-side switch, phase is the phase shift value of the input-side switch, and TBPRD is the preset switching cycle count value. Substituting the obtained phase shift value and the preset switching cycle count value into the formula D = phase / TBPRD (where D is the duty cycle, phase is the phase shift value, and TBPRD is the preset switching cycle count value), the duty cycle of the output-side switch can be calculated. For example, when the preset switching cycle count value TBPRD is 1200 and the phase shift angle is 30°, the phase shift value obtained after mapping is phase = 30° × 600 / 180° = 100 (assuming the phase shift angle 0-180° is mapped to the phase value 0-600). Substituting this into the formula, the duty cycle D = 100 / 1200 ≈ 0.083, meaning the on-time percentage of the output-side switch's drive signal within one switching cycle is 8.3%. For example, when the preset switching cycle count value TBPRD is 1200 and the phase shift angle is 90°, the phase shift value phase = 90° × 600 / 180° = 300 is obtained after mapping (assuming the phase shift angle 0-180° is mapped to the phase value 0-600). Substituting this into the formula, the duty cycle D = 300 / 1200 = 0.25, which means that the on-time of the drive signal of the output-side switch in one switching cycle accounts for 25%.

[0044] It's important to note that TBPRD is the period count value of the PWM timer, determined by both the main chip clock frequency and the PWM drive frequency. The specific calculation relationship is: TBPRD = Main chip frequency / PWM frequency. Taking this system as an example, using a 120MHz DSP chip and setting the PWM drive frequency to 100kHz, TBPRD = 120MHz / 100kHz = 1200, meaning each PWM cycle requires 1200 clock counts. The phase control value, phase, has a maximum value of 600 (corresponding to a 180° phase difference), which is exactly half of TBPRD. This 1:2 ratio design ensures that the phase shift angle θ (0-180°) can be linearly mapped to the phase value (0-600), thus guaranteeing that the duty cycle obtained from the formula D = phase / TBPRD is always between 0 and 0.5. In practical applications, engineers can reset the TBPRD value according to this calculation principle based on the specific main chip frequency and the required PWM frequency.

[0045] S130. Generate a variable duty cycle drive signal for the output switch based on the rising edge of the drive signal of the input switch and the duty cycle to control the conduction state of the output switch.

[0046] In this embodiment, the rising edge of the drive signal for the input-side switching transistor refers to the moment when the input-side MOSFET drive signal transitions from a low level to a high level. This moment serves as a time reference point to trigger the drive signal for the output-side switching transistor. The variable duty cycle drive signal refers to the drive signal for the output-side synchronous rectifier MOSFET, whose on-time ratio (i.e., duty cycle) dynamically changes with the input-side phase shift angle. Specifically, starting from the rising edge of the drive signal for the upper bridge arm switching transistor (e.g., Q1), based on the duty cycle D calculated in step S120, a variable duty cycle drive signal for the output-side switching transistor (e.g., Q5 / Q8) is generated using a timer or PWM module, making its on-time D×TBPRD. Through this synchronous control method, the on-time of the output-side switch can accurately follow the phase shift adjustment of the input side, ensuring that it is turned on during the main current flow period to reduce conduction losses. In other words, when the current is large, the output current does not pass through the diode, but through the switch with a smaller on-resistance, thereby reducing conduction losses. At the same time, it avoids the risk of short circuit due to excessively long drive signals. It realizes synchronous rectification control that automatically adapts to load changes without adding additional current detection circuits, effectively improving the overall working efficiency of the converter.

[0047] In one embodiment, such as Figure 5 As shown, step S130 includes: S131-S133.

[0048] S131. Based on the rising edge of the drive signal of the input-side switch transistor, determine the turn-on time of the drive signal of the output-side switch transistor.

[0049] S133. Generate a variable duty cycle drive signal for the output-side switch based on the on-time of the drive signal of the output-side switch and the duty cycle to control the on-state of the output-side switch.

[0050] In this embodiment, the digital controller (such as a DSP) uses the rising edge of the drive signal of the upper bridge arm switch (such as Q1) on the input side as the time reference point to start a timer counting. When the count value reaches a preset delay value (obtained by phase shift angle mapping), it triggers the rising edge of the drive signal of the corresponding switch (such as Q5) on the output side, thereby determining its conduction time. Then, the digital controller starts timing at the conduction time of the output switch according to the duty cycle D calculated in step S120. When the timing reaches D × TBPRD, the drive signal turns low, completing the variable duty cycle control for one switching cycle. For example, if TBPRD = 1200 and D = 0.25, the conduction time is 300 counting cycles. The controller triggers Q5 to conduct at the rising edge of Q1 and turns it off after 300 counting cycles. Through this embodiment, when the current is large, the output current flows through the switch (Q5, Q8) with smaller on-resistance instead of the diode, thereby significantly reducing conduction losses. To avoid short circuits caused by excessive conduction time, the rising edge of the synchronous output switch drive signal is strictly aligned with the rising edge of the input switch drive signal, and the duty cycle is adjusted in real time according to the current phase shift value. Finally, the timing control is based on the rising edge of PWM1, which not only ensures the high efficiency of synchronous rectification, but also avoids the risk of short circuits through precise duty cycle adjustment, thus ensuring the safe operation of the system.

[0051] In one embodiment, the input-side circuit topology of the CLLLC converter includes a first switch, a second switch, a third switch, and an output-side circuit topology includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The method, when executed, specifically includes: During each cycle, in the forward current phase, the first switch receives a drive signal and turns on; the drive signal of the fourth switch is phase-shifted based on the drive signal of the first switch and controls its conduction; the fifth and eighth switches are controlled to turn on based on a variable duty cycle drive signal calculated according to the phase shift value of the first switch. In the reverse current phase, the third switch receives a drive signal and turns on; the drive signal of the second switch is phase-shifted based on the drive signal of the third switch and controls its conduction; the sixth and seventh switches are controlled to turn on based on a variable duty cycle drive signal calculated according to the phase shift value of the third switch.

[0052] During the forward current phase, the first switch (Q1) and the fourth switch (Q4) form the upper and lower arms of the input side bridge, while the fifth switch (Q5) and the eighth switch (Q8) form a diagonal pair of switches in the output side synchronous rectifier bridge. Specifically, when the rising edge of the drive signal for Q1 arrives, Q1 turns on, and current flows from the positive terminal of the DC bus into the primary side of the transformer via Q1. Simultaneously, the drive signal for Q4 turns on based on the phase shift angle θ lag of the drive signal for Q1. At this time, the output current is positive, and the drive signals for Q5 and Q8 are generated based on the duty cycle D calculated according to the phase shift value of Q1 (e.g., D = phase / TBPRD), causing them to turn on when the secondary voltage of the transformer is positive, replacing the parasitic diode for rectification. This control method precisely aligns the conduction periods of Q5 / Q8 with the forward current flow period of the transformer secondary side, ensuring that the current flows through the low on-resistance MOSFETs instead of the diodes, thereby significantly reducing conduction losses. Simultaneously, the output-side switches are precisely controlled by the phase shift value, strictly limiting the duty cycle of the drive signal, thus avoiding the short-circuit risk caused by Q5 / Q8 and Q6 / Q7 conducting simultaneously due to an excessively long drive signal. For example, when the phase shift angle is 90°, TBPRD = 1200, and phase = 300, the duty cycle D = 300 / 1200 = 0.25, and the switching period T = 1 / 100kHz = 10μs. Therefore, the conduction time of Q5 / Q8 in each cycle is 10μs × 0.25 = 2.5μs, achieving high-efficiency rectification.

[0053] During the reverse current phase, the third switch (Q3) and the second switch (Q2) form another set of upper and lower bridge arms on the input side, while the sixth switch (Q6) and the seventh switch (Q7) form another set of diagonal switches on the output side synchronous rectifier bridge. Specifically, when the rising edge of the drive signal for Q3 arrives, Q3 turns on, and current flows from the positive terminal of the DC bus into the primary side of the transformer via Q3; the drive signal for Q2 turns on based on the phase shift angle θ lag of the drive signal for Q3. At this time, the output current is reversed, and the drive signals for Q6 and Q7 are generated based on the duty cycle calculated according to the phase shift value of Q3 (e.g., D = phase / TBPRD), causing them to turn on when the secondary voltage of the transformer is negative, replacing the parasitic diode for rectification. This symmetrical control architecture ensures that the conduction period of Q6 / Q7 completely covers the reverse current range on the secondary side when the current flows in the reverse direction, so that the current is always conducted through the MOSFET channel rather than the diode, thereby significantly reducing conduction losses. The complementary conduction of Q6 / Q7 and Q5 / Q8 avoids short circuits caused by simultaneous conduction of both sets of switches, completely eliminating the risk of bridge arm shoot-through. For example, when the phase shift angle is 45°, TB PRD = 1200, phase = 150, the duty cycle D = 150 / 1200 = 0.125, and the switching period T = 10μs, the conduction time of Q6 / Q7 in each cycle is 10μs × 0.125 = 1.25μs, ensuring timely switching of the rectification path when the current reverses, improving system efficiency and reliability.

[0054] In this embodiment, based on the phase shift angle in phase shift control, the primary input-side switch generates an equivalent duty cycle through normal phase shift. The secondary side switches synchronously turn on the primary-side switch based on the rising edge of the primary-side drive signal. The drive method adopts the concept of variable duty cycle, and the duty cycle is calculated based on the size of the phase shift angle, automatically following the changes in the system resonant current.

[0055] In summary, this paper, based on the operating characteristics of CLLLC converters, employs phase-shift control as the drive signal for the input-side switching transistors. It cleverly utilizes this phase-shift angle as the duty cycle of the drive signal for the output-side switching transistors. By adjusting the output-side current and the control strategy for the output-side switching transistors, and using the input-side drive signal as a reference, it performs variable duty cycle control on the output-side drive signal. This enables the switching transistors to be turned on during periods of high current rectification, thereby reducing conduction losses. Furthermore, it avoids excessively long on-time of the switching transistors during the forward and reverse current conversion process, which could lead to short circuits, while simultaneously improving efficiency.

[0056] Figure 7 This is a schematic block diagram of a synchronous rectification control device 200 based on a CLLLC converter provided in an embodiment of the present invention. Figure 7 As shown, corresponding to the above-described synchronous rectification control method based on a CLLLC converter, the present invention also provides a synchronous rectification control device 200 based on a CLLLC converter. This synchronous rectification control device 200 includes a unit for executing the above-described synchronous rectification control method based on a CLLLC converter, and the device can be configured in a computer device. Specifically, please refer to... Figure 7 The synchronous rectification control device 200 based on the CLLLC converter includes: a phase shifting unit 201, a calculation unit 202, and a variable duty cycle unit 203.

[0057] The phase-shifting unit 201 is used to control the CLLLC converter according to a preset closed-loop control strategy and obtain the phase-shifting value of the input-side switch of the CLLLC converter through the closed-loop control strategy; the calculation unit 202 is used to determine the duty cycle of the output-side switch of the CLLLC converter according to the phase-shifting value and a preset switching cycle count value; the variable duty cycle unit 203 is used to generate a variable duty cycle drive signal for the output-side switch according to the rising edge of the drive signal of the input-side switch and the duty cycle to control the conduction state of the output-side switch.

[0058] In one embodiment, the phase-shifting unit 201 is further configured to perform dual closed-loop control of the CLLLC converter based on the voltage loop and the current loop.

[0059] In one embodiment, the phase shifting unit 201 is further configured to: acquire the output voltage of the CLLLC converter, compare the output voltage with a preset reference voltage and input the voltage loop PI controller to generate a current reference value; acquire the bus current, compare the bus current with the current reference value and input the current loop PI controller to output a phase shift angle, and perform mapping conversion on the phase shift angle to obtain the phase shift value of the input-side switching transistor.

[0060] In one embodiment, the phase shifting unit 201 is further configured to: shift the driving signal of the upper bridge arm switch on the input side of the CLLLC converter according to the phase shift angle to obtain the driving signal of the lower bridge arm switch on the input side so as to drive it to conduct.

[0061] In one embodiment, the duty cycle of the output-side switch of the computing unit 202 satisfies the following formula:

[0062] D = phase / TBPRD

[0063] Where D is the duty cycle of the output-side switch, phase is the phase shift value of the input-side switch, and TBPRD is the preset switching cycle count value.

[0064] In one embodiment, the variable duty cycle unit 203 is further configured to: determine the on-time of the drive signal of the output-side switch based on the rising edge of the drive signal of the input-side switch; and generate a variable duty cycle drive signal of the output-side switch according to the on-time of the drive signal of the output-side switch and the duty cycle to control the on-state of the output-side switch.

[0065] In one embodiment, the synchronous rectification control device 200 based on the CLLLC converter is configured to: in each cycle, during the forward current phase, the first switch receives a drive signal and turns on, the drive signal of the fourth switch is phase-shifted based on the drive signal of the first switch and controls its conduction, and the fifth and eighth switches are controlled to turn on based on a variable duty cycle drive signal calculated based on the phase shift value of the first switch; during the reverse current phase, the third switch receives a drive signal and turns on, the drive signal of the second switch is phase-shifted based on the drive signal of the third switch and controls its conduction, and the sixth and seventh switches are controlled to turn on based on a variable duty cycle drive signal calculated based on the phase shift value of the third switch.

[0066] The aforementioned synchronous rectification control device 200 based on a CLLLC converter can be implemented as a computer program, which can be used in, for example... Figure 8 It runs on the computer device shown.

[0067] Please see Figure 8 , Figure 8This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 may be a terminal.

[0068] See Figure 8 The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0069] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a synchronous rectification control method based on a CLLLC converter.

[0070] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0071] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a synchronous rectification control method based on a CLLLC converter.

[0072] This network interface 505 is used for network communication with other devices. Those skilled in the art will understand that... Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0073] The processor 502 is used to run a computer program 5032 stored in a memory to implement the steps of the above method.

[0074] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0075] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0076] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When executed by a processor, the program instructions cause the processor to perform the steps of the above-described method.

[0077] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0078] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0079] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0080] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0081] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0084] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A synchronous rectification control method based on a CLLLC converter, characterized in that, The method includes: The CLLLC converter is controlled according to a preset closed-loop control strategy, and the phase shift value of the input-side switching transistor of the CLLLC converter is obtained through the closed-loop control strategy. The duty cycle of the output-side switching transistor of the CLLLC converter is determined based on the phase shift value and the preset switching cycle count value. A variable duty cycle drive signal for the output switch is generated based on the rising edge of the drive signal of the input switch and the duty cycle to control the conduction state of the output switch.

2. The method according to claim 1, characterized in that, The steps of controlling the CLLLC converter according to the preset closed-loop control strategy include: The CLLLC converter is controlled by a dual closed-loop system based on the voltage loop and the current loop.

3. The method according to claim 2, characterized in that, The step of controlling the CLLLC converter according to a preset closed-loop control strategy and obtaining the phase shift value of the input-side switching transistors of the CLLLC converter through the closed-loop control strategy includes: The output voltage of the CLLLC converter is obtained, and the output voltage is compared with a preset reference voltage and then input to the voltage loop PI controller to generate a current reference value; The bus current is obtained, and after comparing the bus current with the current reference value, it is input into the current loop PI controller to output the phase shift angle. The phase shift angle is then mapped and converted to obtain the phase shift value of the input-side switch.

4. The method according to claim 3, characterized in that, After the steps of acquiring the bus current, comparing the bus current with the current reference value, inputting the current loop PI controller to output a phase shift angle, and mapping the phase shift angle to obtain the phase shift value of the input-side switch, the method further includes: The drive signal of the upper bridge arm switch on the input side of the CLLLC converter is phase-shifted according to the phase shift angle to obtain the drive signal of the lower bridge arm switch on the input side, so as to drive it to conduct.

5. The method according to claim 4, characterized in that, The input-side circuit topology of the CLLLC converter includes a first switch, a second switch, a third switch, and a fourth switch, and the output-side circuit topology includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The method further includes: During each cycle, in the forward current phase, the first switch receives a drive signal and turns on. The drive signal of the fourth switch is phase-shifted based on the drive signal of the first switch and controls its turn on. The fifth and eighth switches are controlled to turn on by a variable duty cycle drive signal calculated based on the phase shift value of the first switch. During the reverse current phase, the third switch receives a drive signal and turns on. The drive signal of the second switch is phase-shifted based on the drive signal of the third switch and then controls its turn on. The sixth and seventh switches are controlled to turn on by a variable duty cycle drive signal calculated based on the phase shift value of the third switch.

6. The method according to any one of claims 1-5, characterized in that, The duty cycle of the output-side switch of the CLLLC converter, determined based on the phase shift value and the preset switching cycle count value, satisfies the following formula: D = phase / TBPRD Where D is the duty cycle of the output-side switch, phase is the phase shift value of the input-side switch, and TBPRD is the preset switching cycle count value.

7. The method according to any one of claims 1-5, characterized in that, The step of generating a variable duty cycle drive signal for the output-side switch based on the rising edge of the drive signal of the input-side switch and the duty cycle to control the conduction state of the output-side switch includes: The turn-on time of the drive signal of the input-side switch is determined based on the rising edge of the drive signal of the output-side switch. A variable duty cycle drive signal for the output-side switch is generated based on the on-time of the drive signal of the output-side switch and the duty cycle to control the on-state of the output-side switch.

8. A synchronous rectification control device based on a CLLLC converter, characterized in that, The apparatus includes a unit for performing the method of any one of claims 1-7.

9. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, can implement the method as described in any one of claims 1-7.

Images