Speed adjusting device for sigma-delta ADC and sigma-delta ADC system

Abstract

The invention provides a speed adjusting device for a sigma-delta ADC and a sigma-delta ADC system. The speed adjustment device comprises: a clock signal generation circuit configured to generate two-phase non-overlapping first and second clock signals, the first and second clock signals having a frequency fq of fs / 2N, fs being a sampling clock frequency of a sigma-delta ADC; a switching circuit configured to be controlled by the first and second clock signals to periodically switch to operate in a first or second on state, first ends of a first sampling impedance element and a second sampling impedance element of the sigma-delta ADC being connected to a reference voltage input end of the sigma-delta ADC; in a first on-state, the switching circuit is configured to apply an analog input signal to a second end of the first sampling impedance element and to apply an analog feedback signal of the sigma-delta ADC to a second end of the second sampling impedance element, and in a second on-state, the switching circuit is configured to apply an analog feedback signal of the sigma-delta ADC to the second end of the second sampling impedance element. The switching circuit is configured to apply an analog input signal to the second end of the second sampling impedance element and to apply an analog feedback signal to the second end of the first sampling impedance element.

Description

Technical Field

[0001] This application generally relates to analog-to-digital converters (ADCs), and more specifically to speed adjustment devices and Σ-Δ ADC systems for Sigma-Delta (Σ-Δ) ADCs. Background Technology

[0002] Σ-Δ ADCs are widely used in the conversion and processing of various analog signals, such as audio recording and processing, sensor data acquisition (e.g., temperature, voltage, or pressure measurement), and signal modulation and demodulation. These applications often require high precision, high resolution, high integration, and low power consumption. Figure 1 An exemplary circuit diagram of a conventional Σ-Δ ADC circuit 100 is shown. Ideally, the two sampling resistors R1 and R2 of the circuit 100 are expected to have the same impedance value; however, due to the manufacturing process of the resistors themselves and the stray parameters of the circuit, the impedance values ​​of the two sampling resistors R1 and R2 may be different, causing errors in the Σ-Δ ADC output, i.e., resistor mismatch errors, which affect the output accuracy.

[0003] Therefore, it is necessary to eliminate this resistor mismatch error in order to achieve higher accuracy of the Σ-Δ ADC to meet application requirements. Summary of the Invention

[0004] According to one aspect of this disclosure, a speed adjustment device for a sigma-delta analog-to-digital converter (Σ-Δ ADC) is provided. The speed adjustment device includes: a clock signal generation circuit configured to generate two non-overlapping first and second clock signals, wherein the frequencies f of the first and second clock signals are... q f s / 2 N f s The sampling clock frequency of the Σ-Δ ADC is N, and N is a positive integer; a switching circuit is configured to periodically switch between a first on state and a second on state controlled by the first clock signal and the second clock signal, wherein a first terminal of the first sampling impedance element of the Σ-Δ ADC and a first terminal of the second sampling impedance element of the Σ-Δ ADC are connected to the reference voltage input terminal of the Σ-Δ ADC; and wherein, in the first on state, the switching circuit is configured to apply an analog input signal to the second terminal of the first sampling impedance element and apply an analog feedback signal of the Σ-Δ ADC to the second terminal of the second sampling impedance element, and in the second on state, the switching circuit is configured to apply the analog input signal to the second terminal of the second sampling impedance element and apply the analog feedback signal to the second terminal of the first sampling impedance element.

[0005] According to another aspect of this disclosure, a sigma-delta analog-to-digital converter (Σ-Δ ADC) system is also provided, comprising: a Σ-Δ ADC circuit; and a speed adjustment device for the Σ-Δ ADC as described above.

[0006] The speed adjustment device and Σ-Δ ADC system according to embodiments of this disclosure can periodically switch the connection mode of the two sampling impedance elements using a non-overlapping clock to achieve dynamic averaging of the sampling results. This technical solution essentially modulates low-frequency mismatch errors to high frequencies so that they can be filtered out by a low-pass filter at the back end, achieving high-precision analog-to-digital conversion while saving overall measurement time. Attached Figure Description

[0007] In the accompanying drawings, the same reference numerals denote the same or functionally similar elements in various views, and are incorporated in and form a part of the following detailed description to illustrate various embodiments and explain the various principles and advantages according to these embodiments. In the drawings:

[0008] Figure 1 An exemplary circuit diagram of a conventional Σ-Δ ADC circuit 100 is shown;

[0009] Figure 2 An exemplary circuit diagram of a Σ-Δ ADC system 200 according to an embodiment of the present disclosure is shown;

[0010] Figure 3 An exemplary circuit diagram of a Σ-Δ ADC system 300 according to one embodiment of the present disclosure is shown;

[0011] Figure 4 An exemplary circuit diagram of a two-phase non-overlapping clock generation circuit 400 according to an embodiment of the present disclosure is shown; and

[0012] Figure 5 Shown Figure 4 Timing diagram of the clock signal generated by the two-phase non-overlapping clock generation circuit 400. Detailed Implementation

[0013] It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of this disclosure. Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be considered limiting. The use of “comprising,” “including,” or “having,” and variations thereof, is intended to cover the items listed thereafter and their equivalents, as well as additional items. Unless otherwise limited, the term “connection” and its variations herein are used broadly and cover both direct and indirect connections, and may include electrical or physical connections.

[0014] Temperature detection devices are used to monitor the temperature of electronic devices, such as microprocessors. When the measured temperature exceeds a threshold, the temperature detection device warns the microprocessor, prompting it to take appropriate action, such as shutting down the microprocessor or limiting its performance to reduce the temperature. Failure to take timely and appropriate action can lead to overheating and catastrophic failure of the microprocessor. Therefore, obtaining accurate temperature readings is crucial for protecting electronic devices. Temperature detection devices typically utilize the relationship between the voltage across a diode and the ambient temperature to estimate the ambient temperature. An analog-to-digital converter (ADC) is usually used to measure the voltage across the diode separately. In scenarios involving two current-to-temperature measurements, four voltage measurements are required. However, due to resistor mismatch errors within the ADC, each voltage measurement requires two measurements and averaging, resulting in eight voltage measurements per temperature measurement, increasing measurement time. The present disclosure addresses this problem.

[0015] Figure 2 An exemplary circuit diagram of a Σ-Δ ADC system 200 according to an embodiment of this disclosure is shown. Figure 2 As shown, the Σ-Δ ADC system 200 includes a Σ-Δ ADC circuit 202 and a Σ-Δ ADC speed adjustment device 204. The Σ-Δ ADC circuit 200 includes a first sampling impedance element Z1 and a second sampling impedance element Z2, an integration quantization module ʃ+Qntz., a digital-to-analog converter module DAC, and an inverter INV. The output of the Σ-Δ ADC circuit 200 is sequentially connected to the inverter INV and the digital-to-analog converter module DAC to convert the output Vout of the Σ-Δ ADC circuit 200 into an analog feedback signal Vfb. According to some embodiments of this disclosure, the DAC may be a 1-bit DAC, i.e., the output is a positive reference voltage (e.g., power supply voltage) when the input is 1 and a negative reference voltage (e.g., ground voltage, such as 0V) when the input is 0. The first terminal of the first sampling impedance element Z1 and the first terminal of the second sampling impedance element Z2 are connected to the reference voltage input terminal of the Σ-Δ ADC, which is the input terminal of the integration quantization module ʃ+Qntz. and has a reference voltage Vref (e.g., typically half of the power supply voltage). The output of the Σ-Δ ADC circuit 202 is input to a back-end filter (not shown) to obtain the filtered measurement value.

[0016] The speed adjustment device 204 of the Σ-Δ ADC includes a clock signal generation circuit CLK_GEN and a switching circuit 205. The clock signal generation circuit CLK_GEN generates two non-overlapping first clock signals CLK1 and CLK2 (i.e., the high-level portions of the first clock signal CLK1 and the second clock signal CLK2 do not overlap), wherein the frequencies f of the first clock signal CLK1 and the second clock signal CLK2 are... q f s / 2 N , where f s Let be the sampling clock frequency of the Σ-Δ ADC. Figure 5 The timing diagrams for the first clock signal CLK1 and the second clock signal CLK2 are shown. Figure 5 As shown, the high-level portions of the first clock signal CLK1 and the second clock signal CLK2 do not overlap; that is, when one clock signal is high, the other clock signal must be low. For example, when N=1, assuming that the Σ-Δ ADC performs one measurement with 1000 sampling clock cycles, the first clock signal CLK1 and the second clock signal CLK2 alternately remain at a high level for approximately 500 sampling clock cycles.

[0017] The switching circuit 205 includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. The first terminal of the first switch SW1 receives the analog input signal Vin, and the second terminal of the first switch SW1 is connected to the second terminal of the first sampling impedance element Z1. The first terminal of the second switch SW2 receives the analog feedback signal Vfb, and the second terminal of the second switch SW2 is connected to the second terminal of the second sampling impedance element Z2. The first terminal of the third switch SW3 receives the analog feedback signal Vfb, and the second terminal of the third switch SW3 is connected to the second terminal of the first sampling impedance element Z1. The first terminal of the fourth switch SW4 receives the analog input signal Vin, and the second terminal of the fourth switch SW4 is connected to the second terminal of the second sampling impedance element Z2. Furthermore, a first clock signal CLK1 is input to the control terminals of the first switch SW1 and the second switch SW2 to control the on / off states of the first and second switches; a second clock signal CLK2 is input to the control terminals of the third switch SW3 and the fourth switch SW4 to control the on / off states of the third and fourth switches.

[0018] It should be noted that Figure 2 The Σ-Δ ADC system 200 shown is merely an example. In reality, the Σ-Δ ADC system 200 may include more or fewer modules or components, without limitation.

[0019] The switching circuit 205 is controlled by a first clock signal CLK1 and a second clock signal CLK2, periodically switching between a first on state and a second on state. Specifically, in the first on state, the first clock signal CLK1 is high and the second clock signal CLK2 is low, causing the first switch SW1 and the second switch SW2 to be turned on and the third switch SW3 and the fourth switch SW4 to be turned off. This allows the analog input signal Vin to be applied to the second terminal of the first sampling impedance element Z1 and the analog feedback signal Vfb to be applied to the second terminal of the second sampling impedance element Z2. In the second on state, the first clock signal CLK1 is low and the second clock signal CLK2 is high, causing the first switch SW1 and the second switch SW2 to be turned off and the third switch SW3 and the fourth switch SW4 to be turned on. This allows the analog feedback signal Vfb to be applied to the second terminal of the first sampling impedance element Z1 and the analog input signal Vin to be applied to the second terminal of the second sampling impedance element Z2. Controlling the switching circuit with a non-overlapping clock prevents capacitor leakage within the Σ-Δ ADC's integration and quantization module ʃ+Qntz.

[0020] During the quantization process of one analog input of the Σ-Δ ADC, by controlling the periods of the first clock signal CLK1 and the second clock signal CLK2, the switching circuit 205 is continuously in the first on state during the first half of the sampling clock cycle to obtain the first quantization result of the Σ-Δ ADC, and continuously in the second on state during the second half of the sampling clock cycle to obtain the second quantization result of the Σ-Δ ADC. The two quantization results are averaged to obtain the final quantization result after eliminating impedance mismatch error. For example, when the Σ-Δ ADC samples and quantizes an analog input over 1000 sampling clock cycles, the first clock signal CLK1 can remain high and the second clock signal CLK2 can remain low for the first 500 sampling clock cycles, and the first clock signal CLK1 can remain low and the second clock signal CLK2 can remain high for the next 500 sampling clock cycles. This allows the switching circuit 205 to be continuously in the first ON state for the first 500 sampling clock cycles to obtain the first quantization result of the Σ-Δ ADC, and continuously in the second ON state for the next 500 sampling clock cycles to obtain the second quantization result of the Σ-Δ ADC. This Σ-Δ ADC measurement method is also referred to as the static measurement method in this paper. In the static measurement method, when the switching circuit 205 is in the first ON state and the output Vout of the Σ-Δ ADC is high, the current I1 flowing into the reference voltage input terminal can be calculated according to the following formula (1):

[0021] Formula (1)

[0022] Wherein, R1 is the impedance value of the first sampling impedance element Z1, and R2 is the impedance value of the second sampling impedance element Z2.

[0023] When the switching circuit 205 is in the first ON state and the output Vout of the Σ-Δ ADC is low, the current I2 flowing into the reference voltage input terminal can be calculated according to the following formula (2):

[0024] Formula (2)

[0025] Where VDD is the power supply voltage.

[0026] In steady state, the current flowing into and out of the reference voltage input terminal is equal, that is, the currents satisfy the following formula (3):

[0027] Formula (3)

[0028] Where A represents the proportion of high-level outputs in multiple ADC cycles.

[0029] When the oversampling rate is sufficiently large, the quantization noise of the Σ-Δ ADC output is very small. The filtered output Y1 of the Σ-Δ ADC can be calculated according to formulas (1)-(3) to obtain the following formula (4):

[0030] Formula (4)

[0031] Assuming the impedance mismatch is R E R1=RR E R² = R + R E Where R is the desired ideal impedance value, then the error caused by impedance mismatch is... It can be calculated using the following formula (5):

[0032] Formula (5)

[0033] In static measurement mode, when the switching circuit 205 is in the second on state, the filtered output Y2 of the Σ-Δ ADC can be calculated according to formula (6):

[0034] Formula (6)

[0035] The average of the two output measurements It can be calculated using the following formula (7):

[0036] Formula (7)

[0037] Therefore, the average of the two output measurements caused by impedance mismatch is taken. Error can be calculated according to the following formula (8):

[0038] Formula (8)

[0039] Since usually R E < R / 10, so , reducing the error of the Σ-Δ ADC output.

[0040] However, in the above static measurement method, the switch circuit is continuously in the first on state in the first half of the sampling clock cycle to obtain the first quantization result, and continuously in the second on state in the second half of the sampling clock cycle to obtain the second quantization result, and the average of the two quantization results is taken to obtain the final quantization result that eliminates the impedance mismatch error. Two samplings and averaging are required, and the sampling time is nearly doubled.

[0041] Some embodiments of the present disclosure propose to control the periods / frequencies of the first clock signal CLK1 and the second clock signal CLK2, so that the first clock signal CLK1 and the second clock signal CLK2 alternately cycle to be in the high level state, and further make the switch circuit alternately cycle to be in the first on state and the second on state, so as to achieve dynamic averaging of the measurement results without measuring twice and taking the average value.

[0042] The input spectrum of the analog input signal Vin can be regarded as an ideal mismatch-free part plus a mismatch error part , as shown in the following formula (9):

[0043] Formula (9)

[0044] After dynamic averaging, the spectrum of the ideal mismatch-free part remains unchanged, while the spectrum of the mismatch error part can be calculated according to the following formula (10):

[0045] Formula (10)

[0046] Where is the clock period of the first clock signal CLK1 and the second clock signal CLK2, . It can be seen from formula (10) that the spectrum of the input error is periodically extended centered on f q . In other words, the low-frequency mismatch error is modulated to high frequency, so that the high-frequency error can be easily filtered by the low-pass filter at the backend of the Σ-Δ ADC. In some embodiments of the present disclosure, the frequencies f q of the first clock signal CLK1 and the second clock signal CLK2 are greater than or equal to 2*f adcmax, where f adcmax This is the cutoff frequency of the low-pass filter to achieve good filtering of mismatch errors. Furthermore, according to the sampling theorem, the frequencies f of the first clock signal CLK1 and the second clock signal CLK2 are... q Greater than 2*f inmax , where f inmax To simulate the maximum frequency of the input signal Vin, a higher sampling frequency is used to disperse the quantization noise across a wider frequency band, thereby reducing the noise density within the signal bandwidth. This avoids frequency aliasing between the ideal mismatch-free portion and the mismatch error portion. Furthermore, f adcmax Greater than f inmax This is to avoid filtering out analog input signals.

[0047] The dynamic averaging measurement method improves the accuracy of the measurement results by modulating the mismatch error to a high frequency for filtering, and saves measurement time by eliminating the need to average two measurements.

[0048] Taking a first-order Σ-Δ ADC as an example, the signal-to-noise ratio (SNR) of the measurement result can be calculated according to the following formula (11):

[0049] Formula (11)

[0050] Where OSR is the oversampling rate and B is the number of bits in the ADC. As can be seen from formula (11), the higher the oversampling rate, the higher the signal-to-noise ratio (SNR). Furthermore, the oversampling rate is directly related to the number of quantizations within one sampling clock cycle. Therefore, dynamic averaging can ensure that the number of quantizations is consistent with the single measurement of static averaging, without loss of accuracy, and is twice as fast. For example, compared to averaging two 500-sampling-clock-cycle static measurements, dynamic averaging over 1000 sampling clock cycles doubles the oversampling rate, increases the SNR by 9 dB, and improves accuracy by 1.5 bits. Moreover, dynamic averaging over 1000 sampling clock cycles is twice as fast as averaging two 1000-sampling-clock-cycle static measurements.

[0051] In summary, the embodiments disclosed herein can improve measurement accuracy within the same measurement time, or double the measurement speed without sacrificing accuracy. Furthermore, the embodiments disclosed herein do not require an excessive number of components, have low power consumption and small footprint, simple structure, and high reliability.

[0052] In some embodiments of this disclosure, the first sampling impedance element Z1 and the second sampling impedance element Z2 can be resistive elements. That is, in this example, Figure 2The first sampling impedance element Z1 and the second sampling impedance element Z2 can be regarded as resistive elements, while maintaining their connection relationship with other elements. However, in other embodiments of this disclosure, the first sampling impedance element Z1 and the second sampling impedance element Z2 can be switched capacitor elements. Figure 3 An exemplary circuit diagram of a Σ-Δ ADC system 300 according to one embodiment of the present disclosure is shown, wherein the first sampling impedance element Z1 and the second sampling impedance element Z2 are switched capacitor elements. The Σ-Δ ADC system 300 is compared with a reference... Figure 2 The Σ-Δ ADC system 200 described is similar, and the identical parts will not be repeated here. The Σ-Δ ADC system 300 uses switched capacitor elements as the first sampling impedance element Z1 and the second sampling impedance element Z2. For example... Figure 3 As shown, the first sampling impedance element Z1 includes a first capacitor C1, a fifth switch SW5, and a sixth switch SW6. The first terminal of the fifth switch SW5 is connected to the second terminal of the first switch SW1 and the second terminal of the third switch SW3. The second terminal of the fifth switch SW5 is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is grounded. The first terminal of the sixth switch SW6 is connected to the first terminal of the first capacitor C1, and the second terminal of the sixth switch SW6 is connected to the reference voltage input terminal. Furthermore, the second sampling impedance element Z2 includes a second capacitor C2, a seventh switch SW7, and an eighth switch SW8. The first terminal of the eighth switch SW8 is connected to the second terminal of the second switch SW2 and the second terminal of the fourth switch SW4. The second terminal of the eighth switch SW8 is connected to the first terminal of the second capacitor C2, and the second terminal of the second switch C2 is grounded. The first terminal of the seventh switch SW7 is connected to the first terminal of the second capacitor C2, and the second terminal of the seventh switch SW7 is connected to the reference voltage input terminal. The fifth switch SW5 and the sixth switch SW6 are alternately turned on, and the seventh switch SW7 and the eighth switch SW8 are alternately turned on. The switching cycles of the fifth to eighth switches SW5, SW6, SW7, and SW8 are determined by the magnitude of the equivalent impedance and the capacitance values ​​of the first capacitor C1 and the second capacitor C2.

[0053] Figure 4 An exemplary circuit diagram of a two-phase non-overlapping clock generation circuit 400 according to an embodiment of the present disclosure is shown. Figure 4As shown, the two-phase non-overlapping clock generation circuit 400 includes a first inverter INV1, a first NAND gate NAND1, a second NAND gate NAND2, a second inverter INV2, a third inverter INV3, 2M first delay inverters Delay_INV1, and 2M second delay inverters Delay_INV2, where M is a positive integer. The input of the first inverter INV1 is used to receive the reference clock signal CLK_ref. The first input of the first NAND gate NAND1 is connected to the input of the first inverter INV1. The second input of the second NAND gate NAND2 is connected to the output INV1 of the first inverter. The input of the second inverter INV2 is connected to the first input of the second NAND gate NAND2. 2M first delay inverters Delay_INV1 are connected between the output of the first NAND gate NAND1 and the input of the second inverter INV2. 2M second delay inverters Delay_INV2 are connected between the output of the second NAND gate NAND2 and the input of the third inverter. The number of first delay inverters Delay_INV1 and second delay inverters Delay_INV2 is determined based on the non-overlapping time between the high levels of the first clock signal CLK1 and the second clock signal CLK2, and this number is an integer multiple of 2.

[0054] pass Figure 4 The two-phase non-overlapping clock generation circuit 400 shown can generate clocks such as... Figure 5 The first clock signal CLK1 and the second clock signal CLK2 are shown. However, those skilled in the art will understand that the clock signal generation circuit CLK_GEN of this disclosure is not limited to... Figure 4 The two-phase non-overlapping clock generation circuit 400 shown can be replaced by any circuit capable of generating two-phase non-overlapping clocks (e.g., Figure 5 The clock generation circuit for the first clock signal CLK1 and the second clock signal CLK2 shown.

[0055] The basic principles of this disclosure have been described above with reference to specific embodiments. It should be noted that the advantages, benefits, and effects mentioned in the embodiments of this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations; these details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details. It should also be noted that in the apparatus of this disclosure, the components can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered equivalent solutions of this disclosure.

[0056] It will be understood by one of ordinary skill in the art that all or any part of the methods and apparatus of this disclosure can be implemented in hardware, firmware, software, or a combination thereof in any computing device (including processors, storage media, etc.) or network of computing devices. Hardware can be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but alternatively, it can be any commercially available processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration. Software can reside in any form of computer-readable tangible storage medium. By way of example and not limitation, such computer-readable tangible storage media can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other tangible medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a computer. If used herein, the discs include compact discs (CDs), laser discs, optical discs, digital universal discs (DVDs), floppy discs, and Blu-ray discs.

[0057] The block diagrams of elements, components, devices, apparatuses, and systems involved in the embodiments of this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these elements, components, devices, apparatuses, and systems can be connected, arranged, and configured in any manner.

[0058] Furthermore, the scope of protection claimed in this disclosure is not limited to the specific aspects of the processing, machinery, manufacture, event composition, means, methods, and actions described above. There are currently existing or later-developed processing, machinery, manufacture, event composition, means, methods, or actions that can perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein.

[0059] Furthermore, words such as “including,” “contains,” and “has” are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The words “or” and “and” as used here refer to the words “and / or,” and are used interchangeably with them unless the context explicitly indicates otherwise. The word “such as” as used here refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0060] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A speed adjustment device for a sigma-delta analog-to-digital converter (Σ-Δ ADC), comprising: A clock signal generation circuit is configured to generate a first clock signal and a second clock signal that are two non-overlapping phases, wherein the frequencies f of the first clock signal and the second clock signal are... q f s / 2 N f s Let N be the sampling clock frequency of the Σ-Δ ADC, and N be a positive integer; The switching circuit is configured to periodically switch between a first ON state and a second ON state, controlled by the first clock signal and the second clock signal. Wherein, the first terminal of the first sampling impedance element of the Σ-Δ ADC and the first terminal of the second sampling impedance element of the Σ-Δ ADC are connected to the reference voltage input terminal of the Σ-Δ ADC; and In the first ON state, the switching circuit is configured to apply an analog input signal to the second terminal of the first sampling impedance element and apply the analog feedback signal of the Σ-Δ ADC to the second terminal of the second sampling impedance element; and in the second ON state, the switching circuit is configured to apply the analog input signal to the second terminal of the second sampling impedance element and apply the analog feedback signal to the second terminal of the first sampling impedance element.

2. The apparatus of claim 1, wherein the switching circuit comprises: A first switch, wherein a first end of the first switch is used to receive the analog input signal and a second end of the first switch is connected to the second end of the first sampling impedance element; A second switch, wherein a first end of the second switch is used to receive the analog feedback signal and a second end of the second switch is connected to the second end of the second sampling impedance element; A third switch, wherein the first end of the third switch is used to receive the analog feedback signal and the second end of the third switch is connected to the second end of the first sampling impedance element; as well as, A fourth switch, wherein the first terminal of the fourth switch is used to receive the analog input signal and the second terminal of the fourth switch is connected to the second terminal of the second sampling impedance element. The on / off state of the first switch and the second switch is controlled by the first clock signal, and the on / off state of the third switch and the fourth switch is controlled by the second clock signal.

3. The apparatus according to claim 1 or 2, wherein the first sampling impedance element and the second sampling impedance element are resistive elements.

4. The apparatus according to claim 1 or 2, wherein the first sampling impedance element and the second sampling impedance element are switched capacitor elements.

5. The apparatus of claim 4, wherein the first sampling impedance element comprises a first capacitor, a fifth switch, and a sixth switch, a first terminal of the fifth switch being connected to a second terminal of the first switch and a second terminal of the third switch, a second terminal of the fifth switch being connected to a first terminal of the first capacitor, a second terminal of the first capacitor being grounded, a first terminal of the sixth switch being connected to a first terminal of the first capacitor, and a second terminal of the sixth switch being connected to the reference voltage input terminal of the Σ-Δ ADC; and The second sampling impedance element includes a second capacitor, a seventh switch, and an eighth switch. The first terminal of the eighth switch is connected to the second terminal of the second switch and the second terminal of the fourth switch. The second terminal of the eighth switch is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded. The first terminal of the seventh switch is connected to the first terminal of the second capacitor, and the second terminal of the seventh switch is connected to the reference voltage input terminal of the Σ-Δ ADC.

6. The apparatus according to claim 1 or 2, wherein the frequencies f of the first clock signal and the second clock signal are... q Greater than 2*f inmax , where f inmax The maximum value of the signal frequency of the analog input signal.

7. The apparatus of claim 1 or 2, wherein the output of the Σ-Δ ADC is input to a low-pass filter, and the frequencies f of the first clock signal and the second clock signal are... q Greater than or equal to 2*f adcmax , where f adcmax This is the cutoff frequency of the low-pass filter.

8. The apparatus according to claim 1 or 2, wherein the output of the Σ-Δ ADC is sequentially connected to an inverter and a digital-to-analog converter (DAC) to convert the output of the Σ-Δ ADC into the analog feedback signal.

9. The apparatus according to claim 1 or 2, wherein, The clock signal generation circuit includes: The first inverter, the input of which is used to receive a reference clock signal; The first NAND gate, the first input of the first NAND gate is connected to the input of the first inverter; The second NAND gate, the second input of the second NAND gate is connected to the output of the first inverter; A second inverter, the input of which is connected to the first input of the second NAND gate; and A third inverter, wherein the input terminal of the third inverter is connected to the second input terminal of the first NAND gate; 2M first delay inverters are connected between the output of the first NAND gate and the input of the second inverter, where M is a positive integer; and Two million second delay inverters are connected between the output of the second NAND gate and the input of the third inverter. The second inverter outputs the first clock signal, and the third inverter outputs the second clock signal.

10. A sigma-delta analog-to-digital converter (Σ-Δ ADC) system, comprising: Σ-Δ ADC circuit; as well as The speed adjustment device for a Σ-Δ ADC according to any one of claims 1 to 9.

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