Semiconductor structure

Abstract

A semiconductor structure according to the present disclosure includes a backside metal line, a backside dielectric layer over the backside metal line, a first source / drain feature and a second source / drain feature over the backside dielectric layer, a first backside contact extending through the backside dielectric layer to couple to a bottom surface of the first source / drain feature, and a second backside contact extending through the backside dielectric layer to couple to a bottom surface of the second source / drain feature. A first backside contact extending through the backside dielectric layer to couple to a bottom surface of the first source / drain feature, a second backside contact extending through the backside dielectric layer to couple to a bottom surface of the second source / drain feature, a dielectric layer disposed over the backside dielectric layer, the first source / drain feature and the second source / drain feature, a common contact extending through the dielectric layer to electrically couple to the first source / drain feature and the second source / drain feature, and an etch stop layer disposed over and in contact with the dielectric layer and the common contact. The common contact is not electrically coupled to any conductive feature extending through the etch stop layer.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures. Background Technology

[0002] The electronics industry's growing demand for smaller, faster electronic devices capable of supporting increasingly complex and multifaceted functions has fueled a sustained trend in the semiconductor industry towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest component size), thereby increasing production efficiency and reducing associated costs. However, this shrinkage has also increased the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar progress in semiconductor manufacturing processes and technologies.

[0003] Static Random Access Memory (“SRAM”) generally refers to any memory or memory device that retains stored data only when powered on. As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate structures, such as FinFETs or Gate All-Around (GAA) transistors, are integrated into SRAM cells to improve performance. As the size of SRAM cells continues to shrink, the contact structures of the transistors functionally interconnecting the SRAM cells present additional challenges in reducing resistance (R) and capacitance (C). Summary of the Invention

[0004] According to one aspect of the embodiments of this application, a semiconductor structure is provided, comprising: a back-side metal line; a back-side dielectric layer located above the back-side metal line; a first source / drain component and a second source / drain component located on the back-side dielectric layer; a first back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the first source / drain component; a second back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the second source / drain component; a dielectric layer disposed above the back-side dielectric layer, the first source / drain component, and the second source / drain component; a common contact extending through the dielectric layer to be electrically coupled to the first source / drain component and the second source / drain component; and an etch stop layer disposed above the dielectric layer and the common contact and in contact with the dielectric layer and the common contact, wherein the common contact is not electrically coupled to any conductive component extending through the etch stop layer.

[0005] According to another aspect of the embodiments of this application, a semiconductor structure is provided, comprising: a back-side metal line extending along a first direction; a back-side dielectric layer located above the back-side metal line; a first gate structure and a second gate structure located above the back-side dielectric layer and extending longitudinally along a second direction perpendicular to the first direction; an isolation structure disposed above the back-side dielectric layer and sandwiched between the first gate structure and the second gate structure along the first direction; a dielectric layer located above and in contact with the isolation structure; a contact member extending through the dielectric layer and partially extending into the isolation structure; and an etch stop layer located above the top surface of the dielectric layer and the top surface of the contact member and in contact with the top surface of the dielectric layer and the top surface of the contact member; wherein the contact member is not electrically coupled to any conductive member extending through the etch stop layer.

[0006] According to another aspect of the embodiments of this application, a semiconductor structure is provided, comprising: a back-side metal line; a back-side dielectric layer located above the back-side metal line; a first n-type epitaxial member and a second n-type epitaxial member located above the back-side dielectric layer; a first back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the first n-type epitaxial member; a second back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the second n-type epitaxial member; a dielectric layer disposed above the back-side dielectric layer, the first n-type epitaxial member, and the second n-type epitaxial member; a common contact extending through the dielectric layer to be electrically coupled to the first n-type epitaxial member and the second n-type epitaxial member; and an etch stop layer disposed above and in contact with the top surface of the dielectric layer and the top surface of the common contact, wherein the common contact is not electrically coupled to any conductive member extending through the etch stop layer, and wherein the lower portion of the common contact extends between the first n-type epitaxial member and the second n-type epitaxial member. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 This is a circuit diagram of an SRAM cell according to various aspects of this disclosure.

[0009] Figure 2 This is a top view of an SRAM cell according to various aspects of this disclosure.

[0010] Figure 3 This is a partial top view of the front-side interconnect structure of an SRAM quad cell according to various aspects of this disclosure.

[0011] Figure 4 It is based on the various aspects of this disclosure. Figure 3 Partial cross-sectional view of midsection A-A'.

[0012] Figure 5 It is based on the various aspects of this disclosure. Figure 3 Partial cross-sectional view of midsection B-B'.

[0013] Figure 6 Based on all aspects of this disclosure Figure 3 A partial top view of the source / drain contact structure (MD / VD) of a four-cell SRAM.

[0014] Figure 7 Based on all aspects of this disclosure Figure 3 A partial top view of the first metal layer (M0) of a four-cell SRAM.

[0015] Figure 8 Based on all aspects of this disclosure Figure 3 A partial top view of the second metal layer (M1) of a four-cell SRAM.

[0016] Figure 9 Based on all aspects of this disclosure Figure 3 A partial top view of the third metal layer (M2) of a quad SRAM cell.

[0017] Figure 10 Based on all aspects of this disclosure Figure 3 A partial top view of the fourth metal layer (M3) of a quad SRAM cell.

[0018] Figure 11 According to the first embodiment of this disclosure Figure 3 A partial cross-sectional view of section A-A'.

[0019] Figure 12 According to the first embodiment of this disclosure Figure 3 A partial cross-sectional view of section B-B'.

[0020] Figure 13 According to the first embodiment of this disclosure Figure 3 A partial top view of the source / drain structure (MD / VD) of a four-cell SRAM.

[0021] Figure 14 According to the first embodiment of this disclosure Figure 3 A partial top view of the first metal layer (M0) of a four-cell SRAM.

[0022] Figure 15 According to the first embodiment of this disclosure Figure 3A partial top view of the second metal layer (M1) of a four-cell SRAM.

[0023] Figure 16 According to the first embodiment of this disclosure Figure 3 A partial top view of the third metal layer (M2) of a quad SRAM cell.

[0024] Figure 17 According to the first embodiment of this disclosure Figure 3 A partial top view of the fourth metal layer (M3) of a quad SRAM cell.

[0025] Figure 18 According to the second embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0026] Figure 19 According to the second embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection B-B'.

[0027] Figure 20 According to the second embodiment of this disclosure Figure 3 A partial top view of the source / drain structure (MD / VD) of a four-cell SRAM.

[0028] Figure 21 According to the third embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0029] Figure 22 According to the third embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection B-B'.

[0030] Figure 23 According to the third embodiment of this disclosure Figure 3 A partial top view of the first metal layer (M0) of a four-cell SRAM.

[0031] Figure 24 According to the fourth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0032] Figure 25 According to the fourth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection B-B'.

[0033] Figure 26 According to the fourth embodiment of this disclosure Figure 3 A partial top view of the second metal layer (M1) of a four-cell SRAM.

[0034] Figure 27 According to the fifth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0035] Figure 28 According to the fifth embodiment of this disclosure Figure 3 Partial cross-sectional view of the midsection B-B'.

[0036] Figure 29 According to the fifth embodiment of this disclosure Figure 3 A partial top view of the third metal layer (M2) of a quad SRAM cell.

[0037] Figure 30 According to the sixth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0038] Figure 31 According to the sixth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection B-B'.

[0039] Figure 32 According to the sixth embodiment of this disclosure Figure 3 A partial top view of the fourth metal layer (M3) of a quad SRAM cell.

[0040] Figure 33 According to the seventh embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0041] Figure 34 According to the eighth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection B-B'.

[0042] Figure 35 According to the eighth embodiment of this disclosure Figure 3 A partial top view of the source / drain structure (MD / VD) of a four-cell SRAM.

[0043] Figure 36 According to the eighth embodiment of this disclosure Figure 3 A partial top view of the first metal layer (M0) of a four-cell SRAM.

[0044] Figure 37 According to the eighth embodiment of this disclosure Figure 3 A partial top view of the second metal layer (M1) of a four-cell SRAM.

[0045] Figure 38 According to the eighth embodiment of this disclosure Figure 3 A partial top view of the third metal layer (M2) of a quad SRAM cell.

[0046] Figure 39According to the eighth embodiment of this disclosure Figure 3 A partial top view of the fourth metal layer (M3) of a quad SRAM cell.

[0047] Figure 40 According to the ninth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0048] Figure 41 According to the ninth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection B-B'.

[0049] Figure 42 According to the tenth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection A-A'.

[0050] Figure 43 According to the tenth embodiment of this disclosure Figure 3 Partial cross-sectional view of midsection B-B'. Detailed Implementation

[0051] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0052] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0053] Furthermore, when using terms such as "about," "approximately," etc., to describe numbers or ranges of numbers, the term is intended to encompass a reasonable range resulting from inherent variations in the manufacturing process, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with the number, the number or range includes a reasonable range that includes the described number, such as within + / - 10% of the described number. For instance, a material layer with a thickness of "about 5 nm" can include a size range of 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. In describing transistors, the source / drain regions may be referred to individually or collectively as source or drain, depending on the context.

[0054] Static Random Access Memory (SRAM) is a type of semiconductor memory that retains data in a static form as long as the memory is powered. Compared to Dynamic Random Access Memory (DRAM), SRAM is faster, more reliable, and does not require refreshing. SRAM is widely used in many applications, such as cache memory in computers and the random access memory portion of digital-to-analog converters in video cards. As integrated circuit (IC) technology advances towards smaller technology nodes, multi-gate structures, such as FinFETs or gate-all-around (GAA) transistors, are integrated into SRAM cells to improve performance. This shrinking size puts stress on electrical wiring. When only front-side interconnects exist, the tight spacing of contact vias and metal lines can exhibit high resistance at the front-side connections to the various transistor nodes within the SRAM cell. This tight spacing and high contact resistance can lead to high resistance and capacitance, which can result in low drive current and low speed.

[0055] This disclosure provides an SRAM device that includes not only front-side interconnects but also back-side interconnects to improve SRAM device performance. In one embodiment, the source of a pull-down transistor is coupled to a back-side ground rail via a back-side contact to improve pull-down current, while the source region of a transmission gate transistor is not coupled to the back-side ground rail. To reduce the resistance and capacitance of the front-side contact structure, some or all of the front-side contact structures electrically coupled to the source of the pull-down transistor can be omitted. In one embodiment, although a common source contact is formed to couple to the source of the pull-down transistor, no conductive parts are formed to physically contact the top surface of the common source contact. Omitting the front-side contact structure allows for wider metal lines or greater spacing between metal lines.

[0056] Figure 1 An example type of memory device is shown, in which transistors such as planar transistors, FinFET transistors, or gate-all-around (GAA) transistors can be implemented. Embodiments described in this disclosure include GAA transistors. Figure 1A circuit schematic of an example SRAM device is shown, for example, as a single-port SRAM cell (e.g., a 1-bit SRAM cell) 10. The single-port SRAM cell 10 includes first and second transmission gate transistors PG1 and PG2, first and second pull-up transistors PU1 and PU2, and first and second pull-down transistors PD1 and PD2. The gates of the first and second transmission gate transistors PG1 and PG2 are electrically coupled to a word line (WL) that determines whether the SRAM cell 10 is selected. In the SRAM cell 10, memory bits (e.g., latches or flip-flops) are formed by the first and second pull-up transistors PU1 and PU2 and the first and second pull-down transistors PD1 and PD2 to store bits of data. The complementary values ​​of these bits are stored in a first storage node SN1 and a first complementary storage node SNB1. The stored bits can be written to or read from the SRAM cell 10 via bit lines (BL) and anti-phase lines (BLB). In this arrangement, BL and BLB can carry complementary bit line signals. The SRAM cell 10 is powered by a positive supply voltage Vdd and is also connected to ground potential Vss.

[0057] SRAM cell 10 includes a first inverter 12 formed by a first pull-up transistor PU1 and a first pull-down transistor PD1, and a second inverter 14 formed by a second pull-up transistor PU2 and a second pull-down transistor PD2. For example... Figure 1 As shown, the drains of the first pull-up transistor PU1 and the first pull-down transistor PD1 are coupled together, and the drains of the second pull-up transistor PU2 and the second pull-down transistor PD2 are also coupled together. The first inverter 12 and the second inverter 14 are coupled between the positive power supply voltage Vdd and the ground potential Vss. Figure 1 As shown, the first inverter 12 and the second inverter 14 are cross-coupled. That is, the input of the first inverter 12 is connected to the output of the second inverter 14. Similarly, the input of the second inverter 14 is connected to the output of the first inverter 12. The output of the first inverter 12 is referred to as the first storage node SN1. Similarly, the output of the second inverter 14 is referred to as the first complementary storage node SNB1. In normal operating mode, the first storage node SN1 is in the opposite logic state (logic high or logic low) to the first complementary storage node SNB1. By employing two cross-coupled inverters, the SRAM cell 10 can use a latching structure to retain data, so that the stored data will not be lost as long as it is powered by Vdd without applying a refresh cycle.

[0058] Now for reference Figure 2 It shows Figure 1 Example layout of SRAM cell 10. (Compared to...) Figure 1 Similar to SRAM cell 10 in the example, Figure 2The layout includes six (6) transistors, which are respectively used as a first transmission gate transistor PG1, a second transmission gate transistor PG2, a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2. Figure 2 In some embodiments shown, the SRAM cell 10 may be formed on an n-type well 32 (or n-well 32) sandwiched between two p-type wells 30 and 34 (or p-wells 30 and 34). The N-well 32 and p-wells 30, 34 are formed on the substrate by an ion implantation process. In some embodiments, such as Figure 2 As shown, the first transmission gate transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second transmission gate transistor PG2 can be formed on P-wells 30 and 34; the first pull-up transistor PU1 and the second pull-up transistor PU2 are formed in N-well 32. In these embodiments, the first transmission gate transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second transmission gate transistor PG2 are n-type GAA transistors; the first pull-up transistor PU1 and the second pull-up transistor PU2 are p-type GAA transistors.

[0059] In some embodiments, the SRAM cell 10 includes four fin-shaped vertical stacks—a first fin-shaped vertical stack 40, a second fin-shaped vertical stack 42, a third fin-shaped vertical stack 44, and a fourth fin-shaped vertical stack 46. The first fin-shaped vertical stack 40 is formed over the P-well 30 and forms the channel regions for the first transmission gate transistor PG1 and the first pull-down transistor PD1. The second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 are formed over the N-well 32 and form the channel regions for the first pull-up transistor PU1 and the second pull-up transistor PU2, respectively. The fourth fin-shaped vertical stack 46 is formed over the P-well 34 and forms the channel regions for the second pull-down transistor PD2 and the second transmission gate transistor PG2. Each of the first, second, third, and fourth fin-shaped vertical stacks 40, 42, 44, and 46 may include about two (2) to about ten (10) channel members. In some embodiments, each of the first, second, third, and fourth fin-shaped vertical stacks 40, 42, 44, and 46 includes three channel members. Each of the first, second, third, and fourth finned vertical stacks 40, 42, 44, and 46 can be referred to as an active region. For each GAA transistor described herein, the channel member in the vertical stack extends between two source / drain components. Because the source / drain components are formed using epitaxial processes, such as molecular beam epitaxy (MBE) or vapor phase epitaxy (VPE), they can also be referred to as epitaxial components.

[0060] In some cases, fin-shaped vertical stacks can be formed by depositing or epitaxially growing alternating layers of two different semiconductor materials, patterning the alternating layers to form fin structures, and selectively removing layers formed from one of the two semiconductor materials. For example, alternating layers of epitaxially grown silicon (Si) and silicon germanium (SiGe) can be formed on a substrate. The substrate can be a silicon (Si) substrate. The alternating layers can then be patterned to form fin structures comprising stacks of staggered Si strips and SiGe strips. In the process of forming transistor channel regions in an SRAM cell, the channel regions of the fin structure can undergo different etching processes to selectively remove the SiGe strips, releasing the silicon layer as suspended silicon channel members. The channel members can take on different shapes and sizes and can be referred to as nanostructures, nanowires, or nanosheets. These fin structures are separated by isolation components (e.g., shallow trench isolation (STI) components). In some embodiments, each fin-shaped vertical stack can include a top formed from the alternating layers and a base formed from the substrate. The base of the fin-shaped vertical stack has a fin shape and can be referred to as a fin structure or base fin. The base of the fin-shaped vertical stack can be substantially embedded in the isolation member, and the top of the base of the fin-shaped vertical stack can be flush with the top surface of the isolation member. The top of the fin-shaped vertical stack extends from and is higher than the isolation member.

[0061] Still referencing Figure 2 The channel members in the first fin-shaped vertical stack 40 form the channel regions of the first transmission gate transistor PG1 and the first pull-down transistor PD1. The channel members in the second fin-shaped vertical stack 42 form the channel region of the first pull-up transistor PU1. The channel members in the third fin-shaped vertical stack 44 form the channel region of the second pull-up transistor PU2. The channel members in the fourth fin-shaped vertical stack 46 form the channel regions of the second pull-down transistor PD2 and the second transmission gate transistor PG2. In the depicted embodiment, the first fin-shaped vertical stack 40 and the fourth fin-shaped vertical stack 46 are used to form an n-type GAA transistor, and the second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 are used to form a p-type GAA transistor. Figure 2 In the illustrated embodiment, the first transmission gate transistor PG1, the first pull-down transistor PD1, the second transmission gate transistor PG2, and the second pull-down transistor PD2 are n-type GAA transistors, and the first pull-up transistor PU1 and the second pull-up transistor PU-2 are p-type GAA transistors. Figure 2In this configuration, each of the first fin vertical stack 40 and the fourth fin vertical stack 46 has a first width W1 along the X direction, and each of the second fin vertical stack 42 and the third fin vertical stack 44 has a second width W2 along the X direction. In some embodiments, to achieve better read / write performance, the channel width of the n-type GAA transistor is greater than that of the p-type GAA transistor. That is, the first width W1 can be greater than the second width W2. In some cases, the ratio of the first width W1 to the second width W2 (W1 / W2) is between about 1 and about 5, including between about 1.1 and about 3.0.

[0062] The GAA transistor of this disclosure can be formed using two process flows. In a first process flow, the channel component is released after the source / drain components are formed. In a second process flow, the channel component is released before the source / drain components are formed. The channel component, which can be formed from silicon, is released from the interleaved sacrificial layer formed from silicon-germanium. Because the formation of the source / drain components involves epitaxial processes involving high temperatures, and these high temperatures can promote mixing of silicon-germanium in the sacrificial layer and silicon in the channel component, the first process flow tends to result in more silicon-germanium mixing into the silicon, while the second process flow tends to result in little or no mixing. When the channel component is released, the mixing at the interface between the channel component and the sacrificial layer can affect the selective removal of the sacrificial layer. Generally, the first process flow may involve fewer process steps than the second process flow, but the second process flow may result in a channel component with a larger channel width and shape uniformity. Embodiments of this disclosure are applicable to SRAM cells formed from GAA transistors formed using both process flows.

[0063] like Figure 2 As shown, the channel of the first transmission gate transistor PG1 is controlled by gate structure 20, the channels of the first pull-down transistor PD1 and the first pull-up transistor PU1 are controlled by gate structure 24, the channels of the second pull-down transistor PD2 and the second pull-up transistor PU2 are controlled by gate structure 22, and the channel of the second transmission gate transistor PG2 is controlled by gate structure 26. Since gate structures 20 and 22 are separated from a single gate structure, they are longitudinally aligned along the X direction. Since gate structures 24 and 26 are separated from a single gate structure, they are longitudinally aligned along the X direction. The first fin vertical stack 40, the second fin vertical stack 42, the third fin vertical stack 44, and the fourth fin vertical stack 46 extend longitudinally along the Y direction, which is perpendicular to the X direction. In circuit and physical design, Figure 2 The SRAM cell 10 shown can be used as a repeating cell in an SRAM array. To facilitate signal routing, adjacent SRAM cells 10 in the SRAM array can be mirrored to each other along their boundaries.

[0064] Figure 3-Figure 5Various aspects of the example embodiment are illustrated, wherein the sources of two adjacent second pull-down transistors PD2 are electrically coupled to the back-side ground rail via back-side contacts. Regarding this example embodiment, Figure 3 The front interconnect layer of an SRAM quad cell 100 comprising four SRAM cells 10 is shown. The SRAM cells 10 are in... Figure 3 The text is displayed as a dashed rectangle. For clarity, Figure 3 It also includes a first mirror axis MA1 extending along the Y direction and a second mirror axis MA2 extending along the X direction. It can be seen that the SRAM cell separated from SRAM cell 10 by the first mirror axis MA1 is a mirror image of SRAM cell 10. Similarly, the SRAM cell separated from SRAM cell 10 by the second mirror axis MA2 is a mirror image of SRAM cell 10. This mirror configuration allows for the merging of pull-up transistors, pull-down transistors, and transmission gate transistors to achieve efficient wiring and electrical connections. Figure 3 The front interconnect layer includes mating contacts, such as a first front mating contact 102F and a second front mating contact 104F. The first front mating contact 102F couples the gate structure 24 of the first pull-up transistor PU1 to the source of the second pull-up transistor PU2. The second front mating contact 104F couples the gate structure 22 of the second pull-up transistor PU2 to the source of the first pull-up transistor PU1. Figure 3 Also shown is a common front-side source contact 120F that couples the sources of two adjacent pull-down transistors together.

[0065] Figure 4 Showing along Figure 3 A partial cross-sectional view of the midsection A-A'. (See attached image.) Figure 4As shown, cross section A-A' passes through the source portion 116 of the second pull-up transistor PU2 and the source portion 112 of the second pull-down transistor PD2 in SRAM cell 10, as well as the source portion 118 of the second pull-up transistor PU2 and the source portion 114 of the second pull-up transistor PD2 in an adjacent SRAM cell, which is a mirror image of SRAM cell 10 relative to the second mirror axis MA2. Source portions 116 and 118 comprise silicon germanium (SiGe) doped with p-type dopants (such as boron or boron difluoride (BF2)). Source portions 112 and 114 comprise silicon (Si) doped with n-type dopants (such as phosphorus (P) or arsenic (As)). Because p-type source components 116 and 118 are formed with narrower fin-shaped surfaces, while n-type source components 112 and 114 are formed with wider fin-shaped surfaces, n-type source components 112 and 114 are wider in the Y direction than p-type source components 116 and 118. P-type source components 116 and 118 are disposed above a substrate fin 104B formed of a semiconductor material, such as silicon (Si). To control strain, a bottom isolation component 109 is disposed between the substrate fin 104B and the p-type source component 116 (or p-type source component 118). In some embodiments, the back-side dielectric layer 102 may comprise silicon oxide, and the bottom isolation component 109 may comprise silicon nitride. A portion of a shallow trench isolation (STI) 106 is disposed along the sidewall of the substrate fin 104B, and a gate spacer 110 is disposed along the sidewall of the bottom isolation component 109. In some embodiments, a pad 108 is vertically sandwiched between a portion of the STI 106 and the gate spacer 110. In some embodiments, STI 106 may include silicon oxide, gate spacer 110 may include silicon carbonitride or silicon carbonitride, and pad 108 may include silicon nitride. Pad 108 is used to prevent loss of STI 106. In some embodiments, the channel components of the GAA transistor in the SRAM cell are released by selectively removing the dummy layer between the interleaved channel components. Because both the dummy layer and STI 106 can be formed of silicon oxide, pad 108 is formed to cover STI 106 to prevent damage to STI 106 during the channel release process.

[0066] Still referencing Figure 4A back-side metal rail 126B is disposed below the back-side dielectric layer 102. A first back-side source contact 112B is formed extending from the top surface of the back-side metal rail 126B through the back-side dielectric layer 102 to electrically connect to the bottom surface of the n-type source component 112. A second back-side source contact 114B is formed extending from the top surface of the back-side metal rail 126B through the back-side dielectric layer 102 to electrically connect to the bottom surface of the n-type source component 114. An isolation structure 111 is formed between the first back-side source contact 112B and the second back-side source contact 114B. The isolation structure 111 may include an inner layer and an outer layer. In some cases, the inner layer may include silicon oxide, and the outer layer may include silicon nitride, silicon carbonitride, or silicon carbonitride. The dielectric constant of the outer layer is greater than that of the inner layer. As will be further described below, the isolation structure 111 is used to cut the gate structure into segments, and may also be referred to as gate dicing segment 111. Figure 4 In the illustrated example structure, a first front source contact 116F is disposed above and electrically coupled to the p-type source component 116, a second front source contact 118F is disposed above and electrically coupled to the p-type source structure 118, and a common front source contact 120F is disposed above and coupled to the n-type source components 112 and 114. In some embodiments, the first front source contact 116F, the second front source contact 118F, and the common front source contact 120F may include cobalt (Co), ruthenium (Ru), or tungsten (W). In one embodiment, they include tungsten (W). Figure 4 As shown, the first front source contact 116F, the second front source contact 118F, and the common front source contact 120F are located in the source / drain contact (MD) layer.

[0067] Source components 112, 114, 116, and 118 are disposed in a first interlayer dielectric (ILD) layer 115. A second ILD layer 124 is disposed above the first ILD layer 115. A first front source contact 116F, a second front source contact 118F, and a common front source contact 120F extend through the first ILD layer 115 and the second ILD layer 124 to couple to the source components 112, 114, 116, and 118. Due to a planarization process, the top surfaces of the first front source contact 116F, the second front source contact 118F, and the common front source contact 120F are coplanar. An etch stop layer (ESL) 128 is disposed on the coplanar top surface of the first front source contact 116F, the second front source contact 118F, the common front source contact 120F, and the second ILD layer 124. ESL 128 may include silicon nitride, silicon carbide, silicon carbonitride, aluminum nitride, or aluminum oxynitride. A third ILD layer 132 is disposed on ESL 128. A front contact via 122F extends through the third ILD layer 132 and ESL 128 to be electrically coupled to a common front source contact 120F. A first contact via 121F extends through the third ILD layer 132 and ESL 128 to be electrically coupled to a first front source contact 116F, and a second contact via 123F extends through the third ILD layer 132 to be electrically coupled to a second front source contact 118F. The front contact via 122F, the first contact via 121F, and the second contact via 123F may include cobalt (Co), ruthenium (Ru), or tungsten (W) and are located in the source / drain contact via (VD) layer. In one embodiment, they include tungsten (W). The common front source contact 120F is electrically coupled to the fourth metal layer (M3) metal rail 138F through the front contact via 122F, the first metal layer (M0) metal island 126F, the second metal layer (M1) metal island 130F, and the third metal layer (M2) metal line 134F. (Refer to...) Figure 4The front-side connections to the n-type source components 112 and 114 include contact structures located in the MD layer, VD layer, M0 layer, M1 layer, M2 layer, and M3 layer. When any of these contact structures is missing, the n-type source components 112 and 114 are not connected to the front-side power rail, i.e., the fourth metal layer (M3) metal rail 138F. Instead, when any of these contact structures is missing, the n-type source components 112 and 114 are connected only to the back-side metal rail 126B. A first metal layer (M0) is located in a first intermetallic dielectric (IMD) layer 136, a second metal layer (M1) is located in a second IMD layer 140, a third metal layer (M2) is located in a third IMD layer 144, and a fourth metal layer (M3) is located in a fourth IMD layer 148. The first, second, third, and fourth IMD layers 136, 140, 144, and 148 may comprise silicon oxide. Although not explicitly shown, the first, second, third, and fourth IMD layers 136, 140, 144, and 148 may be interleaved with etch stop layers formed of aluminum oxide, aluminum nitride, or aluminum oxynitride. Figure 4 In the image, the M3 metal rail 138F is shown as a dashed line because it is not in the plane.

[0068] Figure 5 Showing along Figure 3 A partial cross-sectional view of the midsection B-B'. The isolation structure 111 serves as a gate dicing component to diced the gate structure. For example, as... Figure 3 As shown, gate structure 22 is aligned with another gate structure 52 in the mirrored SRAM cell on the other side of the second mirror axis MA2. Isolation structure 111 is cut between gate structure 22 and gate structure 52. Please refer to [reference needed]. Figure 3 The isolation structure 111 does not cut through the gate structures 26 and 56, as... Figure 5 As shown, gate structures 26 and 56 extend along the sidewalls of isolation structure 111. Gate contact 26G extends through the third ILD layer 132 and ESL 128 to be electrically coupled to gate structure 26. Figure 5 As shown, a portion of the common front source contact 120F extends into the isolation structure 111. The STI 106 is covered and protected by a gasket 108 to prevent damage to the STI 106. Cross-sectional views of the back metal rail 126B, front contact via 122F, first metal layer (M0) island 126F, second metal layer (M1) island 130F, third metal layer (M2) line 134F, and fourth metal layer (M3) rail 138F are shown below. Figure 5 As shown. Combined with Figure 4 It can be seen that the back metal rail 126B extends longitudinally along the X direction, the M2 metal line 134F extends longitudinally along the X direction, and the M3 metal rail 138F extends longitudinally along the Y direction. For example... Figure 5As shown, the M3 metal rail 138F is not vertically aligned with the common front source contact 120F, the front contact via 122F, the first metal layer (M0) metal island 126F, and the second metal layer (M1) metal island 130F. This is why it is... Figure 4 The reason why it is shown with a dashed line.

[0069] Figure 6 yes Figure 3 A partial top view of the source / drain contacts (MD) and source / drain contact vias (VD) of a quad SRAM cell 100. Figure 6 A top view of the common front source contact 120F and the front contact via 122F is shown. Although the common front source contact 120F is longer along the Y direction than the first front source contact 116F and the second front source contact 118F, its presence does not necessarily affect the area of ​​the first front source contact 116F and the second front source contact 118F. In other words, even if the common front source contact 120F is removed, the first front source contact 116F and the second front source contact 118F will not increase in size. There are at least two reasons for this. First, unless all source / drain contacts in similar locations can share these benefits, enlarging only a few source / drain contacts will only lead to inconsistencies in process and performance. Second, it is generally not recommended to extend source / drain contacts over another source / drain component, as doing so may increase the risk of electrical short circuits.

[0070] Figure 7 yes Figure 3 A partial top view of the first metal layer (M0) of a quad SRAM cell 100. (See attached image.) Figure 7 As shown, the M0 metal island 126F in the first metal layer (M0) is directly disposed above and in physical and electrical contact with the front contact via 122F. The presence of the M0 metal island 126F reduces the space occupied by other metal islands 126FN in similar locations. In other words, when the M0 metal island 126F is removed, the metal island 126FN can be lengthened at least along the X direction to increase the process window and via landing area.

[0071] Figure 8 yes Figure 3 A partial top view of the second metal layer (M1) of the SRAM quad cell 100. (See attached image.) Figure 8 As shown, the M1 metal island 130F in the second metal layer (M1) is directly disposed above the M0 metal island 126F and includes a contact via 130V (e.g., Figure 4As shown), the M0 metal island 126F is in physical and electrical contact. The presence of the M1 metal island 130F requires the M1 metal line 130L to be split. In other words, when the M1 metal island 130F and similarly located M1 metal islands are removed, the M1 metal line 130L can have a rectangular shape, which is easier to form and has a larger process window.

[0072] Figure 9 yes Figure 3 A partial top view of the third metal layer (M2) of the SRAM quad cell 100. Figure 9 In the SRAM quad cell 100, the M2 metal line 134F extends longitudinally along the X direction and includes a contact via 134V for physical and electrical contact with the M1 metal island 130F. The third metal layer (M2) on the SRAM quad cell 100 consists only of the M2 metal line 134F. If all the M2 metal lines 134F are removed, the entire third metal layer (M2) on the SRAM quad cell 100 can be reused to include conductive components that improve the performance of the SRAM quad cell 200.

[0073] Figure 10 yes Figure 3 A partial top view of the fourth metal layer (M3) of the SRAM quad cell 100. (See attached image.) Figure 10 As shown, the M3 metal rail 138F extends longitudinally along the Y direction and includes a contact via 138V for physical and electrical coupling to the M2 metal line 134F. The presence of the M3 metal rail 138F reduces the usable area of ​​the M3 metal line 138L. In other words, when the M3 metal rail 138F is removed, the M3 metal lines 138L can each have a larger width to reduce resistance, or be spaced further apart to reduce parasitic capacitance.

[0074] As the processes for forming GAA transistors improve over time, the channel components in GAA transistors can have more uniform shapes and smoother surfaces to exhibit larger channel currents and lower channel resistances. Given the reduced channel resistance, coupling the source of the pull-down transistor to the ground rail or negative supply voltage via front and back contacts may become redundant and unnecessary. This is especially true when front connections in multiple metal layers occupy space that could accommodate other conductive components. This disclosure provides various embodiments in which some or all connections to the front power rail are eliminated.

[0075] Figures 11-17A first embodiment of the present disclosure is shown. In the first embodiment, the source component 112 of the second pull-down transistor PD2 of SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of an adjacent SRAM cell are coupled to a back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. A common front-side source contact 120F extends through the first ILD layer 115 and the second ILD layer 124 to electrically couple to the source component 112 of the second pull-down transistor PD2 of SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of an adjacent SRAM cell. Figure 11 As shown, the common front-side source contact 120F spans source components 112 and 114 along the Y direction and connects them via silicide components, which may include tungsten silicide, titanium silicide, cobalt silicide, or nickel silicide. Figure 11 In some embodiments shown, the lower portion of the common front source contact 120F is disposed between source component 112 and source component 114, and connected to the isolation structure 111. For example... Figure 11 and Figure 12 As shown, the ESL 128 is directly disposed on the top surface of the common front source contact 120F and the second ILD layer 124. In the first embodiment, the common front source contact 120F is not electrically coupled to any conductive component disposed above it. That is, no conductive component extends through the ESL 128 to make electrical or physical contact with the top surface of the common front source contact 120F.

[0076] like Figures 11-17 As shown, the front contact via 122F, M0 metal island 126F, M1 metal island 130F, M2 metal line 134F, and M3 metal rail 138F are omitted. That is, not only is the front power rail—M3 metal rail 138F—removed, but all conductive components on the conductive path between the common front source contact 120F and the M3 metal rail 138F are also omitted. Retaining the common front source contact 120F is not a simple choice. When the common front source contact 120F is still formed as in the first embodiment, all source / drain components in the SRAM cell 10 are etched when the contact opening (e.g., the opening for the common front source contact 120F) is formed. If the common front source contact 120F is omitted, only the source components 112 and 114 are not etched; this inconsistent etching may introduce reliability issues. When the common front-side source contact 120F is retained, source components 112 and 114 are etched similarly to other source / drain components in the SRAM cell, which can improve the process window and performance of the memory device. (Reference) Figure 13The common front source contact 120F still exists, but the front contact via 122F is omitted. (Refer to...) Figure 14 The metal island 126F of M0 is omitted from the first metal layer M0, allowing other metal islands 126FN at similar locations to be lengthened along the X direction, or the spacing between other metal islands 126FL at similar locations to be increased. (Refer to...) Figure 15 The M1 metal island 130F is omitted from the second metal layer M1, allowing the M1 metal line 130L to be straightened to reduce resistance and improve the process window. (Reference) Figure 16 The M2 metal line 134F in the third metal layer M2 is omitted, thus allowing the third metal layer M2 on the SRAM cell 10 to be reused. (Refer to...) Figure 17 The M3 metal rail 138F in the fourth metal layer M3 is omitted, which allows the M3 metal line 138L in the fourth metal layer M3 to be widened in the X direction and the spacing between them to be further increased.

[0077] Figures 18-20 A second embodiment of this disclosure is shown. In the second embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. Figures 18-20 As shown, in the second embodiment, the common front source contact 120F and the front contact via 122F are omitted. The M0 metal island 126F, M1 metal island 130F, M2 metal line 134F, and M3 metal rail 138F are retained in place, even though they are no longer electrically coupled to source components 112 and 114. Because the common front source contact 120F is not formed in the second embodiment, the isolation structure 111 is not etched, and a portion of the isolation structure 111 extends along the Y direction between source components 112 and 114. Although the M0 metal island 126F, M1 metal island 130F, M2 metal line 134F, and M3 metal rail 138F no longer have any circuit function, they may be retained simply because of the cost associated with manufacturing a new photomask. In addition, M0 metal island 126F, M1 metal island 130F, M2 metal line 134F and M3 metal rail 138F can be retained because removing them may cause process changes or load changes.

[0078] Figures 21-23A third embodiment of this disclosure is shown. In this third embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. Figures 21-23 As shown, the M0 metal island 126F is omitted from the first metal layer M0. The omission of the M0 metal island 126F interrupts the electrical connection between source components 112 and 114 and the M3 metal rail 138F. Figure 23 As shown, when the M0 metal island 126F is omitted, the metal island 126FN in the same first metal layer (M0) can be lengthened along the X direction to increase the process window and via landing area.

[0079] Figures 24-26 A fourth embodiment of this disclosure is shown. In this fourth embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. Figures 24-26 As shown, the M1 metal island 130F is omitted from the second metal layer M1. The omission of the M1 metal island 130F interrupts the electrical connection between source components 112 and 114 and the M3 metal rail 138F. Figure 26 As shown, when the M1 metal island 130F is omitted, the M1 metal line 130L can have a rectangular shape, which is easier to form and has a larger process window.

[0080] Figures 27-29 A fifth embodiment of this disclosure is shown. In the fifth embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. Figures 27-29 As shown, the M2 metal line 134F is omitted in the third metal layer M2. The omission of the M2 metal line 134F interrupts the electrical connection between source components 112 and 114 and the M3 metal rail 138F. Figure 29As shown, when the M2 metal line 134F is omitted, the third metal layer M2 can be redistributed to accommodate other conductive components.

[0081] Figures 30-32 A sixth embodiment of this disclosure is shown. In the sixth embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. Figures 30-32 As shown, the M3 metal rail 138F is omitted in the fourth metal layer M3. That is, source components 112 and 114 no longer have connectable front power rails. Figure 32 As shown, when the M3 metal rail 138F is omitted, the M3 metal lines 138L can each have a larger width to reduce resistance, or be spaced further apart to reduce parasitic capacitance.

[0082] Figures 33-39 A seventh embodiment of this disclosure is shown. In the seventh embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. In the seventh embodiment, the common front-side source contact 120F, the front contact via 122F, the M0 metal island 126F, the M1 metal island 130F, the M2 metal line 134F, and the M3 metal rail 138F are omitted. Because the common front-side source contact 120F is not formed in the second embodiment, the isolation structure 111 is not etched, and a portion of the isolation structure 111 extends along the Y direction between the source components 112 and 114. Figure 36 As shown, when the M0 metal island 126F is omitted, the metal island 126FN in the same metal layer can be lengthened along the X direction to increase the process window and via landing area. Figure 37 As shown, when the M1 metal island 130F is omitted, the M1 metal line 130L can have a rectangular shape, which is easier to form and has a larger process window. Figure 38 As shown, when the M2 metal line 134F is omitted, the third metal layer M2 can be redistributed to accommodate other conductive components. For example... Figure 39As shown, when the M3 metal rail 138F is omitted, the M3 metal lines 138L can each have a larger width to reduce resistance, or be spaced further apart to reduce parasitic capacitance.

[0083] Figures 40-41 An eighth embodiment of this disclosure is shown. In the eighth embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. Figure 40 and 41 As shown, the M1 metal island 130F and the M3 metal rail 138F are omitted.

[0084] Figures 42-43 A ninth embodiment of this disclosure is shown. In the ninth embodiment, the source component 112 of the second pull-down transistor PD2 of the SRAM cell 10 and the source component 114 of the second pull-down transistor PD2 of the adjacent SRAM cell are coupled to the back-side metal rail 126B via a first back-side source contact 112B and a second back-side source contact 114B. An isolation structure 111 is disposed along the Y direction between the first back-side source contact 112B and the second back-side source contact 114B. Figure 42 and Figure 43 As shown, the common front source contact 120F, front contact via 122F, and M0 metal island 126F are omitted. Because the common front source contact 120F is not formed in the second embodiment, the isolation structure 111 is not etched, and a portion of the isolation structure 111 extends along the Y direction between source components 112 and 114. Although not explicitly shown, omitting the M0 metal island 126F allows a similarly located metal island in the first metal layer (M0) to be elongated along the X direction, increasing the process window and via landing area.

[0085] In one example aspect, this disclosure provides a semiconductor structure. The semiconductor structure includes: a back-side metal line; a back-side dielectric layer located above the back-side metal line; a first source / drain component and a second source / drain component located on the back-side dielectric layer; a first back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the first source / drain component; a second back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the second source / drain component; a dielectric layer disposed above the back-side dielectric layer, the first source / drain component, and the second source / drain component; a common contact extending through the dielectric layer to be electrically coupled to the first source / drain component and the second source / drain component; and an etch stop layer disposed above and connected to the dielectric layer and the common contact. The common contact is not electrically coupled to any conductive component extending through the etch stop layer.

[0086] In some embodiments, the lower portion of the common contact extends between the first source / drain component and the second source / drain component. In some embodiments, the semiconductor structure further includes an isolation structure dielectric fin disposed above a back-side dielectric layer between the first and second back-side contacts. The lower portion of the common contact rests on the isolation structure. In some embodiments, the semiconductor structure further includes: a first base fin and a second base fin located above the back-side dielectric layer, such that the first and second back-side contacts are disposed between the first and second base fins; a third source / drain component disposed above the first base fin; and a fourth source / drain component disposed above the second base fin. The first and second source / drain components are disposed between the third and fourth source / drain components. In some embodiments, the first and second source / drain components comprise silicon and an n-type dopant, wherein the third and fourth source / drain components comprise silicon-germanium and a p-type dopant. In some embodiments, the semiconductor structure further includes: a first bottom isolation layer disposed between the top surface of the first base fin and the bottom surface of the third source / drain component; and a second bottom isolation layer disposed between the top surface of the second base fin and the bottom surface of the fourth source / drain component. In some embodiments, the first and second bottom isolation layers comprise silicon nitride. In some embodiments, the semiconductor structure further includes: a first source / drain contact extending through the dielectric layer to be electrically coupled to the third source / drain component; and a second source / drain contact extending through the dielectric layer to be electrically coupled to the fourth source / drain component. An etch stop layer is disposed on the top surface of the first and second source / drain contacts. In some embodiments, the semiconductor structure further includes: a first contact via extending through the etch stop layer and partially extending into the first source / drain contact; and a second contact via extending through the etch stop layer and partially extending into the second source / drain contact.

[0087] Another aspect of this disclosure relates to a semiconductor structure. The semiconductor structure includes: a back-side metal line extending along a first direction; a back-side dielectric layer located above the back-side metal line; a first gate structure and a second gate structure located above the back-side dielectric layer and extending longitudinally along a second direction perpendicular to the first direction; an isolation structure disposed above the back-side dielectric layer and sandwiched between the first gate structure and the second gate structure along the first direction; a dielectric layer located above and in contact with the isolation structure; a contact member extending through the dielectric layer and partially extending into the isolation structure; and an etch stop layer located above and in contact with the top surfaces of the dielectric layer and the contact member. The contact member is not electrically coupled to any conductive component extending through the etch stop layer.

[0088] In some embodiments, the semiconductor structure further includes: a first gate contact extending through an etch stop layer and a dielectric layer to couple to a first gate structure; and a second gate contact extending through an etch stop layer and a dielectric layer to couple to a second gate structure. In some embodiments, the isolation structure includes silicon oxide. In some embodiments, the top surfaces of the first gate structure, the gate dicing member, and the second gate structure are coplanar. In some embodiments, the dielectric layer includes silicon oxide, and the etch stop layer includes silicon nitride, silicon carbide, silicon carbonitride, aluminum oxide, or aluminum oxynitride. In some embodiments, the contact member includes cobalt.

[0089] Another aspect of this disclosure relates to a semiconductor structure. The semiconductor structure includes: a back-side metal line; a back-side dielectric layer located above the back-side metal line; a first n-type epitaxial member and a second n-type epitaxial member located above the back-side dielectric layer; a first back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the first n-type epitaxial member; a second back-side contact extending from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the second n-type epitaxial member; a dielectric layer disposed above the back-side dielectric layer, the first n-type epitaxial member, and the second n-type epitaxial member; a common contact extending through the dielectric layer to be electrically coupled to the first n-type epitaxial member and the second n-type epitaxial member; and an etch stop layer disposed above and in contact with the top surface of the dielectric layer and the top surface of the common contact. The common contact is not electrically coupled to any conductive member extending through the etch stop layer, and the lower portion of the common contact extends between the first n-type epitaxial member and the second n-type epitaxial member.

[0090] In some embodiments, the semiconductor structure further includes an isolation structure disposed above a back-side dielectric layer between the first back-side contact and the second back-side contact. The lower portion of a common contact rests on the isolation structure. In some embodiments, the semiconductor structure further includes: a first semiconductor fin and a second semiconductor fin, located above the back-side dielectric layer, such that the first back-side contact and the second back-side contact are disposed between the first semiconductor fin and the second semiconductor fin; a first p-type epitaxial member disposed above the first semiconductor fin; and a second p-type epitaxial member disposed above the second semiconductor fin. A first n-type epitaxial member and a second n-type epitaxial member are disposed between the first p-type epitaxial member and the second p-type epitaxial member. In some embodiments, the semiconductor structure further includes: a first bottom isolation layer disposed between the top surface of the first semiconductor fin and the bottom surface of the first p-type epitaxial member; and a second bottom isolation layer disposed between the top surface of the second semiconductor fin and the bottom surface of the second p-type epitaxial member. In some embodiments, the first bottom isolation layer and the second bottom isolation layer comprise silicon nitride.

[0091] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A semiconductor structure, comprising: Back side metal wire; A back-side dielectric layer is located above the back-side metal line; The first source / drain component and the second source / drain component are located on the back dielectric layer; A first back-side contact extends from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the first source / drain component. The second back-side contact extends from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the second source / drain component. A dielectric layer is disposed above the back dielectric layer, the first source / drain component, and the second source / drain component; A common contact extends through the dielectric layer to be electrically coupled to the first source / drain component and the second source / drain component; as well as An etching stop layer is disposed above and connected to the dielectric layer and the common contact. The common contact is not electrically coupled to any conductive component extending through the etch stop layer.

2. The semiconductor structure according to claim 1, wherein, The lower portion of the common contact extends between the first source / drain component and the second source / drain component.

3. The semiconductor structure according to claim 2, further comprising: An isolation structure is disposed above the back-side dielectric layer between the first back-side contact and the second back-side contact. The lower part of the common contact element rests on the isolation structure.

4. The semiconductor structure according to claim 1, further comprising: The first base fin and the second base fin are located above the back dielectric layer, such that the first back contact and the second back contact are disposed between the first base fin and the second base fin. The third source / drain component is disposed above the first base fin; as well as The fourth source / drain component is disposed above the second base fin. The first source / drain component and the second source / drain component are disposed between the third source / drain component and the fourth source / drain component.

5. The semiconductor structure according to claim 4, in, The first source / drain component and the second source / drain component comprise silicon and an n-type dopant. The third source / drain component and the fourth source / drain component include silicon germanium and p-type dopant.

6. The semiconductor structure according to claim 4, further comprising: The first source / drain contact extends through the dielectric layer to be electrically coupled to the third source / drain component; as well as The second source / drain contact extends through the dielectric layer to be electrically coupled to the fourth source / drain component. The etch stop layer is disposed on the top surface of the first source / drain contact and the top surface of the second source / drain contact.

7. A semiconductor structure comprising: The back metal wire extends along the first direction; A back-side dielectric layer is located above the back-side metal line; The first gate structure and the second gate structure are located above the back dielectric layer and extend longitudinally along a second direction perpendicular to the first direction. An isolation structure is disposed above the back-side dielectric layer and sandwiched between the first gate structure and the second gate structure along the first direction; A dielectric layer is located above and connected to the isolation structure; The contact component extends through the dielectric layer and partially extends into the isolation structure; An etch stop layer is located above and in contact with the top surfaces of the dielectric layer and the contact components. The contact component is not electrically coupled to any conductive component extending through the etch stop layer.

8. The semiconductor structure according to claim 7, further comprising: A first gate contact extends through the etch stop layer and the dielectric layer to couple to the first gate structure; as well as A second gate contact extends through the etch stop layer and the dielectric layer to couple to the second gate structure.

9. A semiconductor structure, comprising: Back side metal wire; A back-side dielectric layer is located above the back-side metal line; The first n-type epitaxial component and the second n-type epitaxial component are located above the back-side dielectric layer; A first back-side contact extends from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the first n-type epitaxial member; The second back-side contact extends from the back-side metal line through the back-side dielectric layer to be electrically coupled to the bottom surface of the second n-type epitaxial member; A dielectric layer is disposed above the back-side dielectric layer, the first n-type epitaxial member, and the second n-type epitaxial member; A common contact extends through the dielectric layer to be electrically coupled to the first n-type epitaxial component and the second n-type epitaxial component; as well as An etching stop layer is disposed above and in contact with the top surfaces of the dielectric layer and the common contact. The common contact is not electrically coupled to any conductive component extending through the etch stop layer. The lower part of the common contact extends between the first n-type extension member and the second n-type extension member.

10. The semiconductor structure according to claim 9, further comprising: The first semiconductor fin and the second semiconductor fin are located above the back dielectric layer, such that the first back contact and the second back contact are disposed between the first semiconductor fin and the second semiconductor fin. A first p-type epitaxial component is disposed above the first semiconductor fin; as well as The second p-type epitaxial component is disposed above the second semiconductor fin. The first n-type epitaxial component and the second n-type epitaxial component are disposed between the first p-type epitaxial component and the second p-type epitaxial component.

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