NAND flash memory storage device and method of making the same

Abstract

The application relates to the technical field of semiconductors, and particularly discloses a NAND flash memory device and a preparation method thereof, which comprises the following steps: providing a silicon substrate; forming a memory cell array in a memory area of the silicon substrate and forming a driving circuit in a driving area of the silicon substrate, wherein the driving circuit at least comprises a CMOS transistor, and the CMOS transistor at least comprises a high-voltage CMOS transistor; a field ion implantation process under an isolation area of the high-voltage CMOS transistor and a forming process of a P-type well area unit in the memory cell array are realized based on the same mask plate; and the doping concentration of the field ion under the isolation area of the high-voltage CMOS transistor is greater than the doping concentration of the silicon substrate. The preparation method of the NAND flash memory device can control the cost increase of the NAND flash memory device without reducing the performance of the NAND flash memory device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a NAND flash memory storage device and the NAND flash memory storage device itself. Background Technology

[0002] NAND flash memory devices in semiconductor devices consist of a memory cell array region and peripheral driving circuitry that drives this memory cell array region. The driving circuitry is specifically composed of active devices (such as CMOS transistors and BJTs) and passive devices (such as resistors and capacitors). During operation, the NAND flash memory device requires operating voltages ranging from low to high. Like other semiconductor devices, the operating voltage of the peripheral driving circuitry of a NAND flash memory device is typically in the range of 1.2 V to 3.3 V. However, to achieve data read / write operations (i.e., programming data to or erasing data from memory cells), a high voltage of 20 V or higher is usually required. Therefore, the CMOS transistors in NAND flash memory devices differ from other ordinary non-high-voltage CMOS semiconductor devices (which typically operate at relatively low voltages). The CMOS transistors in NAND flash memory devices require high-voltage operation. Achieving high-voltage operation of CMOS transistors usually requires additional special processes, which not only increase the complexity of the process but also increase costs.

[0003] In semiconductor devices, performance and low cost are two key indicators of a semiconductor's competitiveness, and increased costs undoubtedly reduce the market competitiveness of semiconductor devices.

[0004] Therefore, how to control the cost increase of NAND flash memory devices without reducing their performance has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This invention provides a method for manufacturing a NAND flash memory storage device and a NAND flash memory storage device, solving the problem of increased cost caused by adding special processes to NAND flash memory devices in related technologies.

[0006] As a first aspect of the present invention, a method for manufacturing a NAND flash memory storage device is provided, comprising:

[0007] A silicon substrate is provided, the silicon substrate being divided into a storage region and a driving region;

[0008] A memory cell array is formed in the memory region of the silicon substrate and a driving circuit is formed in the driving region of the silicon substrate. The driving circuit includes at least a CMOS transistor, and the CMOS transistor includes at least a high-voltage CMOS transistor.

[0009] The field region ion implantation process below the isolation region of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented based on the same mask template, and the doping concentration of the field region ions below the isolation region of the high-voltage CMOS transistor is greater than the doping concentration of the silicon substrate.

[0010] Further, a memory cell array is formed in the memory region of the silicon substrate, and a driving circuit is formed in the driving region of the silicon substrate, including:

[0011] A deep N-type well region is formed in the storage region of the silicon substrate;

[0012] N-type well regions are formed at intervals on the deep N-type well region;

[0013] A first P-type well unit is formed in the storage region and a second P-type well unit is formed at intervals in the driving region on the silicon substrate of the driving region based on the same mask between each two adjacent N-type well regions in the storage region and on the silicon substrate of the driving region. Field ion implantation is performed below the second P-type well unit. The first P-type well unit is located between two adjacent N-type well regions.

[0014] Simultaneously, a first isolation region is formed in the storage region and a second isolation region is formed in the drive region, wherein the first isolation region is located in the contact region between the N-type well region and the first P-type well region unit, and there is a gap between the lower edge of the first isolation region and the deep N-type well region, and the second isolation region is formed at the position of the second P-type well region unit;

[0015] A memory cell is formed on the upper surface of the first P-type well region cell to obtain a memory cell array;

[0016] A source, drain, and gate are formed between the second isolation regions to obtain the high-voltage CMOS transistor.

[0017] Further, a second isolation region is formed located in the driving region, including:

[0018] The location of the second P-type well unit is etched, and the inner diameter of the etched area is larger than the diameter of the second P-type well unit.

[0019] The second P-type well region cell is removed, and the etched region is filled with oxide to form a second isolation region.

[0020] Further, a source, a drain, and a gate are formed between the second isolation regions to obtain the high-voltage CMOS transistor, including:

[0021] A gate is formed by polysilicon etching on the upper surface of the silicon substrate between the second isolation regions;

[0022] N-ion implantation is performed in the silicon substrate between the second isolation regions and in the corresponding regions on both sides of the gate to form N-S / D regions;

[0023] N+ ion implantation is performed between the second isolation region and the N-S / D region to form N+S / D regions located on both sides of the second isolation region and in contact with the sidewall of the second isolation region. The depth of the N+S / D region is greater than the depth of the N-S / D region. Both the N+S / D region and the N-S / D region are used to form the source and drain.

[0024] Furthermore, a gate insulating film is disposed between the gate and the upper surface of the silicon substrate, and the gate insulating film has two or more different thicknesses.

[0025] Further, on the silicon substrate of the driving region and between every two adjacent N-type well regions in the storage region, a first P-type well region cell located in the storage region and a second P-type well region cell spaced apart in the driving region are formed based on the same mask, and field ion implantation is performed below the second P-type well region cells, including:

[0026] P-type ion implantation is performed on the silicon substrate of the driving region and between every two adjacent N-type well regions in the storage region, based on the same mask, to form a first P-type well region unit located in the storage region and a second P-type well region unit located at intervals in the driving region.

[0027] Field ion implantation is performed below the second P-type well unit using the same mask template.

[0028] Furthermore, the operating voltage of the high-voltage CMOS transistor is at least greater than 10V.

[0029] Furthermore, the silicon substrate includes a P-type silicon substrate.

[0030] Furthermore, when the CMOS transistor also includes a low-voltage CMOS transistor, the field region ion implantation process below the isolation region of the high-voltage CMOS transistor and the formation process of the P-type well region cell of the low-voltage CMOS transistor are implemented based on the same mask, and the doping concentration of the field region ions below the isolation region of the high-voltage CMOS transistor is greater than the doping concentration of the silicon substrate.

[0031] As another aspect of the present invention, a NAND flash memory storage device is provided, wherein the device is prepared according to the method for preparing a NAND flash memory storage device described above.

[0032] The present invention provides a method for fabricating a NAND flash memory device, which completes the fabrication of a memory cell array and a driving circuit on the same silicon substrate to obtain a NAND flash memory device. In this fabrication process, the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented using the same mask, thus eliminating the need for a mask layer and effectively reducing costs. The NAND flash memory device fabricated using this method enhances the isolation characteristics of the isolation region, thereby ensuring high-voltage operation of the CMOS transistor. Furthermore, since the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented using the same mask, the cost is significantly reduced compared to existing technologies that separately add a mask for the field region ion implantation process, and is comparable to the fabrication cost of ordinary non-high-voltage CMOS semiconductor devices. Therefore, the NAND flash memory device fabrication method provided by the present invention can guarantee the performance of the NAND flash memory device without increasing additional process costs. Attached Figure Description

[0033] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.

[0034] Figure 1 This is a schematic diagram of the storage area, which includes storage cells and well areas, in a typical NAND flash memory storage device.

[0035] Figure 2 This is a schematic diagram of a high-voltage CMOS transistor in a typical NAND flash memory storage device.

[0036] Figure 3 A flowchart illustrating the method for fabricating a NAND flash memory storage device provided by the present invention.

[0037] Figure 4This is a schematic diagram of the overall structure of the NAND flash memory storage device provided by the present invention.

[0038] Figure 5a This is a schematic diagram illustrating the fabrication process of forming a first P-type well region cell, a second P-type well region cell, and field region ion implantation based on the same mask template in the NAND flash memory storage device provided by the present invention.

[0039] Figure 5b This is a schematic diagram illustrating the fabrication process of forming a first isolation region and a second isolation region in the NAND flash memory storage device provided by the present invention.

[0040] Figure 5c A schematic diagram illustrating the fabrication process of forming a memory cell array and the gate-source-drain of a CMOS transistor in the NAND flash memory storage device provided by the present invention.

[0041] Figure 6a This diagram illustrates the formation of a trap region in a NAND flash memory storage device and the field region ion implantation process in the formation of a CMOS transistor.

[0042] Figure 6b This is a schematic diagram of the existing technology for forming a trap region and forming an isolation region after ion implantation in the field region.

[0043] Figure 7 A flowchart illustrating the method for forming a memory cell array and a driving circuit provided by the present invention.

[0044] Figure 8 The flowchart illustrates the method for forming a first P-type well unit, a second P-type well unit, and field region ion implantation based on the same mask template provided by the present invention.

[0045] Figure 9 A flowchart illustrating the method for forming a second isolation region provided by the present invention.

[0046] Figure 10 A flowchart illustrating the method for forming the source, drain, and gate electrodes provided by this invention. Detailed Implementation

[0047] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] like Figure 1 The diagram illustrates a typical NAND flash memory storage device containing memory cells and well regions. Specifically, it includes a silicon substrate 1, a deep N-type well region 2 formed on the silicon substrate 1, and an N-type well region 3 and a P-type well region 4 formed on the deep N-type well region 2. The N-type well region 3 is located in the peripheral region of the P-type well region 4. An isolation region 7 is provided between the N-type well region 3 and the P-type well region 4. The upper surface of the isolation region 7 is flush with the N-type well region 3 and the P-type well region 4, and there is a gap between the lower surface of the isolation region 7 and the deep N-type well region 2. A memory cell array 5 is formed on the upper surface of the P-type well region 4.

[0051] like Figure 2The diagram illustrates a typical high-voltage CMOS transistor in a NAND flash memory device. Specifically, it includes a silicon substrate 1' (note that the doping concentration of the silicon substrate 1' is lower than that of a typical CMOS silicon substrate to achieve high-voltage operation), an isolation region 7' ​​formed within the silicon substrate 1', an N+ type S / D region 10 and an N- type S / D region 9 located on either side of the isolation region 7', wherein the N+ type S / D region 10 is in contact with the isolation region 7', and the N- type S / D region 9 is in contact with the side of the N+ type S / D region 10 away from the isolation region 7', and a gate layer 8 formed on the silicon substrate 1'. To enhance the isolation characteristics of the isolation region 7' ​​located between the two N+ type S / D regions, field ion implantation is performed below the isolation region 7' ​​to form a field ion implantation region 6. This field ion implantation process is an additional special process, which is not required in ordinary non-high-voltage CMOS transistors. It is precisely this additional special process that increases the manufacturing cost of existing NAND flash memory devices.

[0052] Based on this, an embodiment of the present invention provides a method for manufacturing a NAND flash memory storage device. Figure 3 This is a flowchart of a method for manufacturing a NAND flash memory storage device according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the overall structure of the NAND flash memory storage device provided in an embodiment of the present invention, as shown below. Figure 3 and Figure 4 As shown, it includes:

[0053] S100. A silicon substrate is provided, the silicon substrate being divided into a storage region and a driving region;

[0054] In embodiments of the present invention, such as Figure 4 As shown, the silicon substrate 100 is divided into a storage region 110 and a driving region 120. In this embodiment of the invention, the silicon substrate 100 includes a P-type silicon substrate.

[0055] S200: A memory cell array is formed in the memory region of the silicon substrate and a driving circuit is formed in the driving region of the silicon substrate. The driving circuit includes at least a CMOS transistor, and the CMOS transistor includes at least a high-voltage CMOS transistor.

[0056] Specifically, such as Figure 4 As shown, a memory cell array 111 is formed in the memory region 110 of the silicon substrate 100, and a drive circuit 121 is formed in the drive region 120 of the silicon substrate 100.

[0057] It should be understood that the driving circuit 121 may specifically include active devices and passive devices. Active devices include CMOS transistors and BJT transistors, while passive devices include resistors and capacitors. For a complete NAND flash memory storage device, after the driving circuit and memory cell array are fabricated, an interlayer dielectric layer (ILD) 200 and a back-end process (BEOL) 300 also need to be fabricated. In this embodiment of the invention, the fabrication process of the CMOS transistors constituting the driving circuit 121 is described in detail.

[0058] It should also be understood that the CMOS transistors in the embodiments of the present invention may specifically include high-voltage CMOS transistors and low-voltage CMOS transistors. High voltage in a high-voltage CMOS transistor typically refers to a driving voltage applied to the CMOS transistor greater than 10V, and the operating voltage of the high-voltage CMOS transistor is typically greater than 20V when the memory cell array performs data read / write operations. Low voltage in a low-voltage CMOS transistor specifically refers to an operating voltage applied to the low-voltage CMOS transistor between 1.2V and 3.3V.

[0059] The field region ion implantation process below the isolation region of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented based on the same mask template, and the doping concentration of the field region ions below the isolation region of the high-voltage CMOS transistor is greater than the doping concentration of the silicon substrate.

[0060] It should be noted that, as Figure 5a As shown, in this embodiment of the invention, the field region ion implantation process below the isolation region of the high-voltage CMOS transistor and the formation process of the P-type well region cells in the memory cell array are implemented using the same mask. However, in the prior art, as described above, specifically... Figure 6a and Figure 6b As shown, after the P-type well cells in the memory cell array are formed, the field region ion implantation process of the high-voltage CMOS transistor is then performed. In other words, the existing technology requires two mask templates to implement these two steps. In this embodiment of the invention, the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented based on the same mask template, which can save one mask template and thus effectively reduce costs.

[0061] Furthermore, since the field ion region formed by the field ion implantation process is intended to enhance the isolation characteristics of the isolation region, the doping concentration of the field ions below the isolation region of the high-voltage CMOS transistor in this embodiment of the invention is greater than the doping concentration of the silicon substrate.

[0062] In summary, the fabrication method of the NAND flash memory device provided by this invention completes the fabrication of the memory cell array and driving circuit on the same silicon substrate to obtain the NAND flash memory device. During this fabrication process, the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented using the same mask, thus eliminating the need for a mask layer and effectively reducing costs. The NAND flash memory device fabricated using this method enhances the isolation characteristics of the isolation region, thereby ensuring high-voltage operation of the CMOS transistor. Furthermore, since the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented using the same mask, the cost is significantly reduced compared to existing technologies that separately add a mask for the field region ion implantation process, and is comparable to the fabrication cost of ordinary non-high-voltage CMOS semiconductor devices. Therefore, the fabrication method of the NAND flash memory device provided by this invention can guarantee the performance of the NAND flash memory device without increasing additional process costs.

[0063] In specific embodiments of the present invention, as follows: Figure 7 As shown, a memory cell array is formed in the memory region of the silicon substrate, and a driving circuit is formed in the driving region of the silicon substrate, including:

[0064] S210, A deep N-type well region is formed in the storage region of the silicon substrate;

[0065] In embodiments of the present invention, such as Figure 5a As shown, a deep N-type well region 130 is fabricated on a silicon substrate 100. The specific fabrication process can be to perform N-type ion implantation on the storage region of the silicon substrate 100 through a mask, which is well known to those skilled in the art and will not be described in detail here.

[0066] S220, N-type well regions 140 are formed at intervals on the deep N-type well region 130;

[0067] In embodiments of the present invention, such as Figure 5a As shown (where Figure 5a The left-hand view shows the process of forming a memory cell array on memory region 110. Figure 5a The right-hand view shows the process of forming the driving circuit on the driving region 120. Based on a mask layer, N-type ion implantation is performed on the deep N-type well region 130 to obtain spaced N-type well regions 140. It should be understood that the deep N-type well region 130 and the N-type well region 140 have different ion implantation concentrations. The specific fabrication process is well known to those skilled in the art and will not be described in detail here.

[0068] S230, a first P-type well unit 150 is formed in the storage region 110 and a second P-type well unit 160 is formed at intervals in the driving region 120 on the silicon substrate of the driving region 120 based on the same mask between every two adjacent N-type well regions 140 in the storage region and on the silicon substrate of the driving region 120. Field ion implantation 170 is performed below the second P-type well unit 160, wherein the first P-type well unit 150 is located between two adjacent N-type well regions 140.

[0069] In embodiments of the present invention, such as Figure 5a As shown, a first P-type well unit 150 is formed between two adjacent N-type well regions 140 in the storage region 110 by ion implantation. Second P-type well units 160 are formed at intervals on the silicon substrate of the driving region, and field ions 170 are formed below the second P-type well units 160. It should be noted that in this process, the fabrication of the first P-type well unit 150, the second P-type well unit 160, and the field ions 170 are all based on the same photomask.

[0070] Specifically, a first P-type well unit 150 is formed in the storage region 110 between every two adjacent N-type well regions 140 and on the silicon substrate of the driving region 120 based on the same mask. Second P-type well units 160 are spaced apart in the driving region 120. Field ion implantation is then performed below the second P-type well units 160. Figure 8 As shown, it includes:

[0071] S231. P-type ion implantation is performed on the silicon substrate of the driving region 120 between every two adjacent N-type well regions 140 in the storage region 110 and based on the same mask to form a first P-type well region unit 150 located in the storage region and a second P-type well region unit 160 located at intervals in the driving region.

[0072] In this embodiment of the invention, when fabricating based on the same mask, firstly, P-type ion implantation is performed between every two adjacent N-type well regions of the storage region 110 based on the same mask, and simultaneously, P-type ion implantation is performed on the silicon substrate of the driving region to obtain a first P-type well region unit 150 located in the storage region and a second P-type well region unit 160 located in the driving region.

[0073] Specifically, the first P-type well region unit 150 is adjacent to and in contact with the N-type well region, and a plurality of second P-type well region units 160 are spaced apart within the driving region.

[0074] S232. Field ion implantation is performed below the second P-type well unit 160 based on the same mask template.

[0075] In this embodiment of the invention, field ion implantation 170 is performed below the second P-type well unit based on the same mask used to form the P-type well unit. The field ion implantation also implants P-type ions, and the concentration of P-type ions implanted in this field ion implantation is greater than the concentration of P-type ions on the P-type silicon substrate.

[0076] Therefore, the simultaneous formation of the first P-type well unit, the second P-type well unit, and field ions was achieved using the same mask template.

[0077] S240, simultaneously forming a first isolation region 171 located in the storage region and a second isolation region 172 located in the drive region, wherein the first isolation region 171 is located in the contact region between the N-type well region and the first P-type well region unit 150, and there is a gap between the lower edge of the first isolation region 171 and the deep N-type well region 130, and the second isolation region 172 is formed at the position of the second P-type well region unit 160;

[0078] In embodiments of the present invention, such as Figure 5b As shown, after the processes for the first P-type well unit 150, the second P-type well unit 160, and the field ion 170 are completed, a first isolation region 171 and a second isolation region 172 are formed in the storage region 110 and the driving region 120 based on the same mask. It should be understood that while the first P-type well unit 150, the second P-type well unit 160, and the field ion 170 are formed based on the same mask in the above process steps, the mask used to form the first isolation region 171 and the second isolation region 172 in this process step is different from the mask used in the above process steps; it is a different mask, meaning that the two process steps do not use the same mask.

[0079] It should be noted that, as Figure 5b shown (specific Figure 5b (Left view), the first isolation region 171 is located at the contact position between the N-type well region 140 and the first P-type well region unit 150. The depth of the first isolation region is less than the depth of the N-type well region, therefore there is a gap between the lower edge of the first isolation region and the deep N-type well region; as Figure 5b shown (specific Figure 5b (Right view) The second isolation region 172 is formed at the position of the second P-type well unit 160, and the diameter of the formed second isolation region 172 is larger than the diameter of the original second P-type well unit 160.

[0080] Specifically, in this embodiment of the invention, a second isolation region 172 is formed located in the driving region 120, such as... Figure 9 As shown, it includes:

[0081] S241. Etch the location of the second P-type well unit 160, and the inner diameter of the etched area is larger than the diameter of the second P-type well unit 160.

[0082] It should be understood that etching is performed on the location of the second P-type well unit 160, wherein the inner diameter of the etched area formed after etching is larger than the diameter of the second P-type well unit 160. Here, the second P-type well unit 160 is etched away, and the etched area is larger than the original area where the second P-type well unit 160 was located.

[0083] S242. Remove the second P-type well region unit 160 and fill the etched area with oxide to form the second isolation region 172.

[0084] It should be understood that after the second P-type well unit 160 is etched away, oxide is filled in the etched area, including the area where the original second P-type well unit 160 was located, to form the second isolation region 172.

[0085] It should be noted that, Figure 5b The dashed box of the second P-type well unit 160 shown is actually the etched area. Therefore, the mark of the second P-type well unit 160 no longer exists. That is, the area within the dashed box is filled with oxide to form the second isolation area 172.

[0086] S250. A memory cell is formed on the upper surface of the first P-type well region cell to obtain a memory cell array.

[0087] In embodiments of the present invention, such as Figure 5c As shown (specifically) Figure 5c (Left view of the image) A memory cell array 180 is fabricated on the upper surface of the first P-type well region cell. The specific fabrication method of the memory cell array 180 is well known to those skilled in the art and will not be described in detail here.

[0088] S260, A source, a drain, and a gate are formed between the second isolation regions 172 to obtain the high-voltage CMOS transistor.

[0089] In this embodiment of the invention, a polysilicon gate is prepared on the surface of the driving region of the silicon substrate and at corresponding positions between two adjacent second isolation regions, and the source and drain of a transistor are formed between the second isolation regions.

[0090] Specifically, a source, drain, and gate are formed between the second isolation regions to obtain the high-voltage CMOS transistor, such as... Figure 10 As shown, it includes:

[0091] S261, such as Figure 5c As shown (specifically as follows) Figure 5c (Right view), polysilicon etching is performed on the upper surface of the silicon substrate between the second isolation regions 172 to form the gate 191;

[0092] S262. N-ion implantation is performed in the silicon substrate between the second isolation regions 172 and in the corresponding regions on both sides of the gate 191 to form N-S / D regions 192.

[0093] S263. N+ ion implantation is performed between the second isolation region 172 and the N-S / D region 192 to form N+S / D regions 193 located on both sides of the second isolation region 172 and in contact with the sidewalls of the second isolation region 172. The depth of the N+S / D region 193 is greater than the depth of the N-S / D region 192. Both the N+S / D region 193 and the N-S / D region 192 are used to form the source and drain electrodes.

[0094] It should be noted that a gate insulating film (not shown in the figure) is disposed between the gate 191 and the upper surface of the silicon substrate, and the gate insulating film has two or more different thicknesses.

[0095] It should be understood that since CMOS transistors include low-voltage transistors and high-voltage transistors, there are at least two different thicknesses of the gate insulating film, and the gate insulating film of the high-voltage transistor is thicker.

[0096] In this embodiment of the invention, when the CMOS transistor further includes a low-voltage CMOS transistor, the field region ion implantation process below the isolation region of the high-voltage CMOS transistor and the formation process of the P-type well region cell of the low-voltage CMOS transistor are implemented based on the same mask, and the doping concentration of the field region ions below the isolation region of the high-voltage CMOS transistor is greater than the doping concentration of the silicon substrate.

[0097] It should be understood that the field region ion implantation process below the isolation region of the high-voltage CMOS transistor in the embodiments of the present invention can also be implemented using the same mask as the formation process of the P-type well cell of the low-voltage CMOS transistor. Therefore, compared with the prior art of separately adding a mask to implement the field region ion implantation process, the cost is effectively reduced, and it is comparable to the fabrication cost of ordinary non-high-voltage CMOS semiconductor devices. Therefore, the fabrication method of the NAND flash memory device provided by the present invention can guarantee the performance of the NAND flash memory device without increasing the additional process cost.

[0098] In summary, the method for fabricating a NAND flash memory device provided by this invention completes the fabrication of a memory cell array and a driving circuit on the same silicon substrate to obtain a NAND flash memory device. During this fabrication process, the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented using the same mask, thus eliminating the need for a mask layer and effectively reducing costs. The NAND flash memory device fabricated using this method enhances the isolation characteristics of the isolation region, thereby ensuring high-voltage operation of the CMOS transistor. Furthermore, since the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented using the same mask, the cost is significantly reduced compared to the prior art which separately adds a mask to achieve the field region ion implantation process, and is comparable to the fabrication cost of ordinary non-high-voltage CMOS semiconductor devices. Additionally, the field region ion implantation process below the isolation region of the high-voltage CMOS transistor in this embodiment can also be implemented using the same mask as the formation process of the P-type well cells of the low-voltage CMOS transistor. Therefore, the method for manufacturing NAND flash memory devices provided by the present invention can guarantee the performance of NAND flash memory devices without increasing additional process costs.

[0099] As another embodiment of the present invention, a NAND flash memory storage device is provided, which is prepared according to the preparation method of the NAND flash memory storage device described above.

[0100] In summary, the NAND flash memory device and its fabrication method provided by this invention utilize the same mask for both the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array. This eliminates the need for a mask layer, effectively reducing costs. The NAND flash memory device fabricated using this method enhances the isolation characteristics of the isolation region, ensuring high-voltage operation of the CMOS transistor. Furthermore, since the field region ion implantation process of the high-voltage CMOS transistor and the formation process of the P-type well cells in the memory cell array are implemented using the same mask, the cost is significantly reduced compared to existing technologies that separately add a mask for the field region ion implantation process, and is comparable to the fabrication cost of ordinary non-high-voltage CMOS semiconductor devices. Additionally, the field region ion implantation process below the isolation region of the high-voltage CMOS transistor in this invention can also be implemented using the same mask as the formation process of the P-type well cells of the low-voltage CMOS transistor. Therefore, the NAND flash memory device and its fabrication method provided by this invention can guarantee the performance of the NAND flash memory device without increasing additional process costs.

[0101] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A method for fabricating a NAND flash memory storage device, characterized in that, include: A silicon substrate is provided, the silicon substrate being divided into a storage region and a driving region; A memory cell array is formed in the memory region of the silicon substrate and a driving circuit is formed in the driving region of the silicon substrate. The driving circuit includes at least a CMOS transistor, and the CMOS transistor includes at least a high-voltage CMOS transistor. The field region ion implantation process below the isolation region of the high-voltage CMOS transistor and the formation process of the P-type well region cells in the memory cell array are implemented based on the same mask. The doping concentration of the field region ions below the isolation region of the high-voltage CMOS transistor is greater than the doping concentration of the silicon substrate. The method includes forming a memory cell array in the memory region of the silicon substrate and forming a driving circuit in the driving region of the silicon substrate, comprising: A deep N-type well region is formed in the storage region of the silicon substrate. N-type well regions are formed at intervals on the deep N-type well region; A first P-type well unit is formed in the storage region and a second P-type well unit is formed at intervals in the driving region on the silicon substrate of the driving region based on the same mask between each two adjacent N-type well regions in the storage region and on the silicon substrate of the driving region. Field ion implantation is performed below the second P-type well unit. The first P-type well unit is located between two adjacent N-type well regions. Simultaneously, a first isolation region is formed in the storage region and a second isolation region is formed in the drive region, wherein the first isolation region is located in the contact region between the N-type well region and the first P-type well region unit, and there is a gap between the lower edge of the first isolation region and the deep N-type well region, and the second isolation region is formed at the position of the second P-type well region unit; A memory cell is formed on the upper surface of the first P-type well region cell to obtain a memory cell array; A source, drain, and gate are formed between the second isolation regions to obtain the high-voltage CMOS transistor; Forming first P-type well cells in the storage region and spaced second P-type well cells in the driving region on the silicon substrate of the driving region based on the same mask between every two adjacent N-type well cells in the storage region, and performing field ion implantation below the second P-type well cells, including: P-type ion implantation is performed on the silicon substrate of the driving region and between every two adjacent N-type well regions in the storage region, based on the same mask, to form a first P-type well region unit located in the storage region and a second P-type well region unit located at intervals in the driving region. Field ion implantation is performed below the second P-type well unit using the same mask template.

2. The method for manufacturing a NAND flash memory storage device according to claim 1, characterized in that, Forming a second isolation region located in the driving region includes: The location of the second P-type well unit is etched, and the inner diameter of the etched area is larger than the diameter of the second P-type well unit. The second P-type well region cell is removed, and the etched region is filled with oxide to form a second isolation region.

3. The method for manufacturing a NAND flash memory storage device according to claim 1, characterized in that, Forming a source, drain, and gate between the second isolation regions to obtain the high-voltage CMOS transistor includes: A gate is formed by polysilicon etching on the upper surface of the silicon substrate between the second isolation regions; N-ion implantation is performed in the silicon substrate between the second isolation regions and in the corresponding regions on both sides of the gate to form N-S / D regions; N+ ion implantation is performed between the second isolation region and the N-S / D region to form N+S / D regions located on both sides of the second isolation region and in contact with the sidewall of the second isolation region. The depth of the N+S / D region is greater than the depth of the N-S / D region. Both the N+S / D region and the N-S / D region are used to form the source and drain.

4. The method for manufacturing a NAND flash memory storage device according to claim 3, characterized in that, A gate insulating film is disposed between the gate and the upper surface of the silicon substrate, and the gate insulating film has two or more different thicknesses.

5. The method for manufacturing a NAND flash memory storage device according to claim 1, characterized in that, The operating voltage of the high-voltage CMOS transistor is at least greater than 10V.

6. The method for manufacturing a NAND flash memory storage device according to claim 1, characterized in that, The silicon substrate includes a P-type silicon substrate.

7. The method for manufacturing a NAND flash memory storage device according to claim 1, characterized in that, When the CMOS transistor also includes a low-voltage CMOS transistor, the field region ion implantation process below the isolation region of the high-voltage CMOS transistor and the formation process of the P-type well region cell of the low-voltage CMOS transistor are implemented based on the same mask, and the doping concentration of the field region ions below the isolation region of the high-voltage CMOS transistor is greater than the doping concentration of the silicon substrate.

8. A NAND flash memory storage device, characterized in that, The NAND flash memory storage device is prepared according to any one of claims 1 to 7.

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