Ferroelectric capacitor and preparation method thereof, and three-dimensional ferroelectric memory array

Abstract

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor, a preparation method thereof and a three-dimensional ferroelectric memory array, and the ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric dielectric layer, a deoxidizing layer and a top electrode which are sequentially arranged from bottom to top; the ferroelectric medium layer is an Hf < 1-x > Zr < x > O < 2 > layer, 0 lt; xlt; the Hf-rich composition is realized by controlling the Hf: Zr super-cycle ratio of atomic layer deposition; the thickness of the ferroelectric medium layer is 1-6 nm, and the thickness of the bottom electrode is 0.1-5 nm. Compared with the prior art, the problems of polarization characteristic degradation caused by thinning of the ferroelectric layer in the hafnium-based ferroelectric capacitor and crosstalk in the FeRAM in the prior art are solved. According to the scheme, the oxygen vacancy concentration is accurately adjusted to inhibit the formation of a non-ferroelectric phase, so that the ultra-thin ferroelectric film can still maintain relatively high remanent polarization while the size is reduced, a storage window is effectively improved, and the wake-up requirement is reduced.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics, specifically relating to a ferroelectric capacitor and its preparation method, and a three-dimensional ferroelectric memory array. Background Technology

[0002] Ferroelectric RAM (FeRAM) is a device that stores data by utilizing the reversible polarization of ferroelectric materials when an electric field is applied. Its basic principle is to write and read information by changing the polarization state of the material. For decades, although ferroelectric RAM has shown advantages in read / write speed and durability, its development has been limited by issues related to size miniaturization and integration into CMOS processes. Since the first report of the ferroelectricity of doped HfO2 thin films in 2011, this discovery has attracted widespread attention from academia and industry. Hafnium-based ferroelectric capacitors not only possess high dielectric constants, good thermal stability, and low-temperature crystallization characteristics, but also exhibit good compatibility with existing CMOS technologies, making them a promising candidate for next-generation non-volatile memories.

[0003] To achieve higher storage density and lower operating voltage, the thickness of ferroelectric thin films needs to be miniaturized. However, while thin film miniaturization increases device integration density, it also introduces numerous reliability issues, such as dielectric breakdown, fatigue failure, and retention degradation. Furthermore, as the thickness decreases, HfO2-based thin films are more likely to stabilize in the non-ferroelectric tetragonal phase, leading to a degradation in the film's polarization characteristics and a reduction in initial remanent polarization intensity. This results in a smaller storage window and exacerbates the wake-up effect, undoubtedly increasing the difficulty of device design and application.

[0004] In existing technologies, such as CN117881194A, a method for preparing an HfO2-based ferroelectric capacitor and its application are disclosed. This method introduces a built-in electric field by annealing the ferroelectric dielectric layer before growing the top electrode, thereby achieving ferroelectric hysteresis without the need for wake-up. However, this method only achieves 8.5 μC / cm² when a voltage of 1.2 V is applied. 2 The residual polarization intensity is low, and its performance is poor.

[0005] Besides the reliability challenges brought about by thin-film miniaturization, three-dimensional vertical stacking technology of FeRAM has also been widely studied to further improve storage density. Typical cell structures include 1T1C, 2T1C, 0T1C, 1TnC, and 2TnC. Among them, the 1TnCFeRAM structure can share multiple ferroelectric capacitors on a single common node to achieve high-density storage. However, this structure is affected by crosstalk from adjacent cells during operation, which in turn affects the read / write accuracy and overall data reliability of the storage array. Therefore, how to effectively reduce the impact of crosstalk by optimizing thin-film processes, structural design, and material control while ensuring the excellent performance of hafnium-based ferroelectric capacitors has become a critical technical challenge that urgently needs to be solved. Summary of the Invention

[0006] The purpose of this invention is to solve at least one of the problems in the prior art caused by the miniaturization of ferroelectric thin film (ferroelectric dielectric layer) size, such as polarization degradation, reduced storage window, decreased reliability, and crosstalk of storage array, and to provide a high-reliability ferroelectric capacitor, a three-dimensional ferroelectric memory array and its manufacturing method, so as to improve device performance and achieve high-density three-dimensional integration.

[0007] Specifically, this invention achieves precise regulation of oxygen vacancy concentration by optimizing the material composition, interface engineering, and process control of ferroelectric thin films, suppressing the formation of non-ferroelectric T phases, and promoting the stable existence of ferroelectric O phases. As a result, even as the size of ultrathin ferroelectric thin films is further reduced, they still maintain a high initial polarization intensity, significantly improve the storage window, and reduce dependence on the wake-up process.

[0008] The following key features and their functions are specifically introduced in this invention and explained below:

[0009] (1) By appropriately increasing the doping ratio of Hf in the ultrathin HZO ferroelectric dielectric layer, the formation energy of the nonferroelectric T phase is effectively enhanced, the formation of the T phase is suppressed, and the formation of the O phase is promoted.

[0010] (2) The use of ultrathin bottom electrodes has a low nucleation density. After annealing, the grain size of the ferroelectric thin film can be significantly increased, and the uniformity of grain orientation can be improved.

[0011] (3) An oxygen removal layer is set on the ferroelectric thin film to introduce an appropriate amount of oxygen vacancies, further reducing the potential barrier for the transition from the T phase to the O phase and significantly increasing the proportion of the ferroelectric O phase in the thin film.

[0012] The three key features mentioned above work together to enable the ultrathin ferroelectric thin film of the present invention to have a high content of ferroelectric O phase and uniform grain orientation, thereby exhibiting high initial polarization intensity, concentrated and sharp polarization peaks even in a non-awakened state, and the device as a whole exhibits excellent high-temperature stability and anti-interference characteristics.

[0013] In addition, in view of the crosstalk problem of the storage array caused by uneven polarization switching distribution in the 1TnC structure, the present invention utilizes the characteristic of concentrated polarization peak distribution to effectively reduce the interference of unselected devices and significantly improve the read / write accuracy and data retention ability of the three-dimensional storage array.

[0014] The present invention further proposes a ferroelectric memory array design scheme suitable for high-density three-dimensional integration. By adopting the above-optimized ferroelectric capacitor structure and manufacturing method, the ferroelectric capacitors can be vertically stacked to achieve higher storage density on a limited chip area, meeting the requirements of the new generation of non-volatile memories for high density, low power consumption and high reliability.

[0015] The object of the present invention is achieved by the following technical solutions:

[0016] In the first aspect, the present invention discloses a ferroelectric capacitor, comprising a substrate, a bottom electrode, a ferroelectric dielectric layer, a deoxidation layer and a top electrode, which are sequentially arranged from bottom to top;

[0017] Among them, the ferroelectric dielectric layer is a Hf 1-x Zr x O2 layer, where 0 < x < 0.5; the Hf-rich composition of the ferroelectric dielectric layer is achieved by controlling the Hf:Zr supercycle ratio of atomic layer deposition; the thickness of the ferroelectric dielectric layer is 1 - 6 nm, and the thickness of the bottom electrode is 0.1 - 5 nm.

[0018] Preferably, the substrate includes a highly doped silicon substrate, a highly doped germanium substrate and a silicon-germanium substrate; and / or, the material of the bottom electrode includes TiN, W, Ru, Mo, Ta, TaN, Ti and Pt; and / or, the material of the top electrode includes TiN, W, Ru, Mo, Ta, TaN, Ti and Pt; and / or, the thickness of the top electrode is 10 - 100 nm; and / or, the material of the deoxidation layer includes Ti, Nb, Ta, Al, Zr, Mo and Hf, and oxides of Ti, Nb, Ta, Al, Zr, Mo and Hf; and / or, the thickness of the deoxidation layer is 0.1 - 5 nm.

[0019] Preferably, the ferroelectric dielectric layer is a Hf 0.6 Zr 0.4 O2 layer.

[0020] In the second aspect, the present invention discloses a preparation method of any one of the above ferroelectric capacitors, comprising the following steps:

[0021] Step 1: Grow a bottom electrode on the surface of the substrate;

[0022] Step 2: Deposit a ferroelectric dielectric layer on the surface of the bottom electrode by atomic layer deposition, and achieve the Hf-rich composition of the ferroelectric dielectric layer by controlling the Hf:Zr supercycle ratio;

[0023] Step 3: Grow an oxygen-removing layer on the surface of the ferroelectric layer;

[0024] Step 4: Coat the surface of the deoxygenated layer with photoresist and expose and develop it, then grow the top electrode on the surface;

[0025] Step 5: Peeling process;

[0026] Step 6: Post-annealing.

[0027] Preferably, the bottom electrode is grown by magnetron sputtering; and / or, the top electrode is grown by magnetron sputtering.

[0028] The magnetron sputtering process uses a TiN target with a DC sputtering power of 100W and an Ar gas flow rate of 1.15 mTorr; and / or, the magnetron sputtering process uses a W target with a DC sputtering power of 100W and an Ar gas flow rate of 3 mTorr; and / or, the magnetron sputtering process uses a Ru target with a DC sputtering power of 100W and an Ar gas flow rate of 3 mTorr.

[0029] Preferably, in the atomic layer deposition: the Zr precursor source includes tetra(ethylmethylamino)zirconium and tetra(dimethylamino)zirconium; and / or, the Hf precursor source includes tetra(ethylmethylamino)hafnium and tetra(dimethylamino)hafnium; and / or, the oxygen source is deionized water, hydrogen peroxide or ozone; and / or, the Hf:Zr supercycle ratio is 3:2.

[0030] Preferably, the deoxygenated layer is grown by magnetron sputtering.

[0031] Preferably, the post-annealing process is carried out in an inert atmosphere, with a heating rate of 10-30℃ / s, an annealing temperature of 300-700℃, and an annealing time of 10s-24h.

[0032] A third aspect of the present invention discloses a three-dimensional ferroelectric memory array, including bit lines, word lines, board lines, transistors, and ferroelectric capacitors as described above.

[0033] The three-dimensional ferroelectric memory array is an M-row N-column array, therefore, there are M transistors and M×N ferroelectric capacitors, where M and N are both natural numbers greater than 0.

[0034] The bit line is connected to the source of the M transistors, so that the M transistors share the bit line as a common node.

[0035] The word line is connected to the gate of the transistor in row M to achieve row selection;

[0036] The drain of the m-th transistor is connected to one end of the N ferroelectric capacitors in the m-th row, and the other end of the N ferroelectric capacitors is connected to the plate line, so that the N ferroelectric capacitors are interconnected with the plate line as a common node, where m is a natural number between 0 and M.

[0037] Preferably, the three-dimensional ferroelectric memory array comprises:

[0038] Substrate;

[0039] Two field-effect transistors are formed on a substrate and stacked vertically along the z-axis, wherein the lower layer is a select transistor and the upper layer is an access transistor; the source of the select transistor is used as a bit line; the gates of multiple select transistors located in the same column in the x-axis direction are connected by source select lines to achieve column selection; the gates of multiple access transistors located in the same row in the y-axis direction are connected by word lines to achieve row selection.

[0040] The drain of the access transistor is connected to a columnar bottom electrode grown on the substrate along the z-axis, and the bottom electrode constitutes the inner electrode support structure of the ferroelectric capacitor; an atomic layer is deposited on the ferroelectric dielectric layer on the sidewall of the bottom electrode.

[0041] Oxygen-removing layer grown on ferroelectric dielectric layer;

[0042] Top electrode grown on deoxygenated layer;

[0043] The substrate, bottom electrode, ferroelectric dielectric layer, deoxygenation layer and top electrode are used to form a ferroelectric capacitor;

[0044] And, several layers of wires connecting each ferroelectric capacitor.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] 1. The high-reliability ferroelectric capacitor of this invention requires no wake-up and has an initial remanent polarization intensity as high as 62 μC / cm. 2 The main method is to increase the content of the ferroelectric O phase and suppress the formation of the non-ferroelectric T phase to achieve excellent ferroelectric properties in the initial state.

[0047] 2. The high-reliability ferroelectric capacitor of the present invention still has excellent retention characteristics under extreme temperature conditions, which is due to the increase in grain size and the improvement of orientation consistency, which reduces grain boundary defects and leakage current, and significantly improves environmental adaptability and long-term stability.

[0048] 3. The high-reliability ferroelectric capacitor of the present invention has the characteristic of concentrated polarization switching distribution, that is, the polarization peak is relatively sharp. This is due to the high O phase content and the uniformity of grain orientation, which effectively reduces the crosstalk effect on unselected devices in the 1TnC structure, reduces misreading, and enhances the stability and accuracy of data storage.

[0049] 4. The three-dimensional ferroelectric memory array of the present invention can be vertically stacked. By adopting an ultra-thin ferroelectric capacitor structure, it achieves a significant increase in storage integration density, low operating voltage, and meets the requirements of high-density storage applications. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the structure of the ferroelectric capacitor prepared in Example 1;

[0051] Figure 2 This is a comparison diagram of the initial / wake-up state PV ferroelectric hysteresis characteristics of the ferroelectric capacitors of Example 1 and Comparative Example 1;

[0052] Figure 3 This is a comparison chart of the initial state PV hysteresis curves of Example 1 and Comparative Examples 1, 2, and 3.

[0053] Figure 4 This is a comparison chart of the ferroelectric capacitors of Example 1 and Comparative Example 1 under a cycle durability test at a voltage of 2V and a frequency of 455kHz.

[0054] Figure 5 The results show the retention characteristics of the ferroelectric capacitors of Example 1 and Comparative Example 1 under high temperature baking conditions of 225°C. Among them, Example 1 still has a sufficient memory window after being baked at 225°C for 1000 hours and can work normally.

[0055] Figure 6 The shift results of PV ferroelectric hysteresis before and after continuous baking at 225℃ for 7 days in Comparative Example 1.

[0056] Figure 7 The results show the shift of PV ferroelectric hysteresis before and after continuous baking at 225°C for 7 days in Example 1.

[0057] Figure 8 This is a schematic diagram of the circuit structure of a ferroelectric memory array provided in Embodiment 9;

[0058] Figure 9 This is a schematic diagram of the structure of the three-dimensional ferroelectric memory array provided in Example 10;

[0059] In the diagram: 100 - bit line; 101 - word line m; 102 - word line m+1; 103 - word line M-1; 104 - word line M; 105 - board line n; 106 - board line n+1; 107 - board line n+2; 108 - board line N-1; 109 - board line N;

[0060] 200 - Substrate; 201 - Source of the select transistor; 202 - Source select line; 203 - Word line; 204 - Drain of the access transistor; 205 - Bottom electrode; 206 - Oxygen removal layer; 207 - First layer board line; 208 - Second layer board line; 209 - Third layer board line; 210 - Fourth layer board line. Detailed Implementation

[0061] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0062] Unless otherwise specified, the reagents used in the following description are conventional commercial products, the methods used are known in the art, and any other matters not covered herein can be handled using existing technology.

[0063] Example 1

[0064] A highly reliable ferroelectric capacitor has a structure consisting of, from bottom to top, a substrate, an ultrathin bottom electrode, and an ultrathin Hf electrode. 1-x Zr x O2 ferroelectric dielectric layer, deoxygenation layer and top electrode.

[0065] This ferroelectric capacitor is manufactured through the following steps:

[0066] Step 1: Grow an ultrathin bottom electrode on the substrate surface;

[0067] Step 2: Deposit an ultrathin Hf layer on the surface of the ultrathin bottom electrode 1-x Zr x O2 ferroelectric dielectric layer;

[0068] Step 3: Grow an oxygen-removing layer on the surface of the ultrathin ferroelectric layer;

[0069] Step 4: Coat the surface of the deoxygenated layer with photoresist and expose and develop it, then grow the top electrode on the surface;

[0070] Step 5: Peeling process;

[0071] Step 6: Post-annealing.

[0072] in:

[0073] The substrate can be a highly doped silicon substrate (n-type or p-type), or it can be replaced with a highly doped Ge or SiGe single crystal material.

[0074] The ultra-thin bottom / top electrodes are grown by magnetron sputtering. The materials for the ultra-thin bottom electrode can be TiN, W, Ru, Mo, Ta, TaN, Ti, Pt, etc. The thickness of the ultra-thin bottom electrode is 0.1 - 5 nm, and the thickness of the top electrode is 10 - 100 nm. The magnetron sputtering process uses a TiN target, with a DC sputtering power of 100 W and an Ar gas flow rate of 1.15 mTorr; or the magnetron sputtering process uses a W target, with a DC sputtering power of 100 W and an Ar gas flow rate of 3 mTorr; or the magnetron sputtering process uses a Ru target, with a DC sputtering power of 100 W and an Ar gas flow rate of 3 mTorr.

[0075] Ultra-thin Hf 1-x Zr x The preparation of the O2 ferroelectric dielectric layer is by atomic layer deposition technology, depositing ultra-thin ferroelectric Hf 1-x Zr x O2 dielectric layer (0 < x < 0.5) with a thickness of 1 - 6 nm. Through precise control of the Hf:Zr supercycle ratio (such as a 3:2 supercycle mode), the Hf-rich composition and excellent ferroelectric phase stability of the thin film are ensured. The Zr precursor sources include tetrakis(ethylmethylamino)zirconium (TEMAZr) and tetrakis(diethylamino)zirconium (TDMAZr), the Hf precursor sources include tetrakis(ethylmethylamino)hafnium (TEMAHf) and tetrakis(diethylamino)hafnium (TDMAHf), and the oxygen source is deionized water or hydrogen peroxide or ozone.

[0076] The oxygen removal layer is grown by magnetron sputtering, depositing a 0.1 - 5 nm oxygen removal layer on the ultra-thin ferroelectric dielectric layer. The materials for the oxygen removal layer can be metals such as Ti, Nb, Ta, Al, Zr, Mo, Hf and their oxides.

[0077] The post-annealing treatment is as follows: carried out in an inert atmosphere, with a heating rate of 10 - 30 °C / s, an annealing temperature of 300 - 700 °C, and an annealing time of 10 s - 24 h.

[0078] In this embodiment, specifically:

[0079] First, a 2 nm ultra-thin TiN bottom electrode is grown on an n-type highly doped silicon substrate by magnetron sputtering; the magnetron sputtering process uses a TiN target, with a DC sputtering power of 100 W and an Ar gas flow rate of 1.15 mTorr;

[0080] Secondly, a 5 nm ultra-thin Hf 1-x Zr xThe O2 ferroelectric dielectric layer was deposited at a temperature of 250℃. Tetra(ethylmethylamino)zirconium was used as the Zr precursor, and tetra(ethylmethylamino)hafnium as the Hf precursor. The Hf:Zr supercycle ratio was 3:2, meaning three HfO2 cycles were deposited followed by two ZrO2 cycles, alternating between the two cycles, ultimately growing Hf. 0.6 Zr 0.4 O2 thin film;

[0081] Then, a 2nm Ti deoxygenation layer was grown on the ferroelectric dielectric layer by magnetron sputtering;

[0082] Next, photoresist is coated on the deoxygenated layer, pre-baked at 150°C for 2 minutes, exposed and then post-baked at 120°C for 2 minutes, immersed in developer for 55 seconds, rinsed with deionized water and dried.

[0083] Then, a 40nm TiN top electrode was grown by magnetron sputtering. The magnetron sputtering process used a TiN target, a DC sputtering power of 100W, and an Ar gas flow rate of 1.15mTorr.

[0084] Next, a patterned top electrode is obtained through a stripping process; it is then immersed in an acetone solution until the photoresist and excess metal are removed, followed by immersion in anhydrous ethanol to remove the acetone, and finally rinsed with deionized water and dried.

[0085] Finally, the device was directly treated in an N2 atmosphere using a rapid thermal annealing process, with a heating rate controlled at 15-20℃ / s, an annealing temperature of 600℃, and an annealing time of 30s.

[0086] like Figure 1 As shown, the high-reliability ferroelectric capacitor prepared in Example 1 consists of, from bottom to top, a highly silicon-doped substrate, an ultrathin TiN bottom electrode, an ultrathin ferroelectric dielectric layer, a deoxygenation layer, and a TiN top electrode; wherein, the TiN bottom electrode has a thickness of 2 nm and Hf 0.6 Zr 0.4 The O2 ferroelectric dielectric layer is 5 nm thick, the Ti deoxygenation layer is 2 nm thick, and the TiN top electrode is 40 nm thick.

[0087] Example 2

[0088] This embodiment is basically the same as Embodiment 1, the main difference being that the substrate is a p-type highly doped silicon.

[0089] Example 3

[0090] This embodiment is basically the same as embodiment 1, the main difference being that the bottom / top electrode uses a W electrode.

[0091] Example 4

[0092] This embodiment is basically the same as embodiment 1, the main difference being that the bottom / top electrode uses a Ru electrode.

[0093] Example 5

[0094] This embodiment is basically the same as Embodiment 1, the main difference being that: in the deposition of the ferroelectric dielectric layer, tetra(diethylamino)zirconium (TDMAZr) is used as the Zr precursor source and tetra(diethylamino)hafnium (TDMAHf) is used as the Hf precursor source.

[0095] Example 6

[0096] This embodiment is basically the same as Embodiment 1, the main difference being that the thickness of the ferroelectric dielectric layer is 3.5 nm.

[0097] Example 7

[0098] This embodiment is basically the same as Embodiment 1, the main difference being that the deoxidation layer uses Hf metal.

[0099] Example 8

[0100] This embodiment is basically the same as Embodiment 1, with the main difference being that: during the annealing process, the heating rate is controlled at 25-30℃ / s, the annealing temperature is 400℃, and the annealing time is 900s.

[0101] Comparative Example 1

[0102] First, a 40 nm TiN bottom electrode was grown on a SiO2 / Si substrate by magnetron sputtering. The magnetron sputtering process used a TiN target, a DC sputtering power of 100 W, and an Ar gas flow rate of 1.15 mTorr.

[0103] Secondly, a 5nm ultrathin Hf layer is deposited on the bottom electrode using atomic layer deposition technology. 0.5 Zr 0.5 An O2 ferroelectric dielectric layer was deposited at a temperature of 250℃. A 1:1 Hf:Zr supercycle ratio was used, meaning one HfO2 cycle was deposited followed by one ZrO2 cycle, alternating between the two, until an Hf layer was finally grown. 0.5 Zr 0.5 O2 thin film.

[0104] Then, in ultra-thin Hf 0.5 Zr 0.5 Photoresist was coated on the O2 ferroelectric dielectric layer, pre-baked at 150°C for 2 minutes, exposed and then post-baked at 120°C for 2 minutes. The layer was then immersed in the developer for 55 seconds and developed, rinsed with deionized water and dried.

[0105] Next, a 40nm TiN top electrode was grown by magnetron sputtering. The magnetron sputtering process used a TiN target, a DC sputtering power of 100W, and an Ar gas flow rate of 1.15mTorr.

[0106] Next, a patterned top electrode is obtained through a stripping process; it is then immersed in an acetone solution until the photoresist and excess metal are removed, followed by immersion in anhydrous ethanol to remove the acetone, and finally rinsed with deionized water and dried.

[0107] Finally, the ultrathin ferroelectric layer was directly treated in an N2 atmosphere using a rapid thermal annealing process, with the heating rate controlled at 15-20℃ / s, the annealing temperature at 600℃, and the annealing time at 30s.

[0108] Comparative Example 2

[0109] This comparative example is basically the same as Comparative Example 1, the main difference being that a 5.5nm ultrathin Hf layer is deposited on the bottom electrode using atomic layer deposition technology. 1-x Zr x The O2 ferroelectric dielectric layer was deposited using an Hf:Zr supercycle ratio of 3:2.

[0110] Comparative Example 3

[0111] This comparative example is basically the same as Comparative Example 1, the main difference being that a 5.5nm ultrathin Hf layer is deposited on the bottom electrode using atomic layer deposition technology. 1-x Zr x The O2 ferroelectric dielectric layer was deposited using an Hf:Zr supercycle ratio of 3:2, and the bottom electrode thickness was replaced with 2nm.

[0112] like Figure 2 As shown, the high-reliability ferroelectric capacitor prepared in Example 1 has the characteristics of not requiring wake-up and having a dense distribution of polarization peaks, with an initial-state remanent polarization intensity as high as 62 μC / cm. 2 This indicates its excellent ferroelectric properties.

[0113] like Figure 3 As shown, Comparative Example 1 (Hf:Zr = 1:1) exhibits a lower initial polarization intensity and obvious wake-up characteristics; Comparative Example 2, after appropriate Hf doping, shows a slight increase in the O phase ratio, but the initial polarization enhancement is limited; Comparative Example 3, based on appropriate Hf doping, also introduces an ultrathin bottom electrode, which increases the grain size and enhances polarization; Example 1 further introduces an oxygen removal layer to regulate the oxygen vacancy distribution, synergistically improve the O phase content and grain orientation consistency, and achieve high initial polarization intensity and sharp and full ferroelectric hysteresis characteristics.

[0114] like Figure 4 As shown, the high-reliability ferroelectric capacitor prepared in Example 1 has a >10 10The high cycle life demonstrates its excellent durability.

[0115] like Figure 5 As shown, compared with Comparative Example 1, Example 1 exhibits superior high-temperature retention characteristics with a holding time of over 1000 hours under baking conditions at 225°C.

[0116] like Figure 6 , Figure 7 As shown, Example 1 exhibits a smaller PV hysteresis offset after high-temperature baking compared to Comparative Example 1, indicating that it maintains stability.

[0117] Example 9

[0118] Based on the ferroelectric capacitor structure of Embodiment 1, this embodiment provides a three-dimensional 1TnC ferroelectric memory array for mitigating crosstalk effects.

[0119] Figure 8 A circuit diagram of an M-row × N-column 1TnC ferroelectric memory array is shown. The specific structure is as follows:

[0120] Bit line 100 (BL) serves as a common node, connecting to the source of the M row of transistors. Word lines (WL), including word lines m 101, m+1 102, ..., M-1 103, and M 104, control the gates of the 1st to mth transistors respectively, enabling row selection. The drain of the first transistor is connected to one end of the N ferroelectric capacitors in the first column. The other ends of the N ferroelectric capacitors are connected to plate lines (PL), including plate lines n 105, n+1 106, n+2 107, ..., N-1 108, and N 109. Here, M and N are both natural numbers greater than 0; m is a natural number between 0 and M; and n is a natural number between 0 and N.

[0121] The plate lines (PL) of each column of ferroelectric capacitors are interconnected as common nodes to optimize signal transmission, improve data storage stability, and reduce crosstalk.

[0122] Example 10

[0123] Based on the ferroelectric capacitor structure of Embodiment 1, this embodiment provides a 4×4×4 three-dimensional 1TnC ferroelectric memory array.

[0124] Figure 9 A schematic diagram of a 4×4×4 three-dimensional 1TnC ferroelectric memory array is shown, which mainly includes the following:

[0125] Two field-effect transistors are formed on substrate 200 by etching and deposition processes, stacked vertically along the z-axis. The bottom transistor is called the gate transistor, and the transistor above it is the access transistor (used for data access). The gate / access transistor can be structured as a gate ring or a channel ring, and the channel can be made of semiconductor materials such as Si, Ge, IGZO, MoS2, and WS2.

[0126] The source 201 of the selector is used as bit line 100 (BL). The gates of multiple selectors in the same column (x direction) are connected through source select line 202 (SSL) to achieve column selection.

[0127] The gates of multiple access transistors in the same row (y direction) are connected via word line 203 (WL) to achieve row selection.

[0128] The drain 204 of the access transistor is connected to a columnar bottom electrode 205 grown on the substrate 200 along the z-axis direction. This bottom electrode constitutes the internal electrode support structure of the ferroelectric capacitor.

[0129] A ferroelectric dielectric layer and a deoxygenation layer 206 are grown on the sidewall of the metal columnar bottom electrode 205 using atomic layer deposition (ALD) to ensure high-quality deposition of the ferroelectric thin film.

[0130] The outer top electrode is formed through processes such as etching and deposition, thereby constructing a complete columnar ferroelectric capacitor structure.

[0131] Depending on the number of layers, each layer of ferroelectric capacitors is connected through the first layer plate line 207, the second layer plate line 208, the third layer plate line 209, and the fourth layer plate line 210 to achieve a complete three-dimensional stacked structure.

[0132] This embodiment optimizes the columnar ferroelectric capacitor structure design, achieving concentrated current distribution, effectively reducing crosstalk between devices, and enhancing anti-interference capability and high-temperature reliability. Furthermore, the optimized columnar capacitor structure significantly improves the initial polarization intensity (2Pr) of the ferroelectric thin film, enhancing the device's storage window and data reliability. Simultaneously, the three-dimensional vertical stacking structure employed in this embodiment substantially increases storage density, making it suitable for high-density storage and advanced process node three-dimensional memory applications.

[0133] This invention solves the problems of polarization degradation / shortening of storage window, decreased reliability and crosstalk of storage array caused by the miniaturization of ferroelectric thin film (ferroelectric dielectric layer) in the prior art, improves device performance and realizes high-density three-dimensional integration.

[0134] This invention achieves precise regulation of oxygen vacancy concentration by optimizing the material composition, interface engineering, and process control of ferroelectric thin films, thereby suppressing the formation of non-ferroelectric phases. This allows ultrathin ferroelectric thin films to maintain high residual polarization intensity while reducing size, thus effectively improving the storage window and reducing wake-up requirements.

[0135] This invention addresses the crosstalk problem caused by uneven polarization switching distribution in 1TnC structures by proposing a high-reliability ferroelectric capacitor with concentrated polarization switching distribution. Its polarization peak is sharper, which helps reduce interference from unselected devices and improves the read / write accuracy and data retention capability of the memory array.

[0136] This invention further proposes a design scheme for a three-dimensional ferroelectric memory array suitable for high-density integration. This scheme employs an optimized ferroelectric capacitor structure and manufacturing method, enabling vertical stacking of ferroelectric capacitors, thereby achieving higher storage density within a limited chip area. Simultaneously, by optimizing the memory cell design, the high-temperature stability and long-term reliability of the device are effectively improved, enabling it to meet the requirements of next-generation non-volatile memories for high density, low power consumption, and high reliability.

[0137] The above description of the embodiments is provided to enable those skilled in the art to understand and use the invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without inventive effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope of the invention should be within the protection scope of the present invention.

Claims

1. A ferroelectric capacitor, characterized in that, It includes, from bottom to top, a substrate, a bottom electrode, a ferroelectric dielectric layer, a deoxidizing layer, and a top electrode; Among them, the ferroelectric dielectric layer is Hf 1-x Zr x O2 layer, where 0 < x < 0.5; the Hf-rich composition of the ferroelectric dielectric layer is achieved by controlling the Hf:Zr supercycle ratio of atomic layer deposition; the thickness of the ferroelectric dielectric layer is 1-6 nm, and the thickness of the bottom electrode is 0.1-5 nm.

2. A ferroelectric capacitor according to claim 1, characterized in that, The substrate includes a highly silicon-doped substrate, a highly germanium-doped substrate, and a silicon-germanium substrate; and / or, the material of the bottom electrode includes TiN, W, Ru, Mo, Ta, TaN, Ti, and Pt; and / or, the material of the top electrode includes TiN, W, Ru, Mo, Ta, TaN, Ti, and Pt; and / or, the thickness of the top electrode is 10-100 nm; and / or, the material of the deoxidation layer includes Ti, Nb, Ta, Al, Zr, Mo, and Hf, as well as oxides of Ti, Nb, Ta, Al, Zr, Mo, and Hf; and / or, the thickness of the deoxidation layer is 0.1-5 nm.

3. A ferroelectric capacitor according to claim 1, characterized in that, The ferroelectric dielectric layer is Hf 0.6 Zr 0.4 O2 layer.

4. A method for preparing a ferroelectric capacitor as described in any one of claims 1-3, characterized in that, Includes the following steps: Step 1: Grow the bottom electrode on the substrate surface; Step 2: A ferroelectric dielectric layer is deposited on the surface of the bottom electrode using atomic layer deposition, and the Hf-rich composition of the ferroelectric dielectric layer is achieved by controlling the Hf:Zr supercycle ratio; Step 3: Grow an oxygen-removing layer on the surface of the ferroelectric layer; Step 4: Coat the surface of the deoxygenated layer with photoresist and expose and develop it, then grow the top electrode on the surface; Step 5: Peeling process; Step 6: Post-annealing.

5. The method for preparing a ferroelectric capacitor according to claim 4, characterized in that, The bottom electrode is grown by magnetron sputtering; and / or the top electrode is grown by magnetron sputtering. The magnetron sputtering process uses a TiN target with a DC sputtering power of 100W and an Ar gas flow rate of 1.15 mTorr; and / or, the magnetron sputtering process uses a W target with a DC sputtering power of 100W and an Ar gas flow rate of 3 mTorr; and / or, the magnetron sputtering process uses a Ru target with a DC sputtering power of 100W and an Ar gas flow rate of 3 mTorr.

6. The method for preparing a ferroelectric capacitor according to claim 4, characterized in that, In the atomic layer deposition described above: the Zr precursor source includes tetra(ethylmethylamino)zirconium and tetra(dimethylamino)zirconium; and / or, the Hf precursor source includes tetra(ethylmethylamino)hafnium and tetra(dimethylamino)hafnium; and / or, the oxygen source is deionized water, hydrogen peroxide or ozone; and / or, the Hf:Zr supercycle ratio is 3:

2.

7. The method for preparing a ferroelectric capacitor according to claim 4, characterized in that, The deoxygenated layer is grown by magnetron sputtering.

8. The method for preparing a ferroelectric capacitor according to claim 4, characterized in that, The post-annealing process is carried out in an inert atmosphere, with a heating rate of 10-30℃ / s, an annealing temperature of 300-700℃, and an annealing time of 10s-24h.

9. A three-dimensional ferroelectric memory array, characterized in that, Includes bit lines, word lines, board lines, transistors, and ferroelectric capacitors as described in any one of claims 1-3; The three-dimensional ferroelectric memory array is an M-row N-column array, therefore, there are M transistors and M×N ferroelectric capacitors, where M and N are both natural numbers greater than 0. The bit line is connected to the source of the M transistors, so that the M transistors share the bit line as a common node. The word line is connected to the gate of the transistor in row M to achieve row selection; The drain of the m-th transistor is connected to one end of the N ferroelectric capacitors in the m-th row, and the other end of the N ferroelectric capacitors is connected to the plate line, so that the N ferroelectric capacitors are interconnected with the plate line as a common node, where m is a natural number between 0 and M.

10. A three-dimensional ferroelectric memory array according to claim 9, characterized in that, The three-dimensional ferroelectric memory array includes: Substrate; Two field-effect transistors are formed on a substrate and stacked vertically along the z-axis, wherein the lower layer is a select transistor and the upper layer is an access transistor; the source of the select transistor is used as a bit line; the gates of multiple select transistors located in the same column in the x-axis direction are connected by source select lines to achieve column selection; the gates of multiple access transistors located in the same row in the y-axis direction are connected by word lines to achieve row selection. The drain of the access transistor is connected to a pillar-shaped bottom electrode grown on the substrate along the z-axis direction, and the bottom electrode constitutes the inner electrode support structure of the ferroelectric capacitor; an atomic layer is deposited on the ferroelectric dielectric layer on the sidewall of the bottom electrode. Oxygen-removing layer grown on ferroelectric dielectric layer; Top electrode grown on deoxygenated layer; The substrate, bottom electrode, ferroelectric dielectric layer, deoxygenation layer and top electrode are used to form a ferroelectric capacitor; And, several layers of wires connecting each ferroelectric capacitor.

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