Silicon controlled rectifier device suitable for rapid and continuous triggering and preparation method thereof

Abstract

The invention provides a silicon controlled rectifier device suitable for rapid and continuous triggering and a preparation method thereof, and belongs to the technical field of silicon controlled rectifiers, and the silicon controlled rectifier device comprises at least one first discrete device group which comprises a plurality of first discrete devices, and each first discrete device comprises a first doped region, a second lightly doped region and a third heavily doped region, the first doped region is formed in the substrate, the second lightly doped region is formed in the first doped region, and the third heavily doped region is formed in the second lightly doped region; and the at least one second discrete device group comprises a plurality of first discrete devices, each second discrete device comprises a fourth doped region and a fifth heavily doped region, the fourth doped region is formed in the substrate, and the fifth heavily doped region is formed in the fourth doped region. The beneficial effects of the invention are that the device switching frequency is improved, the turn-off time is shortened, the holding current is improved, and the device starting speed is accelerated by adopting the discrete device, the combined structure of the second lightly doped region and the third heavily doped region, and the combined structure of the fourth doped region and the fifth heavily doped region.

Description

Technical Field

[0001] This invention relates to the field of thyristor technology, and in particular to a thyristor device suitable for rapid continuous triggering and its fabrication method. Background Technology

[0002] A silicon controlled rectifier (SCR), also known as a thyristor, is a four-layer, three-terminal high-power semiconductor device. SCRs possess high voltage / current carrying capacity, fast switching characteristics, and a controllable conduction mechanism, making them widely used in power electronics. Their core function is to control the switching on and off of high-power circuits using a small current trigger signal, enabling the control of high-power devices with a small-power control, thus earning them the title of "King of Switches in Power Electronics."

[0003] Structurally, a silicon controlled rectifier (SCR) consists of four PNPN semiconductor layers, possessing three PN junctions and three electrodes: an anode, a cathode, and a gate, which are connected to the outer P-type semiconductor layer, the outer N-type semiconductor layer, and the intermediate P-type semiconductor layer, respectively. Its operating principle involves applying a forward voltage between the anode and cathode, while simultaneously injecting a trigger current (IGT) at the gate, causing the reverse-biased PN junction to break down, thus turning the device on. Furthermore, the device remains on even after the trigger current is removed, only turning off when the anode potential falls below the cathode potential or the current falls below a certain value.

[0004] Thyristors are mainly divided into two types: unidirectional thyristors and bidirectional thyristors. Bidirectional thyristors are also known as triode AC semiconductor switches (TRIAC). Unidirectional thyristors are unidirectional semiconductor switching devices that conduct only when the anode voltage is higher than the cathode voltage and a trigger signal is present. They are suitable for applications requiring unidirectional conduction or high power, and are mainly used in dimming and voltage regulation, motor speed control, industrial rectification, and inversion. Bidirectional thyristors are structurally equivalent to two unidirectional thyristors connected in reverse, providing bidirectional conduction. They can directly control the positive and negative half-cycles of AC power, simplifying AC circuit design and making them more suitable for AC circuit control, especially in small and medium power appliances and voltage regulation. Typical applications include AC voltage regulation, temperature control, and static switching. Both types of thyristors, with their high efficiency, reliability, and long lifespan, have become core components of modern power electronic systems.

[0005] With the rapid development of modern industry, applications such as high-frequency switching power supplies, electric vehicle charging piles, and renewable energy inverters place extremely stringent demands on the switching speed, dynamic response, and energy efficiency of power devices. Taking high-frequency switching power supplies as an example, the switching frequency of the device directly affects the size and efficiency of the power supply. However, the turn-off time of traditional thyristors is typically in the microsecond range, making it difficult to meet the high-frequency application requirements above 100 kilohertz. In renewable energy grid-connected inverters, rapid current commutation and low-loss characteristics are crucial for ensuring power quality and system stability. However, the long reverse recovery time of traditional thyristors leads to significant switching losses and electromagnetic interference.

[0006] The performance limitations of traditional thyristors mainly stem from their physical structure and operating mechanism, specifically in two aspects: First, the minority carrier storage effect limits the switching speed. When a thyristor is turned on, a large number of minority carriers are injected into the base region, such as electrons in the P-type base region and holes in the N-type base region. These minority carriers need to recombine or diffuse to disappear. During the turn-off process, if the minority carriers are not cleared in time, or if the minority carrier lifetime is long, the turn-off time will be prolonged. The turn-off time of traditional thyristors is typically between 10-50 microseconds, while high-frequency applications require turn-off times to be shortened to below the microsecond level. Second, junction temperature has an impact. The minority carrier lifetime is temperature-sensitive; a higher junction temperature increases the minority carrier lifetime in the base region and causes thermal excitation, which is detrimental to turn-off. At the same time, a higher junction temperature results in a larger junction capacitance and leakage current, both of which prolong the turn-off time. Summary of the Invention

[0007] To address the above technical problems, this invention provides a thyristor device suitable for rapid continuous triggering; furthermore, it also provides a method for fabricating a thyristor device suitable for rapid continuous triggering.

[0008] The technical problem solved by this invention can be achieved by the following technical solutions: A thyristor device suitable for rapid continuous triggering, comprising: A substrate and a through-hole region formed therein, the through-hole region having a first conductivity type, and the substrate having a second conductivity type opposite to the first conductivity type; At least one first discrete device group, each first discrete device group includes a plurality of first discrete devices arranged at a first preset distance, each first discrete device includes a first doped region having a first conductivity type and a second lightly doped region and a third heavily doped region having a second conductivity type, the first doped region being formed in the substrate from a first surface of the substrate, the second lightly doped region being formed in the first doped region, and the third heavily doped region being formed in the second lightly doped region; At least one second discrete device group, each second discrete device group including a plurality of first discrete devices arranged at a second preset distance, each second discrete device including a fourth doped region and a fifth heavily doped region having a first conductivity type, the fourth doped region being formed in the substrate from a second surface of the substrate opposite to the first surface, and the fifth heavily doped region being formed in the fourth doped region.

[0009] Preferably, it also includes: A trench is formed between the first discrete device group and the through area, and a first oxide layer, a glass sintering layer and a second oxide layer are sequentially provided in the trench from bottom to top. A third oxide layer is formed on the first surface of the substrate. A first contact hole is formed in the third oxide layer. A first metal layer is provided in the first contact hole and on the surface of the third oxide layer. A silicon oxide layer is provided, which is wrapped around the first metal layer, and a second contact hole is formed in the silicon oxide layer; A front metal layer is formed inside the second contact hole and on the surface of the silicon oxide layer; A fourth oxide layer is formed on the second surface of the substrate, and a third contact hole is formed in the fourth oxide layer; A back metal layer is formed in the third contact hole.

[0010] Preferably, the thyristor device satisfies one or more of the following conditions ①-⑧: ①In the first discrete device group, the number of the first discrete devices is not less than 3; ②In the second discrete device group, the number of the second discrete devices is not less than 3; ③ The number of the second discrete components may be the same as or different from the number of the first discrete components; ④ The doping concentration of the third heavily doped region is more than 10 times that of the second lightly doped region; ⑤ The doping concentration of the fifth doped region is more than 5 times that of the fourth doped region; ⑥ The depth of the third heavily doped region is less than or greater than the depth of the second lightly doped region; ⑦ The first preset distance is less than 3μm; ⑧ The second preset distance is less than 4μm.

[0011] Preferably, the doping concentration of the fifth doped region is 15 to 20 times that of the fourth doped region.

[0012] Preferably, the first discrete device group includes one or two or more; When the first discrete device group includes two or more, adjacent first discrete device groups in the two or more first discrete device groups are spaced apart by a third preset distance, the third preset distance being greater than the first preset distance; and / or The second discrete device group includes one or two or more; When the second discrete device group includes two or more, the adjacent second discrete device groups in the two or more second discrete device groups are spaced apart by a fourth preset distance, and the fourth preset distance is greater than the second preset distance.

[0013] Preferably, the third preset distance is greater than 5 μm; and / or The fourth preset distance is greater than 5μm.

[0014] On the other hand, a method for fabricating a thyristor device suitable for rapid continuous triggering is also provided, for fabricating the thyristor device suitable for rapid continuous triggering as described above, the method comprising: A through-region formed in a substrate, the through-region having a first conductivity type, and the substrate having a second conductivity type opposite to the first conductivity type; At least one first discrete device group is formed in the substrate. Each first discrete device group includes a plurality of first discrete devices arranged at a first preset distance. Each first discrete device includes a first doped region having a first conductivity type, a second lightly doped region having a second conductivity type, and a third heavily doped region having a second conductivity type. The first doped region is formed in the substrate from a first surface of the substrate. The second lightly doped region is formed in the first doped region. The third heavily doped region is formed in the second lightly doped region. At least one second discrete device group is formed in the substrate to obtain product A. Each second discrete device group includes a plurality of first discrete devices arranged at a second preset distance. Each second discrete device includes a fourth doped region and a fifth heavily doped region having a first conductivity type. The fourth doped region is formed in the substrate from a second surface opposite to the first surface. The fifth heavily doped region is formed in the fourth doped region.

[0015] Preferably, it also includes: A trench is formed between the first discrete device group and the through area, and a first oxide layer, a glass sintering layer and a second oxide layer are formed sequentially from bottom to top in the trench; A third oxide layer is formed on the first surface of the substrate, and a first contact hole is formed in the third oxide layer; A first metal layer is formed inside the first contact hole and on the surface of the third oxide layer; A silicon oxide layer is wrapped around the first metal layer, and a second contact hole is formed in the silicon oxide layer; A front metal layer is formed inside the second contact hole and on the surface of the silicon oxide layer; A fourth oxide layer is formed on the second surface of the substrate; A third contact hole is formed in the fourth oxide layer, and a back metal layer is formed in the third contact hole. After annealing, the product is diced and packaged to obtain product C.

[0016] Preferably, after forming the fourth oxide layer on the second surface of the substrate, and before forming the second contact hole in the silicon oxide layer, the method further includes: Irradiation or heavy metal doping processes are performed to obtain product B.

[0017] Preferably, product A, product B and product C all have withstand voltage, wherein, under 1mA test conditions, the avalanche breakdown voltage of product A is not higher than the maximum forward voltage of the device, and the avalanche breakdown voltage of product C is greater than 110% of the maximum forward voltage of the device.

[0018] The advantages or beneficial effects of the technical solution of this invention are as follows: (1) By using discrete components, the switching frequency of the device can be increased and the turn-off time of the device can be shortened; (2) By adopting a combination structure of a second lightly doped region and a third heavily doped region, the doping concentration of the third heavily doped region is reduced while ensuring that the on-state voltage drop and current meet the requirements, thereby further increasing the device switching frequency and shortening the turn-off time. (3) By adopting a combination structure of the fourth doping region and the fifth doping region, the doping concentration of the fourth doping region is reduced while ensuring that the on-state voltage drop and current meet the requirements, thereby further increasing the device switching frequency and shortening the turn-off time. (4) When the current decreases, the injection dominated by the third and fifth doped regions will change to the second and fourth doped regions. At this time, the minority carrier number decreases sharply and changes nonlinearly. The sharply reduced minority carriers are insufficient to maintain the reverse bias of the PN junction formed between the first doped region and the substrate, causing the device to switch from the on state to the off state, thereby increasing the holding current (IH).

[0019] (5) When the gate voltage (VG) is low, minority carriers are injected into the second lightly doped region; when the bias voltage continues to increase and reaches the required trigger voltage, the injection of the third heavily doped region dominates, and the minority carrier injection intensity increases nonlinearly. At this time, the PN junction formed between the first doped region and the substrate is rapidly turned on, which can effectively accelerate the turn-on speed of the device. Attached Figure Description

[0020] Figure 1 This is a cross-sectional schematic diagram of a thyristor device suitable for rapid continuous triggering in a preferred embodiment 1 of the present invention; Figure 2A-2J This is a cross-sectional schematic diagram of each step in the device fabrication method in a preferred embodiment 1 of the present invention; Figure 3 This is a cross-sectional schematic diagram of a thyristor device suitable for rapid continuous triggering in a preferred embodiment 2 of the present invention; Figure 4 This is a cross-sectional schematic diagram of a thyristor device suitable for rapid continuous triggering in a preferred embodiment 3 of the present invention; Figure 5 This is a cross-sectional schematic diagram of a thyristor device suitable for rapid continuous triggering in a preferred embodiment 4 of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0023] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0024] See Figures 1 to 5 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a thyristor device suitable for rapid continuous triggering is provided, comprising: The substrate 1 and the through region 2 formed therein have a first conductivity type and the substrate 1 have a second conductivity type opposite to the first conductivity type. In this embodiment, the first conductivity type is P type and the second conductivity type is N type.

[0025] At least one first discrete device group, each first discrete device group including a plurality of first discrete devices spaced apart by a first preset distance S1, each first discrete device including: A first doped region 3 having a first conductivity type is formed in the substrate 1 from a first surface of the substrate 1; A second lightly doped region 5 having a second conductivity type is formed in the first doped region 3; and A third heavily doped region 7 having a second conductivity type is formed in the second lightly doped region 5; At least one second discrete device group, each second discrete device group including a plurality of first discrete devices spaced apart by a second preset distance S2, each second discrete device including: A fourth doped region 4 having a first conductivity type is formed in the substrate 1 from a second surface opposite to the first surface; and A fifth doped region 6 having a first conductivity type is formed in the fourth doped region 4.

[0026] Specifically, in response to the problem that traditional thyristor devices have excessively long turn-off times after triggering, and that the current at both ends of the device cannot return to zero completely when the trigger current is cut off under high-frequency triggering conditions, resulting in the device remaining on and unable to be turned off, this embodiment uses discrete devices, such as a first discrete device and a second discrete device set at intervals, to increase the device switching frequency and reduce the turn-off time.

[0027] In the first discrete device, the second lightly doped region 5 is N-type and the third heavily doped region 7 is N++ type. By adopting a structure combining the N-type second lightly doped region 5 and the N++ type third heavily doped region 7, the doping concentration of the N++ type third heavily doped region 7 is reduced while ensuring that the on-state voltage drop and current are met, thereby further increasing the device switching frequency and shortening the turn-off time.

[0028] In the second discrete device, the fourth doped region 4 is lightly doped and the fifth heavily doped region 6 is P++ type. By adopting a structure combining the lightly doped fourth doped region 4 and the P++ type fifth heavily doped region 6, the doping concentration of the fourth doped region 4 is reduced while ensuring that the on-state voltage drop and current are met, thereby further increasing the device switching frequency and shortening the turn-off time.

[0029] When the current decreases, the implantation dominated by the third doped region 7 and the fifth doped region 6 will change to be dominated by the second light doped region 5 and the fourth doped region 4. At this time, the minority carrier number decreases sharply and changes nonlinearly. The sharply reduced minority carriers are insufficient to maintain the reverse bias of the PN junction formed between the first doped region 3 and the substrate 1, causing the device to switch from the on state to the off state, thereby increasing the holding current (IH).

[0030] When the gate voltage (VG) is low, minority carriers are injected into the second lightly doped region 5. When the bias voltage continues to increase and reaches the required trigger voltage, the injection of the third heavily doped region 7 becomes dominant, and the minority carrier injection intensity increases nonlinearly. At this time, the PN junction formed between the first doped region 3 and the substrate 1 is rapidly turned on, which can effectively accelerate the turn-on speed of the device.

[0031] In a preferred embodiment, it further includes: Trench 8 is formed in substrate 1 and located between the first discrete device group and through region 2. From bottom to top, trench 8 is provided with a first oxide layer, a glass sintering layer and a second oxide layer. A third oxide layer 9 is formed on the first surface of the substrate 1. A first contact hole is formed in the third oxide layer 9. A first metal layer 10 is provided in the first contact hole and on the surface of the third oxide layer 9. The metal layer serves as the electrode G of the thyristor device. A silicon oxide layer 11 is wrapped around a first metal layer 10, and a second contact hole 121 is formed in the silicon oxide layer 11. A front metal layer 12 is formed in the second contact hole 121 and on the surface of the silicon oxide layer 11. The front metal layer 12 serves as the electrode T2 of the silicon controlled rectifier device. A fourth oxide layer 13 is formed on the second surface of the substrate 1, and a third contact hole is formed in the fourth oxide layer 13; A back metal layer 14 is formed in the third contact hole, and the back metal layer 14 serves as the electrode T1 of the thyristor device.

[0032] Furthermore, to address the issue of low breakdown voltage in thin chips, in this embodiment, the chip thickness of the thyristor device is between 100-250 μm.

[0033] The finished thyristor device has a breakdown voltage higher than 800V under 1MA test conditions, a chip area of ​​less than 100 square millimeters, and an operating frequency greater than 1MHz.

[0034] In a preferred embodiment, the number of first discrete devices in the first discrete device group is not less than 3; the number of second discrete devices in the second discrete device group is not less than 3; the number of second discrete devices may be the same as or different from the number of first discrete devices.

[0035] Specifically, if only one or two discrete devices are used, pinch-off cannot be achieved. In order to achieve the pinch-off effect of the silicon controlled rectifier (SCR) device, in this embodiment, the number of the first discrete device is set to at least three, and the number of the second discrete device is also set to at least three.

[0036] In practical applications, the number of the first discrete components and the number of the second discrete components can be the same, for example, three or more can be set simultaneously. Alternatively, they can be different, depending on the actual needs. For example, the number of the first discrete components can be set to four, and the number of the second discrete components can be set to three.

[0037] In a preferred embodiment, the doping concentration of the third heavily doped region 7 is more than 10 times that of the second lightly doped region 5; and the doping concentration of the fifth heavily doped region 6 is more than 5 times that of the fourth doped region 4.

[0038] Specifically, in this embodiment, the doping concentration of the N++ type third doped region 7 is more than 10 times that of the N- type second light doped region 5, and the doping concentration of the P++ type fifth doped region 6 is more than 5 times that of the fourth doped region 4, so as to form a better concentration gradient and meet the requirements of improving IH and accelerating the turn-on speed.

[0039] More preferably, the doping concentration of the P++ type fifth doped region 6 is 15 to 20 times that of the fourth doped region 4.

[0040] In a preferred embodiment, the depth of the third heavily doped region 7 is less than or greater than the depth of the second lightly doped region 5.

[0041] Specifically, the depth of the third heavily doped region 7 can be less than the depth of the second lightly doped region 5. For example, the volume of the third heavily doped region 7 is 1 / 4 of the volume of the second lightly doped region 5. The depth of the third heavily doped region 7 is half the depth of the second lightly doped region 5, that is, the distance between the lower surface of the third heavily doped region 7 and the lower surface of the second lightly doped region 5 is 1 / 2 the depth of the second lightly doped region 5. The width of the third heavily doped region 7 is half the width of the second lightly doped region 5, that is, the distance between the left surface of the third heavily doped region 7 and the left surface of the second lightly doped region 5 is 1 / 4 the width of the second lightly doped region 5, and the distance between the right surface of the third heavily doped region 7 and the right surface of the second lightly doped region 5 is 1 / 4 the width of the second lightly doped region 5.

[0042] Furthermore, in order to achieve a better on-state peak voltage (VTM) and a larger current flow in the same area, the depth of the third heavily doped region 7 can also be greater than the depth of the second lightly doped region 5.

[0043] In a preferred embodiment, the first preset distance S1 is less than 3 μm; the second preset distance S2 is less than 4 μm.

[0044] Specifically, considering that the spacing between two adjacent first discrete devices is short-circuited by the electrode T2 of the thyristor device, if the first preset distance S1 is too large, when a reverse bias voltage is applied, the structure formed by the spacing between the two adjacent first discrete devices is equivalent to a parallel resistor of a PN junction, which makes it impossible to form a reverse bias voltage.

[0045] In this embodiment, the first preset distance S1 is small, specifically below 3μm. The ion diffusion of the junction of the first discrete device can clamp the gap between the first discrete devices. When a reverse bias voltage is applied, the electric field of the first discrete device will further expand, completely clamping the gap between the first discrete devices, thereby enabling the device to meet the reverse withstand voltage requirement. This is similar to the principle of the Inverse Injection Dependency of Emitter Efficiency (IDEE) structure diode.

[0046] Similarly, the spacing between two adjacent second discrete devices is short-circuited by the electrode T1 of the thyristor device. If the second preset distance S2 is too large, it will also be impossible to form a reverse bias voltage. Therefore, in this embodiment, the second preset distance S2 is set below 4μm, so that when a reverse bias voltage is applied, the spacing between the second discrete devices is completely clamped off, thereby enabling the device to meet the reverse withstand voltage requirement.

[0047] In a preferred embodiment, the first discrete device group includes one or two or more. When the first discrete device group includes two or more, the adjacent first discrete device groups in the two or more first discrete device groups are spaced apart by a third preset distance S3, and the third preset distance S3 is greater than the first preset distance S1; and / or The second discrete device group includes one or two or more; When the second discrete device group includes two or more, the adjacent second discrete device groups in the two or more second discrete device groups are spaced apart by a fourth preset distance S4, and the fourth preset distance S4 is greater than the second preset distance S2.

[0048] In a preferred embodiment, the third preset distance S3 is greater than 5 μm; and / or the fourth preset distance S4 is greater than 5 μm.

[0049] Specifically, the substrate surfaces at the locations of the third preset distance S3 and the fourth preset distance S4 are in contact with the fourth oxide layer 13 (passivation layer) but not with the metal layer, thereby increasing the substrate volume. With a constant resistivity, a larger substrate volume results in a smaller on-resistance and a more favorable on-state peak voltage (VTM) parameter.

[0050] To avoid pinch-off, the spacing between two adjacent first discrete device groups and the spacing between two adjacent second discrete device groups are both greater than 5 μm. Moreover, if the spacing is less than 5 μm, the effect of increasing the area to reduce the on-resistance is not significant.

[0051] On the other hand, a method for fabricating a thyristor device suitable for rapid continuous triggering is also provided, for fabricating the thyristor device suitable for rapid continuous triggering as described above, the method comprising: A through-region 2 is formed in the substrate 1, the through-region 2 having a first conductivity type, and the substrate 1 having a second conductivity type opposite to the first conductivity type; At least one first discrete device group is formed in the substrate 1. Each first discrete device group includes a plurality of first discrete devices arranged at a first preset distance S1. Each first discrete device includes a first doped region 3 having a first conductivity type, a second lightly doped region 5 having a second conductivity type, and a third heavily doped region 7 having a second conductivity type. The first doped region 3 is formed in the substrate 1 from the first surface of the substrate 1, the second lightly doped region 5 is formed in the first doped region 3, and the third heavily doped region 7 is formed in the second lightly doped region 5. At least one second discrete device group is formed in substrate 1 to obtain product A. Each second discrete device group includes a plurality of first discrete devices arranged at a second preset distance. Each second discrete device includes a fourth doped region 4 and a fifth heavily doped region 6 having a first conductivity type. The fourth doped region 4 is formed in substrate 1 from the second surface of substrate 1 opposite to the first surface, and the fifth heavily doped region 6 is formed in the fourth doped region 4.

[0052] In a preferred embodiment, it further includes: A trench 8 is formed between the first discrete device group and the through area 2, and a first oxide layer, a glass sintering layer and a second oxide layer are formed sequentially from bottom to top in the trench 8; A third oxide layer 9 is formed on the first surface of the substrate 1, and a first contact hole is formed in the third oxide layer 9; A first metal layer 10 is formed inside the first contact hole and on the surface of the third oxide layer 9; A silicon oxide layer 11 is wrapped around the first metal layer 10, and a second contact hole 121 is formed in the silicon oxide layer 11; A front metal layer 12 is formed inside the second contact hole 121 and on the surface of the silicon oxide layer 11; A fourth oxide layer 13 is formed on the second surface of substrate 1; Irradiation process is performed to obtain product B; the dose used in the irradiation process is between 0.05 KGy and 200 KGy; A third contact hole is formed in the fourth oxide layer 13, and a back metal layer 14 is formed in the third contact hole. After annealing, the product is diced and packaged to obtain product C.

[0053] The annealing temperature is between 200℃ and 800℃.

[0054] This embodiment introduces a process route that combines short base region, electron irradiation, and annealing, which can reduce minority carrier lifetime, increase device switching frequency, and shorten turn-off time. Moreover, for thin chips, this process route can effectively improve their breakdown voltage.

[0055] Furthermore, in addition to irradiation, heavy metal doping and nuclear irradiation can also be used as alternatives. These methods can also introduce deep-level recombination centers, thereby reducing minority carrier lifetime.

[0056] In a preferred embodiment, products A, B, and C all have withstand voltage. Under 1mA test conditions, the avalanche breakdown voltage of product A is not higher than the maximum forward voltage of the device, and the avalanche breakdown voltage of product C is greater than 110% of the maximum forward voltage of the device.

[0057] Specifically, after the doping process, product A is obtained; after irradiation treatment, product B is obtained; and after annealing, product C is obtained. Products A, B, and C all possess certain withstand voltage characteristics. The maximum forward voltage of the device is VRM. The actual avalanche breakdown voltage of product A under 1mA test conditions is no higher than VRM, while the actual avalanche breakdown withstand voltage of product C under 1mA test conditions is greater than 110%VRM.

[0058] The thyristor device of this invention has a turn-off time of less than 0.01 μs at a junction temperature of 100°C; a withstand voltage higher than 800 V under 1 mA test conditions; a leakage current of less than 1 μA at breakdown voltage; and an operating frequency greater than 1 MHz. Through optimization of the device's turn-off time, it is suitable for high-frequency switching applications at the MHz level.

[0059] In summary, the thyristor device of the present invention has the significant advantages of high switching frequency, high withstand voltage, low leakage current and high reliability, and can be widely used in many fields such as industry, automobiles, and aerospace.

[0060] The following specific embodiments are provided to further illustrate and explain this technical solution: Example

[0061] This embodiment provides a high-speed continuously triggered silicon controlled rectifier device, the fabrication method of which includes the following steps: Step 1: As Figure 2A As shown, a phosphorus-doped substrate with a thickness of 210 μm, namely N-type substrate 1, was selected. The resistivity of substrate 1 is 10 ohm-cm. N-type doped epitaxy was performed on substrate 1; subsequently, AL implantation was performed via photolithography and etching, followed by through-hole diffusion at 1200 degrees Celsius for 6 hours. The breakdown voltage between the through-hole region 2 and substrate 1 was higher than 2000V.

[0062] Step 2: As Figure 2B As shown, the first doped region 3 is formed by implantation doping, and the spacing between the first doped regions 3 is 0.8 μm; Similarly, the fourth doped region 4 is formed by implantation doping, and the spacing between the fourth doped regions 4 is 0.5 μm; After injection, rapid thermal annealing (RTA) is performed, with the maximum annealing temperature set at 110 degrees Celsius.

[0063] Step 3: As Figure 2C and Figure 2D As shown, the second lightly doped region 5 and the fifth heavily doped region 6 are implanted respectively, followed by annealing. The annealing temperature was 100℃ and the annealing time was 15 minutes.

[0064] After annealing, the doping concentration of the fifth heavily doped region 6 is 15-20 times that of the second lightly doped region 5.

[0065] Step 4: As Figure 2E As shown, the third doped region 7 is formed by using the front diffusion method.

[0066] The doping concentration of the third heavily doped region 7 is 10 times that of the second lightly doped region 5, and the volume of the third heavily doped region 7 is approximately 1 / 4 of the volume of the second lightly doped region 5. Spatially, the distance between the lower surface of the third heavily doped region 7 and the lower surface of the second lightly doped region 5 is half the depth of the second lightly doped region 5; the distance between the left surface of the third heavily doped region 7 and the left surface of the second lightly doped region 5 is 1 / 4 of the width of the second lightly doped region 5; and the distance between the right surface of the third heavily doped region 7 and the right surface of the second lightly doped region 5 is 1 / 4 of the width of the second lightly doped region 5.

[0067] Step 5: As Figure 2F As shown, a deep trench 8 is formed using a wet etching process. Then, an LTO oxide layer is grown inside the trench 8. The location where glass needs to be deposited is opened by photolithography etching. Then, glass powder is deposited by electrophoresis and sintered. After sintering, an LTO oxide layer is grown again. Finally, the residual oxide layer on the chip surface is removed by photolithography etching.

[0068] Step 6: As Figure 2G As shown, a third oxide layer 9 is grown on the front side of the chip, and the thickness of the third oxide layer 9 is 1200 angstroms.

[0069] Step 7: As Figure 2H As shown, the trigger electrode contact hole is opened by photolithography etching, and then aluminum (AL) metal is grown to form the first metal layer 10; Photolithography etching is performed again to remove excess aluminum metal, followed by the growth of a 1000 angstrom thick silicon oxide layer 11 to encapsulate the aluminum. In three-dimensional space, all the aluminum metal is now in a connected state.

[0070] Step 8: As Figure 2I As shown, photolithography is performed, and a combination of dry and wet etching methods is used to open the second contact hole 121, preparing for the next step of metal growth.

[0071] Step 9: As Figure 2J As shown, AL metal is grown on the front side of the chip to form a front metal layer 12, followed by two photolithography etching processes to expose the electrodes T2 and G of the thyristor device.

[0072] On the back of the chip, the original oxide layer is etched away using HF. At this point, the device has a breakdown voltage of 600V under a 1mA test condition.

[0073] Next, a fourth oxide layer 13 with a thickness of 3000 angstroms was grown on the back side, followed by irradiation treatment with an irradiation dose set to 2 kGy. After irradiation, the actual avalanche breakdown voltage of the device reached 1100V.

[0074] Step 10: Perform photolithography etching on the back side of the chip to open the back contact metal vias. Deposit TINIAG metal using CVD to form the back metal layer 14, followed by annealing. After annealing, perform dicing and packaging.

[0075] The annealing temperature was 450℃, the annealing time was 30 minutes, and the annealing atmosphere was N2 / H2.

[0076] Step 11: Test the device. The chip has a surface area of ​​3.0mm x 3.0mm, uses a TO220 package, and has an IT (RMS) parameter of 20A. The device can operate at a maximum voltage of 800V, with a typical avalanche breakdown voltage greater than 950V. The leakage current at 800V is less than 0.1μA, the actual trigger current is between 10-15mA, and the turn-off time is 0.0005μS. It is suitable for 2MHz frequency switching. Example

[0077] See Figure 3 This embodiment provides a thyristor device suitable for rapid continuous triggering. The difference from Embodiment 1 is that the third doped region 7 adopts a high-energy implantation process, so that the depth of the third doped region 7 is greater than the depth of the second lightly doped region 5.

[0078] To achieve a higher current throughput within the same layout, the third doped region 7 in this embodiment has a higher doping concentration compared to Embodiment 1. During the device turn-on phase, a large number of minority carriers are injected. The greater the number of minority carriers, the smaller the resulting conductance modulation resistance, thus leading to a more favorable on-state peak voltage (VTM) parameter. Due to the greater minority carrier injection, the turn-off time is slightly longer than in Embodiment 1. Example

[0079] See Figure 4 This embodiment provides a thyristor device suitable for rapid continuous triggering. The difference from Embodiment 1 is that: there is a third preset distance S3 between two adjacent first discrete device groups, which is greater than the first preset distance S1; and there is a fourth preset distance S4 between two adjacent second discrete device groups, which is greater than the second preset distance S2.

[0080] In this embodiment, the number of both the first and second discrete device groups is set to two, and each group comprises three discrete devices. However, this is not a limitation; in fact, the number of the first and second discrete device groups can be three or more. The number of first discrete devices in the two first discrete device groups can be the same or different. For example, the first first discrete device group G1 may contain three first discrete devices, and the second first discrete device group G1' may contain four. Similarly, the number of second discrete devices in the two second discrete device groups can be the same or different.

[0081] In this embodiment, the distance between the first first discrete device group G1 and the second first discrete device group G1' is 10 μm, and the distance between the first second discrete device group G2 and the second first discrete device group G2' is 10 μm.

[0082] Compared with Example 1, since the minority carrier injection adjustment in this example is the same as in Example 1, it is possible to increase the substrate volume and reduce the on-resistance while keeping the turn-off time almost unchanged, thereby achieving higher flux and lower on-state peak voltage (VTM). Example

[0083] See Figure 5 This embodiment provides a thyristor device suitable for rapid continuous triggering. The difference from Embodiment 1 is that the number of the first discrete device and the number of the second discrete device are different. The structures of the first and second discrete devices are the same as in Embodiment 1, and will not be described again here.

[0084] The first discrete component consists of four components: D11, D12, D13, and D14; the second discrete component consists of five components: D21, D22, D23, D24, and D25.

[0085] Of course, this is not the only limitation. In practical applications, the number of the first discrete components can be greater than, equal to or less than the number of the second discrete components.

[0086] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A thyristor device suitable for rapid continuous triggering, characterized in that, include: A substrate and a through-hole region formed therein, the through-hole region having a first conductivity type, and the substrate having a second conductivity type opposite to the first conductivity type; At least one first discrete device group, each first discrete device group includes a plurality of first discrete devices arranged at a first preset distance, each first discrete device includes a first doped region having a first conductivity type and a second lightly doped region and a third heavily doped region having a second conductivity type, the first doped region being formed in the substrate from a first surface of the substrate, the second lightly doped region being formed in the first doped region, and the third heavily doped region being formed in the second lightly doped region; At least one second discrete device group, each second discrete device group including a plurality of first discrete devices arranged at a second preset distance, each second discrete device including a fourth doped region and a fifth heavily doped region having a first conductivity type, the fourth doped region being formed in the substrate from a second surface of the substrate opposite to the first surface, and the fifth heavily doped region being formed in the fourth doped region.

2. The thyristor device suitable for rapid continuous triggering according to claim 1, characterized in that, Also includes: A trench is formed between the first discrete device group and the through area, and a first oxide layer, a glass sintering layer and a second oxide layer are sequentially provided in the trench from bottom to top. A third oxide layer is formed on the first surface of the substrate. A first contact hole is formed in the third oxide layer. A first metal layer is provided in the first contact hole and on the surface of the third oxide layer. A silicon oxide layer is provided, which is wrapped around the first metal layer, and a second contact hole is formed in the silicon oxide layer; A front metal layer is formed inside the second contact hole and on the surface of the silicon oxide layer; A fourth oxide layer is formed on the second surface of the substrate, and a third contact hole is formed in the fourth oxide layer; A back metal layer is formed in the third contact hole.

3. The thyristor device suitable for rapid continuous triggering according to claim 1, characterized in that, The thyristor device satisfies one or more of the following conditions ①-⑧: ①In the first discrete device group, the number of the first discrete devices is not less than 3; ②In the second discrete device group, the number of the second discrete devices is not less than 3; ③ The number of the second discrete components may be the same as or different from the number of the first discrete components; ④ The doping concentration of the third heavily doped region is more than 10 times that of the second lightly doped region; ⑤ The doping concentration of the fifth doped region is more than 5 times that of the fourth doped region; ⑥ The depth of the third heavily doped region is less than or greater than the depth of the second lightly doped region; ⑦ The first preset distance is less than 3μm; ⑧ The second preset distance is less than 4μm.

4. The thyristor device suitable for rapid continuous triggering according to claim 1, characterized in that, The doping concentration of the fifth doped region is 15 to 20 times that of the fourth doped region.

5. The thyristor device suitable for rapid continuous triggering according to claim 1, characterized in that, The first discrete device group includes one or two or more; When the first discrete device group includes two or more, adjacent first discrete device groups in the two or more first discrete device groups are spaced apart by a third preset distance, the third preset distance being greater than the first preset distance; and / or The second discrete device group includes one or two or more; When the second discrete device group includes two or more, the adjacent second discrete device groups in the two or more second discrete device groups are spaced apart by a fourth preset distance, and the fourth preset distance is greater than the second preset distance.

6. The thyristor device suitable for rapid continuous triggering according to claim 5, characterized in that, The third preset distance is greater than 5 μm; and / or The fourth preset distance is greater than 5μm.

7. A method for fabricating a thyristor device suitable for rapid continuous triggering, characterized in that, The method for fabricating a thyristor device suitable for rapid continuous triggering as described in any one of claims 1-6 includes: A through-region formed in a substrate, the through-region having a first conductivity type, and the substrate having a second conductivity type opposite to the first conductivity type; At least one first discrete device group is formed in the substrate. Each first discrete device group includes a plurality of first discrete devices arranged at a first preset distance. Each first discrete device includes a first doped region having a first conductivity type, a second lightly doped region having a second conductivity type, and a third heavily doped region having a second conductivity type. The first doped region is formed in the substrate from a first surface of the substrate. The second lightly doped region is formed in the first doped region. The third heavily doped region is formed in the second lightly doped region. At least one second discrete device group is formed in the substrate to obtain product A. Each second discrete device group includes a plurality of first discrete devices arranged at a second preset distance. Each second discrete device includes a fourth doped region and a fifth heavily doped region having a first conductivity type. The fourth doped region is formed in the substrate from a second surface opposite to the first surface. The fifth heavily doped region is formed in the fourth doped region.

8. The method for fabricating a thyristor device suitable for rapid continuous triggering according to claim 7, characterized in that, Also includes: A trench is formed between the first discrete device group and the through area, and a first oxide layer, a glass sintering layer and a second oxide layer are formed sequentially from bottom to top in the trench; A third oxide layer is formed on the first surface of the substrate, and a first contact hole is formed in the third oxide layer; A first metal layer is formed inside the first contact hole and on the surface of the third oxide layer; A silicon oxide layer is wrapped around the first metal layer, and a second contact hole is formed in the silicon oxide layer; A front metal layer is formed inside the second contact hole and on the surface of the silicon oxide layer; A fourth oxide layer is formed on the second surface of the substrate; A third contact hole is formed in the fourth oxide layer, and a back metal layer is formed in the third contact hole. After annealing, the product is diced and packaged to obtain product C.

9. The method for fabricating a thyristor device suitable for rapid continuous triggering according to claim 8, characterized in that, After forming the fourth oxide layer on the second surface of the substrate, and before forming the second contact hole in the silicon oxide layer, the method further includes: Irradiation or heavy metal doping processes are performed to obtain product B.

10. The method for fabricating a thyristor device suitable for rapid continuous triggering according to claim 9, characterized in that, Product A, Product B, and Product C all have withstand voltage. Under 1mA test conditions, the avalanche breakdown voltage of Product A is not higher than the maximum forward voltage of the device, and the avalanche breakdown voltage of Product C is greater than 110% of the maximum forward voltage of the device.

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