Forming method of inner side wall
By partially removing the sacrificial sidewalls in the fabrication of GAA devices and forming the inner sidewalls using atomic layer deposition, the problem of source-drain epitaxial crystal orientation fusion in traditional methods is solved, enabling the fabrication of high-performance GAA devices and improving carrier mobility and process compatibility.
Patent Information
- Application Number
- CN202510747532.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-05
- Publication Date
- 2025-10-28
AI Technical Summary
Traditional methods of forming inner walls in GAA device manufacturing lead to source-drain epitaxial crystal orientation fusion, resulting in epitaxial defects, reduced carrier mobility, and poor process compatibility.
By partially removing the sacrificial sidewalls, the inner sidewalls are formed through atomic layer deposition. The location of the inner sidewalls is selectively etched and filled with silicon nitride or low-k dielectric materials. The interface morphology between the inner sidewalls and the channel layer is optimized to avoid the formation of inner sidewalls after source-drain epitaxy.
It reduces epitaxial defects in the source and drain regions, improves carrier mobility, reduces parasitic capacitance, enhances device performance and process compatibility, enables all-around gate control, and strengthens the gate's control over the channel.
Smart Images
Figure CN120857541A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronic inner wall technology, and more particularly to a method for forming an inner wall. Background Technology
[0002] As semiconductor devices evolve toward smaller feature sizes of 3nm and below, gate all-around (GAA) nanosheet transistors are gradually becoming the mainstream structure to replace traditional FinFETs due to their superior gate control capabilities and lower short-channel effects.
[0003] In GAA device manufacturing, the inner spacer is a key structure that isolates the source / drain region from the gate. Its morphology control, material selection, and process compatibility directly affect the parasitic capacitance, drive current, and reliability of the device, making it one of the core process challenges in advanced manufacturing processes.
[0004] Traditional methods for forming inner walls typically employ a process of etching the source / drain region followed by epitaxy. This involves first etching the layered structure of the source / drain region to form a groove, and then epitaxy to fill it with inner wall material. However, this process presents a significant challenge in the subsequent epitaxy formation of the source / drain region:
[0005] The presence of inner sidewalls during epitaxy causes the fusion of source and drain epitaxial crystal orientations, forming epitaxial defects and greatly reducing the carrier mobility of the device.
[0006] To ensure high-quality channel release, a low thermal budget process is required for source and drain epitaxy to reduce germanium diffusion in the sacrificial layer.
[0007] To address the aforementioned issues, there is an urgent need to propose new integration process solutions that can form inner sidewalls without etching the source / drain structure, or form the inner sidewalls after epitaxy of the source / drain to avoid crystal orientation fusion caused by epitaxial orientation interruption due to the presence of inner sidewalls. This provides key process support for the fabrication of high-performance GAA devices. Summary of the Invention
[0008] To address this, the present invention provides a method for forming inner sidewalls. By removing sacrificial sidewalls to form grooved channels with removed inner sidewalls, uniform filling with silicon nitride or low-k dielectric materials adapted for atomic layer deposition (ALD) is achieved. The interface morphology between the inner sidewalls and the channel layer is optimized, avoiding the epitaxial crystal orientation fusion (numerous epitaxial defects) in the source / drain region caused by first removing the source / drain region to form inner sidewalls and then epitaxially extending the source / drain in the traditional process. This provides key process support for the fabrication of high-performance GAA devices.
[0009] To achieve the above objectives, the present invention proposes a method for forming an inner wall, comprising the following steps:
[0010] A stacked structure comprising alternating sacrificial layers and channel layers is formed on the substrate;
[0011] Within the stacked structure, a fin-type active region and a shallow trench isolation structure are formed;
[0012] Within the fin-type active region, a dummy gate structure is formed, sacrificial sidewalls are formed on both sides of the dummy gate structure, and source-drain regions are formed in the regions within the fin-type active region that are not covered by the dummy gate structure and the sacrificial sidewalls;
[0013] Part of the sacrificial sidewalls are removed to form a channel region for positioning the inner sidewalls;
[0014] Within the channel region, a part of the sacrificial layer and the sidewalls of the channel layer in the stacked structure are etched to form grooves;
[0015] After depositing inner sidewall material in the grooves, inner sidewalls are formed.
[0016] Furthermore, the material of the sacrificial layer is silicon germanium (Si 1-x Ge x ), the material of the channel layer is silicon (Si), where x is the molar fraction of germanium in the silicon germanium material, and a component molar fraction range of 0.1 < x < 0.5 is adopted;
[0017] The thicknesses of both the sacrificial layer and the channel layer formed on the substrate are between 5 nm and 20 nm.
[0018] In the above solution, when the thickness of the Si 1-x Ge x layer is within the range of 5 nm to 20 nm, high selectivity can be obtained by using either wet or dry etching processes.
[0019] Furthermore, the process of etching part of the sacrificial layer includes: having an etching selectivity ratio greater than 1 for the sacrificial layer and the channel layer to reduce damage to the channel layer during etching.
[0020] In the above solution, high-selectivity etching can make the lateral etching amount of the sacrificial layer closer to the design value, forming a more regular morphology of the inner sidewall cavity, rather than the semi-circular cavity caused by low selectivity in traditional processes. The more regular morphology enables the filled inner sidewall material to more effectively isolate the source-drain and the gate, reducing the parasitic capacitance (Cgd).
[0021] Furthermore, the inner sidewall material is silicon nitride or a low-k dielectric material.
[0022] Furthermore, the low-k dielectric material includes one or more of silicon oxyfluoride, silicon oxycarbide, or amorphous carbon fluoride.
[0023] In the above scheme, silicon oxyfluoride in the low-K dielectric material can significantly reduce the parasitic capacitance (Cgd) between the source / drain and the gate by reducing the dielectric constant, thereby reducing RC delay and improving the chip signal transmission speed.
[0024] Furthermore, the dielectric constant of the material is controlled by precursor selection and in-situ doping in the atomic layer deposition process to deposit the inner sidewall material in the groove.
[0025] Furthermore, the inner wall material is obtained by selecting a precursor in the atomic layer deposition process.
[0026] Furthermore, after forming the inner wall, the following steps are also included:
[0027] Remove the pseudo-gate structure;
[0028] Remove the sacrificial layer in the stacked structure to release the channel layer and form a nanosheet channel;
[0029] A gate structure is formed around the nanosheet channel.
[0030] In the above scheme, the removal of the sacrificial layer releases the channel layer that was originally isolated by the sacrificial layer from the stacked structure, forming an independent nanosheet channel. This allows each nanosheet of the GAA device to be completely wrapped by the gate, achieving full-around gate control. The gate's control capability over the channel is significantly enhanced, effectively suppressing the short-channel effect and improving the device's switching ratio and current regulation accuracy.
[0031] Furthermore, after the inner wall is formed, the side of the inner wall contacts the side of the channel layer, and the shape of the inner wall is approximately rectangular.
[0032] Furthermore, the process of forming a pseudo-gate structure within the finned active region includes:
[0033] A sacrificial gate dielectric layer and an amorphous silicon layer are deposited on the stacked structure of the substrate located in the first region and the stacked structure located in the second region, respectively;
[0034] A mask layer is formed on the amorphous silicon layer, and a pseudo-gate structure pattern is formed on the mask layer by photolithography.
[0035] Using photoresist as a mask, the mask layer, amorphous silicon layer, and sacrificial gate dielectric layer are etched sequentially to form the pseudo-gate structure spanning the stacked structure. The pseudo-gate structure is used to provide self-aligned positioning for the inner sidewall.
[0036] In the above scheme, the formation process of the dummy gate structure provides precise self-aligned positioning for subsequent processes such as inner sidewalls and source / drain doped layers. As a temporary structure, the dummy gate protects the positional accuracy of the gate region, ensures that the morphology of the inner sidewalls is controllable (e.g., approximately rectangular) during the etching of the sacrificial layer, and maintains good contact with the channel layer.
[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0038] 1. By partially removing the sacrificial sidewall, the position of the inner sidewall is accurately located, providing key process support for the manufacturing of high-performance GAA devices.
[0039] 2. The inner sidewalls can be formed without etching the source and drain structure, or the inner sidewalls can be formed after the source and drain are epitaxially extended to avoid the crystal orientation fusion caused by the interruption of the epitaxial crystal orientation due to the presence of the inner sidewalls. This reduces the epitaxial defects in the source and drain region and avoids the reduction of carrier mobility. Attached Figure Description
[0040] Figure 1 The method for forming inner sidewalls according to an embodiment of the present invention involves forming Si on a substrate. 1-x A cross-sectional schematic diagram of the Gex / Si stacked epitaxial structure;
[0041] Figure 2 For the embodiments of the present invention in Figure 1 A cross-sectional schematic diagram showing the formation of the Fin structure active region and the STI structure based on the structural basis;
[0042] Figure 3A This is a three-dimensional schematic diagram of the formation of the pseudo-gate structure and sacrificial sidewalls according to an embodiment of the present invention; Figure 3B As an embodiment of the present invention Figure 3A The diagram shows a cross-sectional view taken along the cutting line direction, after the formation of the pseudo-gate structure, the sacrificial sidewalls, and the completion of source / drain heavy doping.
[0043] Figure 4 For the embodiments of the present invention in Figure 3B A schematic cross-section of the structure after depositing interlayer media and performing CMP to expose the sacrificial sidewall structure;
[0044] Figure 5A In this embodiment of the invention, the sacrificial sidewall layer is selectively etched, and the Si surrounding the sacrificial sidewall layer is selectively etched. 1-x Si in Gex / Si stack 1-x A three-dimensional schematic diagram of the Gex section after the groove is formed; Figure 5B As an embodiment of the present invention Figure 5A The selective etching of the sacrificial sidewalls and part of the sacrificial layer (Si) is shown as viewed along the cutting line direction. 1-x A cross-sectional view of the groove formed in Gex;
[0045] Figure 6 For the embodiments of the present invention Figure 3B A schematic cross-section of the structure after depositing interlayer media and performing CMP to expose the sacrificial sidewall structure;
[0046] Figure 7A For the embodiments of the present invention Figure 6 Based on the structure, a three-dimensional schematic diagram after pseudo-gate removal, channel release, HKMG filling and CMP are performed; Figure 7B For the embodiments of the present invention Figure 7A Based on the structure, a three-dimensional schematic diagram of the interconnected contacts is further developed. Detailed Implementation
[0047] In order to make the objects and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with embodiments; it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0048] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.
[0049] It should be noted that in the description of this invention, the terms "upper", "lower", "left", "right", "inner", "outer", etc., which indicate directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. This is only for the convenience of description and is not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.
[0050] Furthermore, it should be noted that, in the description of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.
[0051] like Figure 1As shown in FIGS. 1 to 7, the present invention provides a method for forming an inner sidewall, which accurately locates the inner sidewall region by partially removing the sacrificial sidewall, controls the etching selectivity ratio to reduce the damage to the channel layer, adapts to the uniform filling of silicon nitride or low-k dielectric materials of the atomic layer deposition process ALD, and optimizes the interface morphology between the inner sidewall and the channel layer, avoiding the epitaxial crystal orientation fusion (a large number of epitaxial defects) in the source / drain region caused by first removing the source / drain region to form the inner sidewall and then epitaxially growing the source / drain in the traditional process method, providing key process support for the manufacture of high-performance GAA devices.
[0052] As Figure 1 shown in FIGS. 1 to 7, the present embodiment proposes a method for forming an inner sidewall, including the following steps:
[0053] Form a stacked structure including an alternating stack of a sacrificial layer 102 and a channel layer 101 on the substrate 100;
[0054] In the stacked structure, form a fin active region 110 and a shallow trench isolation structure 120;
[0055] In the fin active region 110, form a dummy gate structure 131, form sacrificial sidewalls 132 on both sides of the dummy gate structure 131, and form source / drain regions 111 in the region of the fin active region 110 that is not covered by the dummy gate structure 131 and the sacrificial sidewalls 132;
[0056] Remove a part of the sacrificial sidewalls 132 to form a channel region 1321 for positioning and inner sidewall etching;
[0057] In the channel region 1321 where the inner sidewall can be etched, etch a part of the sacrificial layer 102 and the sidewalls of the channel layer 101 in the stacked structure below the sacrificial sidewalls 132 to form a groove 150;
[0058] After depositing inner sidewall material 160 in the groove 150, form an inner sidewall.
[0059] Further, the material of the sacrificial layer 102 is germanium silicon (Si 1-x Ge x ), the material of the channel layer 101 is silicon (Si), where x is the component molar fraction of germanium in the germanium silicon material, and the component molar fraction range of 0.1 < x < 0.5 is adopted;
[0060] The thicknesses of the sacrificial layer 102 and the channel layer 101 formed on the substrate 100 are both between 5 nm and 20 nm.
[0061] In the above solution, when the thickness of the Si 1-x Gex layer is within the range of 5 nm to 20 nm, high selectivity can be obtained by using either wet or dry etching process.
[0062] Furthermore, the process of etching a portion of the sacrificial layer 102 includes having a high etching selectivity ratio greater than 1 for the sacrificial layer 102 and the channel layer 101 to reduce etching damage to the channel layer 101.
[0063] In the above scheme, high selectivity etching allows the lateral etching amount of the sacrificial layer to be closer to the design value, resulting in a more regular inner wall cavity morphology, rather than the semi-circular cavity caused by low selectivity in traditional processes. The more regular morphology allows the filled inner wall material to more effectively isolate the source / drain and gate, reducing parasitic capacitance (Cgd).
[0064] Furthermore, the inner wall material 160 is made of silicon nitride or a low-K dielectric material.
[0065] Furthermore, the low-K dielectric material includes one or more of silicon oxyfluoride, silicon oxycarbonide, or amorphous fluorinated carbon.
[0066] In the above scheme, silicon oxyfluoride in the low-K dielectric material can significantly reduce the parasitic capacitance (Cgd) between the source / drain and the gate by reducing the dielectric constant, thereby reducing RC delay and improving the chip signal transmission speed.
[0067] Furthermore, the low-K value dielectric material is one or more of silicon oxyfluoride, silicon oxycarbonide, or amorphous fluorinated carbon.
[0068] Furthermore, the dielectric constant of the material is controlled by precursor selection and in-situ doping in the atomic layer deposition process to deposit the inner sidewall material 160 in the groove 150.
[0069] Furthermore, the inner wall material 160 is obtained by selecting a precursor in the atomic layer deposition process.
[0070] Furthermore, after forming the inner wall, the following steps are also included:
[0071] Remove the pseudo-gate structure 131;
[0072] Remove the sacrificial layer 102 in the stacked structure to release the channel layer 101 to form a nanosheet channel 180;
[0073] A gate structure 190 is formed around the nanosheet channel 180.
[0074] In the above scheme, the removal of the sacrificial layer releases the channel layer that was originally isolated by the sacrificial layer from the stacked structure, forming an independent nanosheet channel. This allows each nanosheet of the GAA device to be completely wrapped by the gate, achieving full-around gate control. The gate's control capability over the channel is significantly enhanced, effectively suppressing the short-channel effect and improving the device's switching ratio and current regulation accuracy.
[0075] Furthermore, the side of the inner wall 160 contacts the side of the channel layer 101, and the shape of the inner wall 160 is approximately rectangular.
[0076] Furthermore, the process of forming the pseudo-gate structure 131 within the fin-type active region 110 includes:
[0077] On the stacked structure in the first region and the stacked structure in the second region of the substrate 100, a sacrificial gate dielectric layer and a sacrificial gate conductor layer are deposited, respectively.
[0078] A mask layer is formed on the sacrificial gate conductor layer, and a pseudo gate structure pattern is formed on the mask layer by photolithography.
[0079] Using photoresist as a mask, the mask layer, the sacrificial gate conductor layer, and the sacrificial gate dielectric layer are etched sequentially to form the pseudo-gate structure 131 that spans the stacked structure. The pseudo-gate structure 131 is used to provide self-alignment for the inner wall.
[0080] In the above scheme, the formation process of the dummy gate structure provides precise self-alignment for subsequent processes such as inner sidewalls and source / drain doped layers. As a temporary structure, the dummy gate protects the positional accuracy of the gate region, ensures that the morphology of the inner sidewalls during the etching of the sacrificial layer is controllable to be approximately rectangular, and maintains good contact with the channel layer.
[0081] Specifically, in this embodiment, for the Gate All Around (GAA) nanosheet (NS) device with a horizontal channel, the inner wall (InnerSpacer) is a very important process module. Its main functions are twofold: reducing the parasitic capacitance between the gate and the source / drain regions; and preventing uncontrolled extension of selective etching into the source / drain regions during channel release.
[0082] The challenges of introducing inner sidewall technology into GAA NS devices: The mainstream process for introducing inner sidewalls into devices requires first etching the source / drain regions to form inner sidewalls before performing source / drain epitaxy. This process faces the following challenges: epitaxial merging caused by inner sidewalls leads to epitaxial defects; interruptions in the superlattice structure cause changes in channel stress; high-quality channel release requires low thermal budget; and low parasitic resistance places high demands on source / drain doping concentration. The process in this embodiment solves these problems.
[0083] Specifically, see Figure 1 Prepare a substrate wafer 100, such as a silicon substrate. On the substrate 100, alternately stacked sacrificial layers 102 and channel layers 101 are formed using an epitaxial growth process. Multiple pairs of sacrificial layers and channel layers can be formed to constitute a multilayer nanosheet structure. The thickness of each layer can be selected in the range of, for example, 5 nanometers to 20 nanometers. This stacked structure will be used to subsequently form the source, drain, and nanosheet channels of the device.
[0084] See Figure 2 The stacked structure is patterned using standard photolithography and etching processes to form fin-type active regions 110 extending along a specific direction. Subsequently, dielectric material, such as silicon oxide, is filled between the fin-type active regions 110 and planarized to form shallow trench isolation (STI) structures 120 for isolating different active regions.
[0085] See Figure 3A and Figure 3B First, above the predetermined gate region of the finned active region 110, a gate dielectric layer, such as silicon oxide, a dummy gate electrode material layer, such as amorphous silicon, and a hard mask layer, such as silicon oxide, silicon nitride, or a stack thereof, are sequentially deposited to form a dummy gate stack 130. Then, the dummy gate stack 130 is patterned using photolithography and etching processes to form a dummy gate structure 131. The dummy gate structure 131 defines the location of the future real gate. Next, a sacrificial sidewall film layer, such as silicon nitride or silicon oxide, is conformally deposited on both sides of the dummy gate structure 131. Then, the sacrificial sidewall film layer on the horizontal surface is removed by anisotropic etching, such as reactive ion etching (RIE), leaving only sacrificial sidewalls 132 on the sidewalls of the dummy gate structure 131. Subsequently, ion implantation (e.g., implantation of P-type or N-type dopants) is performed on the region of the fin-type active region 110 that is not covered by the pseudo-gate structure 131 and the sacrificial sidewall 132, i.e. the expected source / drain region, and high-temperature annealing is performed to activate the dopants and repair implantation damage, forming a heavily doped source / drain region 111.
[0086] See Figure 4 An interlayer dielectric (ILD) layer 140 is deposited over the entire structure. The interlayer dielectric 140 may be made of silicon oxide, silicon nitride, or a stacked structure thereof. After deposition, the interlayer dielectric 140 is planarized using a chemical mechanical polishing (CMP) process until the top of the sacrificial sidewall 132 is exposed.
[0087] See Figure 5A and Figure 5BFirst, a highly selective wet or dry etching process is employed. The wet etching method can utilize H2O2, HNO3, CH3COOH, and HF solutions, while the dry etching method can use a CH4 / CH2F2 / / O2 / Ar mixed gas. This selectively removes the sacrificial sidewalls 132, forming channel regions 1321 for positioning and inner sidewall etching, exposing the underlying stacked structure, namely the sidewalls of the Si1-xGex / Si stack. Then, the sacrificial layer 102 (Si...) is further... 1-x Ge x The etching process (e.g., plasma etching based on HCl or HBr, or specific wet chemical etching solutions) with high selectivity, while essentially not etching the channel layer 101 (Si), selectively etches away a portion of the sacrificial layer 102 in the stacked structure below the area surrounded by the channel region 1321. The etching depth is precisely controlled, removing only the sacrificial layer 102 located at the future inner sidewall position, forming the groove 150. The remaining portion of the sacrificial layer 102 and the channel layer 101 remains unaffected. Due to the high selectivity of the etching, the sidewalls of the formed groove 150, i.e., the sides of the channel layer 101, are relatively steep, approaching a rectangle.
[0088] See Figure 6 Within the formed groove 150, an inner sidewall material 160 is deposited using conformal deposition processes such as atomic layer deposition (ALD). The inner sidewall material 160 may be silicon nitride (Si). N Alternatively, a low-k dielectric material can be used, such as silicon oxyfluoride (SiOF), silicon oxycarbide (SiOC), or amorphous fluorinated carbon (a-CF). When selecting the inner sidewall material 160, it is necessary to ensure that it has a high etching selectivity with the subsequent etching process used to release the channel, i.e., remove the remaining sacrificial layer 102 in the stacked structure, to avoid damage to the inner sidewall 160 during channel release. Subsequently, a filling dielectric 170, preferably silicon nitride, silicon oxide, or a low-k material, can be deposited to fill any voids that may exist above the recess 150 and around the dummy gate structure 131, and planarization, such as CMP, can be performed.
[0089] See Figure 7A and Figure 7B After forming the inner sidewall 160, the mainstream ring-gate nanosheet GAA NS device fabrication process is used to sequentially complete the subsequent steps, including: removing the dummy gate structure 131, including the hard mask layer and the dummy gate electrode material layer thereon; channel release; and selective etching to remove the remaining sacrificial layer 102 (Si) in the stacked structure. 1-x Ge xThe channel layer 101 (Si) is suspended, forming a nanosheet channel 180. During this process, the inner sidewall 160 protects the edges of the leakage region. A high-k gate dielectric and a high-k metal gate electrode (HKMG) material are deposited, filling the gate trench formed by removing the dummy gate structure 131 and the sacrificial layer 102, and CMP planarization is performed to form the final all-around gate structure 190. An interlayer insulating layer is formed, contact holes are etched, and metal is filled to form the contacts 200 of the source, drain, and gate, completing the device interconnection.
[0090] By following the above steps, a ring-gate nanosheet transistor with the inner sidewall structure described in this invention can be manufactured. This method avoids the complex process of source epitaxy after the formation of the inner sidewall and the various problems it brings, while also enabling the formation of high-quality inner sidewalls.
[0091] The above steps have the following beneficial effects:
[0092] Avoiding the challenges of source / drain epitaxy: By directly forming the source / drain and inner sidewalls within the original stacked structure, the step of etching the source / drain before epitaxy, which is common in mainstream processes, is avoided. This fundamentally circumvents potential problems during source / drain epitaxy such as lattice mismatch, epitaxial defects (e.g., stacking faults), channel stress changes, and high thermal budget. The source / drain region remains a stacked epitaxial structure.
[0093] High-quality inner sidewall formation: Selective etching is used to remove the sacrificial layer (such as a germanium-silicon layer) at the inner sidewall location. Due to the high selectivity of the etching, well-shaped (e.g., near-rectangular) inner sidewall grooves can be formed, which is beneficial for the uniform filling of subsequent inner sidewall materials and the formation of high-quality inner sidewalls. This provides better compatibility for integration in subsequent processes and helps to achieve excellent device performance.
[0094] Improved device performance: The regular inner wall structure facilitates precise control of the channel release process, avoiding channel release defects that may be caused by poor inner wall morphology. Simultaneously, by avoiding complex source-drain epitaxial processes, the parasitic parameters and stress states of the device are easier to control, contributing to improved overall device performance and reliability.
[0095] Good process compatibility: The formed inner wall material (such as silicon nitride or low-K material) has good selectivity with the gate oxide layer and subsequent trench release process, ensuring that the inner wall structure is not damaged during trench release.
[0096] In this embodiment, by partially removing the sacrificial sidewall to accurately locate the contact hole area, controlling the etching selectivity to reduce channel layer damage, adapting to the uniform filling of silicon nitride or low-k dielectric materials in atomic layer deposition (ALD) process, and optimizing the interface morphology between the inner sidewall and the channel layer, the problem of contact hole positioning deviation, channel damage, and high parasitic capacitance in traditional processes is effectively solved, providing key process support for the manufacturing of high-performance GAA devices.
[0097] Thus far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present invention.
[0098] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.
Claims
1. A method for forming an inner wall, characterized in that, Includes the following steps: A stacked structure comprising an alternating sacrificial layer (102) and a channel layer (101) is formed on the substrate (100); Within the stacked structure, a fin-type active region (110) and a shallow trench isolation structure (120) are formed; Within the fin-type active region (110), a pseudo-gate structure (131) is formed, and sacrificial sidewalls (132) are formed on both sides of the pseudo-gate structure (131). In the area within the fin-type active region (110) not covered by the pseudo-gate structure (131) and the sacrificial sidewalls (132), a source-drain region (111) is formed. The sacrificial sidewall (132) is partially removed to form a channel area (1321) for locating the inner sidewall; Within the channel region (1321), a portion of the sacrificial layer (102) and the sidewalls of the trench layer (101) in the stacked structure are etched to form a groove (150); An inner wall is formed after depositing inner wall material (160) in the groove (150).
2. The method for forming the inner wall according to claim 1, characterized in that, The material of the sacrificial layer (102) is silicon germanium (Si 1-x Ge x ), and the material of the channel layer (101) is silicon (Si), where x is the molar fraction of germanium in the silicon germanium material, and the molar fraction range of 0.1 < x < 0.5 is adopted; The thickness of the sacrificial layer (102) and the thickness of the channel layer (101) formed on the substrate (100) are both between 5 nm and 20 nm.
3. The method for forming the inner wall according to claim 1, characterized in that, The process of etching a portion of the sacrificial layer (102) includes having an etching selectivity ratio greater than 1 for the sacrificial layer (102) and the channel layer (101) to reduce etching damage to the channel layer (101).
4. The method for forming the inner wall according to claim 1, characterized in that, The inner wall material (160) is made of silicon nitride or a low-K dielectric material.
5. The method for forming the inner wall according to claim 4, characterized in that, The low-K value dielectric material is one or more of silicon oxyfluoride, silicon carbon oxyfluoride, or amorphous fluorinated carbon.
6. The method for forming the inner wall according to claim 4, characterized in that, In the atomic layer deposition process, the dielectric constant of the material is controlled by precursor selection and in-situ doping to deposit the inner sidewall material (160) in the groove (150).
7. The method for forming the inner wall according to claim 6, characterized in that, The inner wall material (160) is obtained by selecting a precursor in the atomic layer deposition process.
8. The method for forming the inner wall according to claim 1, characterized in that, After the inner wall is formed, the following steps are also included: Remove the pseudo-gate structure (131); The sacrificial layer (102) in the stacked structure is removed to release the channel layer (101) to form a nanosheet channel (180); A gate structure (190) is formed around the nanosheet channel (180).
9. The method for forming the inner wall according to claim 1, characterized in that, After the inner wall is formed, the side of the inner wall (160) contacts the side of the channel layer (101), and the shape of the inner wall (160) is approximately rectangular.
10. The method for forming the inner wall according to any one of claims 1 to 9, characterized in that, The process of forming a pseudo-gate structure (131) within the finned active region (110) includes: On the stacked structure located in the first region and the stacked structure located in the second region of the substrate (100), a sacrificial gate dielectric layer and an amorphous silicon layer are deposited respectively; A mask layer is formed on the amorphous silicon layer, and a pseudo-gate structure pattern is formed on the mask layer by photolithography. Using photoresist as a mask, the mask layer, the amorphous silicon layer and the sacrificial gate dielectric layer are etched sequentially to form the pseudo gate structure (131) that spans the stacked structure. The pseudo gate structure (131) is used to provide self-alignment for the inner wall.