SiC Trench MOSFET device

Abstract

The invention relates to a SiC Trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which is characterized in that a scheme that a gate groove extends to a transition region in the prior art is adjusted into a structure that the gate groove and the transition groove are separated, and the gate groove and a source groove are both positioned in an active region, so that the gate groove is arranged in a protection range of the source groove. Moreover, the transition groove extends into the active area, the depth of the transition groove is not smaller than that of the source groove, and P-type injection areas are arranged on the outer sides of the side wall and the bottom of the transition groove. Therefore, the depth of the P-type injection region on the outer side of the transition groove is not smaller than that of the P-type injection region on the outer side of the source groove. Equivalently, the protection of the source groove in the active area to the gate groove extends into the transition area, so that the gate-oxide electric field intensity and the electric leakage risk in the transition area when the device withstands voltage are reduced, and the problems of edge breakdown, electric leakage increase and voltage withstanding capability reduction of the device are solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more particularly to a SiC Trench MOSFET device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are core components of modern power electronic systems, widely used in power management, motor drives, and new energy conversion. As the voltage, current, and power of power electronic devices gradually increase, the performance of traditional Si MOSFETs is limited in high-voltage, high-temperature, and high-frequency applications. SiC MOSFETs, on the other hand, exhibit significant advantages due to their superior material properties: higher voltage withstand capability, lower conduction losses, faster switching speeds, and excellent high-temperature stability, making them the preferred solution for high-voltage, high-power applications such as new energy power generation, electric vehicles, and industrial power supplies. However, due to structural limitations, the cell size of traditional silicon carbide planar gate MOSFETs cannot be further reduced, resulting in an inherent contradiction between their on-resistance (RDSON) and voltage withstand capability, making it difficult to meet the demands for high efficiency and high power density.

[0003] To overcome the performance bottlenecks of planar structures, the silicon carbide trench MOSFET (SiC Trench MOSFET) structure was developed. By etching vertical trenches on the surface of a silicon carbide wafer and filling them with gate material, current can flow vertically, shortening the conduction path, reducing the JFET effect, increasing cell density, and consequently lowering on-resistance. Simultaneously, the trench gate structure also helps reduce gate charge (Qg) and Miller capacitance (Cgd), resulting in superior switching performance and making the device more suitable for high-frequency applications.

[0004] Despite the advantages mentioned above, SiC trench MOSFETs have significant drawbacks compared to traditional planar gate structures. When the device withstands voltage, an electric field concentration effect occurs within the gate oxide layer at the bottom of the trench, making the electric field strength significantly higher than in other areas. This can lead to threshold voltage drift or gate oxide breakdown (as seen in the interface state problem of SiC MOSFETs). Therefore, trench gate structures require additional gate protection structures to reduce the electric field strength within the gate oxide layer and prevent impact on device performance.

[0005] Therefore, a double-trench MOSFET device structure emerged. For example... Figure 1 , Figure 2 and Figure 3As shown, the basic structure of a dual-trench MOSFET device includes an active region, a transition region, and a termination region. Within the active region, gate trenches 10 and source trenches 20 are arranged alternately. Gate trench 10 has a gate oxide layer 101 at its bottom and sidewalls, filled with polysilicon as the gate 102. A body region 103, a source region 104, and an N-type drift region 105 (the area within the active region that has not been etched or ion-implanted) are also provided on both sides and at the bottom of gate trench 10. Source trench 20 also has a gate oxide layer 101 at its bottom and sidewalls, filled with polysilicon (source polysilicon 201). A P-type implantation region 106 is also provided on the outer side of its bottom and sidewalls. The device periphery is the termination region, which has a semi-enclosed gate polysilicon bus 30 for electrical connection between the device and external circuitry. To achieve electrical connection between the gate 102 within gate trench 10 and the outer gate polysilicon bus 30, only gate trench 10 extends into the transition region. The gate polysilicon bus 30 covers the gate trench 10, thereby enabling connection to the polysilicon (gate 102) within the gate trench 10.

[0006] In a dual-trench MOSFET device, P-type implanted regions 106 on both sides of the gate trench 10 protect the gate trench 10 and the gate oxide layer 101. When the device is subjected to a breakdown voltage, the PN junction formed between the P-type implanted region 106 and the N-type drift region 105 is depleted, producing a so-called "shielding effect," which reduces the electric field strength at the bottom of the gate trench 10, thereby preventing the gate oxide layer 101 from being affected by a high electric field. The deeper the P-type implanted region 106, the stronger the "shielding effect," the lower the electric field strength, and the better the protection effect. However, due to the limitations of SiC material properties and ion implantation energy, the depth of the P-type implanted region 106 is usually limited (typically not exceeding 1 μm).

[0007] Within the active region, the introduction of the source trench 20 structure can increase the depth of the P-type implantation region 106, thus enhancing the protection of the gate trench 10 by the P-type implantation region. However, in the transition region, if the source trench 20 and the gate trench 10 extend into the transition region together, the polysilicon filled in the source trench 20 (source polysilicon 201) will also connect with the polysilicon in the gate trench 10 (gate 102), resulting in a short circuit. Therefore, the source trench 20 structure cannot be placed in the transition region. Simultaneously, since the polysilicon in the gate trench 10 (gate 102) needs to be connected to the gate polysilicon bus 30, the length of the gate trench 10 must be greater than the length of the source trench 20. As a result, the gate trench 10 loses the enhanced protection effect of the source trench 20 in the transition region, causing the electric field strength near the gate oxide layer 101 in the transition region to be higher than that in the active region. This easily becomes a weak area of ​​the entire device, leading to edge breakdown, increased leakage current, and reduced withstand voltage. Summary of the Invention

[0008] Therefore, it is necessary to provide a SiC Trench MOSFET device to address the above problems, such as edge breakdown, increased leakage current, and reduced withstand voltage.

[0009] Therefore, the technical solution adopted by the present invention is as follows:

[0010] A SiC Trench MOSFET device includes an active region, a transition region, and a termination region, wherein a gate polysilicon bus is disposed in the termination region, and further includes:

[0011] Gate trenches and source trenches are alternately distributed within the active region, and the gate trenches and source trenches are filled with polysilicon.

[0012] A transition trench is located within the transition region, with one end extending to the active region and the other end extending to the terminal region. The depth of the transition trench is not less than the depth of the source trench. A P-type injection region is provided on the sidewall and bottom outer side of the transition trench. The transition trench is filled with a gate polysilicon protection strip, and both ends of the gate polysilicon protection strip are electrically connected to the gate polysilicon bus and the polysilicon filled in the gate trench, respectively.

[0013] The SiC Trench MOSFET device disclosed in this invention modifies the existing scheme of extending the gate trench into the transition region to a structure where the gate trench and the transition trench are separate, and both the gate trench and the source trench are located within the active region, thus placing the gate trench within the protection range of the source trench. Furthermore, the transition trench extends into the active region, and the depth of the transition trench is not less than the depth of the source trench. P-type injection regions are provided on the sidewalls and bottom outer sides of the transition trench. Thus, the depth of the P-type injection region outside the transition trench is not less than the depth of the P-type injection region outside the source trench. This effectively extends the protection of the gate trench by the source trench within the active region into the transition region, reducing the gate oxide electric field strength and leakage risk in the transition region during device breakdown, and solving the problems of edge breakdown, increased leakage, and reduced breakdown voltage.

[0014] In one embodiment, the length of the grid groove is less than the length of the source groove, and the grid groove is surrounded on both sides by the source groove. Therefore, the grid groove is located within the protection range of the source groove, and the source groove can provide comprehensive and effective protection for the grid groove.

[0015] In one embodiment, the transition groove and the gate groove are distributed on the same straight line, and the distance between the transition groove and the gate groove is greater than or equal to 0.

[0016] When the distance between the transition groove and the gate groove is 0, the transition groove and the gate groove are closely connected; when the distance between the transition groove and the gate groove is greater than 0, there is a certain distance between the transition groove and the gate groove, which can reduce the etching difficulty.

[0017] In one embodiment, the surface width of the gate polycrystalline protective strip is greater than the width of the transition groove.

[0018] In one embodiment, the depth of the transition groove is 1.5 μm to 3.5 μm. Therefore, the depth of the P-type injection region can reach 2.5 μm to 4.5 μm, providing effective protection for the transition groove.

[0019] In one embodiment, the depth of the transition groove is equal to the depth of the source groove.

[0020] In one embodiment, the transition trench and the source trench are formed in the same etching process.

[0021] In one embodiment, the depth of the transition slot is equal to the sum of the source slot depth and the gate slot depth.

[0022] In one embodiment, the transition trench formation process includes: performing a first etching simultaneously with the gate trench; and performing a second etching simultaneously with the source trench.

[0023] In one embodiment, the transition groove is formed by a separate etching process.

[0024] As can be seen, the transition trench can be formed not only by a separate etching process, but also in the same etching process as the source trench, or simultaneously etched once with the source trench and once simultaneously etched with the gate trench. Thus, its fabrication process only requires appropriate adjustment of the mask shape, without adding extra etching processes and therefore no additional costs. Attached Figure Description

[0025] Figure 1 This is a top view of an existing SiC Trench MOSFET device;

[0026] Figure 2 This is a cross-sectional view of an existing SiC Trench MOSFET device at point A-A';

[0027] Figure 3 This is a cross-sectional view of an existing SiC Trench MOSFET device at C-C'.

[0028] Figure 4 A top view of a SiC Trench MOSFET device provided in an embodiment of the present invention;

[0029] Figure 5 A cross-sectional view of a SiC Trench MOSFET device at point A-A' provided in an embodiment of the present invention;

[0030] Figure 6 A cross-sectional view of a SiC Trench MOSFET device at C-C' provided for an embodiment of the present invention;

[0031] Figure 7 A cross-sectional view of a SiC Trench MOSFET device at point B-B' provided for an embodiment of the present invention;

[0032] Figure 8 A cross-sectional view at B-B' of another SiC Trench MOSFET device provided in an embodiment of the present invention;

[0033] Figure 9 A cross-sectional view at A-A' of another SiC Trench MOSFET device provided in an embodiment of the present invention;

[0034] Figure 10 A cross-sectional view at A-A' of another SiC Trench MOSFET device provided in an embodiment of the present invention;

[0035] Figures 11-14 This is a process diagram illustrating the fabrication of the gate trench, source trench, and transition trench of a SiC Trench MOSFET device according to Embodiment 1 of the present invention.

[0036] Figures 15-17 This is a process diagram illustrating the fabrication of the gate trench, source trench, and transition trench of a SiC Trench MOSFET device according to Embodiment 2 of the present invention.

[0037] Figures 18-20 This is a process diagram illustrating the fabrication of the gate trench, source trench, and transition trench of a SiC Trench MOSFET device provided in Embodiment 3 of the present invention.

[0038] Among them, 10 is the gate trench; 101 is the gate oxide layer; 102 is the gate; 103 is the body region; 104 is the source region; 105 is the N-type drift region; 106 is the P-type implantation region; 20 is the source trench; 201 is the source polysilicon; 30 is the gate polysilicon bus; 40 is the transition trench; 401 is the gate polysilicon guard strip; 111 is the source hard mask; 112 is the gate hard mask; 113 is the source hard mask; 114 is the hard mask; and 115 is the gate hard mask. Detailed Implementation

[0039] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0041] One embodiment of the present invention discloses a SiC Trench MOSFET device, such as Figure 4 , Figure 5 and Figure 6 As shown, it includes an active region, a transition region, and a termination region, wherein a gate polysilicon bus 30 is disposed in the termination region. The SiC Trench MOSFET device further includes:

[0042] Gate trench 10 and source trench 20 are alternately distributed in the active region, and the gate trench 10 and source trench 20 are filled with polysilicon, wherein the polysilicon filled in the gate trench 10 is gate 102, and the polysilicon filled in the source trench 20 is source polysilicon 201.

[0043] A transition groove 40 is located within the transition region, with one end extending to the active region and the other end extending to the terminal region, and the depth of the transition groove 40 is t. GTR_tran The depth t of the source trench 20 is not less than STR (that is, t) GTR_tran ≥t STR The transition trench 40 has a P-type injection region 106 on its sidewall and bottom outer side. The transition trench 40 is filled with a gate polysilicon protection strip 401 (the material of the gate polysilicon protection strip 401 is polysilicon). The two ends of the gate polysilicon protection strip 401 are electrically connected to the gate polysilicon bus 30 and the polysilicon (gate 102) filled in the gate trench 10, respectively.

[0044] The gate trench 10, source trench 20, and transition trench 40 are further provided with a gate oxide layer 101 on their inner surfaces to isolate the polysilicon material filled within them. A body region 103, a source region 104, and an N-type drift region 105 are also provided on both sides and at the bottom of the gate trench 10. Figure 6 (The screenshot at C-C' is similar to that in the prior art). A P-type injection zone 106 is also provided at the bottom and on the outer side wall of the source tank 20.

[0045] It should be noted that in this embodiment, the gate slot 10 is located within the active region, that is, the gate slot 10 ends within the active region and does not extend into the transition region.

[0046] In one embodiment, the length of the gate slot 10 is less than the length of the source slot 20, and the gate slot 10 is surrounded on both sides by the source slot 20. Therefore, the gate slot 10 is located within the protection range of the source slot 20, and the source slot 20 can provide comprehensive and effective protection for the gate slot 10.

[0047] In one embodiment, the transition groove 40 and the gate groove 10 are distributed on the same straight line, and the distance between the transition groove 40 and the gate groove 10 is greater than or equal to 0.

[0048] It should be noted that the distance between the transition groove 40 and the gate groove 10 refers to the distance between the two ends of the transition groove 40 and the gate groove 10 that are close to each other.

[0049] In one embodiment, the distance d between the transition groove 40 and the gate groove 10 is... GTR The distance is 0~5.0μm. Preferably, the distance d between the transition groove 40 and the gate groove 10 is... GTR The micrometers are 0, 1.0 μm, 2.0 μm, 3.0 μm, 4.0 μm, or 5.0 μm, etc.

[0050] like Figure 7 As shown, when the distance d between the transition groove 40 and the gate groove 10... GTR When the value is 0, the transition groove 40 is tightly connected to the gate groove 10, and the junction has a ladder-like structure. At this time, one end of the gate polycrystalline protection strip 401 extends to the bottom of the gate polycrystalline bus and is electrically connected to the gate polycrystalline bus, while the other end is directly electrically connected to the end of the gate groove 10 in the active region near the transition region.

[0051] like Figure 8 As shown, when the distance d between the transition groove 40 and the gate groove 10... GTR When the value is greater than 0, there is a certain distance between the transition trench 40 and the gate trench 10, and a raised platform appears at the junction, separating the transition trench 40 and the gate trench 10. At this time, one end of the gate polycrystalline protection strip 401 extends to the bottom of the gate polycrystalline bus and is electrically connected to the gate polycrystalline bus, while the other end covers the gap between the gate trench 10 and the transition trench 40 in the active region. This reduces the requirement for mask alignment accuracy during etching, thus reducing the etching difficulty.

[0052] One embodiment, such as Figure 5 As shown, the surface width W of the gate polycrystalline protective strip 401 poly Width W greater than the transition groove 40 GTR_tranIn this way, width defects generated during the etching process of the transition groove 40 can be eliminated, which is beneficial to improving the stability of the device.

[0053] In one embodiment, the surface width W of the gate polycrystalline protective strip 401 poly The width is 0.2μm to 2.5μm. Preferably, the surface width W of the gate polycrystalline protective strip 401 is... poly The micrometers are 0.2μm, 0.6μm, 1.0μm, 1.4μm, 1.8μm, 2.0μm, 2.2μm, or 2.5μm, etc.

[0054] In addition, it can also be like Figure 9 As shown, the surface width W of the gate polycrystalline protective strip 401 poly The width W of the transition groove is equal to 40. GTR_tran Or, as Figure 10 As shown, the surface width W of the gate polycrystalline protective strip 401 poly The width W is less than the width of the transition groove 40. GTR_tran .

[0055] The SiC Trench MOSFET device disclosed in this embodiment modifies the existing scheme of extending the gate trench into the transition region to a structure where the gate trench and the transition trench are separate, and both the gate trench and the source trench are located within the active region, thus placing the gate trench within the protection range of the source trench. Furthermore, the transition trench extends into the active region, and the depth of the transition trench is not less than the depth of the source trench. P-type injection regions are provided on the sidewalls and bottom outer sides of the transition trench. Thus, the depth of the P-type injection region outside the transition trench will not be less than the depth of the P-type injection region outside the source trench. This effectively extends the protection of the gate trench by the source trench within the active region into the transition region, reducing the gate oxide electric field strength and leakage risk in the transition region during device breakdown, and solving the problems of edge breakdown, increased leakage, and reduced breakdown voltage.

[0056] In another embodiment, the transition groove 40 has a depth of t. GTR_tran The diameter is 1.5μm to 3.5μm. Preferably, the transition groove has a depth of 40t. GTR_tran The sizes are 1.5μm, 2μm, 2.5μm, 3μm, or 3.5μm, etc.

[0057] In one embodiment, in the active region, the source trench is 20 at a depth of t. STR The micrometer diameter is 1.5μm to 2.5μm, and the source trench width is 20W. STR The thickness is 1.5μm to 2.5μm; the gate slot depth is 10 t. GTR_act The diameter is 0.8μm~1.2μm, and the width of the gate slot is W. GTR_act The width is 0.4μm to 1.2μm. Preferably, the transition groove 40 has a width W. GTR_tranEqual to the width W of the gate slot 10 GTR_act .

[0058] In existing technologies, to achieve electrical connection between the gate inside the gate trench and the polysilicon bus on the outer gate, the gate trench extends into the transition region. Therefore, the gate trench in the transition region and the gate trench in the active region are a single structure with the same depth, typically 0.8 μm to 1.2 μm. In contrast, the depth of the P-type implantation region is usually no more than 1 μm. Thus, the P-type implantation region in the transition region cannot effectively protect the gate trench in existing technologies. In this embodiment, the depth of the transition trench is 1.5 μm to 3.5 μm, and the depth of the P-type implantation region injected using the transition trench as a mask can reach 2.5 μm to 4.5 μm. This depth is not lower than the depth of the P-type implantation region near the source trench, extending the protection effect of the source trench on the gate trench in the active region to the transition region, reducing the gate oxide electric field strength and leakage risk in the transition region during device breakdown voltage.

[0059] In another embodiment, the depth of the transition trench is equal to the depth of the source trench. In this case, the transition trench and the source trench are formed in the same etching process.

[0060] In another embodiment, the transition trench depth is equal to the sum of the source trench depth and the gate trench depth. In this case, the transition trench formation process includes: performing a first etching simultaneously with the gate trench; and performing a second etching simultaneously with the source trench.

[0061] In another embodiment, the transition groove is formed by a separate etching process. In this case, the depth of the transition groove can be freely chosen.

[0062] As can be seen from the above embodiments, the transition trench can be formed by a separate etching process, or it can be formed in the same etching process as the source trench, or it can be formed by combining the etching processes of the source trench and the gate trench. Thus, the SiC Trench MOSFET device disclosed in this embodiment of the invention can be fabricated simply by appropriately adjusting the mask shape and process steps, without increasing additional costs.

[0063] The SiC Trench MOSFET device disclosed in this solution will now be described in conjunction with specific embodiments.

[0064] Example 1

[0065] Example 1 discloses a SiC Trench MOSFET device, such as Figure 4 , Figure 5 , Figure 6 and Figure 8 As shown, it includes an active region, a transition region, and a termination region, wherein a gate polysilicon bus 30 is disposed in the termination region. The SiC Trench MOSFET device further includes:

[0066] Gate trench 10 and source trench 20 are alternately distributed in the active region, and the gate trench 10 and source trench 20 are filled with polysilicon, wherein the polysilicon filled in the gate trench 10 is gate 102, and the polysilicon filled in the source trench 20 is source polysilicon 201.

[0067] A transition groove 40 is located within the transition region, with one end extending to the active region and the other end extending to the terminal region, and the depth of the transition groove 40 is t. GTR_tran Equal to the depth t of the source groove 20 STR (that is, t) GTR_tran =t STR The transition trench 40 has a P-type injection region 106 on its sidewall and bottom outer side. The transition trench 40 is filled with a gate polysilicon protection strip 401 (the material of the gate polysilicon protection strip 401 is also polysilicon). The two ends of the gate polysilicon protection strip 401 are electrically connected to the gate polysilicon bus 30 and the polysilicon (gate 102) filled in the gate trench 10, respectively.

[0068] Wherein, the transition groove 40 has a depth t GTR_tran Equal to the source trench 20 depth t STR The depth t of the gate slot 10 is equal to 2.0 μm. GTR_act The width is 0.8 μm. The transition groove 40 has a width W. GTR_tran Equal to the width W of the gate slot 10 GTR_act The distance d between the transition groove 40 and the gate groove 10 is equal to 1.0 μm. GTR The surface width W of the gate polycrystalline protective strip 401 is 3.0 μm. poly It is 2.0 μm.

[0069] In this embodiment, the transition groove and the source groove are formed in the same etching process.

[0070] Specifically, the fabrication process of the SiC Trench MOSFET device includes:

[0071] A SiC substrate is provided, wherein an N-type drift region, a body region and a source region are disposed in the active region of the SiC substrate;

[0072] A shallow P-type implantation region is formed in the pre-defined active and transition regions of the SiC substrate using an ion implantation process (the shallow P-type implantation region has the same depth as the P-type implantation region in the prior art).

[0073] An oxide layer is deposited and photolithographically etched to form a hard mask for dry etching of the source trench and transition trench (source hard mask 111, such as...). Figure 11 ).

[0074] Source trench 20 and transition trench 40 are formed by dry etching. After etching, the source hard mask 111 is retained (e.g., ...). Figure 12 ).

[0075] A deep P-type implantation region 106 was formed by ion implantation (e.g.) Figure 13 The sidewalls and bottom of the source trench 20 and the transition trench 40 need to be injected. After the injection is completed, the source hard mask 111 is removed.

[0076] The active region is formed by dry etching (e.g., the gate trench 10). Figure 14 ).

[0077] A gate oxide layer is deposited, followed by polysilicon deposition, which must completely fill all trenches.

[0078] The gate, source polysilicon, gate polysilicon guard strip, and gate polysilicon bus of the terminal region are formed by photolithography and dry etching.

[0079] According to the above process steps, the source trench depth is equal to the transition trench depth and greater than the active region grid trench depth, i.e., t STR = t GTR_tran > t GTR_act .

[0080] The SiC Trench MOSFET device structure and fabrication method disclosed in Example 1, compared with the prior art, adjusts the existing scheme of extending the gate trench into the transition region to a structure where the gate trench and the transition trench are separate, and both the gate trench and the source trench are located within the active region, thus placing the gate trench within the protection range of the source trench. Furthermore, the transition trench extends into the active region, and the depth of the transition trench is equal to the depth of the source trench. Thus, the depth of the P-type injection region outside the transition trench is equal to the depth of the P-type injection region outside the source trench. This effectively extends the protection of the gate trench by the source trench within the active region into the transition region, reducing the gate oxide electric field strength and leakage risk in the transition region during device breakdown, and solving the problems of edge breakdown, increased leakage, and reduced breakdown voltage. Moreover, the corresponding fabrication process only requires adjusting the mask shape, with virtually no increase in fabrication cost.

[0081] Example 2

[0082] Example 2 discloses another SiC Trench MOSFET device, such as Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, it includes an active region, a transition region, and a termination region, wherein a gate polysilicon bus 30 is disposed in the termination region. The SiC Trench MOSFET device further includes:

[0083] Gate trench 10 and source trench 20 are alternately distributed in the active region, and the gate trench 10 and source trench 20 are filled with polysilicon, wherein the polysilicon filled in the gate trench 10 is gate 102, and the polysilicon filled in the source trench 20 is source polysilicon 201.

[0084] A transition groove 40 is located within the transition region, with one end extending to the active region and the other end extending to the terminal region, and the depth of the transition groove 40 is t. GTR_tran Equal to the depth t of the source groove 20 STR and gate depth t GTR_act The sum of (i.e., t) GTR_tran =t STR +t GTR_act The transition trench 40 has a P-type injection region 106 on its sidewall and bottom outer side. The transition trench 40 is filled with a gate polysilicon protection strip 401 (the material of the gate polysilicon protection strip 401 is also polysilicon). The two ends of the gate polysilicon protection strip 401 are electrically connected to the gate polysilicon bus 30 and the polysilicon (gate 102) filled in the gate trench 10, respectively.

[0085] Wherein, the source groove 20 has a depth t STR The depth t of the gate slot 10 is 2.0 μm. GTR_act The transition groove has a depth of 40 μm and a diameter of 1.0 μm. GTR_tran It is equal to 3.0 μm. The transition groove has a width of 40 W. GTR_tran Equal to the width W of the gate slot 10 GTR_act The distance d between the transition groove 40 and the gate groove 10 is equal to 1.2 μm. GTR The surface width W of the gate polycrystalline protective strip 401 is 0. poly It is 2.0 μm.

[0086] In this embodiment, the transition trench formation process includes: performing a first etching simultaneously with the gate trench; and performing a second etching simultaneously with the source trench.

[0087] Specifically, the fabrication process of the SiC Trench MOSFET device includes:

[0088] A SiC substrate is provided, wherein an N-type drift region, a body region and a source region are disposed in the active region of the SiC substrate;

[0089] A shallow P-type implantation region is formed in the pre-defined active and transition regions of the SiC substrate using an ion implantation process.

[0090] An oxide layer is deposited and photolithographically formed to create a dry etching hard mask for the gate trench and transition trench (gate hard mask 112, such as...). Figure 15 ).

[0091] The gate trench 10 is formed by dry etching, and the transition trench region is etched for the first time. After etching, the gate overhard mask 112 is removed (e.g., Figure 16 ).

[0092] An oxide layer is deposited and photolithographically formed to create a dry etching hard mask (source hard mask) for the source trench and transition trench.

[0093] The source trench 20 is formed by dry etching, and the transition trench region is etched a second time to finally form the transition trench 40. After etching, the source hard mask 111 is retained (e.g., Figure 17 ).

[0094] A deep P-type implantation region is formed through ion implantation. The sidewalls and bottom of both the source and transition trenches need to be implanted. After implantation, the hard mask of the source trench is removed.

[0095] A gate oxide layer is deposited, followed by polysilicon deposition, which must completely fill all trenches.

[0096] The gate, source polycrystalline, gate polycrystalline guard strip, and gate polycrystalline bus are formed by photolithography and dry etching.

[0097] According to the above process steps, the depth of the transition slot is equal to the sum of the source slot depth and the gate slot depth, i.e., t GTR_tran = t STR + t GTR_act .

[0098] The SiC Trench MOSFET device structure and fabrication method disclosed in Example 2, compared with the prior art, adjusts the existing scheme of extending the gate trench into the transition region to a structure where the gate trench and the transition trench are separate, and both the gate trench and the source trench are located within the active region, thus placing the gate trench within the protection range of the source trench. Furthermore, the transition trench extends into the active region, and the depth of the transition trench is equal to the sum of the depths of the source trench and the gate trench. Thus, the depth of the P-type injection region outside the transition trench is greater than the depth of the P-type injection region outside the source trench. This not only extends the protection of the gate trench from the source trench within the active region into the transition region, but also provides deeper P-type injection region protection, greatly reducing the gate oxide electric field strength and leakage risk in the transition region during device breakdown, solving the problems of edge breakdown, increased leakage, and reduced breakdown voltage. Moreover, the corresponding fabrication process only requires adjustments to the mask shape and some process sequences, with virtually no increase in fabrication costs.

[0099] Example 3

[0100] Example 3 discloses another SiC Trench MOSFET device, such as Figure 4 , Figure 5 , Figure 6 and Figure 8 As shown, it includes an active region, a transition region, and a termination region, wherein a gate polysilicon bus 30 is disposed in the termination region. The SiC Trench MOSFET device further includes:

[0101] Gate trench 10 and source trench 20 are alternately distributed in the active region, and the gate trench 10 and source trench 20 are filled with polysilicon, wherein the polysilicon filled in the gate trench 10 is gate 102, and the polysilicon filled in the source trench 20 is source polysilicon 201.

[0102] A transition groove 40 is located within the transition region, with one end extending to the active region and the other end extending to the terminal region, and the depth of the transition groove 40 is t. GTR_tran The depth t of the source trench 20 is greater than STR (that is, t) GTR_tran >t STR The transition trench 40 has a P-type injection region 106 on its sidewall and bottom outer side. The transition trench 40 is filled with a gate polysilicon protection strip 401. The two ends of the gate polysilicon protection strip 401 are electrically connected to the gate polysilicon bus 30 and the polysilicon (gate 102) filled in the gate trench 10, respectively.

[0103] Wherein, the source groove 20 has a depth t STR The depth t of the gate slot 10 is 2.0 μm. GTR_act The transition groove has a depth of 40 μm and a diameter of 1.0 μm. GTR_tran It is equal to 2.5 μm. The width W of the transition groove is 40. GTR_tran Equal to the width W of the gate slot 10 GTR_act The distance d between the transition groove 40 and the gate groove 10 is equal to 1.2 μm. GTR The surface width W of the gate polycrystalline protective strip 401 is 1.0 μm. poly It is 2.0 μm.

[0104] In this embodiment, the transition groove is formed by a separate etching process.

[0105] Specifically, the fabrication process of the SiC Trench MOSFET device includes:

[0106] A SiC substrate is provided, wherein an N-type drift region, a body region and a source region are disposed in the active region of the SiC substrate;

[0107] A shallow P-type implantation region is formed in the pre-defined active and transition regions of the SiC substrate using an ion implantation process.

[0108] An oxide layer is deposited and photolithography is performed to form a dry etching hard mask (source hard mask) for the source trench.

[0109] Source trenches are formed by dry etching, and the source hard mask is retained after etching is completed.

[0110] A deep P-type implantation region 106 is formed in the source trench 20 by ion implantation (e.g., Figure 18 The sidewalls and bottom of the source trench 20 need to be injected, and the source hard mask 113 is removed after the injection is completed.

[0111] A dry etching hard mask (overhard mask) is formed by depositing an oxide layer and photolithography to create a transition trench.

[0112] Transition grooves are formed by dry etching, and an overly hard mask is retained after etching is completed.

[0113] A deep P-type implantation region 106 is formed by ion implantation into a transition trench 40 (e.g., Figure 19 The sidewalls and bottom of the transition groove 40 need to be injected, and the hard mask 114 is removed after the injection is completed.

[0114] A dry etching hard mask (gate hard mask) is formed by depositing an oxide layer and photolithography to create a gate trench.

[0115] The gate trench 10 is formed by dry etching, and the gate hard mask 115 is removed after etching (e.g., ...). Figure 20 ).

[0116] A gate oxide layer is deposited, followed by polysilicon deposition, which must completely fill all trenches.

[0117] The gate, source polycrystalline, gate polycrystalline guard strip, and gate polycrystalline bus are formed by photolithography and dry etching.

[0118] According to the above process steps, the depth of the transition tank is 2.5 μm, which is greater than the depth of the source tank, i.e., t GTR_tran >t STR Furthermore, the depth of the transition groove can be adjusted arbitrarily within the range of 2.0 μm to 3.5 μm. When the source groove depth is 1.5 μm, the range of the transition groove depth can be expanded to 1.5 μm to 3.5 μm.

[0119] The SiC Trench MOSFET device structure and fabrication method disclosed in Example 3, compared with the prior art, adjusts the existing scheme of extending the gate trench into the transition region to a structure where the gate trench and the transition trench are separate, and both the gate trench and the source trench are located within the active region, thus placing the gate trench within the protection range of the source trench. Furthermore, the transition trench extends into the active region, and the depth of the transition trench is greater than the depth of the source trench. Thus, the depth of the P-type injection region outside the transition trench is greater than the depth of the P-type injection region outside the source trench. This not only extends the protection of the gate trench from the source trench within the active region into the transition region, but also provides deeper P-type injection region protection, significantly reducing the gate oxide electric field strength and leakage risk in the transition region during device breakdown, solving the problems of edge breakdown, increased leakage, and reduced breakdown voltage. Moreover, the corresponding fabrication process only requires adjustments to the mask shape and some process sequences, with virtually no increase in fabrication cost.

[0120] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The terms "first" and "second" used in this document are for distinction only and are not intended to limit the content of this invention.

[0121] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A SiC Trench MOSFET device, comprising an active region, a transition region, and a termination region, wherein, The terminal area is provided with a gate polycrystalline bus, characterized in that it further includes: Gate trenches and source trenches are alternately distributed within the active region, and the gate trenches and source trenches are filled with polysilicon. A transition trench is located within the transition region, with one end extending to the active region and the other end extending to the terminal region. The depth of the transition trench is not less than the depth of the source trench. A P-type injection region is provided on the sidewall and bottom outer side of the transition trench. The transition trench is filled with a gate polysilicon protection strip, and both ends of the gate polysilicon protection strip are electrically connected to the gate polysilicon bus and the polysilicon filled in the gate trench, respectively.

2. The SiC Trench MOSFET device according to claim 1, characterized in that, The length of the grid groove is less than the length of the source groove, and the grid groove is surrounded by the source groove on both sides.

3. The SiC Trench MOSFET device according to claim 1, characterized in that, The transition groove and the grid groove are distributed on the same straight line, and the distance between the transition groove and the grid groove is greater than or equal to 0.

4. The SiC Trench MOSFET device according to claim 1, characterized in that, The surface width of the gate polycrystalline protective strip is greater than the width of the transition groove.

5. The SiC Trench MOSFET device according to claim 1, characterized in that, The depth of the transition groove is 1.5μm to 3.5μm.

6. The SiC Trench MOSFET device according to claim 5, characterized in that, The depth of the transition groove is equal to the depth of the source groove.

7. The SiC Trench MOSFET device according to claim 6, characterized in that, The transition groove and the source groove are formed in the same etching process.

8. The SiC Trench MOSFET device according to claim 5, characterized in that, The depth of the transition slot is equal to the sum of the source slot depth and the gate slot depth.

9. The SiC Trench MOSFET device according to claim 8, characterized in that, The process of forming the transition trench includes: performing a first etching simultaneously with the gate trench; and performing a second etching simultaneously with the source trench.

10. The SiC Trench MOSFET device according to claim 5, characterized in that, The transition groove is formed by a separate etching process.

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