A SiC trench MOSFET device

Abstract

The application relates to a SiC Trench MOSFET device, which adjusts the scheme that a gate slot in the prior art is extended to a transition region into a structure that the gate slot is separated from a transition slot, and the gate slot and a source slot are located in an active region, so that the gate slot is located in the protection range of the source slot. Moreover, the transition slot extends into the active region, the depth of the transition slot is not less than the depth of the source slot, and a P-type injection region is arranged outside the side wall and the bottom of the transition slot. In this way, the depth of the P-type injection region outside the transition slot is not less than the depth of the P-type injection region outside the source slot. The protection of the source slot to the gate slot in the active region is extended to the transition region, the gate oxide electric field intensity and the leakage risk in the transition region are reduced when the device withstands voltage, and the problems of edge breakdown, increased leakage and reduced withstand voltage capacity of the device are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a SiC Trench MOSFET device. BACKGROUND

[0002] Metal-oxide-semiconductor field-effect transistor (MOSFET) devices, as the core devices of modern power electronic systems, are widely used in power management, motor drive, new energy conversion and other fields. With the gradual increase of voltage / current / power of power electronic devices, the performance of traditional Si MOSFET is limited in high-voltage, high-temperature and high-frequency scenarios, while SiC MOSFET shows significant advantages due to its excellent material properties: higher withstand voltage, lower on-state loss, faster switching speed, and excellent high-temperature stability, becoming the preferred solution for high-voltage and high-power applications such as new energy power generation, electric vehicles and industrial power supplies. However, due to the structural limitations of traditional silicon carbide planar gate MOSFET, its cell size is difficult to further reduce, and therefore there is an inherent contradiction between its on-state resistance (RDSON) and withstand voltage capability, making it difficult to meet the demand for high efficiency and high power density.

[0003] To break through the performance bottleneck of the planar structure, a silicon carbide trench MOSFET (SiC Trench MOSFET) structure is born. By etching a vertical trench on the surface of a silicon carbide wafer and filling it with a gate material, the current can flow in the vertical direction, thereby shortening the conduction path, reducing the JFET effect, increasing the cell density, and thus reducing the on-state resistance. At the same time, the trench gate structure is also beneficial to reducing the gate charge (Qg) and Miller capacitance (Cgd), making the device have better switching performance and being more suitable for high-frequency applications.

[0004] Although the SiC Trench MOSFET has the above advantages, its trench gate structure has obvious disadvantages compared to the traditional planar gate structure: when the device withstands voltage, there is an electric field concentration effect in the gate oxide layer at the bottom of the gate trench, making the electric field strength at this point significantly higher than the rest, thereby causing threshold voltage drift or gate oxide breakdown (such as the interface state problem of SiC MOSFET). Therefore, the trench gate structure needs an additional gate trench protection structure to reduce the electric field strength in the gate oxide layer and prevent the performance of the device from being affected.

[0005] Therefore, a double-trench MOSFET device structure appears. As shown in Figure 1 , Figure 2 and Figure 3As shown, the basic structure of the double-trench MOSFET device includes an active region, a transition region and a termination region. In the active region, gate trenches 10 and source trenches 20 are arranged alternately. The bottom and sidewall of the gate trench 10 are provided with a gate oxide layer 101, and filled with polysilicon as a gate 102. A body region 103, a source region 104 and an N-type drift region 105 (regions in the active region that are not etched and ion implanted) are also provided on both sides and the lower part of the gate trench 10. The bottom and sidewall of the source trench 20 are also covered with a gate oxide layer 101, and filled with polysilicon (source polysilicon 201). The bottom and sidewall of the source trench 20 are also provided with a P-type implant region 106. The periphery of the device is the termination region, which is provided with a semi-enclosed gate polysilicon bus 30 for electrical connection of the device to an external circuit. In order to achieve electrical connection between the gate 102 in the gate trench 10 and the gate polysilicon bus 30 outside, only the gate trench 10 extends into the transition region. The gate polysilicon bus 30 is overlaid on the gate trench 10, thereby achieving connection with the polysilicon (gate 102) in the gate trench 10.

[0006] In the double-trench MOSFET device, the P-type implant region 106 on both sides of the gate trench 10 protects the gate trench 10 and the gate oxide layer 101. When the device is subjected to voltage resistance, the PN junction formed between the P-type implant region 106 and the N-type drift region 105 will be depleted, resulting in a so-called "shielding effect" that can reduce the electric field intensity at the bottom of the gate trench 10, thereby preventing the gate oxide layer 101 from being affected by high electric fields. The deeper the P-type implant region 106, the stronger the "shielding effect", the lower the electric field intensity, and the better the protection effect. However, due to the limitations of SiC material properties and ion implantation energy, the depth of the P-type implant region 106 is usually limited (usually not more than 1 μm).

[0007] In the active region, the introduction of the source trench 20 structure can increase the depth of the P-type implant region 106, thereby enhancing the protection of the P-type implant region on the gate trench 10. However, in the transition region, if the source trench 20 and the gate trench 10 extend into the transition region together, the polysilicon (source polysilicon 201) filled in the source trench 20 will also be connected to the polysilicon (gate 102) in the gate trench 10, thereby causing a short circuit. Therefore, the source trench 20 structure cannot be provided in the transition region. At the same time, since the polysilicon (gate 102) in the gate trench 10 needs to be connected to the gate polysilicon bus 30, the length of the gate trench 10 must be greater than the length of the source trench 20. In this way, the gate trench 10 in the transition region will lose the enhanced protection effect of the source trench 20, resulting in a higher electric field intensity near the gate oxide layer 101 in the transition region than in the active region, which can easily become a weak area of the entire device, leading to edge breakdown, increased leakage current and reduced voltage resistance of the device. SUMMARY

[0008] Therefore, it is necessary to provide a SiC Trench MOSFET device to solve the problems of edge breakdown, increased leakage current and reduced voltage resistance of the device.

[0009] To this end, the technical solution adopted by the present application is as follows:

[0010] A SiC Trench MOSFET device, comprising an active region, a transition region and a terminal region, wherein a gate polysilicon bus is arranged in the terminal region, and further comprising:

[0011] Gate trenches and source trenches, which are alternately distributed in the active region, and the gate trenches and the source trenches are filled with polysilicon;

[0012] A transition trench, which is located in the transition region, extends to the active region at one end and extends to the terminal region at the other end, and the depth of the transition trench is not less than the depth of the source trench, the sidewall and the outer bottom of the transition trench are provided with a P-type implantation region, and the transition trench is filled with a gate polysilicon protection strip, and the two ends of the gate polysilicon protection strip are electrically connected with the gate polysilicon bus and the polysilicon filled in the gate trench, respectively.

[0013] The SiC Trench MOSFET device disclosed in the present application adjusts the scheme of extending the gate trench in the prior art to the transition region to a separate structure of the gate trench and the transition trench, and the gate trench and the source trench are both located in the active region, so that the gate trench is placed in the protection range of the source trench. Moreover, the transition trench extends into the active region, and the depth of the transition trench is not less than the depth of the source trench, and the sidewall and the outer bottom of the transition trench are provided with a P-type implantation region. In this way, the depth of the P-type implantation region outside the transition trench will not be less than the depth of the P-type implantation region outside the source trench. It is equivalent to extending the protection of the source trench to the gate trench in the active region to the transition region, reducing the gate oxide electric field strength and the risk of leakage in the transition region when the device withstands voltage, and solving the problems of edge breakdown, increased leakage and reduced withstand voltage of the device.

[0014] In one embodiment, the length of the gate trench is less than the length of the source trench, and the gate trench is surrounded by the source trench on both sides. Therefore, the gate trench is located in the protection range of the source trench, and the source trench can provide comprehensive and effective protection for the gate trench.

[0015] In one embodiment, the transition trench and the gate trench are distributed on the same straight line, and the distance between the transition trench and the gate trench is greater than or equal to 0.

[0016] When the distance between the transition trench and the gate trench is 0, the transition trench and the gate trench are closely connected; when the distance between the transition trench and the gate trench is greater than 0, there is a certain distance between the transition trench and the gate trench, which can reduce the etching difficulty.

[0017] In one embodiment, the surface width of the gate polysilicon protection strip is greater than the width of the transition trench.

[0018] In one embodiment, the transition trench has a depth of 1.5 μm to 3.5 μm. In this case, the P-type implantation region has a depth of 2.5 μm to 4.5 μm, which can effectively protect the transition trench.

[0019] In one embodiment, the depth of the transition trench is equal to the depth of the source trench.

[0020] In one embodiment, the transition trench is formed in the same etching process as the source trench.

[0021] In one embodiment, the depth of the transition trench is equal to the sum of the depth of the source trench and the depth of the gate trench.

[0022] In one embodiment, the transition trench is formed by a first etching process simultaneously with the gate trench and a second etching process simultaneously with the source trench.

[0023] In one embodiment, the transition trench is formed by a separate etching process.

[0024] As can be seen, the transition trench can be formed by a separate etching process, or can be formed in the same etching process as the source trench, or can be formed by a first etching process simultaneously with the source trench and a second etching process simultaneously with the gate trench. In this way, only the mask shape needs to be adjusted in the manufacturing process, without increasing the number of etching processes and thus without increasing the cost. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a top view of a prior art SiC Trench MOSFET device;

[0026] Figure 2 is a cross-sectional view of a prior art SiC Trench MOSFET device at A-A';

[0027] Figure 3 is a cross-sectional view of a prior art SiC Trench MOSFET device at C-C';

[0028] Figure 4 is a top view of a SiC Trench MOSFET device according to an embodiment of the present application;

[0029] Figure 5 is a cross-sectional view of a SiC Trench MOSFET device according to an embodiment of the present application at A-A';

[0030] Figure 6 is a cross-sectional view of a SiC Trench MOSFET device according to an embodiment of the present application at C-C';

[0031] Figure 7 A cross-sectional view of a SiC Trench MOSFET device provided by an embodiment of the present application at B-B';

[0032] Figure 8 A cross-sectional view of another SiC Trench MOSFET device provided by an embodiment of the present application at B-B';

[0033] Figure 9 A cross-sectional view of another SiC Trench MOSFET device provided by an embodiment of the present application at A-A';

[0034] Figure 10 A cross-sectional view of another SiC Trench MOSFET device provided by an embodiment of the present application at A-A';

[0035] Figures 11-14 A process diagram of manufacturing a gate trench, a source trench and a transition trench of a SiC Trench MOSFET device provided by Embodiment 1 of the present application;

[0036] Figures 15-17 A process diagram of manufacturing a gate trench, a source trench and a transition trench of a SiC Trench MOSFET device provided by Embodiment 2 of the present application;

[0037] Figures 18-20 A process diagram of manufacturing a gate trench, a source trench and a transition trench of a SiC Trench MOSFET device provided by Embodiment 3 of the present application.

[0038] wherein, 10, gate trench; 101, gate oxide layer; 102, gate electrode; 103, body region; 104, source region; 105, N-type drift region; 106, P-type implanted region; 20, source trench; 201, source poly; 30, gate poly bus; 40, transition trench; 401, gate poly protection bar; 111, source over hard mask; 112, gate over hard mask; 113, source hard mask; 114, over hard mask; 115, gate hard mask. DETAILED DESCRIPTION

[0039] In order to facilitate the understanding of the present application, the present application will be described in more detail below. However, it should be understood that the present application can be realized in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0041] One embodiment of the present invention discloses a SiC Trench MOSFET device, such as Figure 4 , Figure 5 and Figure 6 As shown, it includes an active region, a transition region, and a termination region, wherein a gate polysilicon bus 30 is disposed in the termination region. The SiC Trench MOSFET device further includes:

[0042] Gate trench 10 and source trench 20 are alternately distributed in the active region, and the gate trench 10 and source trench 20 are filled with polysilicon, wherein the polysilicon filled in the gate trench 10 is gate 102, and the polysilicon filled in the source trench 20 is source polysilicon 201.

[0043] A transition groove 40 is located within the transition region, with one end extending to the active region and the other end extending to the terminal region, and the depth of the transition groove 40 is t. GTR_tran The depth t of the source trench 20 is not less than STR (that is, t) GTR_tran ≥t STR The transition trench 40 has a P-type injection region 106 on its sidewall and bottom outer side. The transition trench 40 is filled with a gate polysilicon protection strip 401 (the material of the gate polysilicon protection strip 401 is polysilicon). The two ends of the gate polysilicon protection strip 401 are electrically connected to the gate polysilicon bus 30 and the polysilicon (gate 102) filled in the gate trench 10, respectively.

[0044] The gate trench 10, source trench 20, and transition trench 40 are further provided with a gate oxide layer 101 on their inner surfaces to isolate the polysilicon material filled within them. A body region 103, a source region 104, and an N-type drift region 105 are also provided on both sides and at the bottom of the gate trench 10. Figure 6 (The screenshot at C-C' is similar to that in the prior art). A P-type injection zone 106 is also provided at the bottom and on the outer side wall of the source tank 20.

[0045] It should be noted that in this embodiment, the gate slot 10 is located within the active region, that is, the gate slot 10 ends within the active region and does not extend into the transition region.

[0046] In one embodiment, the length of the gate slot 10 is less than the length of the source slot 20, and the gate slot 10 is surrounded on both sides by the source slot 20. Therefore, the gate slot 10 is located within the protection range of the source slot 20, and the source slot 20 can provide comprehensive and effective protection for the gate slot 10.

[0047] In one embodiment, the transition groove 40 and the gate groove 10 are distributed on the same straight line, and the distance between the transition groove 40 and the gate groove 10 is greater than or equal to 0.

[0048] It should be noted that the distance between the transition groove 40 and the gate groove 10 refers to the distance between the two ends of the transition groove 40 and the gate groove 10 that are close to each other.

[0049] In one embodiment, the distance d between the transition groove 40 and the gate groove 10 is... GTR The distance is 0~5.0μm. Preferably, the distance d between the transition groove 40 and the gate groove 10 is... GTR The micrometers are 0, 1.0 μm, 2.0 μm, 3.0 μm, 4.0 μm, or 5.0 μm, etc.

[0050] like Figure 7 As shown, when the distance d between the transition groove 40 and the gate groove 10... GTR When the value is 0, the transition groove 40 is tightly connected to the gate groove 10, and the junction has a ladder-like structure. At this time, one end of the gate polycrystalline protection strip 401 extends to the bottom of the gate polycrystalline bus and is electrically connected to the gate polycrystalline bus, while the other end is directly electrically connected to the end of the gate groove 10 in the active region near the transition region.

[0051] like Figure 8 As shown, when the distance d between the transition groove 40 and the gate groove 10... GTR When the value is greater than 0, there is a certain distance between the transition trench 40 and the gate trench 10, and a raised platform appears at the junction, separating the transition trench 40 and the gate trench 10. At this time, one end of the gate polycrystalline protection strip 401 extends to the bottom of the gate polycrystalline bus and is electrically connected to the gate polycrystalline bus, while the other end covers the gap between the gate trench 10 and the transition trench 40 in the active region. This reduces the requirement for mask alignment accuracy during etching, thus reducing the etching difficulty.

[0052] One embodiment, such as Figure 5 As shown, the surface width W of the gate polycrystalline protective strip 401 poly Width W greater than the transition groove 40 GTR_tranIn this way, width defects generated during the etching process of the transition groove 40 can be eliminated, which is beneficial to improving the stability of the device.

[0053] In one embodiment, the surface width W of the gate polycrystalline protective strip 401 poly The width is 0.2μm to 2.5μm. Preferably, the surface width W of the gate polycrystalline protective strip 401 is... poly The micrometers are 0.2μm, 0.6μm, 1.0μm, 1.4μm, 1.8μm, 2.0μm, 2.2μm, or 2.5μm, etc.

[0054] In addition, it can also be like Figure 9 As shown, the surface width W of the gate polycrystalline protective strip 401 poly The width W of the transition groove is equal to 40. GTR_tran Or, as Figure 10 As shown, the surface width W of the gate polycrystalline protective strip 401 poly The width W is less than the width of the transition groove 40. GTR_tran .

[0055] The SiC Trench MOSFET device disclosed in this embodiment modifies the existing scheme of extending the gate trench into the transition region to a structure where the gate trench and the transition trench are separate, and both the gate trench and the source trench are located within the active region, thus placing the gate trench within the protection range of the source trench. Furthermore, the transition trench extends into the active region, and the depth of the transition trench is not less than the depth of the source trench. P-type injection regions are provided on the sidewalls and bottom outer sides of the transition trench. Thus, the depth of the P-type injection region outside the transition trench is not less than the depth of the P-type injection region outside the source trench. This effectively extends the protection of the gate trench by the source trench within the active region into the transition region, reducing the gate oxide electric field strength and leakage risk in the transition region during device breakdown, and solving the problems of edge breakdown, increased leakage, and reduced breakdown voltage.

[0056] In another embodiment, the transition groove 40 has a depth of t. GTR_tran The diameter is 1.5μm to 3.5μm. Preferably, the transition groove has a depth of 40t. GTR_tran The sizes are 1.5μm, 2μm, 2.5μm, 3μm, or 3.5μm, etc.

[0057] In one embodiment, in the active region, the source trench is 20 at a depth of t. STR The micrometer diameter is 1.5μm to 2.5μm, and the source trench width is 20W. STR The thickness is 1.5μm to 2.5μm; the gate slot depth is 10 t. GTR_act The diameter is 0.8μm~1.2μm, and the width of the gate slot is W. GTR_act The width is 0.4μm to 1.2μm. Preferably, the transition groove 40 has a width W. GTR_tranequal to the width W of the gate trench 10 GTR_act .

[0058] In the prior art, in order to realize the electrical connection between the gate in the gate trench and the gate polycrystal bus outside, the gate trench extends into the transition area, so that the gate trench in the transition area and the gate trench in the active area belong to an integrated structure, and the depths of the two are the same, generally 0.8 μm~1.2 μm. Relatively speaking, the depth of the P-type implantation region is usually not more than 1 μm. Therefore, the P-type implantation region in the transition area is difficult to effectively protect the gate trench in the prior art. In the embodiment, the depth of the transition trench is 1.5 μm~3.5 μm, and the depth of the P-type implantation region implanted by taking the transition trench as a mask can reach 2.5 μm~4.5 μm, which is not less than the depth of the P-type implantation region near the source trench. Therefore, the protection effect of the source trench in the active area on the gate trench can be extended to the transition area, and the gate oxide electric field strength and the risk of leakage in the transition area during the voltage resistance of the device can be reduced.

[0059] In another embodiment, the depth of the transition trench is equal to the depth of the source trench. At this time, the transition trench is formed in the same etching process as the source trench.

[0060] In another embodiment, the depth of the transition trench is equal to the sum of the depth of the source trench and the depth of the gate trench. At this time, the forming process of the transition trench includes: performing the first etching at the same time as the gate trench; and performing the second etching at the same time as the source trench.

[0061] In another embodiment, the transition trench is formed by a separate etching process. At this time, the depth of the transition trench can be freely selected.

[0062] As can be seen from the above embodiments, the transition trench can be formed by a separate etching process, or can be formed in the same etching process as the source trench, or can be formed in combination with the etching process of the source trench and the etching process of the gate trench. In this way, the SiC Trench MOSFET device disclosed in the embodiments of the present application can be obtained by appropriately adjusting the mask shape and the process steps, without increasing additional costs.

[0063] In the following, the SiC Trench MOSFET device disclosed in the present scheme will be described in conjunction with specific embodiments.

[0064] Embodiment 1

[0065] Embodiment 1 discloses a SiC Trench MOSFET device, as shown in Figure 4 、 Figure 5 、 Figure 6 and Figure 8 , which comprises an active area, a transition area and a terminal area, wherein a gate polycrystal bus 30 is arranged in the terminal area. The SiC Trench MOSFET device further comprises:

[0066] gate trenches 10 and source trenches 20, which are alternately distributed in the active region and filled with polysilicon, wherein the polysilicon filled in the gate trenches 10 is the gate 102, and the polysilicon filled in the source trenches 20 is the source polysilicon 201;

[0067] a transition trench 40, which is located in the transition region, extends to the active region at one end and extends to the terminal region at the other end, and the depth t of the transition trench 40 GTR_tran is equal to the depth t of the source trench 20 STR (that is, t GTR_tran =t STR ), the sidewall and the outer side of the bottom of the transition trench 40 are provided with a P-type implantation region 106, the transition trench 40 is filled with a gate polysilicon protection strip 401 (the material of the gate polysilicon protection strip 401 is also polysilicon), and the two ends of the gate polysilicon protection strip 401 are respectively electrically connected with the polysilicon (gate 102) filled in the gate polysilicon bus 30 and the gate trench 10.

[0068] wherein the depth t of the transition trench 40 GTR_tran is equal to the depth t of the source trench 20 STR is equal to 2.0 μm, the depth t of the gate trench 10 GTR_act is 0.8 μm. The width W of the transition trench 40 GTR_tran is equal to the width W of the gate trench 10 GTR_act is equal to 1.0 μm. The distance d between the transition trench 40 and the gate trench 10 GTR is 3.0 μm, and the surface width W of the gate polysilicon protection strip 401 poly is 2.0 μm.

[0069] In the embodiment, the transition trench and the source trench are formed in the same etching process.

[0070] Specifically, the manufacturing process of the SiC Trench MOSFET device comprises the following steps.

[0071] providing a SiC substrate, wherein an N-type drift region, a body region and a source region are arranged in the active region of the SiC substrate;

[0072] forming a shallow P-type implantation region in the preset active region and transition region of the SiC substrate by an ion implantation process (the depth of the shallow P-type implantation region is the same as that of the P-type implantation region in the prior art);

[0073] depositing an oxide layer and performing photolithography to form a hard mask for dry etching of the source trench and the transition trench (source-over-hard mask 111, such as Figure 11 ).

[0074] The source trench 20 and the transition trench 40 are formed by dry etching, and the source hard mask 111 is reserved after the etching (as shown in Figure 12 ).

[0075] The deep P-type injection region 106 is formed by ion implantation (as shown in Figure 13 ). The sidewall and the bottom of the source trench 20 and the transition trench 40 need to be implanted, and the source hard mask 111 is removed after the implantation.

[0076] The gate trench 10 of the active region is formed by dry etching (as shown in Figure 14 ).

[0077] The gate oxide layer is deposited, and then the polysilicon is deposited, which needs to completely fill all the trenches.

[0078] The gate, source polysilicon, gate polysilicon protection strip and gate polysilicon bus of the termination region are formed by photolithography and dry etching.

[0079] According to the above process steps, the depth of the source trench is equal to the depth of the transition trench, and is greater than the depth of the gate trench of the active region, that is, t STR = t GTR_tran > t GTR_act .

[0080] The SiC Trench MOSFET device structure and manufacturing method disclosed in Embodiment 1 adjust the scheme of extending the gate trench to the transition region in the prior art to a structure in which the gate trench and the source trench are separate, and the gate trench is located in the protection range of the source trench. Moreover, the transition trench extends into the active region, and the depth of the transition trench is equal to the depth of the source trench. In this way, the depth of the P-type injection region outside the transition trench is equal to the depth of the P-type injection region outside the source trench. This is equivalent to extending the protection of the source trench to the gate trench in the active region to the transition region, reducing the gate oxide electric field strength and the risk of leakage in the transition region when the device withstands voltage, and solving the problems of edge breakdown, increased leakage and reduced withstand voltage capability of the device. Moreover, the corresponding manufacturing process only needs to adjust the mask shape, and basically does not increase the manufacturing cost.

[0081] Embodiment 2

[0082] Embodiment 2 discloses another SiC Trench MOSFET device, as shown in Figure 4 , Figure 5 , Figure 6 and Figure 7 , which includes an active region, a transition region and a termination region, wherein the termination region is provided with a gate polysilicon bus 30. The SiC Trench MOSFET device further includes:

[0083] Gate trench 10 and source trench 20, which are alternately distributed in the active area, and the gate trench 10 and source trench 20 are filled with polysilicon, wherein the polysilicon filled in the gate trench 10 is the gate 102, and the polysilicon filled in the source trench 20 is the source polysilicon 201;

[0084] Transition trench 40, which is located in the transition area, extends to the active area at one end and extends to the terminal area at the other end, and the depth t GTR_tran of the transition trench 40 is equal to the depth t STR of the source trench 20 and the gate trench depth t GTR_act , that is, t GTR_tran =t STR +t GTR_act , the sidewall and the outside of the bottom of the transition trench 40 are provided with a P-type implantation region 106, the transition trench 40 is filled with a gate polysilicon protection strip 401 (the material of the gate polysilicon protection strip 401 is also polysilicon), and the two ends of the gate polysilicon protection strip 401 are respectively electrically connected with the polysilicon (gate 102) filled in the gate polysilicon bus 30 and the gate trench 10.

[0085] Wherein, the depth t STR of the source trench 20 is 2.0 μm, the depth t GTR_act of the gate trench 10 is 1.0 μm, and the depth t GTR_tran of the transition trench 40 is equal to 3.0 μm. The width W GTR_tran of the transition trench 40 is equal to the width W GTR_act of the gate trench 10, which is equal to 1.2 μm. The distance d GTR between the transition trench 40 and the gate trench 10 is 0, and the surface width W poly of the gate polysilicon protection strip 401 is 2.0 μm.

[0086] In the embodiment, the transition trench forming process includes: performing first etching at the same time as the gate trench; and performing second etching at the same time as the source trench.

[0087] Specifically, the manufacturing process of the SiC Trench MOSFET device includes:

[0088] Providing a SiC substrate, the active area of the SiC substrate is provided with an N-type drift region, a body region and a source region;

[0089] Forming a shallow P-type implantation region in the pre-set active area and transition area of the SiC substrate by ion implantation process;

[0090] Depositing an oxide layer and performing photolithography to form a dry etching hard mask (gate transition hard mask 112, such as Figure 15 ).

[0091] The gate trench 10 is formed by dry etching, and the first etching is performed on the transition trench area. After the etching is completed, the gate hard mask 112 is removed (as shown in Figure 16 ).

[0092] The oxide layer is deposited and photoetched, and the dry etching hard mask (source hard mask) of the source trench and the transition trench is formed.

[0093] The source trench 20 is formed by dry etching, and the second etching is performed on the transition trench area, and finally the transition trench 40 is formed. After the etching is completed, the source hard mask 111 is retained (as shown in Figure 17 ).

[0094] The deep P-type implantation area is formed by ion implantation. The sidewall and bottom of the source trench and the transition trench need to be implanted, and the source hard mask is removed after the implantation is completed.

[0095] The gate oxide layer is deposited, and then the polysilicon is deposited, which needs to completely fill all the trenches.

[0096] The gate, source polysilicon, gate polysilicon protection strip and gate polysilicon bus are formed by photoetching and dry etching.

[0097] According to the above process steps, the depth of the transition trench is equal to the sum of the depth of the source trench and the depth of the gate trench, that is, t GTR_tran = t STR + t GTR_act .

[0098] The SiC Trench MOSFET device structure and manufacturing method disclosed in Example 2 adjusts the scheme of extending the gate trench to the transition area in the prior art into a structure in which the gate trench and the source trench are separate, and the gate trench is located in the protection range of the source trench. Moreover, the transition trench extends into the active area, and the depth of the transition trench is equal to the sum of the depth of the source trench and the depth of the gate trench. In this way, the depth of the P-type implantation area outside the transition trench is greater than the depth of the P-type implantation area outside the source trench. Not only is the protection of the source trench to the gate trench in the active area extended to the transition area, but also a deeper P-type implantation area protection is provided, which greatly reduces the gate oxide electric field strength and the risk of leakage in the transition area when the device withstands voltage, and solves the problems of edge breakdown, increased leakage and reduced withstand voltage of the device. Moreover, the corresponding manufacturing process only needs to adjust the mask shape and part of the process sequence, and basically does not increase the manufacturing cost.

[0099] Example 3

[0100] Example 3 discloses another SiC Trench MOSFET device, as shown in Figure 4 , Figure 5 , Figure 6 andFigure 8 As shown, it comprises an active region, a transition region and a terminal region, wherein a gate polysilicon bus 30 is arranged in the terminal region. The SiC Trench MOSFET device further comprises:

[0101] a gate trench 10 and a source trench 20, which are alternately arranged in the active region and filled with polysilicon, wherein the polysilicon filled in the gate trench 10 is a gate 102 and the polysilicon filled in the source trench 20 is a source polysilicon 201;

[0102] a transition trench 40, which is arranged in the transition region, extends to the active region at one end and extends to the terminal region at the other end, and the depth t GTR_tran of the transition trench 40 is greater than the depth t STR of the source trench 20 (i.e., t GTR_tran > t STR ), the sidewall and the outer side of the bottom of the transition trench 40 are provided with a P-type implantation region 106, and the transition trench 40 is filled with a gate polysilicon protection strip 401, and the two ends of the gate polysilicon protection strip 401 are respectively electrically connected with the polysilicon (gate 102) filled in the gate trench 10 and the gate polysilicon bus 30.

[0103] In the embodiment, the depth t STR of the source trench 20 is 2.0 μm, the depth t GTR_act of the gate trench 10 is 1.0 μm, and the depth t GTR_tran of the transition trench 40 is equal to 2.5 μm. The width W GTR_tran of the transition trench 40 is equal to the width W GTR_act of the gate trench 10, which is equal to 1.2 μm. The distance d GTR between the transition trench 40 and the gate trench 10 is 1.0 μm, and the surface width W poly of the gate polysilicon protection strip 401 is 2.0 μm.

[0104] In the embodiment, the transition trench is formed by a separate etching process.

[0105] Specifically, the manufacturing process of the SiC Trench MOSFET device comprises:

[0106] providing a SiC substrate, wherein an N-type drift region, a body region and a source region are arranged in the active region of the SiC substrate;

[0107] forming a shallow P-type implantation region in the preset active region and transition region of the SiC substrate by an ion implantation process;

[0108] depositing an oxide layer and performing photolithography to form a dry etching hard mask (source hard mask) of the source trench.

[0109] The source trench is formed by dry etching, and the source hard mask is reserved after the etching is completed.

[0110] The deep P-type injection area 106 of the source trench 20 is formed by ion injection (as shown in Figure 18 ). The sidewall and bottom of the source trench 20 need to be injected, and the source hard mask 113 is removed after the injection is completed.

[0111] The oxide layer is deposited and photoetched to form the dry etching hard mask (over hard mask) of the transition trench.

[0112] The transition trench is formed by dry etching, and the over hard mask is reserved after the etching is completed.

[0113] The deep P-type injection area 106 of the transition trench 40 is formed by ion injection (as shown in Figure 19 ). The sidewall and bottom of the transition trench 40 need to be injected, and the over hard mask 114 is removed after the injection is completed.

[0114] The oxide layer is deposited and photoetched to form the dry etching hard mask (gate hard mask) of the gate trench.

[0115] The gate trench 10 is formed by dry etching, and the gate hard mask 115 is removed after the etching is completed (as shown in Figure 20 ).

[0116] The gate oxide layer is deposited, and then the polysilicon is deposited, which needs to completely fill all the trenches.

[0117] The gate, source polysilicon, gate polysilicon protection strip and gate polysilicon bus are formed by photoetching and dry etching.

[0118] According to the above process steps, the transition trench depth is 2.5 μm, which is greater than the source trench depth, that is, t GTR_tran t STR In addition, the transition trench depth can be adjusted within the range of 2.0 μm~3.5 μm. When the source trench depth is 1.5 μm, the transition trench depth range can be expanded to 1.5 μm~3.5 μm.

[0119] The SiC trench MOSFET device structure and manufacturing method disclosed in Embodiment 3, compared with the prior art, adjusts the scheme of extending the gate trench to the transition region in the prior art to a structure in which the gate trench and the transition trench are separate, and the gate trench and the source trench are both located in the active region, so that the gate trench is placed in the protection range of the source trench. Moreover, the transition trench extends into the active region, and the depth of the transition trench is greater than the depth of the source trench. In this way, the depth of the P-type implanted region outside the transition trench is greater than the depth of the P-type implanted region outside the source trench. Not only is the protection of the source trench to the gate trench in the active region extended to the transition region, but also a deeper P-type implanted region protection is provided, which greatly reduces the gate oxide electric field strength and the risk of leakage in the transition region when the device withstands voltage, and solves the problems of edge breakdown, increased leakage, and reduced withstand voltage capability of the device. Moreover, the corresponding manufacturing process only needs to adjust the mask shape and part of the process sequence, and basically does not increase the manufacturing cost.

[0120] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure. The "first" and "second" are only for distinction and are not a limitation of the present disclosure.

[0121] The above embodiments only express several embodiments of the present disclosure, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are within the scope of the present disclosure. Therefore, the scope of protection of the present patent should be subject to the appended claims.

Claims

1. A SiC Trench MOSFET device, comprising an active region, a transition region, and a termination region, wherein, The terminal area is provided with a gate polycrystalline bus, characterized in that it further includes: Gate trenches and source trenches are alternately distributed within the active region, and the gate trenches and source trenches are filled with polysilicon. A transition trench is located within the transition region, with one end extending to the active region and the other end extending to the terminal region. The depth of the transition trench is not less than the depth of the source trench. A P-type injection region is provided on the sidewall and bottom outer side of the transition trench. A gate polysilicon protection strip is filled in the transition trench, and both ends of the gate polysilicon protection strip are electrically connected to the gate polysilicon bus and the polysilicon filled in the gate trench, respectively. A P-type injection zone is provided at the bottom and on the outer side of the sidewall of the source tank.

2. The SiC Trench MOSFET device according to claim 1, characterized in that, The length of the grid groove is less than the length of the source groove, and the grid groove is surrounded by the source groove on both sides.

3. The SiC Trench MOSFET device according to claim 1, characterized in that, The transition groove and the grid groove are distributed on the same straight line, and the distance between the transition groove and the grid groove is greater than or equal to 0.

4. The SiC Trench MOSFET device according to claim 1, characterized in that, The surface width of the gate polycrystalline protective strip is greater than the width of the transition groove.

5. The SiC Trench MOSFET device according to claim 1, characterized in that, The depth of the transition groove is 1.5μm to 3.5μm.

6. The SiC Trench MOSFET device according to claim 5, characterized in that, The depth of the transition groove is equal to the depth of the source groove.

7. The SiC Trench MOSFET device according to claim 6, characterized in that, The transition groove and the source groove are formed in the same etching process.

8. The SiC Trench MOSFET device according to claim 5, characterized in that, The depth of the transition slot is equal to the sum of the source slot depth and the gate slot depth.

9. The SiC Trench MOSFET device according to claim 8, characterized in that, The process of forming the transition trench includes: performing a first etching simultaneously with the gate trench; and performing a second etching simultaneously with the source trench.

10. The SiC Trench MOSFET device according to claim 5, characterized in that, The transition groove is formed by a separate etching process.

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