A trench MOSFET device, method of manufacture and die

Abstract

The embodiment of the present application provides a trench MOSFET device, a manufacturing method and a chip, the device comprises a first cross section area, a second cross section area and a third cross section area which are arranged alternately along a first direction; the first cross section area, the second cross section area and the third cross section area all comprise: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N area, a P well area, an N+ area, a second trench, a gate and a source; the epitaxial layer is arranged on one side of the N-type substrate; the first N area is arranged below both sides of the first trench; the N+ area is arranged on both sides of the first trench; the P well area is connected below the N+ area; the second trench is arranged at the bottom of the first trench; the P area at the bottom and the corner of the second trench of the first cross section area and the P area at the bottom of the first trench of the third cross section area play an electric field shielding role, so that the device damage caused by the strong electric field at the corner of the trench is avoided, and the reliability of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a trench MOSFET device, manufacturing method, and chip. Background Technology

[0002] Silicon carbide (SiC), with its superior physical and electrical properties such as high electron saturation drift velocity, high critical breakdown electric field, wide bandgap, and excellent thermal conductivity, has become an ideal material for high-temperature and high-voltage power electronics. Within the family of vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, double-diffused MOSFETs (DMOSFETs) and trench-gate MOSFETs (UMOSFETs) each have their strengths. 4H-SiC UMOSFETs, with their higher-density cell structure and high mobility imparted by the non-polar surface, not only achieve a significant reduction in on-resistance but also a substantial increase in channel density. These unique advantages broaden the application prospects of 4H-SiC UMOSFETs in power electronics, indicating their important role in driving the advancement of power electronics technology.

[0003] Silicon carbide (SiC) exhibits significant advantages in high-frequency applications due to its superior physical and electrical properties, such as high electron saturation drift velocity, high thermal conductivity, and high breakdown electric field. These properties not only enhance device performance but also enable stable operation in high-temperature and high-power environments. However, under high breakdown electric field conditions, the electric field strength experienced by the gate dielectric is much higher than under normal operating conditions, which can easily lead to dielectric breakdown, damage, or degradation, resulting in lower gate dielectric reliability. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a trench MOSFET device, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0005] To address the aforementioned problems, embodiments of the present invention disclose a trench MOSFET device, the device comprising a first cross-sectional region, a second cross-sectional region, and a third cross-sectional region arranged alternately along a first direction;

[0006] The first cross-sectional region, the second cross-sectional region, and the third cross-sectional region each include: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N-region, a P-well region, an N+ region, a second trench, a gate, and a source.

[0007] The epitaxial layer is disposed on one side of the N-type substrate; the first N-region is located below both sides of the first trench;

[0008] The N+ region is located on both sides of the first trench;

[0009] The P-well region is connected below the N+ region; the P-well region and the N+ region are respectively connected to the sidewall of the first trench;

[0010] The second trench is located at the bottom of the first trench;

[0011] The gate electrode is embedded in the first trench; the source electrode is embedded in the second trench; the gate electrode is located on both sides of the source electrode;

[0012] The oxide layer is disposed in the first trench and the second trench, and encapsulates the gate and the source.

[0013] The first cross-sectional area further includes: a P region located below the first trench, the P region being located on the same layer as the first N region; the second trench extends into the interior of the P region;

[0014] The third cross-sectional area further includes: a P region located below the first trench, the P region being connected to the bottom of the first trench; the second trench penetrating the P region.

[0015] Optionally, the device further includes:

[0016] Both the first cross-sectional area and the third cross-sectional area further include: P+ regions disposed on both sides of the first trench within the epitaxial layer, wherein the P+ regions are located in the same layer as the N+ regions and are connected to the N+ regions;

[0017] The second cross-sectional region further includes: a second N region disposed on both sides of the first trench within the epitaxial layer, the depth of the second N region extending to connect with the first N region, and the second N region connecting with the N+ region and the P-well region.

[0018] Optionally, the device further includes:

[0019] An interlayer dielectric passivation layer is provided on the surface of the epitaxial layer;

[0020] Contact holes are provided on both sides of the interlayer dielectric passivation layer;

[0021] A first metal layer is disposed on the surface of the contact hole; the first metal layer is in contact with a portion of the P+ region and the N+ region;

[0022] A second metal layer is disposed on the surface of the first metal and the interlayer dielectric passivation layer.

[0023] Optionally, the device further includes a drain located on the other side of the N-type substrate.

[0024] Accordingly, this invention discloses a method for manufacturing a trench MOSFET device, used to manufacture the trench MOSFET device as described above, the method comprising:

[0025] Provide N-type substrates;

[0026] An epitaxial layer is grown on one side of the N-type substrate;

[0027] A first trench is etched on the epitaxial layer;

[0028] An oxide layer is grown on the surface of the epitaxial layer;

[0029] N-type ions are implanted below the sides of the first trench in the epitaxial layer to form a first N region; the first N region is located below the sides of the first trench.

[0030] P-type ions are implanted in the epitaxial layer to form a P-well region on both sides of the first trench, and N-type ions are implanted to form an N+ region; the P-well region is connected to the bottom of the N+ region; the P-well region and the N+ region are respectively connected to the sidewall of the first trench.

[0031] A second trench is etched at the bottom of the first trench;

[0032] A gate electrode is formed in the first trench, and a source electrode is formed in the second trench. The gate electrode is located on both sides of the source electrode, and an oxide layer is formed around the gate electrode and the source electrode.

[0033] Within the first cross-sectional area, when N-type ions are implanted below the first trench in the epitaxial layer to form a first N region, P-type ions are implanted below the first trench in the epitaxial layer to form a P region; the first N region and the P region are located in the same layer.

[0034] In the third cross-sectional area, when N-type ions are injected below the first trench on both sides of the epitaxial layer to form a first N region, P-type ions are injected below the first trench in the epitaxial layer to form a P region; the P region is connected to the bottom of the first trench.

[0035] Optionally, the method further includes:

[0036] When P-type ions are implanted in the epitaxial layer to form a P-well region on both sides of the first trench, and N-type ions are implanted to form an N+ region, P-type ions are implanted in the epitaxial layer to form a P+ region on both sides of the first trench. The P+ region and the N+ region are located in the same layer and are connected to the N+ region.

[0037] Within the second cross-sectional region, P-type ions are injected into the epitaxial layer corresponding to both sides of the first trench to form a P-well region. When N-type ions are injected to form an N+ region, N-type ions are injected into the epitaxial layer corresponding to both sides of the first trench, with the injection depth reaching the first N region to form a second N region. The second N region is connected to the N+ region and the P-well region.

[0038] Optionally, forming a gate electrode in the first trench and a source electrode in the second trench, wherein the gate electrode is located on both sides of the source electrode, and an oxide layer is formed around the gate electrode and the source electrode, includes:

[0039] Remove the oxide layer from the surface of the epitaxial layer, and grow a gate oxide layer on the surface of the first trench and the second trench;

[0040] Polysilicon is deposited on the surface of the epitaxial layer to deposit polysilicon in the first trench and the second trench;

[0041] The polysilicon on the surface of the epitaxial layer is etched, and the polysilicon on both sides of the first trench is retained as the gate.

[0042] An oxide layer is grown in the first trench and the second trench;

[0043] The oxide layer in the first trench and the second trench is etched to form a groove in the oxide layer, while retaining the oxide layer covering the gate and the surface of the second trench;

[0044] Polycrystalline silicon is deposited in the groove as a source electrode;

[0045] An oxide layer is formed around the gate and the source.

[0046] Optionally, forming an oxide layer around the gate and the source includes:

[0047] An oxide layer is grown in the first cross-sectional area, in the first trench and the second trench;

[0048] Within the second cross-sectional area, an oxide layer is grown in the first trench and the second trench, and the oxide layer on the surface of the source electrode is removed;

[0049] Within the third cross-sectional region, an oxide layer is grown in the first trench and the second trench, and polysilicon is deposited on the surface of the epitaxial layer so that the gates on both sides of the first trench are connected through the polysilicon, and the polysilicon on the surface of the epitaxial layer other than the first trench and the second trench is removed.

[0050] Optionally, the method further includes:

[0051] An insulating material is deposited on the surface of the epitaxial layer to form an interlayer dielectric passivation layer;

[0052] Remove the interlayer dielectric passivation layer above a portion of the N+ region and above the P+ region to create a contact hole.

[0053] A first metal layer is deposited on the surface of the contact hole;

[0054] A second metal layer is deposited on the surface of the first metal and the interlayer dielectric passivation layer.

[0055] Optionally, the method further includes:

[0056] Thinning is performed on the other side of the N-type substrate;

[0057] Metal is deposited on the other side of the N-type substrate as a drain electrode.

[0058] Accordingly, embodiments of the present invention disclose a trench MOSFET device as described in any of the preceding claims.

[0059] The embodiments of the present invention have the following advantages:

[0060] An embodiment of the present invention provides a trench MOSFET device, comprising a first cross-sectional region, a second cross-sectional region, and a third cross-sectional region alternately arranged along a first direction; each of the first, second, and third cross-sectional regions includes: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N-region, a P-well region, an N+ region, a second trench, a gate, and a source; the epitaxial layer is disposed on one side of the N-type substrate; the first N-region is located below both sides of the first trench; the N+ region is located on both sides of the first trench; the P-well region is connected below the N+ region; the P-well region and the N... The first cross-sectional area is connected to the sidewalls of the first trench; the second trench is located at the bottom of the first trench; the gate is embedded in the first trench; the source is embedded in the second trench; the gate is located on both sides of the source; an oxide layer is disposed in the first and second trenches, enclosing the gate and the source; the first cross-sectional area also includes: a P-region located below the first trench, the P-region being on the same layer as the first N-region; the second trench extends into the interior of the P-region; the third cross-sectional area also includes: a P-region located below the first trench, the P-region being connected to the bottom of the first trench; the second trench penetrates through the P-region. This embodiment of the invention utilizes the electric field shielding effect of the P-region located at the bottom and corners of the second trench in the first cross-sectional area, and the electric field shielding effect of the P-region located at the bottom of the first trench in the third cross-sectional area, thereby avoiding device damage caused by a strong electric field at the trench corners, and improving the reliability of the device. Attached Figure Description

[0061] Figure 1 This is a three-dimensional structural diagram of a trench MOSFET device according to an embodiment of the present invention;

[0062] Figure 2 This is a schematic diagram of the structure of the first cross-sectional region of a trench MOSFET device according to an embodiment of the present invention;

[0063] Figure 3 This is a schematic diagram of the second cross-sectional region of a trench MOSFET device according to an embodiment of the present invention;

[0064] Figure 4 This is a schematic diagram of the third cross-sectional region of a trench MOSFET device according to an embodiment of the present invention;

[0065] Figure 5 This is a flowchart illustrating the steps of a method for manufacturing a trench MOSFET device according to an embodiment of the present invention;

[0066] Figure 6 This is a schematic diagram of the structure of a trench MOSFET device manufactured according to an embodiment of the present invention;

[0067] Figure 7 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0068] Figure 8 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0069] Figure 9 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0070] Figure 10 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0071] Figure 11 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0072] Figure 12 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0073] Figure 13 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0074] Figure 14 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0075] Figure 15 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0076] Figure 16This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0077] Figure 17 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0078] Figure 18 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0079] Figure 19 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0080] Figure 20 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0081] Figure 21 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention;

[0082] Figure 22 This is a schematic diagram of another trench MOSFET device fabrication according to an embodiment of the present invention.

[0083] Reference numerals: First cross-sectional region 10, Second cross-sectional region 20, Third cross-sectional region 30, N-type substrate 101, Epitaxial layer 102, First trench 103, Oxide layer 104, First N region 105, P-well region 106, N+ region 107, Second trench 108, Gate 109, Source 110, P region 111, P+ region 112, Second N region 113, Interlayer dielectric passivation layer 114, First metal layer 115, Second metal layer 116, Drain 117. Detailed Implementation

[0084] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0085] Silicon carbide (SiC), with its superior physical and electrical properties such as high electron saturation drift velocity, high critical breakdown electric field, wide bandgap, and excellent thermal conductivity, has become an ideal material for high-temperature and high-voltage power electronics. Within the family of vertical MOSFET devices, double-injection planar gate and trench gate types each have their advantages. 4H-SiC UMOSFETs, with their higher-density cell structure and high mobility imparted by the non-polar surface, not only achieve a significant reduction in on-resistance but also a substantial increase in channel density. These unique advantages broaden the application prospects of 4H-SiC UMOSFETs in power electronics, indicating their important role in driving the advancement of power electronics technology.

[0086] Silicon carbide (SiC) exhibits significant advantages in high-frequency applications due to its superior physical and electrical properties, such as high electron saturation drift velocity, high thermal conductivity, and high breakdown electric field. These properties not only enhance device performance but also enable stable operation in high-temperature and high-power environments. However, under high breakdown electric field conditions, the electric field strength experienced by the gate dielectric is much higher than under normal operating conditions, which can easily lead to dielectric breakdown, damage, or degradation, resulting in lower gate dielectric reliability. Moreover, because SiC MOSFETs have a high switching speed, they are highly susceptible to external circuit interference and have poor anti-interference capabilities.

[0087] One of the core concepts of this invention is that the electric field shielding effect of the P-region located at the bottom and corner of the second trench in the first cross-section area, and the electric field shielding effect of the P-region located at the bottom of the first trench in the third cross-section area, can prevent the device from being damaged by a strong electric field at the corner of the trench, thereby improving the reliability of the device.

[0088] Reference Figure 1 The diagram shows a three-dimensional structural view of a trench MOSFET device according to an embodiment of the present invention, which may specifically include the following structure:

[0089] The first section region 10, the second section region 20, and the third section region 30 are arranged alternately along the first direction.

[0090] The first cross-sectional region 10, the second cross-sectional region 20 and the third cross-sectional region 30 each include: an N-type substrate 101, an epitaxial layer 102, a first trench 103, an oxide layer 104, a first N region 105, a P-well region 106, an N+ region 107, a second trench 108, a gate 109 and a source 110.

[0091] The epitaxial layer is disposed on one side of the N-type substrate 101; the first N-region 105 is located below both sides of the first trench 103.

[0092] The N+ region 107 is located on both sides of the first trench 103.

[0093] The P-well region 106 is connected below the N+ region 107; the P-well region 106 and the N+ region 107 are respectively connected to the sidewall of the first trench 103.

[0094] The second groove 108 is located at the bottom of the first groove 103.

[0095] The gate 109 is embedded in the first trench 103; the source 110 is embedded in the second trench 108; the gate 109 is located on both sides of the source 110.

[0096] The oxide layer 104 is disposed in the first trench 103 and the second trench 108, and encapsulates the gate 109 and the source 110.

[0097] The first cross-sectional area 10 further includes: a P area 111 located below the first trench 103, the P area 111 and the first N area being located in the same layer 105; the second trench 108 extends into the interior of the P area 111.

[0098] The third cross-sectional area 30 further includes: a P area 111 located below the first groove 103, the P area 111 being connected to the bottom of the first groove 103; the second groove 108 penetrating the P area.

[0099] In the first cross-sectional region 10, a gate 109 and a source 110 are fabricated through multi-level trenches. The gate 109 is polysilicon connected to the gate, and the source 110 is polysilicon connected to the source. By depositing a thick oxide layer 104 below and on both sides of the source 110, Cgs (gate-source capacitance) is increased, Cgd (gate-drain capacitance) is decreased, the Cgd / Ciss ratio is reduced, the dv / dt handling capability during switching is improved, and the switching stability of the device is improved.

[0100] Cgd / Ciss is an important parameter ratio used to describe the parasitic capacitance characteristics of a MOSFET, especially its performance related to the Miller effect. Cgd / Ciss: the ratio of gate-drain capacitance to input capacitance, reflecting the proportion of Cgd in the total input capacitance. The Miller effect refers to the phenomenon that during MOSFET switching, due to the presence of Cgd, changes in drain voltage are fed back to the gate through Cgd, causing gate voltage oscillations or delays. A larger Cgd / Ciss value indicates a more pronounced Miller effect and poorer stability of the gate drive circuit. A larger Cgd / Ciss value also results in slower MOSFET switching speed and higher dynamic power consumption. In high-frequency applications, a smaller Cgd / Ciss value helps improve switching speed and efficiency.

[0101] In the first cross-sectional region 10, the P-region 111 is located below and at the corner of the second trench 108, which can act as an electric field shield, preventing the generation of a strong electric field at the corner of the second trench 108 and thus avoiding damage to the chip. Furthermore, the JFET (Junction Field-Effect Transistor) structure formed between the P-regions 111 in the two cell structures has a relatively high resistance, while the first N-region 105, with its deep implantation of N-type ions, can effectively reduce the resistance at that location, thereby reducing the resistance value in the current conduction path. Figure 1 It embodies two cells, and the two cells have the same structure.

[0102] JFET is an abbreviation for Junction Field-Effect Transistor, a type of field-effect transistor based on a PN junction. Unlike MOSFETs, JFETs control the current by adjusting the resistance of the conductive channel through the depletion layer width of the PN junction. The basic structure of a FET includes the following parts: Channel, the core of the JFET, made of N-type or P-type semiconductor materials; Gate, which forms a PN junction with the channel; For N-channel JFETs, the gate is made of P-type material; for P-channel JFETs, the gate is made of N-type material. The conductivity of the channel is controlled by reverse bias (the PN junction is in a reverse bias state); Source, the current input terminal, usually connected to the low end of the channel; Drain, the current output terminal, usually connected to the high end of the channel; and PN junction, the PN junction between the gate and the channel, which is crucial for the operation of the JFET. By changing the gate voltage, the depletion layer width of the PN junction can be adjusted, thereby controlling the conductivity of the channel.

[0103] In the third section region 10, the P region 111 is located below the first trench 103 and above the bottom of the second trench 108, which can better shield the electric field at the bottom corner of the first trench 103.

[0104] An embodiment of the present invention provides a trench MOSFET device, the device comprising a first cross-sectional region, a second cross-sectional region, and a third cross-sectional region alternately arranged along a first direction; each of the first, second, and third cross-sectional regions comprises: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N-region, a P-well region, an N+ region, a second trench, a gate, and a source; the epitaxial layer is disposed on one side of the N-type substrate; the first N-region is located below both sides of the first trench; the N+ region is located on both sides of the first trench; the P-well region is connected below the N+ region; the P-well region and the N+ region are respectively connected to the first trench. The first cross-sectional area includes: a P-region located below the first trench; a source electrode located in the second trench; a gate electrode located on both sides of the source electrode; an oxide layer disposed in the first trench and the second trench, enclosing the gate electrode and the source electrode; the first cross-sectional area further includes: a P-region located below the first trench, the P-region being on the same layer as the first N-region; the second trench extending into the interior of the P-region; the third cross-sectional area further includes: a P-region located below the first trench, the P-region being connected to the bottom of the first trench; the second trench penetrating the P-region. This embodiment of the invention utilizes the electric field shielding effect of the P-region located at the bottom and corners of the second trench in the first cross-sectional area, and the electric field shielding effect of the P-region located at the bottom of the first trench in the third cross-sectional area, thereby avoiding device damage caused by a strong electric field at the trench corners and improving device reliability.

[0105] Reference Figures 2-4 In this embodiment of the invention, the device further includes:

[0106] Both the first cross-sectional area 10 and the third cross-sectional area 30 further include: P+ regions 112 disposed on both sides of the first trench 103 within the epitaxial layer 102, wherein the P+ regions 112 are located in the same layer as the N+ regions 107 and are connected to the N+ regions 107.

[0107] The second cross-sectional area further includes: a second N region 113 disposed on both sides of the first trench 103 within the epitaxial layer 102, the depth of the second N region 113 extending to connect with the first N region 105, and the second N region 113 connecting with the N+ region 107 and the P-well region 106.

[0108] In the second cross-sectional region, the depth of the second N region 113 extends to connect with the first N region 105, forming a Schottky contact at the parasitic diode of the MOSFET, which has a small on-resistance.

[0109] In the third cross-sectional region, the gate 109 is a polysilicon connected to the gate, and the polysilicon on both sides is connected together through the top polysilicon.

[0110] In this embodiment of the invention, the device further includes:

[0111] An interlayer dielectric passivation layer 114 is provided on the surface of the epitaxial layer 102.

[0112] Contact holes are provided on both sides of the interlayer dielectric passivation layer 114.

[0113] A first metal layer 115 is disposed on the surface of the contact hole; the first metal layer 115 is in contact with a portion of the P+ region 112 and the N+ region 107.

[0114] A second metal layer 116 is disposed on the surface 114 of the first metal 115 and the interlayer dielectric passivation layer.

[0115] In this embodiment of the invention, the device further includes a drain 117 located on the other side of the N-type substrate 101.

[0116] Reference Figure 5 This invention illustrates a method for manufacturing a trench MOSFET device, as described above, in an embodiment of the invention. The method includes:

[0117] Step 201: Provide an N-type substrate.

[0118] Step 202: An epitaxial layer is grown on one side of the N-type substrate.

[0119] Step 203: Etch a first trench on the epitaxial layer.

[0120] Step 204: An oxide layer is grown on the surface of the epitaxial layer.

[0121] Step 205: N-type ions are implanted in the epitaxial layer below the sides of the first trench to form a first N region; the first N region is located below the sides of the first trench.

[0122] Step 206: P-type ions are implanted in the epitaxial layer to form a P-well region on both sides of the first trench, and N-type ions are implanted to form an N+ region; the P-well region is connected below the N+ region; the P-well region and the N+ region are respectively connected to the sidewall of the first trench.

[0123] Step 207: Etch a second trench at the bottom of the first trench.

[0124] Step 208: A gate electrode is formed in the first trench and a source electrode is formed in the second trench. The gate electrode is located on both sides of the source electrode, and an oxide layer is formed around the gate electrode and the source electrode.

[0125] Step 209: In the first cross-sectional area, when N-type ions are injected below the first trench on both sides of the epitaxial layer to form a first N region, P-type ions are injected below the first trench in the epitaxial layer to form a P region; the first N region and the P region are located in the same layer.

[0126] Step 210: In the third cross-sectional area, when N-type ions are injected below the first trench on both sides of the epitaxial layer to form a first N region, P-type ions are injected below the first trench in the epitaxial layer to form a P region; the P region is connected to the bottom of the first trench.

[0127] Specifically, the N-type substrate 101 and the epitaxial layer 102 are made of SiC material, as shown in the reference. Figure 6 An epitaxial layer 102 is grown on one side of an N-type substrate 101; (Refer to...) Figure 7 The first trench 103 is etched on the epitaxial layer 102, and an oxide layer is grown on the surface of the epitaxial layer 102; (Refer to...) Figure 8 Deep implantation is performed, and N-type ions are implanted in the epitaxial layer 102 below the sides of the first trench 103 to form a first N-region 105. The first N-region 105 is located below the sides of the first trench 103. (Refer to...) Figure 9 Near-surface implantation is performed, where P-type ions are implanted into the epitaxial layer 102 corresponding to both sides of the first trench 103 to form a P-well region 106, and N-type ions are implanted to form an N+ region 107. The P-well region 106 is connected below the N+ region 107, and the P-well region 106 and the N+ region 107 are respectively connected to the sidewalls of the first trench 103; (Refer to...) Figure 10 A second trench 108 is etched at the bottom of the first trench 103; refer to Figure 11 A gate electrode 109 is formed in the first trench 103, and a source electrode 110 is formed in the second trench 108. The gate electrode 109 is located on both sides of the source electrode 110, and an oxide layer 104 is formed around the gate electrode 109 and the source electrode 110; (Refer to...) Figure 9 In the first cross-sectional region 10, when N-type ions are implanted below the first trench 103 in the epitaxial layer 102 to form a first N-region 105, P-type ions are implanted below the first trench 103 in the epitaxial layer 102 to form a P-region 111. The P-region 111 of the third cross-sectional region 30 is shallower than the P-region 111 of the first cross-sectional region 10. The first N-region 105 and the P-region 111 are located in the same layer. (Refer to...) Figure 12In the third cross-sectional region 30, when N-type ions are injected below the first trench 103 on both sides of the epitaxial layer 102 to form a first N region 105, P-type ions are injected below the first trench 103 in the epitaxial layer 102 to form a P region 111; the P region 111 is connected to the bottom of the first trench 103.

[0128] An embodiment of the present invention provides a trench MOSFET device, the device comprising a first cross-sectional region, a second cross-sectional region, and a third cross-sectional region alternately arranged along a first direction; each of the first, second, and third cross-sectional regions comprises: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N-region, a P-well region, an N+ region, a second trench, a gate, and a source; the epitaxial layer is disposed on one side of the N-type substrate; the first N-region is located below both sides of the first trench; the N+ region is located on both sides of the first trench; the P-well region is connected below the N+ region; the P-well region and the N+ region are respectively connected to the first trench. The first cross-sectional area includes: a P-region located below the first trench; a source electrode located in the second trench; a gate electrode located on both sides of the source electrode; an oxide layer disposed in the first trench and the second trench, enclosing the gate electrode and the source electrode; the first cross-sectional area further includes: a P-region located below the first trench, the P-region being on the same layer as the first N-region; the second trench extending into the interior of the P-region; the third cross-sectional area further includes: a P-region located below the first trench, the P-region being connected to the bottom of the first trench; the second trench penetrating the P-region. This embodiment of the invention utilizes the electric field shielding effect of the P-region located at the bottom and corners of the second trench in the first cross-sectional area, and the electric field shielding effect of the P-region located at the bottom of the first trench in the third cross-sectional area, thereby avoiding device damage caused by a strong electric field at the trench corners and improving device reliability.

[0129] In this embodiment of the invention, the method further includes:

[0130] Reference Figure 9 When P-type ions are implanted in the epitaxial layer 102 to form a P-well region 106 corresponding to both sides of the first trench 103, and N-type ions are implanted to form an N+ region 107, i.e., during near-surface implantation, P-type ions are implanted in the epitaxial layer 102 to form a P+ region 112 corresponding to both sides of the first trench 103. The P+ region 112 and the N+ region 107 are located in the same layer and are connected to the N+ region 107. The near-surface implantation of the first cross-sectional region 10 and the third cross-sectional region 30 is the same, both forming P-well regions 106, P+ regions 112 and N+ regions 107 in the same position.

[0131] Reference Figure 13Within the second cross-sectional region 20, P-type ions are injected into the epitaxial layer 102 corresponding to both sides of the first trench 103 to form a P-well region 106, and N-type ions are injected to form an N+ region 107. N-type ions are then injected into the epitaxial layer 102 corresponding to both sides of the first trench 103, with the injection depth reaching the first N region 105 to form a second N region 113. The second N region 113 is connected to the N+ region 112 and the P-well region 106.

[0132] In this embodiment of the invention, the formation of a gate 109 in the first trench 103 and a source 110 in the second trench 108, wherein the gate 109 is located on both sides of the source 110, and an oxide layer 104 is formed around the gate 109 and the source 110, includes:

[0133] Reference Figure 10 The oxide layer on the surface of the epitaxial layer 102 is removed, and a gate oxide layer 104 is grown on the surface of the first trench 103 and the second trench 108.

[0134] Reference Figure 14 Polysilicon is deposited on the surface of the epitaxial layer 102 to deposit polysilicon in the first trench 103 and the second trench 108.

[0135] Reference Figure 15 The polysilicon on the surface of the epitaxial layer 102 is etched, and the polysilicon on both sides of the first trench 103 is retained as the gate 109.

[0136] Reference Figure 15 An oxide layer 104 is grown in the first trench 103 and the second trench 108; the oxide layer 104 in the first trench 103 and the second trench 108 is etched to form a groove in the oxide layer 104, and the oxide layer covering the gate 109 and the surface of the second trench 108 is retained.

[0137] Reference Figure 17 Polysilicon is deposited in the groove as a source 110; an oxide layer 104 is formed around the gate 109 and the source 110.

[0138] In this embodiment of the invention, forming an oxide layer 104 around the gate 109 and the source 110 includes:

[0139] An oxide layer 104 is grown in the first cross-sectional area 10, in the first trench 103 and the second trench 108;

[0140] Reference Figure 18In the second cross-sectional area 20, an oxide layer 104 is grown in the first trench 103 and the second trench 108, and the oxide layer 104 on the surface of the source electrode 110 is removed.

[0141] Reference Figure 19 Within the third cross-sectional region 30, an oxide layer 104 is grown in the first trench 103 and the second trench 108, and polysilicon is deposited on the surface of the epitaxial layer 102 so that the gates 109 on both sides of the first trench 103 are connected through the polysilicon, and the polysilicon on the surface of the epitaxial layer 102 other than the first trench 103 and the second trench 108 is removed.

[0142] In this embodiment of the invention, the method further includes:

[0143] Reference Figure 20 An insulating material is deposited on the surface of the epitaxial layer 102 to form an interlayer dielectric passivation layer 114; the interlayer dielectric passivation layer above the N+ region and above the P+ region is removed to form a contact hole.

[0144] Reference Figure 21 A first metal layer 115 is deposited on the surface of the contact hole; a second metal layer 116 is deposited on the surfaces of the first metal layer 115 and the interlayer dielectric passivation layer 114.

[0145] In this embodiment of the invention, the method further includes:

[0146] Reference Figure 22 Thinning is performed on the other side of the N-type substrate 101;

[0147] Metal is deposited on the other side of the N-type substrate 101 as a drain electrode 117.

[0148] In this embodiment of the invention, the first cross-sectional region 10 is fabricated as polysilicon connected to the gate and polysilicon connected to the source through multi-level trenches. A thick oxide layer is deposited below and on both sides of the polysilicon connected to the source, thereby increasing Cgs, decreasing Cgd, lowering the Cgd / Ciss ratio, improving the dv / dt handling capability during switching, and improving the switching stability of the device. Moreover, the P-region 111 deeply implanted in the first cross-sectional region 10 is located below the second trench 108, which can play an electric field shielding role, avoiding the generation of a strong electric field at the corner of the second trench 108 (the weak point of the chip structure) and preventing damage to the chip.

[0149] In the second cross-section region 20, the polysilicon is connected to the source metal on the front side. At the same time, during deep implantation, P-type ion implantation is not performed, but N-type ion implantation is performed during near-surface implantation and is connected to the N-type ion region during deep implantation, so that a Schottky contact is formed at the parasitic diode of the MOSFET, which has a small on-resistance.

[0150] In the third cross-section region 30, the polysilicon on both sides is connected together through the top and eventually connected to the gate. At the same time, the P-type ions during deep implantation are located below the bottom of the first trench 103 and above the bottom of the second trench 108, which can better shield the electric field at the bottom corner of the first trench 103.

[0151] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0152] This invention provides a chip including the trench MOSFET device described above.

[0153] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0154] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0155] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0156] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0157] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0158] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0159] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0160] The trench MOSFET device, manufacturing method, and chip provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A trench MOSFET device, characterized in that, The device includes a first cross-sectional region, a second cross-sectional region, and a third cross-sectional region arranged alternately along a first direction; The first cross-sectional region, the second cross-sectional region, and the third cross-sectional region each include: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N-region, a P-well region, an N+ region, a second trench, a gate, and a source. The epitaxial layer is disposed on one side of the N-type substrate; the first N-region is located below both sides of the first trench; The N+ region is located on both sides of the first trench; The P-well region is connected below the N+ region; the P-well region and the N+ region are respectively connected to the sidewall of the first trench; The second trench is located at the bottom of the first trench; The gate electrode is embedded in the first trench; the source electrode is embedded in the second trench; the gate electrode is located on both sides of the source electrode; The oxide layer is disposed in the first trench and the second trench, and encapsulates the gate and the source. The first cross-sectional area further includes: a P region located below the first trench, the P region being located on the same layer as the first N region; the second trench extends into the interior of the P region; The third cross-sectional area further includes: a P region located below the first trench, the P region being connected to the bottom of the first trench; the second trench penetrating the P region.

2. The trench MOSFET device according to claim 1, characterized in that, The device also includes: Both the first cross-sectional area and the third cross-sectional area further include: P+ regions disposed on both sides of the first trench within the epitaxial layer, wherein the P+ regions are located in the same layer as the N+ regions and are connected to the N+ regions; The second cross-sectional region further includes: a second N region disposed on both sides of the first trench within the epitaxial layer, the depth of the second N region extending to connect with the first N region, and the second N region connecting with the N+ region and the P-well region.

3. The trench MOSFET device according to claim 2, characterized in that, The device also includes: An interlayer dielectric passivation layer is provided on the surface of the epitaxial layer; Contact holes are provided on both sides of the interlayer dielectric passivation layer; A first metal layer is disposed on the surface of the contact hole; the first metal layer is in contact with a portion of the P+ region and the N+ region; A second metal layer is disposed on the surface of the first metal and the interlayer dielectric passivation layer.

4. The trench MOSFET device according to claim 1, characterized in that, The device also includes a drain located on the other side of the N-type substrate.

5. A method for manufacturing a trench MOSFET device, characterized in that, The method for manufacturing a trench MOSFET device as described in any one of claims 1 to 4 comprises: Provide N-type substrates; An epitaxial layer is grown on one side of the N-type substrate; A first trench is etched on the epitaxial layer; An oxide layer is grown on the surface of the epitaxial layer; N-type ions are implanted below the sides of the first trench in the epitaxial layer to form a first N region; the first N region is located below the sides of the first trench. P-type ions are implanted in the epitaxial layer to form a P-well region on both sides of the first trench, and N-type ions are implanted to form an N+ region; the P-well region is connected to the bottom of the N+ region; the P-well region and the N+ region are respectively connected to the sidewall of the first trench. A second trench is etched at the bottom of the first trench; A gate electrode is formed in the first trench, and a source electrode is formed in the second trench. The gate electrode is located on both sides of the source electrode, and an oxide layer is formed around the gate electrode and the source electrode. Within the first cross-sectional area, when N-type ions are implanted below the first trench in the epitaxial layer to form a first N region, P-type ions are implanted below the first trench in the epitaxial layer to form a P region; the first N region and the P region are located in the same layer. In the third cross-sectional area, when N-type ions are injected below the first trench on both sides of the epitaxial layer to form a first N region, P-type ions are injected below the first trench in the epitaxial layer to form a P region; the P region is connected to the bottom of the first trench.

6. The method for manufacturing a trench MOSFET device according to claim 5, characterized in that, The method further includes: When P-type ions are implanted in the epitaxial layer to form a P-well region on both sides of the first trench, and N-type ions are implanted to form an N+ region, P-type ions are implanted in the epitaxial layer to form a P+ region on both sides of the first trench. The P+ region and the N+ region are located in the same layer and are connected to the N+ region. Within the second cross-sectional region, P-type ions are injected into the epitaxial layer corresponding to both sides of the first trench to form a P-well region. When N-type ions are injected to form an N+ region, N-type ions are injected into the epitaxial layer corresponding to both sides of the first trench, with the injection depth reaching the first N region to form a second N region. The second N region is connected to the N+ region and the P-well region.

7. The method for manufacturing the trench MOSFET device according to claim 5, characterized in that, The step of forming a gate electrode in the first trench and a source electrode in the second trench, wherein the gate electrode is located on both sides of the source electrode, and an oxide layer is formed around the gate electrode and the source electrode, includes: Remove the oxide layer from the surface of the epitaxial layer, and grow a gate oxide layer on the surface of the first trench and the second trench; Polysilicon is deposited on the surface of the epitaxial layer to deposit polysilicon in the first trench and the second trench; The polysilicon on the surface of the epitaxial layer is etched, and the polysilicon on both sides of the first trench is retained as the gate. An oxide layer is grown in the first trench and the second trench; The oxide layer in the first trench and the second trench is etched to form a groove in the oxide layer, while retaining the oxide layer covering the gate and the surface of the second trench; Polycrystalline silicon is deposited in the groove as a source electrode; An oxide layer is formed around the gate and the source.

8. The method for manufacturing a trench MOSFET device according to claim 7, characterized in that, The formation of an oxide layer around the gate and the source includes: An oxide layer is grown in the first cross-sectional area, in the first trench and the second trench; Within the second cross-sectional area, an oxide layer is grown in the first trench and the second trench, and the oxide layer on the surface of the source electrode is removed; Within the third cross-sectional region, an oxide layer is grown in the first trench and the second trench, and polysilicon is deposited on the surface of the epitaxial layer so that the gates on both sides of the first trench are connected through the polysilicon, and the polysilicon on the surface of the epitaxial layer other than the first trench and the second trench is removed.

9. The method for manufacturing a trench MOSFET device according to claim 6, characterized in that, The method further includes: An insulating material is deposited on the surface of the epitaxial layer to form an interlayer dielectric passivation layer; Remove the interlayer dielectric passivation layer above a portion of the N+ region and above the P+ region to create a contact hole. A first metal layer is deposited on the surface of the contact hole; A second metal layer is deposited on the surface of the first metal and the interlayer dielectric passivation layer.

10. The method for manufacturing a trench MOSFET device according to claim 5, characterized in that, The method further includes: Thinning is performed on the other side of the N-type substrate; Metal is deposited on the other side of the N-type substrate as a drain electrode.

11. A chip, characterized in that, Including the trench MOSFET device as described in any one of claims 1 to 4 above.

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