Gallium nitride groove type MOSFET device and preparation method thereof

Abstract

The invention discloses a gallium nitride groove type MOSFET device and a preparation method thereof, and belongs to the field of semiconductor devices. The device comprises a substrate, an epitaxial structure formed on a first surface of the substrate, a gate dielectric layer formed on the epitaxial structure, a source electrode, a gate electrode and a drain electrode, the epitaxial structure comprises an n-GaN drift layer, a C-doped high-resistance GaN layer and an n +-GaN layer which are sequentially formed on the first surface of the substrate, the C-doped high-resistance GaN layer is located between the n-GaN drift layer and the n +-GaN layer, and the n +-GaN layer is located between the gate dielectric layer and the n +-GaN layer. And a high-resistance current blocking layer. The preparation method comprises the following steps: sequentially growing an n-GaN drift layer, a C-doped high-resistance GaN layer and an n +-GaN layer on a first surface of a substrate to form an epitaxial structure; forming a gate dielectric layer on the epitaxial structure; and forming a grid electrode, a source electrode and a drain electrode. Compared with the prior art, the C-doped high-resistance GaN layer is adopted to replace the Mg-doped p-GaN layer, preparation and activation of the p-GaN layer in a traditional method are avoided, and the vertical voltage endurance capability and the leakage current suppression capability of the device are effectively improved.

Description

A gallium nitride trench MOSFET device and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a gallium nitride trench MOSFET device and its fabrication method. Background Technology

[0002] In the field of power semiconductor devices, gallium nitride (GaN)-based devices have attracted widespread attention and made significant progress due to their excellent material properties, such as high electron mobility, high breakdown electric field, and high electron saturation velocity. GaN-based devices have shown great application potential in high-efficiency power conversion, radio frequency communication, and electric vehicles, becoming one of the characteristics of current semiconductor technology research. Currently, the closest existing technology to the technical solution of this patent application is GaN-based trench metal-oxide-semiconductor field-effect transistor (MOSFET) devices. These devices typically use metal-organic chemical vapor deposition (MOCVD) technology to grow epitaxial layers, and their typical structure is like the common MOCVD-based GaN trench MOSFET structure, generally including a substrate, a nucleation layer, a buffer layer, and an n... - -GaN layer, n + The structure consists of a GaN layer, a p-GaN layer, and the formed trench structure, gate, source, and drain. The main structural principle of existing products is based on a trench conduction mechanism: through etching processes, the n-GaN layer... + -GaN source contact layer, n - -Gate trench structures are formed in regions such as GaN drift layer and p-GaN layer. Insulating dielectric layers, such as high-resistivity oxide or nitride layers, are grown on the sidewalls and bottom of the trench. Then, metal material is filled in situ in the trench to form the gate. Typical forward and reverse mechanisms are formed by different gate metal voltages. Field effect modulation is performed by the gate voltage to control the formation of the channel at the sidewall of the trench.

[0003] Therefore, current products and structures all encounter problems related to the fabrication methods of MOCVD epitaxial p-GaN layers and the passivation and activation of carriers in the epitaxial p-GaN layers. Furthermore, issues also arise in the top n... + -The phenomenon of Mg enrichment and tailing in GaN. p-GaN layers typically achieve p-type conductivity through Mg doping, but in subsequent processes, regardless of whether the p-GaN layer has been activated, when n-type Mg is regrown... + When p-GaN layers are added, the problem of Mg re-passivation always occurs. Furthermore, due to the re-growth of n-GaN layers on top of the p-GaN layer... + In GaN, increasing the temperature also causes Mg to diffuse into n. +In GaN, the p-GaN layer is difficult to activate effectively, making it hard for p-GaN-based device designs to achieve expected performance, increasing process complexity and cost, and reducing product yield and reliability. Furthermore, most GaN epitaxial layer growth uses MOCVD technology, which is expensive and requires significant investment. Moreover, MOCVD technology has a relatively slow growth rate and long production cycle, resulting in low production efficiency and high production costs for GaN epitaxial wafers. Under the demand for large-scale production, this high-cost, low-efficiency production method severely restricts the market promotion and application of GaN-based devices.

[0004] In summary, existing GaN trench MOSFET devices have significant shortcomings in terms of p-GaN layer fabrication and activation, as well as epitaxial growth cost and efficiency.

[0005] Therefore, there is an urgent need for a gallium nitride trench MOSFET device and its fabrication method that can solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to provide a gallium nitride trench MOSFET device and its fabrication method, so as to solve the obvious shortcomings of existing GaN trench MOSFET devices in terms of p-GaN layer fabrication and activation, as well as epitaxial growth cost and efficiency.

[0007] To achieve the above objectives, the present invention provides a gallium nitride trench MOSFET device, comprising a substrate, an epitaxial structure formed on a first surface of the substrate, a gate dielectric layer formed on the epitaxial structure, a source connected to the epitaxial structure, a gate located on the surface of the gate dielectric layer, and a drain connected to the substrate, wherein the epitaxial structure includes n... - -GaN drift layer, formed on the n - - A C-doped high-resistivity GaN layer on the GaN drift layer and n formed on the C-doped high-resistivity GaN layer + -GaN layer, the C-doped high-resistivity GaN layer is located in the n - -GaN drift layer and the n + Between the GaN layers, a high-resistance current-blocking layer is used to isolate the n... - -GaN drift layer and the n + -GaN layer.

[0008] Preferably, from the n + -The top surface of the GaN layer is recessed inward to form an extension to the n -- A mesa structure and trenches for the GaN drift layer, wherein the gate dielectric layer is formed on the outer surface of the mesa structure and the trench walls, and a through-hole is formed from the gate dielectric layer inwards through the gate dielectric layer and the n + - A GaN layer extending into a trench in the C-doped high-resistivity GaN layer, the trench being filled with body metal, the source being located on and electrically connected to the body metal, the gate being formed in the trench and connected to the gate dielectric layer, and the drain being formed on a second surface of the substrate away from the epitaxial structure.

[0009] Preferably, the substrate includes n + -GaN substrate, the n - -GaN drift layer is formed on the n + -On the GaN substrate, the n + The GaN substrate is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 18 cm -3 High doping concentration ensures good conductivity of the substrate, providing stable physical support and current path for the device.

[0010] Preferably, the n - The GaN drift layer is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 16 cm -3 The n + The GaN layer is doped with Si, with a doping concentration of 1–5 × 10⁻⁶. 18 cm -3 High doping characteristics can reduce source contact resistance and improve current transmission efficiency.

[0011] Preferably, the doping concentration of the C-doped high-resistivity GaN layer is 1 to 9 × 10⁻⁶. 18 cm -3 The thickness ranges from 400 to 1000 nm. High resistivity is achieved through carbon doping, enabling current blocking and electric field modulation functions.

[0012] Preferably, the n - The thickness of the GaN drift layer is 20 μm, the thickness of the C-doped high-resistivity GaN layer is 400 nm, and the n + The thickness of the GaN layer is 200 nm. The thickness of the C-doped high-resistivity GaN layer must be equal to the thickness of the n-doped layer. - The thickness of the GaN drift layer is scientifically proportioned. If it is too thin, the current blocking ability will be insufficient, and if it is too thick, the on-resistance of the device will be increased. In practical applications, it needs to be dynamically adjusted according to the target withstand voltage level.

[0013] To achieve the above objectives, the present invention also provides a method for fabricating a gallium nitride trench MOSFET device, comprising: growing n on a first surface of a substrate. - -GaN drift layer; in the n - A C-doped high-resistivity GaN layer is grown on the GaN drift layer; an n-doped high-resistivity GaN layer is grown on the C-doped high-resistivity GaN layer. + -GaN layer to form n - -GaN drift layer, C-doped high-resistivity GaN layer and n + - An epitaxial structure of a GaN layer; a gate dielectric layer is formed on the epitaxial structure; a source electrode connected to the epitaxial structure, a gate electrode located on the surface of the gate dielectric layer, and a drain electrode connected to the substrate are formed.

[0014] Preferably, the substrate includes n + -GaN substrate, the n - -GaN drift layer is grown on the n + -On the GaN substrate, the n + The GaN substrate is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 18 cm -3 .

[0015] Preferably, the n - The GaN drift layer is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 16 cm -3 The n + The GaN layer is doped with Si, with a doping concentration of 1–5 × 10⁻⁶. 18 cm -3 .

[0016] Preferably, the doping material of the C-doped high-resistivity GaN layer is C, and the doping concentration is 1 to 9 × 10⁻⁶. 18 cm -3 The thickness is 400–1000 nm. By adjusting parameters such as the doping concentration and thickness of the C-GaN layer, this invention can also adjust the threshold voltage of the device to a certain extent, enabling the device to better meet the needs of different application scenarios and improving the overall performance and applicability of the device.

[0017] Preferably, the n - -GaN drift layer, C-doped high-resistivity GaN layer and n +All GaN layers are grown using the HVPE process. Traditional methods use Mg-doped p-GaN layers as current-blocking layers. However, due to the presence of hydrogen in the HVPE growth environment, the p-GaN layer forms a Mg-H complex with Mg during growth, causing acceptor passivation. Furthermore, the residual effect of Mg in the HVPE system is significant, leading to unnecessary Mg contamination in subsequent n-type layers and affecting device performance. Therefore, MOCVD is used to grow Mg-doped p-GaN layers. This invention selects a C-doped high-resistivity GaN layer as the current-blocking layer, thus enabling the full HVPE process for epitaxial layer growth. This invention uses full HVPE technology to grow epitaxial layers, offering advantages such as fast growth rates and relatively low equipment costs. Compared to the current mainstream metal-organic chemical vapor deposition (MOCVD) technology, it can significantly shorten the production cycle and reduce the production cost of gallium nitride epitaxial wafers. This is of great significance for achieving large-scale production and promoting the widespread application of gallium nitride devices in the market.

[0018] Preferably, forming a gate dielectric layer on the epitaxial structure includes: on n + - The GaN layer is etched on the side away from the substrate to form an extension extending to the n - -Mesa structure of GaN drift layer; in n + -Etching on the GaN layer forms an extension to the n - -Groove of GaN drift layer; in n + -Etching on the GaN layer forms a penetration through the n + - GaN layer, metal contact hole extending to the C-doped high-resistivity GaN layer; grow a gate dielectric layer on the etched epitaxial structure so that the gate dielectric layer covers the outer surface of the mesa structure and the trench wall.

[0019] Preferably, forming a source connected to the epitaxial structure, a gate located on the surface of the gate dielectric layer, and a drain connected to the substrate includes: forming a contact hole opening from the gate dielectric layer at a position corresponding to the source to form a trench extending to the C-doped high-resistivity GaN layer; fabricating a body metal within the trench; fabricating a source protruding onto the gate dielectric layer on the body metal, the source being electrically connected to the body metal; fabricating a drain on a second surface of the substrate away from the epitaxial structure; and fabricating a gate within the trench.

[0020] Specifically, the via corresponding to the source location includes a hole that penetrates the gate dielectric layer and extends to the n-th electrode. + - A first trench on the upper surface of the GaN layer, and a second trench extending from the bottom of the first trench to the C-doped high-resistivity GaN layer, wherein the width of the first trench is greater than the width of the second trench.

[0021] The present invention also provides a gallium nitride trench MOSFET device, which is fabricated by the above-described method for fabricating a gallium nitride trench MOSFET device.

[0022] Compared with existing technologies, the beneficial effects of this invention are as follows: Firstly, this invention uses a C-doped high-resistivity GaN layer with semi-insulating properties as a current blocking layer, replacing the relatively low-resistivity Mg-doped p-GaN layer. Through the high-resistivity characteristics of the C-doped high-resistivity GaN layer, the electric field distribution inside the device is more uniform, avoiding localized electric field concentration. In high-voltage applications, this effectively improves the vertical withstand voltage of the device, enabling it to withstand higher operating voltages and broadening its application range in high-voltage power conversion, power transmission, and other fields. Secondly, this invention uses a C-doped high-resistivity GaN layer instead of the traditional Mg-doped p-GaN layer, avoiding many difficulties in the preparation and activation of the p-GaN layer in traditional methods. It eliminates the need to consider issues such as Mg re-passivation leading to activation difficulties and Mg tailing phenomena, simplifying the entire device fabrication process, reducing process difficulty and cost, and improving product yield and reliability. Thirdly, the high-resistivity GaN layer, as a semi-insulating layer, is located at the n... - -GaN drift layer and the n + Between GaN layers, leakage current can be effectively suppressed, power loss of the device in the off state can be reduced, and the turn-off characteristics of the device can be improved. Attached Figure Description

[0023] Figure 1 is a structural diagram of the gallium nitride trench MOSFET device provided by the present invention.

[0024] Figure 2 is a schematic diagram of the fabrication method of the gallium nitride trench MOSFET device provided by the present invention.

[0025] Figure 3 is a schematic diagram of the fabrication of the gate dielectric layer.

[0026] Figure 4 shows a schematic diagram of the fabrication of each metal electrode.

[0027] Icon: 1-substrate, 2-n - -GaN drift layer, 3-C-doped high-resistivity GaN layer, 4-n + -GaN layer, 5-Gate dielectric layer, 6-Bulk metal, 60-Second trench, 7-Source, 70-First trench, 8-Drain, 9-Gate. Detailed Implementation

[0028] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0029] Referring to Figure 1, the present invention provides a gallium nitride trench MOSFET device, including a substrate 1, an epitaxial structure formed on a first surface of the substrate 1, a gate dielectric layer 5 formed on the epitaxial structure, a source 7 connected to the epitaxial structure, a gate 9 located on the surface of the gate dielectric layer 5, and a drain 8 connected to the substrate 1. The epitaxial structure includes n... - -GaN drift layer 2, formed on the n - - A C-doped high-resistivity GaN layer 3 on GaN drift layer 2 and n formed on said C-doped high-resistivity GaN layer 3 + -GaN layer 4, the C-doped high-resistivity GaN layer 3 is located in the n - -GaN drift layer 2 and the n + Between the GaN layers 4, a high-resistance current-blocking layer is used to isolate the n... - -GaN drift layer 2 and the n + -GaN layer 4. There are two sources 7 with a spacing between them, and the gate 9 is located between two adjacent sources 7.

[0030] As shown in Figure 1, from the n + -The top surface of GaN layer 4 is recessed inward to form an extension to the n - - The GaN drift layer 2 has a mesa structure and trenches, and the gate dielectric layer 5 is formed on the outer surface of the mesa structure and the trench walls. A through-hole is formed from the gate dielectric layer 5 inwards. + -GaN layer 4 extends into a trench in the C-doped high-resistivity GaN layer 3, the trench is filled with body metal 6, the source 7 is located on the body metal 6 and electrically connected to the body metal 6, the gate 9 is formed in the trench and connected to the gate dielectric layer 5, and the drain 8 is formed on the second surface of the substrate 1 away from the epitaxial structure.

[0031] Specifically, in this embodiment, the substrate 1 is n + -GaN substrate, doped with Si, doping concentration of 2–5 × 10⁻⁶ 18 cm -3 The high doping concentration ensures good conductivity of substrate 1, providing stable physical support and current path for the device.

[0032] Specifically, in this embodiment, the n - The doping material for GaN drift layer 2 is Si, with a doping concentration of 2–5 × 10⁻⁶. 16 cm -3 The n + The doping material for GaN layer 4 is Si, with a doping concentration of 1–5 × 10⁻⁶. 18 cm-3 High doping characteristics can reduce source contact resistance and improve current transmission efficiency.

[0033] Specifically, in this embodiment, the carbon doping concentration of the C-doped high-resistivity GaN layer 3 is 1 to 9 × 10⁻⁶. 18 cm -3 The thickness ranges from 400 to 1000 nm. High resistivity is achieved through carbon doping, enabling current blocking and electric field modulation functions.

[0034] Referring to Figure 2, the present invention also provides a method for fabricating a gallium nitride trench MOSFET device, comprising: growing n on a first surface of a substrate 1. - -GaN drift layer 2; in the n - - A C-doped high-resistivity GaN layer 3 is grown on the GaN drift layer 2; n is grown on the C-doped high-resistivity GaN layer 3. + -GaN layer 4, to form n - -GaN drift layer 2, C-doped high-resistivity GaN layer 3 and n + - An epitaxial structure of GaN layer 4; a gate dielectric layer 5 is formed on the epitaxial structure; a source electrode 7 connected to the epitaxial structure, a gate electrode 9 located on the surface of the gate dielectric layer 5, and a drain electrode 8 connected to the substrate 1 are formed. There are two source electrodes 7 spaced apart, and the gate electrode 9 is located between two adjacent source electrodes 7.

[0035] In this embodiment, the substrate 1 is n + -GaN substrate, doped with Si, doping concentration of 2–5 × 10⁻⁶ 18 cm -3 The thickness of substrate 1 is 300 μm. The surface of substrate 1 needs to be treated with chemical mechanical polishing (CMP) to ensure that the roughness Ra ≤ 0.5 nm and that there are no scratches or impurities on the surface, so as to provide a flat and clean substrate for subsequent epitaxial layer growth and ensure the crystal quality of the epitaxial layer.

[0036] In this embodiment, n - The doping material for GaN drift layer 2 is Si, with a doping concentration of 2–5 × 10⁻⁶. 16 cm -3 The thickness is 10–50 μm. Specifically, the n -The GaN drift layer 2 is 20 μm thick and is grown using the HVPE process, with the growth temperature controlled between 1050 and 1150 °C. Preferably, in this embodiment, the growth temperature is 1100 °C. The gas atmosphere uses H2 as the carrier gas, NH3 as the nitrogen source, GaCl as the gallium source, and SiH4 as the dopant gas. Specifically, the flow rates of each gas during growth are: H2 (5–10 L / min), NH3 (2–4 L / min), GaCl (0.5–1 L / min), and SiH4 (1–5 sccm). - The growth rate of the GaN drift layer 2 was maintained at 5–10 μm / h, and the growth time was 2–4 h, ultimately forming a 20 μm thick drift layer. The growth process was carried out under ambient pressure (1 atm), and the carrier concentration was adjusted to 2–5 × 10⁻⁶ by precisely controlling the dopant gas flow rate. 16 cm -3 .

[0037] In this embodiment, the carbon doping concentration of the C-doped high-resistivity GaN layer 3 is 1 to 9 × 10⁻⁶. 18 cm -3 The thickness is 400–1000 nm. Preferably, in this embodiment, the thickness of the C-doped high-resistivity GaN layer 3 is 400 nm. The C-doped high-resistivity GaN layer 3 is grown using the HVPE process at a growth temperature of 1000–1100 °C, with a preferred temperature of 1050 °C in this embodiment. The gas atmosphere uses H2 as the carrier gas, NH3 as the nitrogen source, GaCl as the gallium source, and CH4 as the carbon doping source; specifically, the gas flow rates during growth are set as follows: H2 (5–8 L / min), NH3 (1.5–3 L / min), GaCl (0.3–0.8 L / min), and CH4 (5–20 sccm). The growth rate of the C-doped high-resistivity GaN layer 3 is 0.5–1 μm / h, the growth time is 40–80 min, and the final thickness reaches 400 nm. It is grown under ambient pressure (1 atm), and the C doping concentration is precisely controlled to 1–9 × 10⁻⁶ by adjusting the CH4 flow rate. 18 cm -3 During the growth process, the layer thickness and doping uniformity need to be monitored in real time.

[0038] It should be noted that the thickness of the C-doped high-resistivity GaN layer 3 needs to be precisely controlled, with a reasonable range between 400 nm and 1000 nm, and a preferred thickness of 400 nm. Its thickness must be consistent with the thickness of the n-doped high-resistivity GaN layer 3. - The 20μm thickness of the GaN drift layer 2 is scientifically proportioned; too thin and it will result in insufficient current blocking capability, while too thick and it will increase the on-resistance of the device. In practical applications, it needs to be dynamically adjusted according to the target breakdown voltage. On the other hand, doping uniformity is one of the key requirements, and the C doping concentration must be strictly controlled within 1 to 9 × 10⁻⁶. 18 cm-3 The concentration range must be uniformly distributed throughout the entire current-blocking layer to avoid electric field distortion caused by local concentration fluctuations, which would affect the device's breakdown voltage performance and reliability. The C-doped high-resistivity GaN layer 3 needs to be connected to the upper n-layer... + -GaN layer 4 and the lower n layer - The interface of the GaN drift layer 2 remains clean and defect-free. By optimizing the HVPE growth process parameters, the interface state density is reduced, preventing carrier recombination at the interface and ensuring the device's switching characteristics. Regarding crystal quality, when growing using HVPE technology, it is necessary to ensure that the C-doped high-resistivity GaN layer 3 has good single-crystal characteristics, with the dislocation density controlled at 1×10⁻⁶. 6 cm -2 The following approach aims to reduce leakage current paths, ensure the stability of device withstand voltage levels, and improve long-term operational stability. Simultaneously, the material system must be fully compatible with the full HVPE epitaxial process, avoiding the introduction of additional impurities during growth to prevent adverse reactions with subsequent etching and deposition processes, thus ensuring smooth process flow. This process setup fully utilizes the high efficiency, high uniformity, and large-area growth advantages of HVPE, significantly improving the accuracy of epitaxial layer thickness control and batch repeatability, effectively reducing device performance fluctuations. By precisely controlling the reactive gas flow rate and substrate temperature gradient, linear controllable doping concentration of the C-doped high-resistivity GaN layer is achieved, further optimizing the electric field distribution and improving dynamic reliability. Furthermore, this process path requires no additional annealing or interface treatment steps, is compatible with existing production line equipment, and is beneficial for improving yield and cost control in large-scale manufacturing, providing a stable and reliable material foundation for high-performance GaN-based power devices.

[0039] It should also be noted that the preparation of the C-doped high-resistivity GaN layer 3 requires the use of high-purity CH4 (purity ≥ 99.999%) as the carbon doping source, and strict removal of impurities such as O2 and H2O to avoid introducing oxygen donor impurities that would affect the high-resistivity characteristics of the current blocking layer. The growth temperature needs to be precisely matched and should be higher than n. - The growth temperature of GaN drift layer 2 is 50-100℃ lower, which avoids the high temperature causing damage to the underlying n-layer. -The diffusion of Si doped atoms in the GaN drift layer 2 ensures effective C doping and lattice matching. Gas flow rates need coordinated adjustment; the CH4 and GaCl flow rates must maintain a reasonable ratio (CH4:GaCl = 0.01–0.04:1) to ensure uniform C doping without affecting the GaN crystal quality and preventing carbide precipitation. Real-time monitoring and feedback are required during growth. In-situ reflection high-energy electron diffraction (RHEED) is used to monitor the film growth status, and X-ray fluorescence spectroscopy (XRF) is used to detect the C doping concentration in real time. The CH4 flow rate is dynamically adjusted based on the detection results to ensure doping uniformity. Post-processing should prioritize compatibility. No additional annealing activation is required after growth; the film can directly proceed to subsequent etching processes. This avoids high-temperature annealing that could lead to C atom diffusion or desorption, ensuring the structural stability and electrical performance of the barrier layer—one of the advantages of this design.

[0040] In this embodiment, n + The doping material for GaN layer 4 is Si, with a doping concentration of 1–5 × 10⁻⁶. 18 cm -3 The thickness is 200nm, and it is grown using the HVPE process.

[0041] In this invention, the n - -GaN drift layer 2, C-doped high-resistivity GaN layer 3 and n + All GaN layers 4 are grown using the HVPE process. Employing full HVPE technology for epitaxial layer growth results in a fast growth rate, significantly shortening the device manufacturing cycle.

[0042] Referring to Figure 3, forming a gate dielectric layer 5 on the epitaxial structure specifically includes the following steps: ... + - The GaN layer 4 is etched on the side away from the substrate 1 to form an extension extending to the n - -The mesa structure of GaN drift layer 2; in n + -Etching on GaN layer 4 forms an extension to the n - -Groove of GaN drift layer 2; in n + -Etching is performed on GaN layer 4 to form a penetration through the n + -GaN layer 4, metal contact hole extending to the C-doped high-resistivity GaN layer 3; grow gate dielectric layer 5 on the etched epitaxial structure so that the gate dielectric layer 5 covers the outer surface of the mesa structure and the trench wall.

[0043] In this embodiment, ultraviolet lithography is used to etch and form the mesa structure. Specific process conditions are: photoresist thickness 1.5–2 μm, exposure dose 80–120 mJ / cm², and development time 30–60 s. An inductively coupled plasma etching (ICP) machine is used, with a Cl₂ / BCl₃ mixed gas at a volume ratio of 3:1. Etching parameters are set as follows: ICP power 600–800 W, bias power 100–150 W, and etching temperature 25°C. A variable-rate etching method is employed, with rapid etching in the initial stage (rate 500–600 nm / min) and slow etching in the later stage (rate 100–200 nm / min), controlling the mesa structure etching depth to 600 nm–2.0 μm. After etching, O₂ plasma ashing is used to remove residual photoresist for 10–15 min. Variable-rate etching reduces sidewall damage to the mesa structure and ensures sidewall perpendicularity.

[0044] In this embodiment, the trench depth is 600nm–1000nm, preferably 700nm. Dry etching is used for the trenches, and ultraviolet lithography is employed. The photoresist thickness is 2–3μm, the exposure dose is 100–150mJ / cm², and the development time is 40–70s. An ICP etching machine is used, with a Cl₂ / BCl₃ mixed gas at a volume ratio of 3:1. The etching parameters are: ICP power 700–900W, bias power 80–120W, etching temperature 25℃, and etching rate 300–400nm / min. After etching, damage repair is performed using a 25% TMAH solution for wet etching at 80–90℃ for 5–10min to remove the damaged layer from the dry etching. The area is then rinsed with deionized water and dried with nitrogen.

[0045] In this embodiment, the depth of the metal contact hole ranges from 200 nm to 600 nm, preferably 300 nm. Dry etching of the metal contact hole is employed, using ultraviolet lithography. The photoresist thickness is 1–1.5 μm, the exposure dose is 70–100 mJ / cm², and the development time is 30–50 s. An ICP etching machine is used, with a Cl₂ / BCl₃ mixed gas at a volume ratio of 3:1. The etching parameters are set as follows: ICP power 500–700 W, bias power 120–180 W, etching temperature 25 °C, and etching rate 200–300 nm / min. The position of the metal contact hole must be precisely aligned with the position of the subsequently fabricated metal electrode.

[0046] In this embodiment, the gate dielectric layer 5 is an Al2O3 layer with a thickness of 70 nm. It is grown using ALD technology, with surface passivation treatment performed using a piranha solution before growth. The deposition temperature range is 150–300 °C, with 300 °C being preferred in this embodiment. The precursors are trimethylaluminum (TMA) and H2O. The deposition parameters are: TMA pulse time 0.1–0.2 s, H2O pulse time 0.1–0.2 s, purge time 5–10 s / cycle; growth rate 0.1–0.15 nm / cycle; and a total growth cycle of 467–700 cycles, ultimately forming a 70 nm thick oxide layer. The growth process is carried out under a pressure environment of 1–5 Torr. The ALD deposition technology ensures the uniformity and density of the oxide layer, with a dielectric constant ≥9. In other embodiments, the gate dielectric layer 5 can also be made of other materials, such as SiO2, HfO2, etc., and can also employ multilayer stacking or surface nitriding processes; this invention does not impose any particular limitations on these aspects.

[0047] Referring to Figure 4, in this embodiment, forming a source 7 connected to the epitaxial structure, a gate 9 located on the surface of the gate dielectric layer 5, and a drain 8 connected to the substrate 1 specifically includes the following steps: making contact holes on the gate dielectric layer 5 corresponding to the source 7 to form a trench extending to the C-doped high-resistivity GaN layer 3; fabricating a body metal 6 in the trench; fabricating a source 7 protruding onto the gate dielectric layer 5 on the body metal 6, the source 7 being electrically connected to the body metal 6; fabricating a drain 8 on the second surface of the substrate 1 away from the epitaxial structure; and fabricating a gate 9 in the trench.

[0048] Specifically, the via corresponding to the source 7 location includes a hole that penetrates the gate dielectric layer 5 and extends to the n-th electrode. + - A first trench 70 on the upper surface of the GaN layer 4, and a second trench 60 extending from the bottom of the first trench 70 to the C-doped high-resistivity GaN layer 3, wherein the area of ​​the first trench 70 is larger than the area of ​​the second trench 60, and the source electrode 7 and the bulk metal 6 are in a stepped shape.

[0049] Specifically, by means of etching, a first trench 70 is formed on the gate dielectric layer 5 at a position corresponding to the source 7, penetrating the gate dielectric layer 5. Then, by means of etching, a second trench 60 extending to the C-doped high-resistivity GaN layer 3 is formed at the bottom of the first trench 70.

[0050] It should be noted that in this embodiment, the body metal 6 is deposited in the second trench 60 and completely occupies the second trench 60, the source electrode 7 is deposited in the first trench 70 and protrudes above the gate dielectric layer 5, and the source electrode 7 and the body metal 6 are in electrical contact at the gate dielectric layer 5 and the n +- At the GaN layer 4 interface, a good ohmic contact is formed. In practice, the source 7 and the body metal 6 are not necessarily strictly connected at the gate dielectric layer 5 and the n + - The contact at the interface of GaN layer 4 can have a certain range of fluctuation. For example, it is also feasible to extend the contact within a certain distance in the second hole groove 60, but it is necessary to ensure that the source electrode 7 and the body metal 6 form a good ohmic contact to ensure the normal function of the device.

[0051] In this embodiment, forming the first hole groove 70 and the second hole groove 60 specifically includes: wet etching of alumina with BOE solution to open the contact hole. The BOE solution ratio is HF:NH4F:H2O=1:6:3 (volume ratio), and the HF volume concentration ratio can be adjusted according to the etching rate requirements (adjustment range is 0.5 to 2 volume parts); the etching temperature is controlled at 25 to 30°C, and the etching time is 30 to 60 seconds, which needs to be monitored in real time according to the contact hole size; after etching, rinse with a large amount of deionized water for 10 to 15 minutes, and then blow dry with nitrogen to avoid HF residue causing device corrosion and affecting device reliability.

[0052] In this embodiment, the bulk metal 6 is a Ni / Au metal stack, with a Ni metal layer thickness of 20 nm and an Au metal layer thickness of 60 nm. The bulk metal 6 is prepared using electron beam evaporation technology, with deposition parameters of vacuum degree ≤ 5 × 10⁻⁶. -6 The deposition rates were: Ni (0.5–1 nm / s) and Au (1–2 nm / s), with film thicknesses controlled at Ni (20 nm) and Au (60 nm). A lift-off process was used for photolithography blocking, with a photoresist thickness of 2–3 μm and an exposure dose of 90–120 mJ / cm². Annealing was not performed immediately after metal deposition; instead, overall annealing was performed after the source and drain metals were fully prepared to ensure good ohmic contact between the bulk metal 6 and the C-doped high-resistivity GaN layer 3. In some other embodiments, magnetron sputtering can also be used to prepare the bulk metal 6; however, electron beam evaporation was chosen in this embodiment to obtain better metal film quality.

[0053] In this embodiment, the source electrode 7 and drain electrode 8 have identical metal structures, both being Ti / Al / Ni / Au metal stacks, with each metal layer having the same thickness: 25nm for Ti, 100nm for Al, 20nm for Ni, and 60nm for Au. This metal stack structure ensures good ohmic contact for the source electrode 7, guaranteeing the efficiency and stability of source current transmission, while also ensuring reliable connection between the drain electrode 8 and the substrate 1 and epitaxial layer, effectively improving the device's withstand voltage performance. Furthermore, the identical metal structures and identical thicknesses of the source electrode 7 and drain electrode 8 reduce the fabrication process steps, allowing for the use of the same batch of metal vapor deposition.

[0054] Specifically, in this embodiment, the source electrode 7 and drain electrode 8 are fabricated using electron beam evaporation or magnetron sputtering techniques. The deposition parameters are a vacuum degree ≤ 5 × 10⁻⁶. -6 The deposition rates for the Torr layer were: Ti (0.3–0.5 nm / s), Al (1–2 nm / s), Ni (0.5–1 nm / s), and Au (1–2 nm / s); the film thicknesses were controlled as follows: Ti (25 nm), Al (100 nm), Ni (20 nm), and Au (60 nm). A lift-off process was used for photolithography, with a photoresist thickness of 2–3 μm. After deposition, the layer was annealed in a nitrogen atmosphere (N2 purity ≥ 99.999%) to alloy the Ti / Al / Ni / Au metal stack. The annealing temperature was 800℃, the annealing time was 60 s, and the heating rate was 5–10℃ / s. After annealing, the temperature was allowed to cool naturally to room temperature. During annealing, compounds such as TiN and AlGa were formed. These compounds can optimize the ohmic contact characteristics, resulting in a contact resistance ≤ 1 × 10⁻⁶. -6 Ωcm 2 .

[0055] In this embodiment, the gate 9 is a Ti / Al metal stack, with a Ti metal layer thickness of 25 nm and an Al metal layer thickness of 100 nm. The gate 9 is fabricated using magnetron sputtering with deposition parameters of vacuum degree ≤ 5 × 10⁻⁶. -6 The deposition rates were: Ti (0.3–0.5 nm / s) and Al (1–2 nm / s); the film thicknesses were controlled as follows: Ti (25 nm) and Al (100 nm). A lift-off process was used for photolithography, with a photoresist thickness of 2–3 μm and an exposure dose of 80–110 mJ / cm². Excess metal film was then removed by ultrasonic lift-off with acetone at a power of 100–150 W for 5–10 min. The film was then rinsed with deionized water and dried with nitrogen to form the Schottky contact gate 9, requiring a gate leakage current ≤ 1 × 10⁻⁶. -6 A / cm² (at a reverse bias of 10V). In some other embodiments, the gate 9 can also be prepared using electron beam evaporation or thermal evaporation techniques. In this embodiment, magnetron sputtering is chosen to enhance the adhesion of the film layer.

[0056] The gallium nitride trench MOSFET device of the present invention is manufactured by the above-described method for manufacturing gallium nitride trench MOSFET devices.

[0057] Compared with existing technologies, the beneficial effects of this invention are as follows: Firstly, this invention uses a C-doped high-resistivity GaN layer with semi-insulating properties as a current blocking layer, replacing the relatively low-resistivity Mg-doped p-GaN layer. Through the high-resistivity characteristics of the C-doped high-resistivity GaN layer, the electric field distribution inside the device is more uniform, avoiding localized electric field concentration. In high-voltage applications, this effectively improves the vertical withstand voltage of the device, enabling it to withstand higher operating voltages and broadening its application range in high-voltage power conversion, power transmission, and other fields. Secondly, this invention uses a C-doped high-resistivity GaN layer instead of the traditional Mg-doped p-GaN layer, avoiding many difficulties in the preparation and activation of the p-GaN layer in traditional methods. It eliminates the need to consider issues such as Mg re-passivation leading to activation difficulties and Mg tailing phenomena, simplifying the entire device fabrication process, reducing process difficulty and cost, and improving product yield and reliability. Thirdly, the high-resistivity GaN layer, as a semi-insulating layer, is located at the n... - -GaN drift layer and the n + Between GaN layers, leakage current can be effectively suppressed, power loss of the device in the off state can be reduced, and the turn-off characteristics of the device can be improved.

[0058] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.

Claims

1. A gallium nitride trench MOSFET device, characterized in that, The system includes a substrate, an epitaxial structure formed on a first surface of the substrate, a gate dielectric layer formed on the epitaxial structure, a gate located on the surface of the gate dielectric layer, a source connected to the epitaxial structure, and a drain connected to the substrate. The epitaxial structure includes n... - -GaN drift layer, formed on the n - - A C-doped high-resistivity GaN layer on the GaN drift layer and n formed on the C-doped high-resistivity GaN layer + -GaN layer, the C-doped high-resistivity GaN layer is located in the n - -GaN drift layer and the n + Between the GaN layers, a high-resistance current-blocking layer is used to isolate the n... - -GaN drift layer and the n + -GaN layer.

2. The gallium nitride trench MOSFET device as described in claim 1, characterized in that: From the n + -The top surface of the GaN layer is recessed inward to form an extension to the n - - A mesa structure and trenches for the GaN drift layer, wherein the gate dielectric layer is formed on the outer surface of the mesa structure and the trench walls, and a through-hole is formed from the gate dielectric layer inwards through the gate dielectric layer and the n + - A GaN layer extending into a trench in the C-doped high-resistivity GaN layer, the trench being filled with body metal, the source being located on and electrically connected to the body metal, the gate being formed in the trench and connected to the gate dielectric layer, and the drain being formed on a second surface of the substrate away from the epitaxial structure.

3. The gallium nitride trench MOSFET device as described in claim 1, characterized in that, The substrate includes n + -GaN substrate, the n - -GaN drift layer is formed on the n + -On the GaN substrate, the n + The GaN substrate is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 18 cm -3 .

4. The gallium nitride trench MOSFET device as described in claim 1, characterized in that, The n - The GaN drift layer is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 16 cm -3 The n + The GaN layer is doped with Si, with a doping concentration of 1–5 × 10⁻⁶. 18 cm -3 .

5. The gallium nitride trench MOSFET device as described in claim 1, characterized in that, The doping concentration of the C-doped high-resistivity GaN layer is 1–9 × 10⁻⁶. 18 cm -3 The thickness is 400–1000 nm.

6. The gallium nitride trench MOSFET device as described in claim 4, characterized in that, The n - The thickness of the GaN drift layer is 20 μm, the thickness of the C-doped high-resistivity GaN layer is 400 nm, and the n + - The thickness of the GaN layer is 200 nm.

7. A method for fabricating a gallium nitride trench MOSFET device, characterized in that, include: n is grown on the first surface of the substrate - -GaN drift layer; in the n - A C-doped high-resistivity GaN layer is grown on the GaN drift layer; an n-doped high-resistivity GaN layer is grown on the C-doped high-resistivity GaN layer. + -GaN layer to form n - -GaN drift layer, C-doped high-resistivity GaN layer and n + - An epitaxial structure of a GaN layer; a gate dielectric layer is formed on the epitaxial structure; A source electrode connected to the epitaxial structure, a gate electrode located on the surface of the gate dielectric layer, and a drain electrode connected to the substrate are formed.

8. The method for fabricating a gallium nitride trench MOSFET device as described in claim 7, characterized in that, The substrate includes n + -GaN substrate, the n - -GaN drift layer is grown on the n + -On the GaN substrate, the n + The GaN substrate is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 18 cm -3 .

9. The method for fabricating a gallium nitride trench MOSFET device as described in claim 7, characterized in that, The n - The GaN drift layer is doped with Si, with a doping concentration of 2–5 × 10⁻⁶. 16 cm -3 The n + The GaN layer is doped with Si, with a doping concentration of 1–5 × 10⁻⁶. 18 cm -3 .

10. The method for fabricating a gallium nitride trench MOSFET device as described in claim 7, characterized in that, The doping concentration of the C-doped high-resistivity GaN layer is 1–9 × 10⁻⁶. 18 cm -3 The thickness is 400–1000 nm.

11. The method for fabricating a gallium nitride trench MOSFET device as described in claim 7, characterized in that, The n - -GaN drift layer, C-doped high-resistivity GaN layer and n + - All GaN layers were grown using the HVPE process.

12. The method for fabricating a gallium nitride trench MOSFET device as described in claim 7, characterized in that, Forming a gate dielectric layer on the epitaxial structure includes: in n + - The GaN layer is etched on the side away from the substrate to form an extension extending to the n - -Mesa structure of GaN drift layer; in n + -Etching on the GaN layer forms an extension to the n - -Groove of GaN drift layer; in n + -Etching on the GaN layer forms a penetration through the n + - GaN layer, metal contact hole extending to the C-doped high-resistivity GaN layer; grow a gate dielectric layer on the etched epitaxial structure so that the gate dielectric layer covers the outer surface of the mesa structure and the trench wall.

13. The method for fabricating a gallium nitride trench MOSFET device as described in claim 7, characterized in that, Forming a source electrode connected to an epitaxial structure, a gate electrode located on the surface of the gate dielectric layer, and a drain electrode connected to a substrate includes: creating a contact hole opening from the gate dielectric layer at a position corresponding to the source electrode to form a trench extending to the C-doped high-resistivity GaN layer; fabricating a body metal within the trench; fabricating a source electrode protruding from the body metal onto the gate dielectric layer, the source electrode being electrically connected to the body metal; fabricating a drain electrode on a second surface of the substrate away from the epitaxial structure; and fabricating a gate electrode within the trench.

14. The method for fabricating a gallium nitride trench MOSFET device as described in claim 12, characterized in that, The via corresponding to the source location includes a hole that penetrates the gate dielectric layer and extends to the n-th electrode. + - A first trench on the upper surface of the GaN layer, and a second trench extending from the bottom of the first trench to the C-doped high-resistivity GaN layer, wherein the width of the first trench is greater than the width of the second trench.

15. A gallium nitride trench MOSFET device, characterized in that, It is manufactured by the method of any one of claims 7-14.

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