Shield gate trench MOSFET device and preparation method thereof
By forming an insulated gate and a shielding gate within the trench of a shielded gate trench MOSFET, and setting insulating layers of different thicknesses outside the shielding gate, the electric field distribution is optimized, overcoming the shortcomings of conventional devices in terms of current density and capacitance, and achieving higher current density and lower internal resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-03-24
AI Technical Summary
Conventional shielded gate trench MOSFETs struggle to meet higher current density requirements per unit area, and the devices have relatively large internal resistance and output capacitance.
In a trench MOSFET, an insulating gate and a shielding gate are formed inside the trench, and insulating layers of different thicknesses are set outside the shielding gate. The electric field distribution is optimized through multiple deposition, etching and planarization processes to reduce the unit on-resistance and output capacitance of the device.
The electric field distribution was optimized, which significantly reduced the unit on-resistance of the device, improved the current density and system efficiency, and reduced the output capacitance.
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Figure CN121728804A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a shield gate trench MOSFET device and a preparation method thereof. BACKGROUND
[0002] The shield gate trench MOSFET is an advanced discrete device MOSFET structure, and has the characteristics of high breakdown voltage, low on-resistance and fast switching speed. Compared with the traditional trench MOSFET, the polycrystalline silicon filled in the trench of the shield gate trench MOSFET is divided into two parts: the polycrystalline silicon located at the lower part of the trench forms a shield gate polycrystalline silicon which is short-circuited with the source electrode of the device; and the polycrystalline silicon located at the upper part of the trench forms a polycrystalline silicon gate, and the shield gate polycrystalline silicon and the polycrystalline silicon gate are separated by a silicon oxide film.
[0003] With the development of technology, greater current density is required, that is, smaller internal resistance is required under unit area, and under the same process, the conventional shield gate trench MOSFET is difficult to fully meet this requirement.
[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY
[0005] In view of the deficiencies of the prior art, the present application discloses a shield gate trench MOSFET device and a preparation method thereof.
[0006] The technical solutions adopted by the embodiments of the present application are as follows: A shield gate trench MOSFET device comprises: a substrate; an epitaxial layer formed on the front surface of the substrate; a trench formed on the inner upper end of the epitaxial layer; wherein the inside of the trench forms a third polycrystalline silicon and a second polycrystalline silicon insulated from each other, which are respectively used as a gate and a shield gate; the second polycrystalline silicon comprises an upper segment and a lower segment, a first insulating layer is arranged between the upper segment and the epitaxial layer, and a second insulating layer is arranged between the lower segment and the epitaxial layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer.
[0007] A further technical solution is that a third dielectric layer is arranged between the third polycrystalline silicon and the second polycrystalline silicon; and a gate oxide layer is arranged between the third polycrystalline silicon and the epitaxial layer.
[0008] A further technical solution is that the first insulating layer, the second insulating layer, the third dielectric layer and the gate oxide layer are all silicon dioxide insulating layers.
[0009] A further technical solution is that the second polysilicon has a structure that is wider at the top and narrower at the bottom in the longitudinal cross-section, and the bottom of the second polysilicon is rounded.
[0010] A further technical solution is that the MOSFET device further includes: The P-well region forms the inner upper end of the epitaxial layer and is located outside the upper end of the trench; The source electrode is formed at the upper part of the interior of the P-well region.
[0011] A further technical solution is that the MOSFET device further includes: A fourth dielectric layer is formed on the upper surface of the epitaxial layer; A contact hole that passes through the fourth dielectric layer and enters the interior of the P-well region, wherein contact hole metal is deposited within the contact hole; A metal layer is formed on top of a fourth dielectric layer and a metal hole.
[0012] A method for manufacturing a shielded gate trench MOSFET device, comprising the following steps in sequence: Obtain a substrate and grow an epitaxial layer with the target thickness and doping concentration on the substrate; Trenches are formed on the epitaxial layer using photolithography and etching processes; A first dielectric layer is formed at the bottom and sidewalls of the trench by thermal oxidation or chemical vapor deposition, and then a first polysilicon is deposited in the trench where the first dielectric layer is formed to planarize the first polysilicon. The first polysilicon is etched away to the first target height, and then the first dielectric layer located on the first polysilicon is removed by a wet etching process. Etch away all of the first polysilicon to expose the first dielectric layer on the trench sidewall; A second dielectric layer is formed on the sidewall of the trench, and the second dielectric layer is planarized; Deposit a second polysilicon in a trench where a second dielectric layer is formed, and planarize the second polysilicon. The second polysilicon is etched to the second target height, and the second dielectric layer located above the second polysilicon is removed by a wet etching process. A third dielectric layer is deposited on the surface of the second polysilicon; After cleaning, gate oxide is grown, then third polysilicon is deposited and planarized.
[0013] A further technical solution is that the method further includes the following steps: P-type impurities are injected into the epitaxial layers on both sides of the upper end of the trench, and then annealed to form a P-well region. An N-type impurity is implanted at the upper end of the P-well region to form a source. A fourth dielectric layer is deposited on the upper surface of the epitaxial layer; Contact holes are formed on the fourth dielectric layer; Metal is deposited in the fourth dielectric layer and the contact hole to form contact hole metal and metal layer.
[0014] The beneficial effects of the embodiments of the present invention are as follows: (i) The shielded gate trench MOSFET device proposed in this invention forms an upper and lower insulating gate and a shielded gate inside the trench, and forms two insulating layers of different thicknesses on the outer longitudinal direction of the shielded gate. This makes the electric field in the middle of the shielded gate stable in the vertical direction along the sidewall of the trench, optimizes the electric field distribution of the device, and under the same withstand voltage conditions, can significantly reduce the unit on-resistance of the device, increase the current density of the device, and at the same time reduce the output capacitance and improve the system efficiency.
[0015] (ii) The method for fabricating the shielded gate trench MOSFET device proposed in this invention, through the design of multiple deposition, etching and planarization processes, forms insulating layers of different structures and thicknesses on the trench sidewalls, thereby improving the overall performance of the shielded gate trench MOSFET device. The method is easy to implement and highly operable, achieving a breakthrough functional innovation in semiconductor devices with less production cost. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the structure of a shielded gate trench MOSFET device proposed in Embodiment 1 of the present invention.
[0017] Figure 2 This is a schematic diagram of the electric field distribution of a conventional shielded trench MOSFET device and the shielded trench MOSFET device designed in Embodiment 1 of this utility model.
[0018] Figure 3 This is a flowchart of steps S1 to S7 in the manufacturing method of a shielded trench MOSFET device structure proposed in Embodiment 2 of the present invention.
[0019] Figure 4 This is a flowchart of steps S8 to S13 in the manufacturing method of a shielded trench MOSFET device structure proposed in Embodiment 2 of the present invention.
[0020] Figure 5 This is a schematic diagram of the device structure in steps S2, S3, and S4.
[0021] Figure 6 This is a schematic diagram of the device structure in steps S5, S6, and S7.
[0022] Figure 7This is a schematic diagram of the device structure in steps S8, S9, and S10.
[0023] Figure 8 This is a schematic diagram of the device structure in steps S11, S12, and S13.
[0024] In the figure: 100, substrate; 101, epitaxial layer; 102, trench; 103, first dielectric layer; 104, first polysilicon; 105, second dielectric layer; 106, second polysilicon; 107, third dielectric layer; 108, third polysilicon; 109, P-well region; 110, source; 111, fourth dielectric layer; 112, contact hole; 113, contact hole metal; 114, metal layer. Detailed Implementation
[0025] The specific embodiments of the present invention will now be described with reference to the accompanying drawings.
[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the device proposed by this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.
[0027] Example 1 Figure 1 This is a schematic diagram of a shielded gate trench MOSFET device according to Embodiment 1 of the present invention. Figure 1As shown, the shielded gate trench MOSFET device of this embodiment includes: a substrate 100, an epitaxial layer 101, and trenches 102. The epitaxial layer 101 is formed on the substrate 100, and a plurality of trenches 102 are formed laterally at the upper end of the epitaxial layer 101. A third polysilicon 108 and a second polysilicon 106, which are insulated from each other, are formed inside the trenches 102, serving as the gate and shielding gate of the device, respectively. The second polysilicon 106 includes a structurally continuous upper segment and a lower segment. A first insulating layer is disposed between the upper segment and the epitaxial layer 101, and a second insulating layer is disposed between the lower segment and the epitaxial layer 101. The thickness of the second insulating layer is greater than the thickness of the first insulating layer. Preferably, the second insulating layer can be composed of two dielectric layers formed by two depositions, achieved through two insulating layer depositions.
[0028] like Figure 1 As shown, in this embodiment, the second polysilicon 106 has a structure that is wider at the top and narrower at the bottom in the longitudinal cross section. The bottom of the second polysilicon 106 is rounded. The lower section of the second polysilicon 106 is narrower than the upper section. The thickness of the second insulating layer on the outside of the lower section is thicker than the first insulating layer on the outside of the upper section.
[0029] Figure 2 This is a schematic diagram of the electric field distribution of a conventional shielded trench MOSFET device and the shielded trench MOSFET device designed in Embodiment 1 of this utility model. Figure 2 The upper and lower frames in the diagram represent the gate and the shielding gate, respectively. Figure 2 The left image corresponds to a conventional device, and the right image corresponds to the device in this embodiment. For example... Figure 2 As shown, this embodiment utilizes this design to form two insulating layers of different structures and thicknesses on the outside of the shielding gate. This optimizes the electric field distribution of the device, ensuring a stable electric field in the center of the shielding gate without sagging, thus resulting in higher blocking voltage efficiency and improved device withstand voltage. Conversely, at a given withstand voltage, the internal resistance of the device can be made lower, and the current density can be increased. Furthermore, because the lower half of the shielding gate has a thicker second insulating layer, the parasitic output capacitance Coss of the device is smaller than that of conventional devices, improving device efficiency.
[0030] Furthermore, such as Figure 1 As shown, in this embodiment, a third dielectric layer 107 is disposed between the third polysilicon 108 and the second polysilicon 106. A gate oxide layer is disposed between the third polysilicon 108 and the epitaxial layer 101. The first insulating layer, the second insulating layer, the third dielectric layer 107, and the gate oxide layer are all silicon dioxide insulating layers.
[0031] Furthermore, such as Figure 1As shown, in this embodiment, the shielded gate trench MOSFET device further includes a P-well region 109 formed within the epitaxial layer 101 and located outside the upper end of the trench 102, with a source 110 formed at the upper end of the inner part of the P-well region 109. A fourth dielectric layer 111 is formed on the upper surface of the epitaxial layer 102.
[0032] The shielded gate trench MOSFET device also includes a contact hole 112 and a metal layer 114. The contact hole 112 passes through the fourth dielectric layer 111 and enters the interior of the P-well region 109. The depth of the contact hole 112 exceeds the depth of the source 110. Contact hole metal 113 is deposited inside the contact hole 112. The metal layer 114 is formed on the fourth dielectric layer 111 and the metal hole 112.
[0033] Example 2 Figure 3 This is a flowchart of steps S1 to S7 in the manufacturing method of a shielded trench MOSFET device structure proposed in Embodiment 2 of the present invention. Figure 4 This is a flowchart of steps S8 to S13 in the manufacturing method of a shielded trench MOSFET device structure proposed in Embodiment 2 of the present invention. Figure 5 This is a schematic diagram of the device structure in steps S2, S3, and S4. Figure 6 This is a schematic diagram of the device structure in steps S5, S6, and S7. Figure 7 This is a schematic diagram of the device structure in steps S8, S9, and S10. Figure 8 This is a schematic diagram of the device structure in steps S11, S12, and S13.
[0034] Combination Figure 3 , Figure 4 As shown, the manufacturing method of the shielded gate trench MOSFET device structure in this embodiment includes the following steps: S1. An epitaxial layer 101 with a target thickness and target doping concentration is grown on a substrate 100.
[0035] S2. Perform the first photolithography and etching processes to form trench 102, such as... Figure 5 As shown.
[0036] S3. A first dielectric layer 103 of target thickness is formed on the bottom and sidewalls of trench 102 using methods not limited to overheating oxidation and CVD (Chemical Vapor Deposition) deposition. A first polysilicon layer 104 is then deposited, trench 102 is backfilled, and the polysilicon 104 is planarized using CMP (Chemical Mechanical Polishing). Figure 5 As shown.
[0037] S4. After etching the first polysilicon layer 104 to the target height, wet-etch the first dielectric layer 103, as follows: Figure 5 As shown.
[0038] S5, etch away the first polysilicon 104, such as Figure 6 As shown.
[0039] S6. Through methods not limited to CVD deposition or thermal oxidation followed by CVD, in Figure 6 The bottom and sidewalls of the trench 102 form a second dielectric layer 105 of the target thickness, and the surface is treated by CMP, such as... Figure 6 As shown.
[0040] S7. Deposit the second polysilicon 106, and planarize the second polysilicon 106 by CMP, such as Figure 6 As shown.
[0041] S8, etch away the second thickest polysilicon layer (106), such as Figure 7 As shown.
[0042] S9. Wet etching removes the second dielectric layer 105, as shown. Figure 7 As shown.
[0043] S10, HPCVD (High Pressure Chemical Vapor Deposition) is used to deposit the third dielectric layer 107 of the target thickness, namely IPO (Inter-Poly Oxide), such as... Figure 7 As shown.
[0044] S11. After cleaning, gate oxide of the target thickness is grown, and a third layer of polysilicon 108 of the target thickness is deposited. The surface is then planarized using CMP. Figure 8 As shown.
[0045] S12, P-type impurities are implanted, followed by annealing to form the P-well region 109. Then, after a fourth photolithography process, N-type impurities are implanted to form the device source 110. Figure 8 As shown.
[0046] S13. Deposit a dielectric layer of the target thickness, followed by photolithography and etching to form contact holes, and deposit contact hole metal 111 and metal layer 112, as shown. Figure 8 As shown.
[0047] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0048] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A shielded gate trench MOSFET device, characterized in that, include: Substrate (100); An epitaxial layer (101) is formed on the front side of a substrate (100); A trench (102) is formed at the upper inner end of the epitaxial layer (101); The trench (102) contains an upper and lower insulating third polysilicon (108) and a second polysilicon (106), which serve as a gate and a shield gate, respectively. The second polysilicon (106) includes an upper section and a lower section. A first insulating layer is disposed between the upper section and the epitaxial layer (101), and a second insulating layer is disposed between the lower section and the epitaxial layer (101). The thickness of the second insulating layer is greater than the thickness of the first insulating layer.
2. The shielded gate trench MOSFET device as described in claim 1, characterized in that, The second insulating layer consists of two dielectric layers formed by two depositions.
3. The shielded gate trench MOSFET device as described in claim 1, characterized in that, A third dielectric layer (107) is disposed between the third polysilicon (108) and the second polysilicon (106); a gate oxide layer is disposed between the third polysilicon (108) and the epitaxial layer (101).
4. The shielded gate trench MOSFET device as described in claim 3, characterized in that, The first insulating layer, the second insulating layer, the third dielectric layer (107) and the gate oxide layer are all silicon dioxide insulating layers.
5. The shielded gate trench MOSFET device as described in claim 1, characterized in that, The second polysilicon (106) has a structure that is wider at the top and narrower at the bottom in the longitudinal section, and the bottom of the second polysilicon (106) is rounded.
6. The shielded gate trench MOSFET device as described in claim 1, characterized in that, The MOSFET device further includes: P-well region (109), which forms the inner upper end of the epitaxial layer (101) and is located on the outer side of the upper end of the trench (102); Source (110), which is formed at the upper part of the interior of the P-well region (109).
7. The shielded gate trench MOSFET device as described in claim 6, characterized in that, The MOSFET device also includes: A fourth dielectric layer (111) is formed on the upper surface of the epitaxial layer (102); Contact hole (112) passes through the fourth dielectric layer (111) and enters the interior of the P-well region (109), and contact hole metal (113) is deposited in the contact hole (112). A metal layer (114) is formed on the fourth dielectric layer (111) and the metal hole (112).
8. A method for manufacturing a shielded gate trench MOSFET device, characterized in that, Perform the following steps in sequence: Obtain a substrate (100) and grow an epitaxial layer (101) with a first target thickness and doping concentration on the substrate (100). Trench (102) is formed on the epitaxial layer (101) by photolithography and etching processes. A first dielectric layer (103) is formed at the bottom and sidewalls of the trench (102) by thermal oxidation or chemical vapor deposition process, and then a first polysilicon (104) is deposited in the trench (102) where the first dielectric layer (103) is formed, and the first polysilicon (104) is planarized. The first polysilicon (104) is etched away to the first target height, and then the first dielectric layer (103) above the first polysilicon (104) is removed by a wet etching process. All of the first polysilicon (104) is etched away, exposing the first dielectric layer (103) on the sidewall of the trench (102). A second dielectric layer (105) is formed on the sidewall of the trench (102), and the second dielectric layer (105) is planarized. A second polysilicon (106) is deposited in a trench (102) in which a second dielectric layer (105) is formed, and the second polysilicon (106) is planarized. The second polysilicon (106) is etched to the second target height, and the second dielectric layer (105) located above the second polysilicon (106) is removed by a wet etching process. A third dielectric layer (107) is deposited on the surface of the second polysilicon (106); After cleaning, gate oxide is grown, and then third polysilicon (108) is deposited and planarized.
9. The method for manufacturing a shielded gate trench MOSFET device as described in claim 8, characterized in that: The method further includes the following steps: P-type impurities are injected into the epitaxial layers (101) on both sides of the upper end of the trench (102), and then annealed to form a P-well region (109). An N-type impurity is injected into the upper end of the P-well region (109) to form a source (110). A fourth dielectric layer (111) is deposited on the upper surface of the epitaxial layer (102). A contact hole (112) is formed on the fourth dielectric layer (111); Metal is deposited in the fourth dielectric layer (111) and the contact hole (112) to form contact hole metal (111) and metal layer (112).