Silicon-based quaternary barrier millimeter wave device with low-temperature protective layer and preparation method of silicon-based quaternary barrier millimeter wave device

Abstract

The invention discloses a quaternary barrier millimeter wave device with a low-temperature protective layer and a preparation method of the quaternary barrier millimeter wave device. The millimeter wave device comprises a Si-rich SixN protection layer which is grown on a quaternary barrier epitaxial structure at low temperature by using a plasma enhanced deposition technology, and an ohmic contact electrode and a T-shaped grid which are directly grown on the Si-rich low-temperature protection layer in combination with an electron beam evaporation process. Compared with an in-situ growth technology, the method has the advantage that In precipitation caused by a high-temperature environment of in-situ growth can be well prevented. Meanwhile, the low-temperature protection layer can assist in forming ohmic contact in the high-temperature annealing process of the electrode and prevent the under-gate barrier layer from being damaged in the high-temperature process. The method provided by the invention is simpler in process, the ohmic contact is optimized, the high-temperature link in the preparation process is reduced, and the precipitation degradation of the under-gate barrier layer is prevented. The device provided by the invention has excellent performances of large current, high power, high breakdown voltage and the like, and is suitable for mass production of high-performance millimeter wave devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer and its fabrication method. Background Technology

[0002] Millimeter-wave devices are crucial modules supporting emerging industries and demands such as consumer electronics, smartphones, communication spread spectrum, and autonomous driving. For example, traditional communication frequency bands below 6GHz are currently quite congested, while the millimeter-wave band (30GHz-300GHz) boasts abundant spectrum resources, enabling bandwidth transmissions exceeding 400MHz or even 800MHz. This provides strong support for ultra-high-speed data transmission; 5G and even future 6G communications consider millimeter waves a key spectrum resource to meet user demands for high-bandwidth data services such as high-definition video, virtual reality, and the Internet of Things. Among these, Si-based devices have garnered widespread attention due to their low cost and highly compatible manufacturing solutions.

[0003] For high-frequency applications, traditional AlGaN barrier layer solutions suffer from limited polarization. As the gate length shrinks, the short-channel effect intensifies, ultimately hindering further improvements in saturation output current and frequency characteristics, thus impacting the device's high-frequency performance. While quaternary strongly polarized materials can provide stronger polarization, their unique low-temperature stability means that in practical applications, unavoidable high-temperature processes can lead to In deposition and barrier layer degradation. Examples include the growth of high-temperature cap layers and high-temperature electrode annealing. This results in a decrease in device saturation current, a decline in frequency characteristics, and a series of performance degradations. Furthermore, the difficulty in growing the cap layer can lead to problems such as high ohmic contact resistance.

[0004] While ohmic growth techniques can mitigate the high-temperature processes in device fabrication to some extent, their complex processes, frequent etching leading to surface state alterations, and poor compatibility with traditional manufacturing processes are significant challenges. Furthermore, the growth of in-situ caps for quaternary barriers is limited by their low-temperature stability. Therefore, protecting the barrier, especially the under-gate region, during high-temperature processes to improve device performance has become a pressing issue. Finding a simple, efficient, and highly compatible barrier protection solution is essential, as it greatly benefits the commercialization, mass production, and large-scale application of millimeter-wave devices. Summary of the Invention

[0005] This invention mainly addresses the problems of barrier layer degradation and In precipitation in quaternary barrier devices during high-temperature processes, providing a simple and adaptable low-temperature protection layer solution for applications in the millimeter-wave field.

[0006] In view of the deficiencies in the existing technology mentioned above, this invention provides a simple and efficient silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer and its fabrication scheme from the perspective of device structure design and process improvement. This scheme can effectively protect the barrier layer and the under-gate region, reduce ohmic contact resistance, and improve the device's saturation output current and cutoff frequency. At the same time, the process is simple, avoiding additional etching and high-temperature growth, and has stronger compatibility with existing mass production processes, making it very suitable for the current industrial production requirements of high efficiency and high yield.

[0007] The objective of this invention is achieved by at least one of the following technical solutions.

[0008] A silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer includes a silicon-based quaternary barrier epitaxial layer, a GaN cap layer above the quaternary barrier, and a low-temperature Si-rich Si layer. x N protective layer, located at low temperature Si-rich Si x The source and drain electrodes are located above the N-layer protective layer, and the gate electrode is located between the source and drain electrodes. The value of x ranges from 0.55 to 1.45.

[0009] Preferably, the distance between the gate electrode and the source electrode is greater than or equal to 500 nm, the maximum distance is equal to the distance between the gate electrode and the drain electrode, and less than or equal to 3 μm.

[0010] Preferably, the gate electrode is composed of a multilayer metal, including a Ni layer and an Au layer from bottom to top, with the thickness of the metal layers being between 10-50 nm and 150-500 nm, respectively.

[0011] Preferably, the source electrode and the drain electrode are composed of stacked metals with the same structure, including a Ti layer, an Al layer, a Ni layer and an Au layer from bottom to top. The thickness of the metal layers is between 10-25 nm, 85-150 nm, 5-15 nm and 85-150 nm respectively, and the total thickness of the metal layers of the source electrode and the drain electrode is less than 310 nm.

[0012] The method for fabricating a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to the present invention includes the following steps:

[0013] S1. Cleaning of the quaternary barrier epitaxial layer. This includes soaking in piranha solution, soaking in organic solvents, and soaking and rinsing in deionized water. All cleaning steps incorporate appropriate ultrasonic treatment. The purpose of the cleaning process is to remove residual metal oxides, organic matter, and other impurities from the surface of the quaternary barrier epitaxial layer.

[0014] S2. Preparation of the cryogenic protective layer. This includes the deposition of Si-rich Si using plasma-enhanced deposition technology at low temperatures. xN. The carrier gas is N2, the Si source is silane gas, and the N source is NH3. During its growth, the ratio of SiH4 to NH3 is between 0.95 and 1.45:1.

[0015] S3. Fabrication of source and drain electrodes. This includes defining the source and drain electrode patterns using photolithography, forming a mask using photoresist, and growing stacked metals using electron beam evaporation.

[0016] S4. Fabrication of the gate electrode. This includes defining the T-shaped gate electrode pattern using electron beam lithography.

[0017] Electron beam evaporation is used to grow stacked metals, and a stripping process is used to achieve gate independence.

[0018] Preferably, in step S2, low-temperature Si-rich Si x The preparation temperature of the N protective layer should be ≤300℃.

[0019] Preferably, in step S2, low-temperature Si-rich Si x The N-protective layer should be less than or equal to 5 nm and greater than or equal to 1 nm.

[0020] Preferably, in step S3, the source electrode and drain electrode are directly grown on the low-temperature protective layer and simultaneously participate in annealing. The annealing environment is N2, the annealing temperature is 850–950°C, and the annealing time is 30–75 s.

[0021] As described above, compared with the prior art, the present invention has the following beneficial features and advantages:

[0022] 1. The quaternary barrier millimeter-wave device structure design with a low-temperature protective layer eliminates the need for additional barrier layer etching and regeneration steps, achieving an extremely simple device process to prevent quaternary barrier In deposition. This reduces ohmic contact resistance and improves saturation current. Simultaneously, the low-temperature protective layer assists in the formation of ohmic contacts during the high-temperature annealing process of the electrodes and prevents damage to the gate barrier layer caused by the high-temperature process.

[0023] 2. Based on the device structure design, no additional barrier layer etching and regrowth steps are required, reducing surface damage caused by etching and improving device reliability.

[0024] 3. It provides excellent gate protection during high-temperature processes such as annealing and ion bombardment in device fabrication, improves gate control capability, and is beneficial to the improvement of device frequency performance, especially millimeter-wave performance.

[0025] 4. The device structure design is seamlessly integrated with existing processes, which is conducive to rapidly improving production quality and realizing the integration and mass production of large-scale millimeter-wave devices. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating the fabrication process of a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer, provided by an embodiment of the present invention.

[0027] Figure 2 This is a cross-sectional schematic diagram of a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer provided by an embodiment of the present invention.

[0028] Figure 3 This is the saturation current curve of a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer provided by an embodiment of the present invention.

[0029] Figure 4 The frequency response curve is provided by an embodiment of the present invention for a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer.

[0030] Figure 5 The output power and power-added efficiency curves of a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer are provided by embodiments of the present invention. Detailed Implementation

[0031] The embodiments of the present invention will be specifically described below with reference to the accompanying drawings and specific examples. It should be noted that the examples of the present invention are not limited to the specific parts indicated.

[0032] Attachment Figure 1 The present invention provides a fabrication flowchart of a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer. The low-temperature protective layer is fabricated before the ohmic electrode fabrication and is used to protect the quaternary barrier layer during metal growth and high-temperature annealing processes. The quaternary barrier epitaxy is an InAlGaN barrier epitaxy grown by metal-organic chemical vapor deposition (MOCVD).

[0033] Example 1: The fabrication method of a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer is as follows:

[0034] S1. The quaternary barrier epitaxial layer 1 was immersed in a piranha solution for 10 minutes to remove residual metal oxides from the surface. The quaternary barrier epitaxial layer 1 was then rapidly rinsed with deionized water for 7 minutes to remove residual acid solution. The quaternary barrier epitaxial layer 1 was then immersed in acetone and sonicated for 5 minutes to remove residual organic matter. The quaternary barrier epitaxial layer 1 was then immersed in isopropanol and sonicated for 5 minutes to remove residual acetone. The quaternary barrier epitaxial layer 1 was then rapidly rinsed with deionized water for 7 minutes to remove residual isopropanol.

[0035] S2. Depositing Si-rich Si using plasma-enhanced deposition technology.x N-type cryogenic protective layer 3. The carrier gas is N2, the Si source is silane gas, and the N source is NH3. The gas flow rate ratio of the Si source to the N source is 1.1:1. The protective layer has a growth thickness of 2 nm.

[0036] S3. The source electrode 6 and drain electrode 4 are directly defined on the protective layer using photolithography, and the electrode area is ensured to be pure by plasma cleaning. A Ti / Al / Ni / Au metal stack is then deposited sequentially from bottom to top using electron beam evaporation. Rapid thermal annealing is performed immediately after metal growth.

[0037] S4. The T-shaped gate electrode 5 pattern is defined using electron beam lithography. A multilayer Ni / Au metal is directly grown on the protective layer using electron beam evaporation, and the gate electrode is made independent using a lift-off process.

[0038] Optionally, the thickness of the cryogenic protective layer in this example is 2 nm, and the growth temperature is 270 °C.

[0039] Optionally, in the preparation process of the low-temperature protective layer in this example, the ratio of SiH4 to NH3 is 1.1:1.

[0040] In this example, the source electrode 6 and the drain electrode 4 are both defined and grown directly on the protective layer using photolithography, and are directly connected to the low-temperature protective layer.

[0041] In this example, the source electrode 6 and the drain electrode 4 are composed of stacked metals with the same structure, including a Ti layer, an Al layer, a Ni layer, and an Au layer from bottom to top. The thicknesses of the metal layers are 20 nm, 150 nm, 5 nm, and 150 nm, respectively.

[0042] In this example, the ohmic contact between the source electrode 6 and the drain electrode 4 is achieved by rapid thermal annealing on the protective layer.

[0043] Optionally, the annealing environment is N2, the annealing temperature is 900℃, and the annealing time is 45s.

[0044] In this example, the gate electrode 5 is equidistant from the source electrode 6 and the drain electrode 4. The gate electrode 5 has a T-shaped structure. The gate electrode 5 is defined by electron beam lithography and is grown directly on the protective layer after the source and drain electrodes are fabricated.

[0045] Optionally, the gate electrode 5 has a structure of stacked metal Ni / Au, with metal layer thicknesses of 10 / 350 nm.

[0046] In this example, the quaternary barrier epitaxial thickness is 700 nm.

[0047] Figure 2A cross-sectional schematic diagram of a silicon-based quaternary barrier millimeter-wave device with a cryogenic protective layer prepared according to this embodiment is provided. Taking this device as an example, after growing the cryogenic protective layer and high-temperature annealing, elemental analysis scans were performed on the device surface and compared with a device without a protective layer. The elemental composition results of the device surface are shown in Table 1. It can be clearly observed that the cryogenic protective layer effectively controls In precipitation in the quaternary barrier, achieving protection for the under-gate region. Simultaneously, the cryogenic protective layer can assist in the formation of ohmic contacts during the high-temperature annealing process of the electrodes and prevent damage to the under-gate barrier layer during the high-temperature process.

[0048] Table 1

[0049]

[0050]

[0051] In this example, the saturation current curve of the device is as follows: Figure 3 As shown. The frequency response curve of the device is as follows. Figure 4 As shown. The output power and power-added efficiency curves of the device are as follows. Figure 5 As shown, compared to regrowth techniques on quaternary barriers or traditional capping techniques, silicon-based quaternary barrier millimeter-wave devices with low-temperature protective layers can avoid the introduction of additional etching work, avoid multi-step high-temperature processes, and also have good functions in preventing In precipitation and protecting the under-gate region. (The text then mentions low-temperature Si-rich Si...) x Devices with N-layer protection exhibit excellent performance, featuring high saturation current, high cutoff frequency, and high output power density and power-added efficiency.

[0052] Example 2: The fabrication method of a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer is as follows:

[0053] S1. The quaternary barrier epitaxial layer 1 (grown by metal-organic chemical vapor deposition, or MOCVD) was immersed in a piranha solution for 10 minutes to remove residual metal oxides from the surface. The layer was then rapidly rinsed with deionized water for 7 minutes to remove residual acid solution. The layer was then immersed in acetone and sonicated for 5 minutes to remove residual organic matter. Finally, the layer was immersed in isopropanol and sonicated for 5 minutes.

[0054] The purpose of this step is to remove residual acetone from the surface. The quaternary barrier epitaxial layer 1 is then rapidly rinsed with deionized water for 7 minutes to remove residual isopropanol from the surface.

[0055] S2. Depositing Si-rich Si using plasma-enhanced deposition technology.x N-type cryogenic protective layer 3. The carrier gas is N2, the Si source is silane gas, and the N source is NH3. The gas flow rate ratio of the Si source to the N source is 1.5:1. The protective layer has a growth thickness of 5 nm.

[0056] S3. The source electrode 6 and drain electrode 4 are directly defined on the protective layer using photolithography, and the electrode area is ensured to be pure by plasma cleaning. A Ti / Al / Ni / Au metal stack is then deposited sequentially from bottom to top using electron beam evaporation. Rapid thermal annealing is performed immediately after metal growth.

[0057] S4. Define the gate electrode pattern using electron beam lithography. A multilayer Ni / Au metal is directly grown on the protective layer using electron beam evaporation, and the gate electrode is made independent using a lift-off process.

[0058] Optionally, in this example, the thickness of the cryogenic protective layer is 5 nm, and the growth temperature is 300 °C.

[0059] Optionally, in the preparation process of the low-temperature protective layer in this example, the ratio of SiH4 to NH3 is 1.5:1.

[0060] In this example, the source electrode 6 and the drain electrode 4 are both defined and grown directly on the protective layer using photolithography, and are directly connected to the low-temperature protective layer.

[0061] In this example, the source electrode 6 and the drain electrode 4 are composed of stacked metals with the same structure, including a Ti layer, an Al layer, a Ni layer, and an Au layer from bottom to top. The thicknesses of the metal layers are 20 nm, 100 nm, 10 nm, and 100 nm, respectively.

[0062] In this example, the ohmic contact between the source electrode 6 and the drain electrode 4 is achieved by rapid thermal annealing on the protective layer.

[0063] Optionally, the annealing environment is N2, the annealing temperature is 850℃, and the annealing time is 30s.

[0064] In this example, the gate electrode 5 is equidistant from the source electrode 6 and the drain electrode 4. The gate electrode structure is type I. The gate electrode is defined by electron beam lithography and grows directly on the protective layer after the source and drain electrodes are fabricated.

[0065] Optionally, the gate electrode has a structure of stacked metal Ni / Au, with metal layer thicknesses of 20 / 300 nm.

[0066] In this example, the quaternary barrier epitaxial thickness is 700 nm.

[0067] Taking this device as an example, after growing a cryogenic protective layer and annealing at high temperature, elemental analysis was performed on the device surface and compared with a device without a protective layer. The elemental composition results of the device surface are shown in Table 2. It can be clearly seen that the cryogenic protective layer effectively controls In precipitation in the quaternary barrier, thus protecting the region under the gate.

[0068] Table 2

[0069]

[0070] The remaining process steps used in the above examples are all mature processes in the semiconductor industry, including low-temperature Si-rich Si. x The simple and easy growth of the N-protective layer indicates that the invention has significant advantages in improving process steps and increasing large-scale productivity, which is beneficial to the performance improvement, process optimization and large-scale manufacturing of millimeter-wave devices.

[0071] It should be emphasized that the embodiments of the present invention are not limited to the specific cases described above. The above embodiments are presented only as preferred examples among the many feasible implementations of the present invention, and are intended to provide a reference for understanding the technical solutions of the present invention, and are by no means intended to limit the scope of protection of the present invention in any way. For those skilled in the art, after fully understanding the technical content, inventive principles and core concepts disclosed in the present invention, they can make various modifications, adjustments and equivalent substitutions to the specific implementation forms, implementation steps, and combinations of technical features of the present invention based on the technical ideas disclosed in the present invention. These modifications and adjustments may involve multiple dimensions such as optimization of specific technical parameters, adjustment of the sequence of process flow, equivalent substitution of structural components, and changes in material selection. However, as long as these changes in technical means do not deviate from the basic principles of the present invention and do not exceed the core scope of the technical solution defined by the claims of the present invention, they should all be regarded as extensions and concretizations of the technical solution of the present invention.

Claims

1. A silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer, characterized by: A quaternary barrier epitaxial layer (1) with a GaN cap layer (2) and a low-temperature protective layer (3) grown on the GaN cap layer (2); a source electrode (6) and a drain electrode (4) forming an ohmic contact are respectively connected on the surface of the low-temperature protective layer (3) to form a Schottky contact gate electrode (5); the gate electrode (5) is located between the source electrode (6) and the drain electrode (4).

2. The silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to claim 1. Its characteristic is that... The low-temperature protective layer (3) has a growth temperature of ≤300℃ and is located above the epitaxial cap layer (2). Its growth thickness is less than 5nm and greater than 1nm.

3. The silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to claim 1, characterized in that, The low-temperature protective layer is made of Si-rich Si grown by PECVD equipment. x The composition is N, and the ratio of SiH4 to NH3 during its growth is 0.55 to 1.45:1, where the value of x ranges from 0.55 to 1.

45.

4. The silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to claim 1, characterized in that, The gate electrode (5) has a T-shaped structure, with the gate pin perpendicular to the device surface and the gate cap located above the gate pin and connected to the gate pin.

5. The silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to claim 1, characterized in that, The gate electrode (5) is composed of stacked metals, including a Ni layer and an Au layer from bottom to top, with the thickness of the metal layers being between 10-50 nm and 150-500 nm, respectively.

6. The silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to claim 1, characterized in that, The distance between the T-type gate electrode and the source electrode (6) is greater than or equal to 500 nm, and the maximum distance is equal to the distance between the T-type gate electrode and the drain electrode (4), and less than or equal to 3 μm.

7. The silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to claim 1, characterized in that, The source electrode (6) and the drain electrode (4) are composed of the same stacked metal structure, including Ti layer, Al layer, Ni layer and Au layer from bottom to top. The thickness of each layer is 10-25nm, 85-150nm, 5-15nm and 85-150nm respectively, and the total thickness of the metal layers of the source electrode (6) and the drain electrode (4) is less than 310nm.

8. The silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer according to any one of claims 1 to 7, characterized in that, The quaternary barrier epitaxy is an InAlGaN barrier epitaxy, obtained by metal-organic chemical vapor deposition (MOCVD).

9. A method for fabricating a silicon-based quaternary barrier millimeter-wave device with a low-temperature protective layer as described in claim 1, characterized in that... Includes the following steps: Cleaning of quaternary barrier epitaxy (1): including soaking in piranha solution, soaking in organic solvents and soaking and cleaning in deionized water; S1. Preparation of the low-temperature protective layer (3): including the deposition of Si-rich Si using plasma-enhanced deposition technology under low-temperature conditions. x N; The growth rate of the cryogenic protective layer (3) is controlled by the gas flow rate, and the composition of the cryogenic protective layer (3) is controlled by the proportion of non-carrier gas; S2. Fabrication of source electrode (6) and drain electrode (4): including defining the pattern of source electrode (6) and drain electrode (4) using photolithography, forming a mask by photoresist, and growing stacked metal by electron beam evaporation; S3. Fabrication of gate electrode (5): This includes defining the pattern of T-type gate electrode (5) using electron beam lithography; growing stacked metal using electron beam evaporation; and achieving gate independence using a lift-off process.

10. The method according to claim 8, characterized in that, In step S3, the source electrode (6) and the drain electrode (4) are directly grown on the low-temperature protective layer (3) and simultaneously participate in annealing. The annealing environment is N2, the annealing temperature is 850-950℃, and the annealing time is 30-75s.

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