Photoelectric synapse device with enhanced nonvolatile performance and preparation method

Abstract

The invention discloses a photoelectric synapse device with enhanced nonvolatile performance and a preparation method, and belongs to the technical field of organic photoelectronics. The system comprises a substrate layer, an insulating layer, a barrier layer and a carrier transport layer which are sequentially stacked from bottom to top, and two metal electrodes are arranged on the top of the carrier transport layer in parallel and are respectively a source electrode and a drain electrode; the method comprises the steps of depositing an insulating layer on a substrate layer according to a first preset spin-coating process condition, growing a barrier layer on the insulating layer based on an atomic layer deposition method, adding a carrier transport layer on the barrier layer according to a second preset spin-coating process condition, and depositing two parallel metal electrodes on the carrier transport layer through a high-vacuum thermal evaporation technology, and a source electrode and a drain electrode. According to the invention, the sensing range of ultraviolet light can be covered, the detection sensitivity is high, the relaxation time of post-synaptic current is prolonged, and the non-volatility of the device is enhanced.

Description

Technical Field

[0001] This invention relates to the field of organic optoelectronics technology, specifically to a photoelectric synapse device with enhanced non-volatile properties and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence technology, further demands are being placed on the long-term information storage capabilities of neuromorphic devices. Non-volatile synaptic transistors (NTTs), integrating sensing, storage, and computing functions, have become a core direction for overcoming technological bottlenecks. In the traditional von Neumann architecture, modularity leads to data redundancy, and discrete storage units struggle to achieve long-term stable information retention, severely restricting the reliability and battery life of terminal devices. NTTs, with their core characteristic of minimal information loss, effectively solve the storage reliability problem of traditional architectures. In recent years, research in this field has continued to advance: polymer dielectric layer-based devices have achieved synaptic plasticity such as PPF, STP, and LTP by controlling charge trapping and releasing behavior; in biomimetic devices for artificial retina, designs based on photoelectric synaptic transistors have further optimized device performance, providing crucial support for the efficient operation of vision systems. Currently, the reliability of information retention under complex conditions has become a core requirement, directly driving the technological iteration of NTTs. Its core lies in overcoming the storage limitations of volatile devices, a prerequisite for building new machine vision systems. However, current technologies still face significant challenges: while oxide-based devices possess a certain degree of non-volatility, there is a compatibility conflict between high processing temperatures and flexible fabrication processes, and their storage stability will significantly decrease after long-term cyclic use; organic-based devices, with their advantages of low cost, low-temperature processing, flexible adaptation, and biocompatibility, can meet the needs of some application scenarios, but due to the insufficient stability of charge trapping sites, there is still considerable room for improvement in information retention time and cyclic reliability.

[0003] To address the aforementioned issues, there is an urgent need for an optoelectronic synaptic device and its fabrication method that enhances non-volatile performance, thereby resolving the problems inherent in traditional methods, improving the charge storage stability of non-volatile synaptic transistors, and extending the information retention time. Summary of the Invention

[0004] The purpose of this invention is to provide a photoelectric synaptic device and its fabrication method with enhanced non-volatile properties. This device can prevent charge carriers in the insulating layer from tunneling to the carrier transport layer and recombinizing under the influence of external voltage. It extends the postsynaptic current relaxation time and enhances the non-volatility of the device. Furthermore, it can be applied to neuromorphic computing. By using this enhanced non-volatile photoelectric synaptic device to construct computational neurons for memory in matrix operations, it demonstrates great potential for achieving handwritten digit recognition. By mimicking the working principles of biological nervous systems, these devices can simulate the adjustment of synaptic weights and the information processing of neurons, thereby achieving efficient pattern recognition tasks, such as handwritten digit recognition.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A photoelectric synaptic device with enhanced non-volatile properties includes: a substrate layer, an insulating layer, a barrier layer and a carrier transport layer stacked sequentially from bottom to top, wherein two metal electrodes are disposed parallel to each other on the top of the carrier transport layer, namely a source electrode and a drain electrode; The substrate layer is used to support the photoelectric synapse device; The insulating layer is a mixed material formed by organic polymer materials and organic lithium salts; The barrier layer is made of inorganic oxide and is used to isolate the insulating layer and the charge carrier transport layer. The carrier transport layer is a hybrid material formed by organic small molecule semiconductor material and inert polymer, used to absorb ultraviolet light; The source and drain are used to connect external electrical signals to the carrier transport layer to form a complete circuit.

[0006] Furthermore, the substrate layer is made of silicon, sapphire, PEN, or PI.

[0007] Furthermore, the organic polymer material of the insulating layer is polyvinyl alcohol, and the organic lithium salt in the insulating layer is lithium bis(trifluoromethanesulfonyl)imide.

[0008] Furthermore, the inorganic oxide of the barrier layer is aluminum oxide, hafnium oxide, or zirconium oxide.

[0009] Furthermore, the organic small molecule semiconductor material of the carrier transport layer is C8-BTBT, and the inert polymer is polystyrene.

[0010] Furthermore, the thickness of the insulating layer is 140-200nm, the thickness of the barrier layer is 5nm, the thickness of the carrier transport layer is 40-60nm, the source and drain are both made of aluminum, silver or gold with a thickness of 60nm-80nm, and the length of the conductive channel between the source and drain is 80μm and the width is 1000μm.

[0011] This invention also provides a method for fabricating a photoelectric synaptic device with enhanced non-volatile properties, applicable to the aforementioned photoelectric synaptic device with enhanced non-volatile properties, comprising: Step 1: Deposit an insulating layer on the substrate according to the first preset spin coating process conditions; Step 2: Based on atomic layer deposition, a barrier layer is grown on the insulating layer, wherein the temperature is maintained at 150°C during the formation of the barrier layer; Step 3: Add a carrier transport layer on the barrier layer according to the second preset spin coating process conditions; Step 4: Deposit two parallel metal electrodes on the carrier transport layer using high-vacuum thermal evaporation technology, serving as the source and drain electrodes.

[0012] Further, in step 1, according to the first preset spin-coating process conditions, an insulating layer is deposited on the substrate layer, specifically as follows: 0.22 g of polyvinyl alcohol and 0.10 g of lithium bis(trifluoromethanesulfonyl)imide were dissolved in 9.73 mL of a mixed solvent of deionized water and ethanol in an average ratio to obtain a mixed solution. The mixed solution was spin-coated onto the substrate at a spin coating speed of 3500 rpm for 40 seconds, and then annealed at 120°C for 60 minutes to obtain the insulating layer.

[0013] Furthermore, in step 3, according to the second preset spin coating process conditions, a carrier transport layer is added to the barrier layer, specifically as follows: Based on a spin coating speed of 1800 rpm, C8-BTBT and polystyrene were mixed at a mass ratio of 1:0.4 to obtain a C8-BTBT / PS solution; After spin-coating the C8-BTBT / PS solution onto the barrier layer for 40 seconds, the layer was annealed at 130°C for 20 minutes to obtain the carrier transport layer.

[0014] Furthermore, in step 4, two parallel metal electrodes are deposited on the carrier transport layer using high-vacuum thermal evaporation technology, serving as the source and drain electrodes, specifically: Based on high-vacuum thermal evaporation technology, source and drain electrodes are deposited on the surface of the carrier transport layer using a strip-shaped mask.

[0015] In summary, the present invention has at least one of the following beneficial technical effects: 1. Significantly enhanced non-volatile performance and extended information storage time: By introducing a dense inorganic oxide layer as a barrier layer, the tunneling and recombination of carriers trapped in the insulating layer into the transport layer under applied voltage is effectively suppressed. This allows the carrier concentration in the channel to remain at a high level for a long time after light stimulation, thereby significantly extending the relaxation time of the postsynaptic current and greatly improving the device's information retention capability and non-volatility, meeting the long-term memory requirements of artificial intelligence systems.

[0016] 2. Enhancing UV Light Sensing Sensitivity and Synaptic Plasticity Simulation Capability: The device employs an organic semiconductor material with characteristic absorption of UV light as the carrier transport layer, enabling it to effectively sense UV light signals outside the range of human vision. Experiments show that the device's postsynaptic current response exhibits a clear dependence on the power, number, and duration of UV light pulses, successfully simulating key behaviors of biological synapses such as short-term plasticity, pulse intensity dependence, and pulse number dependence, laying the foundation for constructing a high-performance artificial vision system.

[0017] 3. Compatible with low-temperature fabrication processes, suitable for flexible electronics: The entire device fabrication process, including spin coating of the polymer insulating layer, atomic layer deposition of the barrier layer, and spin coating of the organic semiconductor layer, has a critical process temperature not exceeding 150℃. This all-low-temperature fabrication process is highly compatible with flexible substrates, avoiding damage to flexible materials caused by high-temperature processes, and providing a reliable technical path for developing wearable, flexible neuromorphic computing and sensing devices.

[0018] 3. Simple fabrication process, conducive to large-area, low-cost manufacturing: Except for the substrate, metal electrode evaporation, and atomic layer deposition barrier layer, the core functional layers of the device (insulating layer, carrier transport layer) can all be prepared by solution spin coating. This process has low equipment requirements, fast film formation speed, and high material utilization, which is very conducive to realizing large-area, uniform, and low-cost manufacturing of devices, and has the potential for industrial application.

[0019] 4. Excellent performance in neuromorphic computing: Based on the device's extended relaxation time and good photoelectric response characteristics, it can accurately simulate the long-term enhancement and long-term inhibition behaviors of biological synapses. Using its conductance change curve as a weight update rule, a single-layer perceptron neural network was constructed for MNIST handwritten digit recognition simulation, improving recognition accuracy and demonstrating practical value in high-efficiency, low-power neuromorphic computing hardware. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a photoelectric synapse device with enhanced non-volatile properties provided in the embodiments of this application; Figure 2This is a schematic diagram of the scan transfer curves of an opto-synaptic device with enhanced non-volatile properties under different gate-source voltages. Figure 3 This is a schematic diagram of the scan output curves of an opto-synaptic device with enhanced non-volatile properties under different drain-source voltages. Figure 4 This is a schematic diagram of the ultraviolet-visible absorption spectra of each layer in the photoelectric synaptic device with enhanced non-volatile properties in the embodiments of this application; Figure 5 A schematic diagram showing the change of postsynaptic current in a photoelectric synaptic device with enhanced non-volatile properties under stimulation by ultraviolet light pulses of different power. Figure 6 A schematic diagram showing the change in postsynaptic current of an opto-synaptic device with enhanced non-volatile properties under stimulation with different numbers of ultraviolet light pulses; Figure 7 A schematic diagram of the relaxation time fitted to the postsynaptic current of an opto-synaptic device with enhanced non-volatile properties. Figure 8 This is a schematic diagram of carrier diffusion in each layer of a photoelectric synaptic device with enhanced non-volatile properties under a negative gate voltage. Figure 9 This is a schematic diagram showing the conductance change of an opto-synaptic device with enhanced non-volatile properties under multi-pulse action. Figure 10 A schematic diagram illustrating the recognition results of handwritten digits by constructing an artificial neural network using the characteristics of photoelectric synaptic devices with enhanced non-volatile properties; Figure 11 This is a schematic flowchart illustrating a method for fabricating an optoelectronic synaptic device with enhanced non-volatile properties, as provided in an embodiment of this application.

[0021] Reference numerals: 1. Substrate; 2. Insulating layer; 3. Barrier layer; 4. Carrier transport layer; 5. Source; 6. Drain. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0023] like Figure 1As shown, the present invention provides a photoelectric synapse device with enhanced non-volatile performance, comprising: a substrate layer 1, an insulating layer 2, a barrier layer 3 and a carrier transport layer 4 stacked sequentially from bottom to top, wherein two metal electrodes are arranged in parallel on the top of the carrier transport layer 4, namely a source electrode 5 and a drain electrode 6. The substrate layer 1 is used to support the photoelectric synapse device and serves as the bottom gate electrode; The insulating layer 2 is a mixed material formed by organic polymer materials and organic lithium salts; The barrier layer 3 is made of inorganic oxide. The barrier layer 3 is used to isolate the insulating layer 2 and the charge carrier transport layer 4, preventing the charge carriers in the insulating layer 2 from tunneling to the charge carrier transport layer 4 and recombinating under the action of external voltage. The concentration of charge carriers in the charge carrier transport layer 4 can be maintained at a high level, the relaxation time of the postsynaptic current is prolonged, and the non-volatility of the device is enhanced. The carrier transport layer 4 is a hybrid material formed by organic small molecule semiconductor material and inert polymer, which is used to absorb ultraviolet light and generate and transport photogenerated carriers under ultraviolet light irradiation, simulating the behavior of synaptic plasticity. The source 5 and drain 6 are used to connect external electrical signals to the carrier transport layer 4 to form a complete circuit.

[0024] It should be noted that the photoelectric synaptic device is fabricated at low temperatures, with the preset temperature range corresponding to low temperatures being below 150°C.

[0025] The substrate layer 1 is made of silicon, sapphire, PEN or PI.

[0026] The organic polymer material of the insulating layer 2 is polyvinyl alcohol, and the organic lithium salt of the insulating layer 2 is lithium bis(trifluoromethanesulfonyl)imide.

[0027] The inorganic oxide of the barrier layer 3 is hafnium oxide, aluminum oxide, or zirconium oxide.

[0028] The organic small molecule semiconductor material of the carrier transport layer 4 is C8-BTBT, and the inert polymer is polystyrene.

[0029] The insulating layer 2 has a thickness of 140-200 nm, the barrier layer 3 has a thickness of 5 nm, the carrier transport layer 4 has a thickness of 40-60 nm, the source 5 and drain 6 are both made of aluminum, silver or gold with a thickness of 60 nm-80 nm, and the conductive channel between the source 5 and drain 6 has a length of 80 μm and a width of 1000 μm.

[0030] In practical applications, the length of the conductive channel between two metal electrodes can range from 20 to 200 μm, and the width can range from 300 to 2000 μm.

[0031] like Figure 11 As shown, the present invention also provides a method for fabricating a photoelectric synaptic device with enhanced non-volatile properties, applicable to the aforementioned photoelectric synaptic device with enhanced non-volatile properties, comprising: Step 1: Deposit an insulating layer 2 on substrate 1 according to the first preset spin coating process conditions; Step 2: Based on atomic layer deposition, a barrier layer 3 is grown on the insulating layer 2, wherein the temperature is maintained at 150°C during the formation of the barrier layer 3. Step 3: According to the second preset spin coating process conditions, add a carrier transport layer 4 on the barrier layer 3; Step 4: Deposit two parallel metal electrodes on the carrier transport layer 4 using high-vacuum thermal evaporation technology, serving as the source 5 and drain 6.

[0032] In step 1, according to the first preset spin-coating process conditions, an insulating layer 2 is deposited on the substrate layer 1, specifically as follows: 0.22 g of polyvinyl alcohol and 0.10 g of lithium bis(trifluoromethanesulfonyl)imide were dissolved in 9.73 mL of a mixed solvent of deionized water and ethanol in an average ratio to obtain a mixed solution. The mixed solution was spin-coated onto substrate 1 at a spin coating speed of 3500 rpm for 40 seconds, and then annealed at 120°C for 60 minutes to obtain insulating layer 2.

[0033] In step 3, according to the second preset spin coating process conditions, a carrier transport layer 4 is added to the barrier layer 3, specifically as follows: Based on a spin coating speed of 1800 rpm, C8-BTBT and polystyrene were mixed at a mass ratio of 1:0.4 to obtain a C8-BTBT / PS solution; After spin-coating the C8-BTBT / PS solution onto the barrier layer 3 for 40 seconds, the layer was annealed at 130°C for 20 minutes to obtain the carrier transport layer 4.

[0034] In step 4, two parallel metal electrodes are deposited on the carrier transport layer 4 using high-vacuum thermal evaporation technology, serving as the source 5 and drain 6, specifically: Based on high-vacuum thermal evaporation technology, source electrode 5 and drain electrode 6 are deposited on the surface of carrier transport layer 4 using strip-shaped mask template; Specifically: The metal material is placed in a tungsten boat, and high-vacuum thermal evaporation technology is used (the metal material melts, evaporates and rises, and is deposited on the carrier transport layer 4). Combined with a strip-shaped mask, two parallel metal electrodes, namely source 5 and drain 6, are deposited on the transport layer. The conductive channel between source 5 and drain 6 has a length of 80μm and a width of 1000μm. The conductive channel is the interval between source 5 and drain 6. In this process, inert polymer polystyrene is dissolved in chloroform to prepare a 2.6 mg / mL polystyrene solution. Using a micropipette, the polystyrene solution and chloroform are added to C8-BTBT powder at a doping concentration of 30-40 wt% to obtain a C8-BTBT / polystyrene mixed solution. The C8-BTBT / polystyrene mixed solution is dropped onto the surface of barrier layer 3, and a C8-BTBT film with a thickness of 40-60 nm is formed by spin coating. The C8-BTBT film is then subjected to heat treatment at a preset time and temperature to complete the preparation of carrier transport layer 4. The preset time is 20 minutes, and the preset temperature is 130 °C.

[0035] This application employs low-temperature fabrication of photoelectric signal modulation. The blocking layer in the synaptic device prevents charge carriers in the insulating layer 2 from tunneling to the charge carrier transport layer 4 and recombinizing under the influence of external voltage, thus prolonging the postsynaptic current relaxation time and enhancing the non-volatility of the device. Subsequently, the device's different responses to light stimulation were tested. Under light signals, the device effectively simulated basic biological synaptic functions, such as pulse-time-dependent, pulse-intensity-dependent, and pulse-number-dependent pulses. By inserting a water-soluble polymer layer in the middle of the device, the hydroxyl groups within it attract electrons to regulate the channel conductivity. Furthermore, each thin film layer of the device is fabricated at low temperatures, ensuring good compatibility with the fabrication of flexible wearable devices. The device's neuromorphic computing capabilities under light-assisted conditions were also simulated and tested.

[0036] Next, this invention provides an embodiment illustrating that, in practical applications, the photoelectric synaptic device (hereinafter referred to as the synaptic device or device) with enhanced non-volatile properties of this application achieves photomodulation of synaptic plasticity under the stimulation of ultraviolet light signals, and on this basis, simulates artificial visual functions. Specifically, the photoelectric synaptic device includes a substrate layer 1, an insulating layer 2, a barrier layer 3, a carrier transport layer 4, a source electrode 5, and a drain electrode 6, which are sequentially stacked. The thickness of the carrier transport layer 4 is 40nm-70nm. The carrier transport layer 4 is prepared by eccentric spin coating, and the preferred spin coating speed is 1600r / min-2000r / min.

[0037] Preferably, the insulating layer 2 is a spin-coated PVA polymer insulating layer, and the spin-coating speed is preferably 3500 r / min to 4000 r / min.

[0038] Preferably, the spacing between the metal electrode pairs is 80 μm. The source electrode 5 and the drain electrode 6 are made of metallic conductive materials.

[0039] In practical applications, the device structure is as follows: Figure 1As shown, the photoelectric synaptic device with enhanced non-volatile properties is fabricated at low temperature. The device includes a substrate layer 1, an insulating layer 2, a barrier layer 3, a carrier transport layer 4, a source electrode 5, and a drain electrode 6.

[0040] The substrate layer 1 is the gate, which is made of ITO (indium tin oxide) electrode or doped silicon and is used to apply electrical stimulation signals. The carrier transport layer 4 is disposed between the barrier layer 3 and the top electrode and is used to simulate synaptic plasticity under light stimulation. It has a positive light response to ultraviolet light stimulation. The top electrode is the source 5 and the drain 6.

[0041] In this application, the substrate layer 1 is a silicon (Si) substrate, which can also be PI (Polyimide), a thin copper sheet, or PEN (Polyethylene Naphthalate).

[0042] In this application, the insulating layer 2 is a mixture of polyvinyl alcohol (PVA) and lithium bis(trifluoromethane)sulfon-imide (Li-TFSI).

[0043] In this application, the barrier layer 3 is aluminum oxide, but it can also be other inorganic metal oxide materials, such as hafnium oxide, zirconium oxide, etc.

[0044] In this application, the carrier transport layer 4 is a small molecule semiconductor material C8-BTBT, whose chemical name is 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene. It can also be other semiconductor materials, such as PDVT-10, P3HT, etc.

[0045] In this application, the source 5 and drain 6 are preferably Ag; the silicon-doped substrate 1 serves as the gate of the photoelectric synaptic device with enhanced non-volatile properties.

[0046] In practical applications, the photoelectric synaptic device with enhanced non-volatile properties of this application can be fabricated using the following methods: Figure 1 In the structure shown, highly doped Si (silicon) is used as the substrate. The SiO2 / Si substrate is cleaned with acetone, isopropanol and deionized water and then dried with a nitrogen stream.

[0047] 0.22 g of polyvinyl alcohol and 0.10 g of lithium bis(trifluoromethanesulfonyl)imide were dissolved in 9.73 mL of a mixed solvent of deionized water and ethanol in an average ratio to obtain a mixed solution. The prepared solution was dropped onto substrate layer 1, and a PVA film of approximately 150 nm was formed by spin coating. The film was then heat-treated for 1 hour at a temperature of 120 °C to obtain insulating layer 2.

[0048] A 5 nm aluminum oxide film was grown on insulating layer 2 using ALD at a growth temperature of 150 °C to obtain barrier layer 3.

[0049] Polystyrene was dissolved in chloroform to prepare a concentration of 2.6 mg / mL. The polystyrene solution was then added to C8-BTBT powder using a micropipette to achieve a doping concentration of 40 wt%. Finally, chloroform was added to adjust the C8-BTBT concentration to 6.5 mg / mL. The prepared solution was then dropped onto the barrier layer 3, and a 60 nm thick C8-BTBT / PS film was formed by spin coating. The film was then heat-treated in air for 20 min at a temperature of 130 °C to obtain the carrier transport layer 4.

[0050] Finally, a 60nm thick Ag layer was grown using a mask and vacuum evaporation method to serve as the source and drain electrodes of the metal electrodes.

[0051] Except for the metal electrode and the barrier layer, all other steps in the preparation method provided in this embodiment can be operated at room temperature under atmospheric conditions.

[0052] Among them, the photoelectric performance test of photoelectric synaptic devices with enhanced non-volatile properties is carried out using a certain type of semiconductor characteristic analyzer test system with a probe station.

[0053] Figure 1 This is a schematic diagram of a photoelectric synaptic device with enhanced non-volatility. The device has a bottom-gate top-electrode structure. The topmost layer, C8-BTBT / PS, serves as the carrier transport layer 4. C8-BTBT / PS is a relatively stable semiconductor material in atmospheric conditions, and the thin film is prepared using a solution method. Next, the second layer is a barrier layer 3, which is a 5nm alumina thin film. Finally, polyvinyl alcohol (PVA) is placed below the barrier layer 3. The alumina thin film is prepared by ALD (atomic layer deposition). The highly dense alumina thin film effectively prevents carriers in the insulating layer 2 from tunneling to the carrier transport layer 4 and recombinating under the influence of external voltage. This prolongs the relaxation time of the postsynaptic current and enhances the non-volatility of the device.

[0054] like Figure 2As shown, different scanning voltages were applied to the device and the transfer curves were tested. The image shows that a hysteresis loop was generated as the scanning voltage changed. The hysteresis loop indicates that the device can simulate memory storage and synaptic behavior.

[0055] like Figure 3 As shown, the device was subjected to different drain-source voltages and the output curves were tested. As the absolute value of the gate voltage gradually increased, the absolute value of the drain-source current also gradually increased. The linear region and the saturation region are clearly visible, both exhibiting typical p-type field-effect characteristics and good saturation properties.

[0056] Figure 4 The diagram shows the UV-Vis absorption spectra of each layer in the synaptic device, revealing that the main absorption wavelength is approximately 365 nm. The device can sense ultraviolet light imperceptible to humans and exhibits different sensing characteristics for different wavelengths of light within the ultraviolet range.

[0057] Figure 5 The changes in postsynaptic current under stimulation with ultraviolet light pulses of different powers are shown. It can be observed that as the ultraviolet light power increases from 0.13 mW / cm², the changes in postsynaptic current become more pronounced. 2 It rose to 6.93 mW / cm 2 At the same time, the maximum response current EPSC also increased from 0.25μA to 4.13μA, indicating that the synaptic plasticity of the device is dependent on the power of the optical pulse.

[0058] Figure 6 The device's response current to different numbers of optical pulses is shown. It can be seen that as the number of pulses increases from 5 to 30, the maximum response current EPSC also increases from 0.96 μA to 1.92 μA (wavelength 365 nm, optical power density 1 mW / cm²). 2 This indicates that the synaptic plasticity of the device depends on the number of light pulses.

[0059] The information storage capacity and performance of synapses are particularly important for artificial synapses, especially as the amount of data that devices need to receive continues to increase with the development of next-generation information technology. Therefore, the relaxation time of the postsynaptic current was further fitted to the device. Illumination was maintained at 1mW / cm². 2 The light, with a wavelength of 365nm, lasts for 5 seconds. For example... Figure 7 The device shown achieved a relaxation time of 480.53 seconds for fitting the postsynaptic current under light pulse irradiation, with an error of 36.12 seconds.

[0060] Figure 8The diagram illustrates the diffusion of carriers in each layer of a photoelectric synaptic device with enhanced non-volatile properties under a negative gate voltage. It can be seen that due to the tunneling barrier and hole blocking characteristics of Al2O3, the diffusion of electrons in the dielectric layer into the semiconductor and their recombination with holes in the semiconductor are restricted. At the same time, the potential well formed by the channel layer and the barrier layer 3 can stably capture the stored holes, keeping the hole concentration in the channel at a high level. The relaxation time of the postsynaptic current between the source 5 and the drain 6 is prolonged, thereby enhancing the non-volatile memory function.

[0061] In the research of photoelectric synaptic devices with enhanced non-volatile properties, long-term potency (LTP) and long-term depression (LTD) characteristics are key to simulating the learning and memory behaviors of biological neurons. By applying different photoelectric pulse patterns to modulate the plasticity of the device, changes in synaptic weights can be mimicked and artificial neural networks can be constructed.

[0062] The device's capabilities in neuromorphic computing were further explored, and its LTP / LTD performance was tested. The LTP / LTD characteristic curves of the device under photoelectric pulse irradiation were measured. DS The drain voltage is fixed at -3V. A voltage V is applied to the device during the LTP phase. GS Amplitude -3V, while applying auxiliary illumination to the device (illuminance 1mW / cm²) for testing. 2 The wavelength is 365nm, the duration is 0.5 seconds, and the interval is 0.05 seconds. During the LTD stage, only a voltage V is applied to the device. GS Amplitude 20V, duration 0.5 seconds, interval 0.05 seconds, such as Figure 8 The device shown exhibits good repeatability under multi-pulse stimulation conditions. (Refer to...) Figure 9 We can observe the conductance changes of photoelectric synaptic devices with enhanced non-volatile properties under multi-pulse action, namely, Long-Term Potentiation (LTP) and Long-Term Depression (LTD) behaviors. Based on the LTP / LTD synaptic weight update curves under these two conditions, an artificial neural network using a single-layer perceptron was simulated and trained. The network was then used for supervised learning to recognize MNIST handwritten digits. MNIST (Modified National Institute of Standards and Technology database) is a classic dataset widely used for image classification tasks. Figure 10As shown, after 50 epochs of training, the recognition accuracy of the device reached 91.64% with the barrier layer 3 added, compared to 90.82% without the barrier layer 3, demonstrating the device's neuromorphic computing capabilities.

[0063] Embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0064] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0065] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0066] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0067] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A photoelectric synaptic device with enhanced non-volatile properties, characterized in that, include: The substrate layer, insulating layer, barrier layer and carrier transport layer are stacked sequentially from bottom to top. Two metal electrodes are arranged in parallel on the top of the carrier transport layer, which are the source and the drain, respectively. The substrate layer is used to support the photoelectric synapse device; The insulating layer is a mixture of organic polymer materials and organic lithium salts. The barrier layer is made of inorganic oxide and is used to isolate the insulating layer and the charge carrier transport layer. The carrier transport layer is a hybrid material formed by organic small molecule semiconductor material and inert polymer, used to absorb ultraviolet light; The source and drain are used to connect external electrical signals to the carrier transport layer to form a complete circuit.

2. The photoelectric synaptic device with enhanced non-volatile properties according to claim 1, characterized in that, The substrate layer is made of silicon, sapphire, PEN, or PI.

3. The photoelectric synaptic device with enhanced non-volatile properties according to claim 1, characterized in that, The organic polymer material of the insulating layer is polyvinyl alcohol, and the organic lithium salt in the insulating layer is lithium bis(trifluoromethanesulfonyl)imide.

4. A photoelectric synaptic device with enhanced non-volatile properties according to claim 1, characterized in that, The inorganic oxide of the barrier layer is hafnium oxide, aluminum oxide, or zirconium oxide.

5. A photoelectric synaptic device with enhanced non-volatile properties according to claim 1, characterized in that, The organic small molecule semiconductor material of the charge carrier transport layer is C8-BTBT, and the inert polymer is polystyrene.

6. A photoelectric synaptic device with enhanced non-volatile properties according to claim 1, characterized in that, The thickness of the insulating layer is 140-200nm, the thickness of the barrier layer is 5nm, the thickness of the carrier transport layer is 40-60nm, the source and drain are both made of aluminum, silver or gold with a thickness of 60nm-80nm, and the length of the conductive channel between the source and drain is 80μm and the width is 1000μm.

7. A method for fabricating a photoelectric synaptic device with enhanced non-volatile properties, applied to the photoelectric synaptic device with enhanced non-volatile properties as described in any one of claims 1-6, characterized in that, include: Step 1: Deposit an insulating layer on the substrate according to the first preset spin coating process conditions; Step 2: Based on atomic layer deposition, a barrier layer is grown on the insulating layer, wherein the temperature is maintained at 150°C during the formation of the barrier layer; Step 3: Add a carrier transport layer on the barrier layer according to the second preset spin coating process conditions; Step 4: Deposit two parallel metal electrodes on the carrier transport layer using high-vacuum thermal evaporation technology, serving as the source and drain electrodes.

8. The method for fabricating a photoelectric synaptic device with enhanced non-volatile properties according to claim 7, characterized in that, In step 1, an insulating layer is deposited on the substrate according to the first preset spin-coating process conditions, specifically as follows: 0.22 g of polyvinyl alcohol and 0.10 g of lithium bis(trifluoromethanesulfonyl)imide were dissolved in 9.73 mL of a mixed solvent of deionized water and ethanol in an average ratio to obtain a mixed solution. The mixed solution was spin-coated onto the substrate at a spin coating speed of 3500 rpm for 40 seconds, and then annealed at 120°C for 60 minutes to obtain the insulating layer.

9. The method for fabricating a photoelectric synaptic device with enhanced non-volatile properties according to claim 8, characterized in that, In step 3, according to the second preset spin coating process conditions, a carrier transport layer is added on the barrier layer, specifically as follows: Based on a spin coating speed of 1800 rpm, C8-BTBT and polystyrene were mixed at a mass ratio of 1:0.4 to obtain a C8-BTBT / PS solution; After spin-coating the C8-BTBT / PS solution onto the barrier layer for 40 seconds, the layer was annealed at 130°C for 20 minutes to obtain the carrier transport layer.

10. The method for fabricating a photoelectric synaptic device with enhanced non-volatile properties according to claim 9, characterized in that, In step 4, two parallel metal electrodes are deposited on the carrier transport layer using high-vacuum thermal evaporation technology, serving as the source and drain electrodes, specifically: Based on high-vacuum thermal evaporation technology, source and drain electrodes are deposited on the surface of the carrier transport layer using a strip-shaped mask.

Images