Method for manufacturing a metal silicide barrier layer and semiconductor device

Abstract

The present disclosure discloses a preparation method of a metal silicide barrier layer and a semiconductor device. The preparation method comprises: preparing a semiconductor device structure, the semiconductor device structure comprising: a substrate, a gate structure located above the substrate, an oxide layer, and a silicon nitride layer, wherein the oxide layer covers surfaces of the substrate and the gate structure, the oxide layer is treated by a density enhancement process, and the silicon nitride layer is located on sidewalls of the gate structure and covers the oxide layer; oxidizing the silicon nitride layer to oxidize part of the silicon nitride layer into a silicon oxide layer; and simultaneously removing the silicon oxide layer and the oxide layer above the substrate and on top of the gate structure by a wet etching process to obtain a metal silicide barrier layer, the metal silicide barrier layer comprising: the oxide layer and the silicon nitride layer located on the sidewalls of the gate structure. Through the scheme of the embodiment of the present disclosure, a metal silicide barrier layer with good morphology can be formed, thereby preventing the semiconductor device structure from being further damaged and metal silicide from laterally diffusing to the channel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the technical field of semiconductor manufacturing. More particularly, the present disclosure relates to a method for manufacturing a metal silicide block layer and a semiconductor device. BACKGROUND

[0002] In the process of manufacturing metal silicide of integrated circuits, metal silicide needs to be formed in the active region of most areas, but the active region of some areas, such as high-resistance polysilicon region and isolated active region, cannot form metal silicide. In order to ensure the accuracy of the region where the metal silicide is formed and guarantee the stability of the semiconductor device, a metal silicide block layer (SAB, Salicide Block Layer) is usually formed in the predetermined region before the metal silicide is manufactured, so as to protect the sensitive region of the semiconductor device in the subsequent etching process and provide a basis for the formation of metal silicide.

[0003] In the existing SAB manufacturing process, dry etching combined with wet etching is usually used to etch the SAB, so as to remove part of the SAB and expose the substrate region and the polysilicon gate where metal silicide needs to be formed. However, in the existing process, the top and bottom of the SAB are often over-etched, which leads to the formation of a concave topography at the top and bottom of the SAB, thereby affecting the accuracy of the metal silicide formation region and causing the semiconductor device to fail.

[0004] Therefore, it is urgent to provide a manufacturing scheme of a metal silicide block layer to solve the problem of over-etching of the top and bottom of the SAB, improve the etching topography of the metal silicide block layer, and guarantee the reliability of the semiconductor device. SUMMARY

[0005] In order to at least solve one or more technical problems mentioned above, the present disclosure provides a manufacturing scheme of a metal silicide block layer in various aspects.

[0006] In a first aspect, the present disclosure provides a method for manufacturing a metal silicide block layer, comprising: manufacturing a semiconductor device structure, the semiconductor device structure comprising: a substrate, a gate structure located above the substrate, an oxide layer, and a silicon nitride layer, wherein the oxide layer covers the surface of the substrate and the gate structure, the oxide layer is treated by a density enhancement process, and the silicon nitride layer is located on the sidewall of the gate structure and covers the oxide layer; oxidizing the silicon nitride layer to oxidize part of the silicon nitride layer into a silicon oxide layer; and simultaneously removing the silicon oxide layer and the oxide layer located above the substrate and on the top of the gate structure by a wet etching process to obtain a metal silicide block layer, the metal silicide block layer comprising: the oxide layer and the silicon nitride layer located on the sidewall of the gate structure.

[0007] In some embodiments, the densification enhancement process comprises a high-density plasma process, wherein the method of fabricating the semiconductor device structure comprises: fabricating a gate structure on a substrate; depositing a growth oxide layer on a surface of the substrate and the gate structure; increasing a density of the oxide layer by a high-density plasma process treatment; depositing a growth silicon nitride layer on the oxide layer; and removing the silicon nitride layer above the substrate and on top of the gate structure by a dry etching process.

[0008] In some embodiments, wherein oxidizing the silicon nitride layer comprises: oxidizing the silicon nitride layer by a high-density plasma process.

[0009] In some embodiments, wherein before the silicon oxide layer and the oxide layer above the substrate and on top of the gate structure are simultaneously removed by the wet etching process, the method of fabricating further comprises: introducing ions to the oxide layer in a direction perpendicular to the substrate to increase an etching rate of the oxide layer above the substrate.

[0010] In some embodiments, wherein increasing the density of the oxide layer by the high-density plasma process treatment comprises: performing a high-density plasma treatment on the oxide layer at a temperature range of 350-550 °C, a discharge power range of 6000-12000 W, and a pressure range of 3-10 mtorr.

[0011] In some embodiments, wherein oxidizing the silicon nitride layer by the high-density plasma process comprises: performing a high-density plasma oxidation treatment on the silicon nitride layer with an oxygen-containing gas as a reaction medium at a temperature range of 350-550 °C, a discharge power range of 10000-18000 W, and a pressure range of 3-20 mtorr.

[0012] In some embodiments, the oxidation thickness of the silicon nitride layer is in a range of 5-15 nm, and the thickness of the silicon oxide layer is in a range of 5-15 nm.

[0013] In some embodiments, wherein introducing ions to the oxide layer in a direction perpendicular to the substrate comprises: introducing hydrogen ions to the oxide layer in a direction perpendicular to the substrate by an inductively coupled plasma process or a high-density plasma process with a hydrogen-containing gas.

[0014] In some embodiments, after increasing the density of the oxide layer by the high-density plasma process treatment, the method of fabricating further comprises: repeating alternately performing the step of depositing the growth oxide layer and the step of increasing the density of the oxide layer by the high-density plasma process treatment until the thickness of the oxide layer reaches a preset value.

[0015] In a second aspect, the present disclosure provides a semiconductor device comprising: a substrate, a gate structure and a metal silicide barrier layer above the substrate; wherein the metal silicide barrier layer covers the sidewall of the gate structure, and the metal silicide barrier layer is prepared by performing the preparation method of any one of the first aspect.

[0016] The unexpected technical effect of the present application is that: through the preparation method of the metal silicide barrier layer as provided above, the embodiments of the present disclosure improve the density of the oxide layer through the density enhancement process, reduce the wet etching rate of the oxide layer, and convert part of the silicon nitride layer to the silicon oxide layer through the oxidation process. The etching rate of this part of the structure during wet etching is higher than that of the unoxidized silicon nitride layer, thereby homogenizing the wet etching rate of the bottom and sidewall of the gate structure, i.e. the wet etching rate of the oxide layer above the substrate and the silicon oxide layer on the sidewall of the gate structure is similar, and thus the oxide layer above the substrate and the silicon oxide layer on the sidewall of the gate structure can be thinned simultaneously during wet etching. Since the barrier layer material on the sidewall of the gate structure, above the substrate and on the top of the gate structure is thinned simultaneously, after the silicon oxide layer on the sidewall of the gate structure and the oxide layer above the substrate and on the top of the gate structure are removed simultaneously through the wet etching process, excessive etching does not occur at the sidewall and bottom of the gate structure, the metal silicide barrier layer formed has a good appearance and does not have a concave appearance, and the reliability of the semiconductor device is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of a metal silicide barrier layer formed by an existing SAB preparation process is shown;

[0019] Figure 2 Another schematic diagram of a metal silicide barrier layer formed by an existing SAB preparation process is shown;

[0020] Figure 3 An exemplary flowchart of a preparation method of a metal silicide barrier layer according to some embodiments of the present disclosure is shown;

[0021] Figure 4 A flowchart of a preparation method of a metal silicide barrier layer according to some embodiments of the present disclosure is shown;

[0022] Figure 5 An exemplary flowchart of a preparation method of a semiconductor device structure according to some embodiments of the present disclosure is shown;

[0023] Figure 6 An exemplary flowchart illustrating a method of preparing a metal silicide barrier layer of some embodiments of the present disclosure is shown.

[0024] Figure 7 A flowchart illustrating a method of preparing a metal silicide barrier layer of some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present disclosure will be apparently and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person skilled in the art without creative work fall within the protection scope of the present disclosure.

[0026] It should be understood that the terms “comprising” and “including” used in the specification and claims of the present disclosure indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] It should also be understood that the terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless otherwise clear from context, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should be further understood that the term “and / or” used in the specification and claims of the present disclosure means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0028] As used in the specification and claims, the term “if’ can be interpreted as meaning “when” or “once” or “in response to a determination” or “in response to a detection” depending on the context. Similarly, the phrases “if determined” or “if detected [the described condition or event]” can be interpreted to mean “once determined” or “in response to a determination” or “once detected [the described condition or event]” or “in response to a detection [the described condition or event]” depending on the context.

[0029] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0030] Exemplary application scenarios

[0031] A metal silicide block layer (SAB) is a special structure layer used to prevent the formation of metal silicide in the semiconductor manufacturing process. Specifically, the SAB can prevent the formation of metal silicide in certain regions, thereby maintaining the high resistance characteristics of these regions. For example, in the metal silicide manufacturing process of an integrated circuit, in addition to the active regions of most regions, there are also active regions of some regions that cannot form metal silicide, such as high-resistance polysilicon regions and isolated active regions, etc. These regions need to be protected by pre-forming a metal silicide block layer.

[0032] In the existing SAB preparation process, dry etching combined with wet etching is usually used to etch the SAB, thereby removing part of the SAB to expose the substrate region and the polysilicon gate where metal silicide needs to be formed. However, in the existing process, over-etching occurs at the top and bottom of the SAB, forming a recessed topography.

[0033] Figure 1 FIG. 1 shows a schematic diagram of a metal silicide block layer formed by the existing SAB preparation process, Figure 2 FIG. 2 shows another schematic diagram of a metal silicide block layer formed by the existing SAB preparation process, as Figure 1 and Figure 2 shown, the existing SAB preparation process forms a recessed region at the top of the SAB, i.e., the top of the gate structure sidewall (the red dashed box in Figure 1 and Figure 2 ), which causes the material inside the gate structure to be exposed prematurely and can be further damaged in subsequent processes. As Figure 1 and Figure 2 shown, a recessed region is also formed at the bottom of the SAB, i.e., the bottom of the gate structure sidewall (the purple dashed box in Figure 1 and Figure 2 ), which causes the lateral width of the bottom opening to increase between adjacent gate structures, thereby causing the metal silicide to laterally diffuse to the channel during heat treatment, resulting in abnormal electrical test of the semiconductor device.

[0034] Exemplary application scenarios

[0035] Therefore, the present disclosure provides a preparation scheme for a metal silicide block layer, which improves the density of the oxide layer through a density enhancement process and converts part of the silicon nitride layer to a silicon oxide layer through oxidation processing, so that the wet etching rates of the bottom and sidewall of the gate structure are uniform, ensuring that they can be thinned simultaneously during wet etching and reducing the risk of recessed topography.

[0036] Figure 3 FIG. 3 shows an exemplary flowchart of a preparation method 300 for a metal silicide block layer according to some embodiments of the present disclosure, asFigure 3 As shown in step S301, a semiconductor device structure is prepared, which includes a substrate, a gate structure, an oxide layer, and a silicon nitride layer.

[0037] In step S302, the silicon nitride layer is subjected to an oxidation process to oxidize part of the silicon nitride layer into a silicon oxide layer.

[0038] In step S303, the silicon oxide layer and the oxide layer above the substrate and on the top of the gate structure are removed simultaneously by a wet etching process to obtain a metal silicide barrier layer.

[0039] In the semiconductor device structure shown in the embodiment, the gate structure is above the substrate, the oxide layer covers the surface of the substrate and the gate structure, and the silicon nitride layer is on the sidewall of the gate structure and covers the oxide layer. The oxide layer is subjected to a density enhancement process, and the increase in the density of the oxide layer leads to a decrease in the wet etching rate of the oxide.

[0040] Further, in actual applications, the oxide layer can include a first oxide layer and a second oxide layer. The first oxide layer covers the substrate and is between the substrate and the gate structure. The second oxide layer, also known as a buffer oxide layer, covers part of the surface of the gate structure and overlaps the first oxide layer and covers the substrate.

[0041] In the preparation process, the first oxide layer is an oxide layer formed by a normal pressure furnace tube process. In the preparation process, the silicon material substrate can be exposed to a high-temperature oxygen-containing environment for a certain period of time, so that a layer of silicon dioxide with good adhesion to the silicon substrate and high chemical stability and electrical insulation is grown on the surface of the substrate, i.e., the first oxide layer. Since the second oxide layer is prepared without exposure of the silicon substrate to air, the second oxide layer cannot be formed by a normal pressure furnace tube process. Due to the difference in preparation process, the density of the second oxide layer is lower than that of the first oxide layer, and the wet etching rate of the second oxide layer is greater than that of the first oxide layer. During wet etching, the oxide layer on the top and sidewall of the gate structure is prone to over-etching, which leads to the formation of a concave morphology. As can be seen from the above preparation process, in actual applications, the material of the oxide layer can be silicon oxide, i.e., both the first oxide layer and the second oxide layer can use silicon oxide material.

[0042] To solve the above problems, the oxide layer in the semiconductor device structure is subjected to a density enhancement process before preparation, specifically, the second oxide layer can be subjected to a density enhancement process to reduce its wet etching rate. Figure 4 A flowchart of a method for preparing a metal silicide barrier layer according to some embodiments of the present disclosure is shown in FIG. 3. Figure 4As shown, in step a, the grown oxide layer can be subjected to a density enhancement process. In some embodiments, the density of the oxide layer can be increased by a high-density plasma process (HDP), such as high-density plasma chemical vapor deposition (HDP-CVD). This process achieves high-quality film deposition by generating high-energy and high-density plasma, and is particularly suitable for filling gaps with high aspect ratios. The high-density plasma provides high ion flux and energy, thereby significantly improving the density and quality of the film.

[0043] As an example, in some embodiments, when performing a density-enhancing process on the oxide layer, high-density plasma treatment can be carried out within a temperature range of 350℃-550℃, a discharge power range of 6000W-12000W, and a pressure range of 3mtorr-10mtorr. The aforementioned discharge power range refers to the discharge power of the RF source in the high-density plasma process equipment; the higher the discharge power, the higher the plasma density and temperature. It should be noted that this embodiment does not impose strict limitations on the gas used for high-density plasma treatment; argon or other gases can be used, and no further restrictions are imposed here.

[0044] After the aforementioned density enhancement process, the wet etching rate of the oxide layer at the top of the gate structure and above the substrate is uniformized, enabling simultaneous thinning. In existing SAB fabrication processes, the formation of top and bottom recesses is also due to the inability to simultaneously etch and thin the gate structure sidewalls with the top and bottom of the gate structure; in other words, the reaction rates of the structural layers at the gate sidewalls and the top and bottom of the gate structure with the wet etchant are inconsistent. Therefore, after uniformizing the wet etching rate of the oxide layer at the top of the gate structure and above the substrate through the density enhancement process, this embodiment also requires oxidation of the silicon nitride layer located on the gate structure sidewalls to oxidize a portion of the silicon nitride layer into a silicon oxide layer. This makes the wet etching rate of the structural layers at the gate structure sidewalls more consistent with the wet etching rate of the oxide layers at the top and bottom of the gate structure.

[0045] like Figure 4 As shown, after step a is completed, the oxide layer is prepared. Next, step b is performed to deposit and grow a silicon nitride layer on the surface of the oxide layer after the density enhancement process. Then, step c is performed to etch away the silicon nitride layer located above the substrate and on top of the gate structure, while retaining the silicon nitride layer at the sidewall positions of the gate structure, thereby preparing the semiconductor device structure in step S301. After the semiconductor device structure is prepared, step S302 is performed, the process of which is as follows:Figure 4 In the process d in FIG. 1, the exposed silicon nitride layer is oxidized into a silicon oxide layer by an oxidation process. Since the second oxide layer and the silicon nitride layer are sequentially deposited on the surface of the sidewall of the gate structure, the N / O structure (N: nitride, O: oxide) is formed at the sidewall of the gate structure (the blue dashed line box in the process c in FIG. 1). Figure 4 In the process d in FIG. 1, the exposed silicon nitride layer is oxidized into a silicon oxide layer by an oxidation process. Since the second oxide layer and the silicon nitride layer are sequentially deposited on the surface of the sidewall of the gate structure, the N / O structure (N: nitride, O: oxide) is formed at the sidewall of the gate structure (the blue dashed line box in the process c in FIG. 1). Figure 4 In the process d in FIG. 1, the exposed silicon nitride layer is oxidized into a silicon oxide layer by an oxidation process. Since the second oxide layer and the silicon nitride layer are sequentially deposited on the surface of the sidewall of the gate structure, the N / O structure (N: nitride, O: oxide) is formed at the sidewall of the gate structure (the blue dashed line box in the process c in FIG. 1).

[0046] In some embodiments, the silicon nitride layer can be oxidized by a high-density plasma process. Further, the silicon nitride layer can be oxidized by a high-density plasma process at a temperature range of 350-550°C, a discharge power range of 10000-18000W, and a pressure range of 3-20mtorr, with an oxygen-containing gas as a reaction medium. The discharge power range refers to the discharge power of the RF source in the high-density plasma process equipment. The higher the discharge power, the higher the density and temperature of the plasma.

[0047] It should be noted that the silicon nitride layer can be oxidized by a high-density plasma process combined with an oxygen-containing auxiliary gas, including a combination of oxygen and argon, a combination of nitrous oxide and argon, or other oxygen-containing combination gas, which is not limited here.

[0048] The wet etching rates of the oxide layer and the silicon nitride layer before and after the high-density plasma process are shown below.

[0049]

[0050] In the above table, WER-before refers to the wet etching rate of the structure layer before the process, and WER-after refers to the wet etching rate of the structure layer after the process. The above data is obtained by experiment with 100:1 hydrofluoric acid solvent as the wet etchant. It should be noted that the silicon nitride layer is converted into a silicon oxide layer after the high-density plasma oxidation process, and therefore the WER-after in the row of the silicon nitride layer can also be understood as the wet etching rate of the silicon oxide layer, and the WER-before in the row of the silicon nitride layer essentially represents the wet etching rate of the silicon nitride layer.

[0051] According to the data in the above table, after the oxidation layer is subjected to the high-density plasma treatment and the silicon nitride layer is subjected to the high-density plasma oxidation treatment, the wet etching rates of the oxidation layer above the substrate, the oxidation layer on the top of the gate structure, and the silicon oxide layer on the sidewall of the gate structure are close to each other, so that the three can be thinned synchronously during the wet etching, thereby effectively avoiding the occurrence of the top recessed morphology and the bottom recessed morphology.

[0052] Referring to Figure 3 and Figure 4 , after the step S302 is performed, the step S303, i.e. Figure 4 , can be performed. Through the wet etching, a metal silicide barrier layer with a good morphology can be formed on the substrate and the surface of the gate structure, which includes the oxidation layer and the silicon nitride layer on the sidewall of the gate structure. In some embodiments, the metal silicide barrier layer can further include the oxidation layer partially on the substrate, which is located in the active region isolated from the active region not forming the metal silicide. It can be understood that the metal silicide barrier layer in the present embodiment can be a composite structure layer formed by multiple materials.

[0053] It should be noted that, in some embodiments, in order to prevent the small spacing between adjacent gate structures from causing the formation of a void between the adjacent gate structures and the formation of a defect when a thin film structure is subsequently deposited, the structure layer on the sidewall position of the gate structure will also be etched before the deposition process, so as to increase the spacing of the adjacent gate structures. At this time, it needs to be ensured that the structure layer on the sidewall position of the gate structure is the silicon nitride layer, so as to avoid the damage to the shallow trench isolation oxide by the etching process used.

[0054] Based on the above reasons, when the silicon nitride layer is subjected to the oxidation treatment, only part of the silicon nitride layer is oxidized, so as to oxidize part of the silicon nitride layer into the silicon oxide layer, thereby avoiding the oxidation of the entire silicon nitride layer into the silicon oxide layer. In some embodiments, the oxidation thickness of the silicon nitride layer can be controlled to be in the range of 5 nm-15 nm, i.e., the thickness of the silicon oxide layer formed by the oxidation treatment is in the range of 5 nm-15 nm. As an example, the above oxidation thickness range can be realized by controlling the oxidation time.

[0055] In the present embodiment, the high-density plasma process is performed on the oxidation layer in order to reduce the wet etching rate thereof, and the high-density plasma process is performed on the silicon nitride layer in order to increase the wet etching rate thereof. Therefore, the oxidation layer and the silicon nitride layer cannot be processed by the same high-density plasma process. In order to prevent the high-density plasma process on the oxidation layer from increasing the density of the silicon nitride layer and further reducing the wet etching rate thereof, the high-density plasma process is performed on the oxidation layer after the oxidation layer is prepared and formed.

[0056] Based on this, some embodiments of the present disclosure provide a semiconductor device structure preparation method, Figure 5 An exemplary flow chart of the semiconductor device structure preparation method 500 of some embodiments of the present disclosure is shown. It can be understood that the semiconductor device structure preparation method is a specific implementation of the foregoing step S301, and thus the foregoing features described in conjunction with Figure 3 the semiconductor device structure preparation method can be similarly applied.

[0057] As shown in FIG. 5, in step S501, a gate structure is prepared on a substrate; Figure 5

[0058] In step S502, an oxide layer is deposited and grown on the surface of the substrate and the gate structure;

[0059] In step S503, the density of the oxide layer is increased by a high-density plasma process treatment;

[0060] In step S504, a silicon nitride layer is deposited and grown on the oxide layer;

[0061] In step S505, the silicon nitride layer above the substrate and on the top of the gate structure is removed by a dry etching process.

[0062] In the present embodiment, the substrate can be made of silicon, and the gate structure includes a polysilicon gate. In some embodiments, a first oxide layer can be formed on the substrate by a normal pressure furnace tube process first, and then step S501 is performed to form the gate structure. At this time, by performing step S502, a second oxide layer is formed on the exposed first oxide layer and on the surface of the gate structure. Since the first oxide layer and the second oxide layer can be made of the same material, such as silicon oxide, the first oxide layer and the second oxide layer can be regarded as the same structure layer, i.e., an oxide layer, the structure of which is shown in process a of FIG. 6. Figure 4

[0063] In the present embodiment, the above steps S503 to S505 can be explained in conjunction with FIG. 7. Figure 4 Figure 5 Step S503 in FIG. 7 is shown in process a of FIG. 6, and the density of the oxide layer is enhanced by a high-density plasma process treatment after the oxide layer is prepared and formed. Then, process b of FIG. 7, i.e., the above step S504, is performed, so as to deposit and grow a layer of silicon nitride on the surface of the oxide layer. After that, in process c of FIG. 7, i.e., the above step S505, part of the silicon nitride layer is removed by a dry etching process, which specifically includes: removing the silicon nitride layer above the substrate and on the top of the gate structure, and retaining the silicon nitride layer on the sidewall of the gate structure. Figure 4 Figure 4 Figure 4

[0064] ​​​​​​As an example, the high-density plasma process can be used to enhance the density of the oxide layer, and the high-density plasma process can be performed at a temperature range of 350 °C to 550 °C, a discharge power range of 6000 W to 12000 W, and a pressure range of 3 mtorr to 10 mtorr.

[0065] It should be noted that the gas used in the high-density plasma process is not strictly limited, and argon or other gases can be used, which is not limited here.

[0066] Further, for some semiconductor devices with high requirements for oxide layer thickness, in order to ensure the uniformity of the density of the oxide layer after the high-density plasma process, steps S502 and S503 can be repeatedly performed alternately until the thickness of the oxide layer reaches the preset value, and then step S504 is performed.

[0067] In other words, if the thickness of the oxide layer to be prepared is large, when preparing the semiconductor device structure, the oxide layer of 1 / 3 thickness can be first deposited and grown on the surface of the substrate and the gate structure, and then the 1 / 3 thickness of the oxide layer formed is subjected to a density enhancement process. Then deposit and grow 1 / 3 thickness of the oxide layer, and then perform the density enhancement process, and finally deposit and grow the remaining 1 / 3 thickness of the oxide layer and perform the density enhancement process. Through this layered preparation and cyclic processing method, the uniformity of the density of the finally formed oxide layer is ensured.

[0068] It should be noted that the above description of the preparation method of the oxide layer is only an example provided by the present embodiment. In actual application, 1 / 4, 1 / 5 or other thickness ratio of the oxide layer is also deposited and grown to complete the layered preparation and cyclic processing.

[0069] Through the method described in the foregoing embodiments, the density of the oxide layer can be improved by the density enhancement process, and the partial silicon nitride layer is converted into a silicon oxide layer by the oxidation process, so that the wet etching rate of the bottom and the sidewall of the gate structure is uniform, to ensure that they can be thinned synchronously during wet etching.

[0070] Further, in order to shorten the time length of the entire metal silicide barrier layer preparation process, some embodiments of the present disclosure also provide a preparation method of a metal silicide barrier layer, Figure 6 An exemplary flowchart of a preparation method 600 of a metal silicide barrier layer of another embodiment of the present disclosure is shown.

[0071] As shown in Figure 6 In step S601, a semiconductor device structure is prepared, which includes a substrate, a gate structure, an oxide layer, and a silicon nitride layer;

[0072] In step S602, the silicon nitride layer is oxidized to oxidize part of the silicon nitride layer into a silicon oxide layer;

[0073] In step S603, ions are introduced to the oxide layer in a direction perpendicular to the substrate to increase the etching rate of the oxide layer located above the substrate;

[0074] In step S604, the silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure are removed simultaneously by a wet etching process to obtain the metal silicide barrier layer.

[0075] In this embodiment, the contents of steps S601 to S602 are consistent with those of steps S301 to S302 in the foregoing embodiment, which will not be described again.

[0076] In the execution of step S603, by introducing ions to the oxide layer in a direction perpendicular to the substrate, the reaction rate of the oxide layer at a specific position to the wet etching agent can be changed, for example, the oxide layer located above the substrate and on top of the gate structure. Since the direction of the introduced ions is fixed, the silicon oxide layer located at the sidewall position of the gate structure is not affected by the ions, and the wet etching rate is maintained.

[0077] As an example, in the execution of step S603, hydrogen ions can be introduced to the oxide layer in a direction perpendicular to the substrate by an inductively coupled plasma (ICP) process or a high-density plasma (HDP) process using a hydrogen-containing gas. For example, hydrogen ions or hydroxyl ions are formed using a hydrogen-containing gas and introduced to the oxide layer. ICP is a process for generating and maintaining plasma using electromagnetic induction principles, the basic principle of which mainly relies on the input of energy to the gas through the inductive coil by the radio frequency power source, thereby generating high-energy particles in the gas. A plurality of parameters in the ICP process can affect the wet etching rate of the thin film, including ICP source power, RF bias power, etching gas ratio, and cavity pressure. By optimizing these parameters, the wet etching rate of the thin film can be adjusted to the desired rate.

[0078] In some embodiments, the oxide layer can include a first oxide layer and a second oxide layer, wherein the preparation sequence and the formation position of the first oxide layer and the second oxide layer have been described in detail in the foregoing embodiments, which will not be described again. Step S603 can introduce ions to increase the wet etching rate of the oxide layer, especially the wet etching rate of the first oxide layer, i.e., to accelerate the etching of the oxide layer above the substrate. Figure 1 The contents of steps S601 to S602 are consistent with those of steps S301 to S302 in the foregoing embodiment, which will not be described again. Step S603 can introduce ions to increase the wet etching rate of the oxide layer, especially the wet etching rate of the first oxide layer, i.e., to accelerate the etching of the oxide layer above the substrate.

[0079] In the metal silicide blocking layer preparation process, the metal silicide blocking layer is to protect a specific region from forming metal silicide, so that the active region not protected by the metal silicide blocking layer forms metal silicide. Therefore, when step S604 is performed to perform wet etching, the etching stops above the substrate. In other words, the wet etching needs to remove the oxide layer above the partial region of the substrate to expose the substrate of the partial region so as to form metal silicide. Therefore, the etching rate of the oxide layer above the substrate greatly affects the time length of the entire metal silicide blocking layer preparation process.

[0080] Based on the above factors, the embodiment introduces ions to the oxide layer in a direction perpendicular to the substrate to increase the etching rate of the oxide layer above the substrate, thereby shortening the time length required for wet etching, and further shortening the time length of the entire metal silicide blocking layer preparation process.

[0081] For the convenience of those skilled in the art to understand, Figure 7 A flowchart of a method for preparing a metal silicide blocking layer of another embodiment of the disclosure is shown as follows. Figure 7 As shown, in process f, a densification enhancement process is performed on the grown oxide layer, for example, a high-density plasma process (HDP) is used to process the oxide layer at a temperature range of 350-550°C, a discharge power range of 6000-12000W, and a pressure range of 3-10mtorr to increase the density of the oxide layer. In process g, a silicon nitride layer is deposited on the oxide layer processed by the densification enhancement process. In process h, the silicon nitride layer above the substrate and on the top of the gate structure is removed by a dry etching process, so that the remaining silicon nitride layer is located at the sidewall position of the gate structure. In process i, the silicon nitride layer is oxidized to oxidize part of the silicon nitride layer to a silicon oxide layer, thereby forming an O / N / O structure at the sidewall position of the gate structure, where N represents nitride and O represents oxide. In process j, ions are introduced in a direction perpendicular to the substrate to increase the wet etching rate of the oxide layer above the substrate, for example, hydrogen ions can be introduced to the oxide layer in a direction perpendicular to the substrate by an inductively coupled plasma process (ICP) or a high-density plasma process (HDP) using a hydrogen-containing gas. In process k, the oxide layer above the substrate, the silicon oxide layer at the sidewall position of the gate structure, and the oxide layer on the top of the gate structure are simultaneously thinned by a wet etching process, thereby forming a metal silicide blocking layer with good morphology.

[0082] In summary, the embodiments of the present disclosure provide a preparation method of a metal silicide barrier layer, which can utilize a densification enhancement process to improve the densification of the oxide layer, thereby reducing the wet etching rate of the oxide layer and facilitating the oxidation process to convert part of the silicon nitride layer into a silicon oxide layer, thereby increasing the wet etching rate of the structure layer (i.e., the silicon oxide layer) on the sidewall of the gate structure to the same level as the oxide layer, so that the barrier layer material on the sidewall of the gate structure, above the substrate and on the top of the gate structure is thinned synchronously, avoiding excessive etching of the sidewall and bottom sidewall of the top of the gate structure to form a recessed morphology, effectively ensuring the reliability of the semiconductor device.

[0083] Further, the embodiments of the present disclosure also provide another preparation method of a metal silicide barrier layer, which increases the wet etching rate of the oxide layer above the substrate by introducing ions before wet etching, thereby effectively shortening the time consumption of the entire metal silicide barrier layer preparation process and improving the preparation efficiency of the metal silicide barrier layer.

[0084] The embodiments of the present disclosure also provide a semiconductor device, which comprises a substrate, a gate structure above the substrate and a metal silicide barrier layer, wherein the metal silicide barrier layer covers the sidewall of the gate structure, and the metal silicide barrier layer can be prepared by performing the preparation method described in any of the preceding embodiments.

[0085] Although the embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided only by way of example. Many changes, modifications and alternatives can be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the present disclosure described herein can be employed in practicing the present disclosure. The appended claims are intended to define the scope of protection of the present disclosure and thus cover equivalents or alternatives within the scope of these claims.

[0086] In the present disclosure, the collection and acquisition of various data comply with relevant legal regulations and are authorized by the data providers. Any organization or individual that needs to acquire external data should obtain authorization and ensure data security in accordance with the law, and shall not illegally collect, use, process, transmit, sell, provide or disclose unauthorized or unprotected data.

Claims

1. A method of forming a metal silicide barrier layer, characterized by, include: A semiconductor device structure is fabricated, the semiconductor device structure comprising: a substrate, a gate structure located above the substrate, an oxide layer, and a silicon nitride layer, wherein the oxide layer covers the surfaces of the substrate and the gate structure, the oxide layer is treated with a density enhancement process, and the silicon nitride layer is located on the sidewall of the gate structure and covers the oxide layer; Oxidation treatment of the silicon nitride layer to oxidize a portion of the silicon nitride layer into a silicon oxide layer; and The silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure are simultaneously removed by a wet etching process to obtain a metal silicide barrier layer, which includes an oxide layer and a silicon nitride layer located on the sidewall of the gate structure.

2. The production method according to claim 1, characterized by, The density enhancement process includes a high-density plasma process, wherein the fabrication of the semiconductor device structure includes: Fabricate a gate structure on a substrate; An oxide layer is deposited and grown on the surfaces of the substrate and the gate structure; The density of the oxide layer is increased by high-density plasma processing. A silicon nitride layer is deposited and grown on the oxide layer; and The silicon nitride layer located above the substrate and on top of the gate structure is removed by a dry etching process.

3. The production method according to claim 1 or 2, characterized by, The oxidation treatment of the silicon nitride layer includes: The silicon nitride layer is oxidized using a high-density plasma process.

4. The method of claim 1, wherein, The fabrication method further includes, prior to the simultaneous removal of the silicon oxide layer and the oxide layer located above the substrate and on top of the gate structure via a wet etching process: Ions are introduced into the oxide layer in a direction perpendicular to the substrate to increase the etching rate of the oxide layer located above the substrate.

5. The preparation method according to claim 2, characterized in that, The high-density plasma process used to increase the density of the oxide layer includes: The oxide layer is subjected to high-density plasma treatment within a temperature range of 350℃-550℃, a discharge power range of 6000W-12000W, and a pressure range of 3mtorr-10mtorr.

6. The preparation method according to claim 3, characterized in that, The oxidation of the silicon nitride layer via high-density plasma process includes: The silicon nitride layer is subjected to high-density plasma oxidation treatment using oxygen-containing gas as the reaction medium within a temperature range of 350℃-550℃, a discharge power range of 10000W-18000W, and a pressure range of 3mtorr-20mtorr.

7. The preparation method according to claim 1, characterized in that, The silicon nitride layer has an oxidation thickness ranging from 5 nm to 15 nm, and the silicon oxide layer has a thickness ranging from 5 nm to 15 nm.

8. The preparation method according to claim 4, characterized in that, Introducing ions into the oxide layer in a direction perpendicular to the substrate includes: Hydrogen ions are introduced into the oxide layer using hydrogen-containing gas in a direction perpendicular to the substrate through inductively coupled plasma or high-density plasma processes.

9. The method of claim 2, wherein, After increasing the density of the oxide layer through a high-density plasma process, the preparation method further includes: The steps of depositing and growing an oxide layer and increasing the density of the oxide layer by high-density plasma processing are repeated alternately until the thickness of the oxide layer reaches a preset value.

10. A semiconductor device, characterized by comprising: include: Substrate, gate structure located above the substrate, and metal silicide barrier layer; The metal silicide barrier layer covers the sidewall of the gate structure, and is prepared by performing the preparation method of any one of claims 1-9.

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