High-voltage silicon stack, production method thereof and lifting device for assembling high-voltage silicon stack

Abstract

The invention relates to a high-voltage silicon stack, a production method thereof and a lifting device for assembling the high-voltage silicon stack, the high-voltage silicon stack adopts a cylindrical axial lead and square copper particle combined structure, the cylindrical axial lead is adopted, the copper particles and chips adopt unitization design, multiple layers of chips are clamped by the copper particles to form a unit structure, and the unit structure is repeatedly welded to form the high-voltage silicon stack. In cooperation with the lifting device and the assembling method, on one hand, the square copper particles increase the heat dissipation efficiency by increasing the contact area, the impact of external stress on the internal chip is reduced, the method can be suitable for automatic production, the production efficiency is effectively improved, the labor cost is saved, and the product quality is improved.

Description

Technical Field

[0001] This invention relates to the field of diode manufacturing technology, and in particular to a high-voltage silicon stack, its production method, and a lifting device for assembly. Background Technology

[0002] High-voltage silicon stacks, composed of multiple silicon chips connected in series, are essential components in high-voltage rectification that convert AC to DC. However, in practical applications, high-voltage silicon stacks have many problems due to their structure: 1. Uneven structural stress: When stacking multiple layers of chips, the uniform thickness of the solder pads easily leads to structural deformation after soldering, resulting in stress concentration in the packaging;

[0003] 2. Low level of automation: Chip counting relies on manual operation, which is inefficient and prone to errors;

[0004] 3. Poor process compatibility: The mixing of GPP (Glass Passivation) and OJ (Open Junction) cleaning processes can easily leave contaminants.

[0005] 4. Insufficient heat dissipation and protection: The lead wire structure design is unreasonable, the heat dissipation efficiency of the copper particles is low, and the poor airtightness leads to the risk of oxidation. Summary of the Invention

[0006] To address the aforementioned problems, the purpose of this invention is to provide a high-voltage silicon stack, its production method, and a lifting device for assembly. The produced high-voltage silicon stack can effectively relieve stress, improve heat dissipation efficiency, and greatly improve product quality.

[0007] To achieve the above objectives, the first technical solution of the present invention is: a high-voltage silicon stack, including leads arranged along the axial direction, a plurality of chip groups are connected in series on the leads, copper particles are provided between adjacent chip groups, and the two sides of the chip groups are connected to the copper particles by buffer solder pads, wherein the chip group consists of a plurality of rectifier chips connected by rectifier solder pads.

[0008] In the above technical solution, the copper particles are square copper particles with a thickness of 0.5 to 1.5 mm, the buffer solder sheet has a thickness of 0.5 to 1.5 mm, and the rectifier solder sheet has a thickness of 0.04 to 0.12 mm.

[0009] In the above technical solution, when the number of rectifier chips in the chipset is 2 to 5 layers, the thickness of the rectifier solder pads is consistent. When the number of rectifier chips is greater than 5 layers, the chipset is divided into a central area and an edge area, and the rectifier solder pads in the central area are thick solder pads with a thickness of 0.1 mm, while the rectifier solder pads in the edge area have a thickness of 0.05 mm.

[0010] To achieve the above objectives, the second technical solution of the present invention is: a precision assembly lifting device for high-voltage silicon stacks, used for producing the above-mentioned high-voltage silicon stacks, comprising tooling, a base frame, a top rod plate, and a lifting mechanism. The tooling is detachably mounted on the base frame, and the tooling is provided with multiple mounting slots. The bottom of the mounting slot is provided with a mounting top rod, which is mounted on the top rod plate. The lifting mechanism can drive the top rod plate to rise and fall, and a counter is connected to the lifting mechanism.

[0011] In the above technical solution, the lifting mechanism is a scissor lift driven by a stepper motor.

[0012] To achieve the above objectives, the third technical solution of the present invention is: a method for producing a high-voltage silicon stack, comprising the following steps:

[0013] S1 is used to place the tooling for the materials to be placed, and the chip solder pads and other materials are placed in the tooling.

[0014] S2 moves the lifting platform to the starting position and activates the vibration of the support platform.

[0015] For each layer of chips placed in the S3 assembly, a counter is used to count once. Every 2-3 counts, the lifting platform descends a certain distance. The thickness of a single descent is 2 × chip thickness + 2 × solder pad thickness.

[0016] S4 removes the assembled semi-finished product, returns the lifting platform to the ready position, and resets the counter to zero;

[0017] S5 welding and cleaning

[0018] Weld and clean the semi-finished products;

[0019] S6 package

[0020] Silicone white glue coating: High viscosity silicone white glue (≥5000cps) is used to fill the gaps between chips and cured at 80°C for 2 hours under nitrogen protection;

[0021] S7 Curing Molding Aging Optimization: Extend the aging time after molding to 12-16 hours to promote stress release of epoxy resin.

[0022] In the above technical solution, S2 uses high-frequency vibration-assisted positioning with a frequency of 50-100Hz and an amplitude of ≤0.1mm.

[0023] In the above technical solution, the S5 is produced by welding GPP chip, square welding pad is loaded on square hole graphite boat, the welding temperature is set to 300±10℃, the residual flux is cleaned with organic solvent after welding is completed, and it is baked at 150℃ for 2 hours in nitrogen-protected oven.

[0024] In the above technical solution, the welding of S5 produces OJ cores, which are loaded with circular welding sheets using a round-hole graphite boat. The welding temperature is raised to 320±10℃. After welding, cleaning is performed, and the cleaning process is as follows:

[0025] ① Acid washing / alkali washing: Complexing metal ions in a mixture of 5% ammonia and 3% hydrogen peroxide;

[0026] ② Neutralization: Soak in 2% HCl solution for 5 minutes;

[0027] ③Use pure water for ultrasonic cleaning at 85℃ for 10 minutes;

[0028] ④ After dehydration of isopropanol, dry under nitrogen protection at 100°C for 1 hour.

[0029] In summary, the advantages of using the technical solution of this invention compared to traditional technical means are as follows:

[0030] The high-voltage silicon stack in this invention adopts a structure combining cylindrical axial leads and square copper particles. The cylindrical axial leads and the copper particles and chips adopt a modular design, with copper particles sandwiching multiple layers of chips to form a unit structure, and then this unit structure is repeatedly soldered.

[0031] In this way, the square copper particles improve heat dissipation efficiency by increasing the contact area (the measured heat dissipation capacity is improved by 20%), and at the same time, they serve as a mechanical protective layer to reduce the impact of external stress on the internal chip.

[0032] The silicon material used in chips has a certain degree of warpage, which causes uneven stress distribution on the chip. This unevenness worsens with the accumulation of chips. Specifically, the stress is: σ(stress) = 6(1-ν) s R (radius of warpage)E s t s2 • f(number of layers, material): Through experiments, 4-5 layers of silicon material for chips are within an acceptable range. Therefore, the chips are modularized and protected by copper particles to keep the chip deformation stress within a certain range.

[0033] In this invention, a differentiated solder thickness design is adopted for the high-voltage silicon stack. Since the chips are made of the same material, a thinner solder is used between them to ensure that the chips are flat and consistent after soldering. A thicker solder is used between the chips and the copper particles to buffer the stress caused by the different coefficients of material expansion.

[0034] The precision assembly lifting device can realize the automated assembly of chips, effectively improving production efficiency, saving labor costs, and improving product quality. Attached Figure Description

[0035] The foregoing and other objects, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0036] Figure 1 This is a schematic diagram of the high-voltage silicon stack in this invention;

[0037] Figure 2 This is a schematic diagram of the chipset in this invention;

[0038] Figure 3 This is a schematic diagram of the first state of the lifting mechanism in this invention;

[0039] Figure 4 This is a schematic diagram of the second state of the lifting mechanism in this invention;

[0040] Figure 5 This is a schematic diagram of the third state of the lifting mechanism in this invention;

[0041] Figure 6 This is a flowchart illustrating the assembly process of the present invention.

[0042] Figure 7 A schematic diagram of a graphite boat with a circular hole;

[0043] Figure 8 A schematic diagram of a square-holed graphite boat;

[0044] The following are the labels: 100, High-voltage silicon stack; 110, Lead wire; 120, Chipset; 121, Rectifier chip; 122, Rectifier solder pad; 123, Side solder pad; 130, Copper chip; 140, Buffer solder pad; 200, Lifting device; 210, Tooling; 211, Mounting slot; 220, Base frame; 230, Lifting platform; 240, Lifting mechanism; 241, Counter; 250, Top rod plate; 251, Loading top rod. Detailed Implementation

[0045] Based on the preferred embodiments of the present invention, and through the following description, those skilled in the art can make various changes and modifications without departing from the technical concept of the present invention. The technical scope of the present invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

[0046] The invention will be further described with reference to the following figures:

[0047] Example 1:

[0048] like Figure 1 , 2As shown, a high-voltage silicon stack 100 includes a lead 110 arranged along the axial direction, a plurality of chip groups 120 are connected in series on the lead 110, copper particles 130 are provided between adjacent chip groups 120, and the two sides of the chip group 120 are connected to the copper particles 130 by buffer solder pads 140. The chip group 120 consists of a plurality of rectifier chips 121 connected by rectifier solder pads 122.

[0049] In actual use, the copper particle 130 is a square copper particle with a thickness of 0.5 to 1.5 mm, the buffer solder sheet 140 has a thickness of 0.5 to 1.5 mm, and the rectifier solder sheet 122 has a thickness of 0.04 to 1.2 mm.

[0050] When the number of rectifier chips 121 in the chipset 120 is 2 to 5 layers, the thickness of the rectifier solder pads 122 is consistent. When the number of rectifier chips 121 is greater than 5 layers, the chipset 120 is divided into a central area and an edge area. The rectifier solder pads 122 in the central area are thick solder pads with a thickness of 0.1 mm, while the rectifier solder pads 122 in the edge area have a thickness of 0.05 mm. This arrangement of chips with different thicknesses can effectively avoid stress concentration in the packaging and prevent structural deformation of the chipset after soldering.

[0051] Example 2:

[0052] like Figure 3 , 4 As shown in Figure 5, a precision assembly lifting device 200 for a high-voltage silicon stack includes a tooling 210, a base frame 220, a top rod plate 230, and a lifting mechanism 240. The tooling 210 is detachably mounted on the base frame 220. The tooling 210 is provided with multiple mounting slots 211. The bottom of the mounting slot 210 is provided with a mounting top rod 231, which is mounted on the top rod plate 230. The lifting mechanism 240 can drive the top rod plate 230 to rise and fall. A counter 241 is connected to the lifting mechanism 240. A vibrator is provided on the base frame 220.

[0053] The lifting mechanism 240 is a scissor lift driven by a stepper motor.

[0054] Example 3:

[0055] like Figure 6 As shown, a method for producing a high-voltage silicon stack includes the following steps:

[0056] S1 is a tooling unit where chip solder pads and other materials are placed.

[0057] S2 moves the lifting platform to the starting position and activates the vibration of the support platform, with a frequency of 50-100Hz and an amplitude of ≤0.1mm.

[0058] For each layer of chips placed in the S3 assembly, a counter is used to count once. Every 2-3 counts, the lifting platform descends a certain distance. The thickness of a single descent is 2 × chip thickness + 2 × solder pad thickness.

[0059] S4 removes the assembled semi-finished product, returns the lifting platform to the ready position, and resets the counter to zero;

[0060] S5 welding and cleaning

[0061] If producing GPP chips, use a square-hole graphite boat to load square solder pads, set the soldering temperature to 300±10℃, clean the residual flux with organic solvents after soldering, and bake in a nitrogen-protected oven at 150℃ for 2 hours to prevent copper oxide formation.

[0062] If producing OJ cores, use a round-hole graphite boat to load the circular welding sheet, raise the welding temperature to 320±10℃, and clean after welding. The cleaning process is as follows:

[0063] ① Acid washing / alkali washing: Complexing metal ions in a mixture of 5% ammonia and 3% hydrogen peroxide;

[0064] ② Neutralization: Soak in 2% HCl solution for 5 minutes;

[0065] ③Use pure water for ultrasonic cleaning at 85℃ for 10 minutes;

[0066] ④ After dehydration of isopropanol, it is dried under nitrogen protection at 100°C for 1 hour.

[0067] The combined use of GPP (Glass Passivation) and OJ (Open Junction) cleaning processes offers better applicability and effectively saves costs.

[0068] S6 package

[0069] Silicone white glue coating: High viscosity silicone white glue (≥5000cps) is used to fill the gaps between chips and cured at 80℃ for 2 hours under nitrogen protection;

[0070] S7 curing molding aging optimization extends the aging time after molding to 12-16 hours (compared to 8 hours in the traditional process), which can effectively promote the stress release of epoxy resin.

[0071] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-voltage silicon stack, characterized in that: It includes leads arranged along the axial direction, with multiple chip groups strung together on the leads, copper particles between adjacent chip groups, and the two sides of the chip groups connected to the copper particles by buffer solder pads. The chip group consists of multiple rectifier chips connected by rectifier solder pads.

2. The high-voltage silicon stack according to claim 1, characterized in that: The copper particles are square copper particles with a thickness of 0.5 to 1.5 mm, the buffer solder sheet has a thickness of 0.5 to 1.5 mm, and the rectifier solder sheet has a thickness of 0.04 to 0.12 mm.

3. The high-voltage silicon stack according to claim 1, characterized in that: When the number of rectifier chips in the chipset is 2 to 5 layers, the thickness of the rectifier solder pads is consistent. When the number of rectifier chips is greater than 5 layers, the chipset is divided into a central area and an edge area, and the rectifier solder pads in the central area are thick solder pads with a thickness of 0.1 mm, while the rectifier solder pads in the edge area have a thickness of 0.05 mm.

4. A precision assembly lifting device for high-voltage silicon stacks, used for producing high-voltage silicon stacks according to any one of claims 1 to 3, characterized in that: The device includes a tooling, a base frame, a top rod plate, and a lifting mechanism. The tooling is detachably mounted on the base frame and has multiple mounting slots. The bottom of each mounting slot has a mounting rod, which is mounted on the top rod plate. The lifting mechanism can drive the top rod plate to rise and fall, and a counter is connected to the lifting mechanism.

5. The precision assembly of the high-voltage silicon stack according to claim 4, characterized in that: The lifting mechanism is a scissor lift driven by a stepper motor.

6. A method for producing a high-voltage silicon stack, used to produce the high-voltage silicon stack according to any one of claims 1 to 3, characterized in that: The steps are as follows: S1 is used to place the tooling for the materials to be placed, and the chip solder pads and other materials are placed in the tooling. S2 moves the lifting platform to the starting position and activates the vibration of the support platform. For each layer of chips placed in the S3 assembly, a counter is used to count once. Every 2-3 counts, the lifting platform descends a certain distance. The thickness of a single descent is 2 × chip thickness + 2 × solder pad thickness. S4 removes the assembled semi-finished product, returns the lifting platform to the ready position, and resets the counter to zero; S5 welding and cleaning Weld and clean the semi-finished products; S6 package Silicone white glue coating: High viscosity silicone white glue (≥5000cps) is used to fill the gaps between chips and cured at 80°C for 2 hours under nitrogen protection; S7 Curing Molding Aging Optimization: Extend the aging time after molding to 12-16 hours to promote stress release of epoxy resin.

7. The method for producing a high-voltage silicon stack according to claim 6, characterized in that: S2 is a medium-to-high frequency vibration-assisted positioning system with a frequency of 50–100 Hz and an amplitude of ≤0.1 mm.

8. The method for producing a high-voltage silicon stack according to claim 6, characterized in that: The S5 is produced by GPP chip manufacturing, which uses a square-hole graphite boat to load square solder pads. The soldering temperature is set to 300±10℃. After soldering, residual flux is cleaned with organic solvents and baked in a nitrogen-protected oven at 150℃ for 2 hours.

9. The method for producing a high-voltage silicon stack according to claim 6, characterized in that: The S5 welding process produces OJ cores, using a round-hole graphite boat to load round welding pieces. The welding temperature is raised to 320±10℃. After welding, cleaning is performed, and the cleaning process is as follows: ① Acid washing / alkali washing: Complexing metal ions in a mixture of 5% ammonia and 3% hydrogen peroxide; ② Neutralization: Soak in 2% HCl solution for 5 minutes; ③Use pure water for ultrasonic cleaning at 85℃ for 10 minutes; ④ After dehydration of isopropanol, dry it under nitrogen protection at 100°C for 1 hour.

Images