Method for improving nmos and pmos height difference, semiconductor structure and device

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a method for improving height difference between NMOS and PMOS, a semiconductor structure and a device, which comprises the following steps: providing an intermediate product comprising a PMOS region and an NMOS region, and forming a polysilicon gate structure and a first oxide layer covering the polysilicon gate structure on the PMOS region and the NMOS region, wherein the polysilicon gate structure comprises a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed in sequence from inside to outside; grinding the first oxide layer so that the surface of the first oxide layer is flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching the top of the silicon nitride layer and a part of the side wall to expose the top of the silicon oxide layer; thinning the remaining first oxide layer, and removing the top of the silicon oxide layer and the hard mask layer until the top surface of the gate polysilicon layer stops. The application effectively reduces the height difference between the NMOS region and the PMOS region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a method for improving height difference between NMOS and PMOS, semiconductor structure and device. BACKGROUND

[0002] In modern semiconductor manufacturing processes, especially in the manufacture of high-performance complementary metal-oxide-semiconductor (CMOS) devices, it is crucial to precisely control material removal and deposition in each process step. Among them, EPI (epitaxial growth) dry etching technology is widely used to define the key features of transistors, such as gate structures. However, this technology also faces a series of challenges in implementation.

[0003] Specifically, when performing EPI dry etching, it is often necessary to selectively cover or expose specific areas according to device type (NMOS (N-type metal-oxide-semiconductor) and PMOS (P-type metal-oxide-semiconductor)). For example, in the process step of Cap N Open P (covering a protective layer on the N-type region while processing the P-type region), it aims to protect the NMOS region while etching the PMOS region. However, partial loss of PMOS region oxide may occur during this process due to non-ideal factors such as improper etching rate control, mask alignment errors, or etching depth non-uniformity.

[0004] The loss of the first oxide layer introduces a height difference between the PMOS region and the NMOS region (for example: there is a height difference in the silicon oxide layer 3 in the two polysilicon gate structures, see Figure 1 ), which has a significant impact on the subsequent ILD0 (first interlayer dielectric) CMP (chemical mechanical polishing) step. ILD0 CMP aims to flatten the wafer surface to provide a uniform base for subsequent multi-layer metallization and interconnection structures. However, due to the inconsistency of oxide height between NMOS and PMOS regions, this height difference causes different N / P loadings during ILD0 CMP, causing PMOS to inherit a lower status than NMOS. During ILD0 CMP, if the bottom film height is not uniform, the etching rate is different when different films are polished, and when the loading effect during CMP is large, not only the surface uniformity is affected, but also the height difference between NMOS and PMOS gate exists. This height difference directly affects the electrical performance of the transistor, such as threshold voltage, leakage current, and transconductance, key parameters, thereby adversely affecting the performance and reliability of the overall CMOS device.

[0005] Therefore, it is necessary to develop a new method for improving the height difference between NMOS and PMOS, semiconductor structure and device. SUMMARY

[0006] The present application aims to provide a method for improving the height difference between NMOS and PMOS, a semiconductor structure and a device, so as to reduce the height difference between NMOS and PMOS regions.

[0007] In a first aspect, the present application provides a method for improving the height difference between NMOS and PMOS, comprising the following steps:

[0008] Step 1. Providing an intermediate product, the intermediate product comprising at least a PMOS region and an NMOS region, the PMOS region and the NMOS region each being provided with a polysilicon gate structure and a first oxide layer covering the polysilicon gate structure, the polysilicon gate structure comprising a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed in sequence from inside to outside;

[0009] Step 2. Performing a grinding process to grind the first oxide layer so that the surface of the first oxide layer is flush;

[0010] Step 3. Performing an etching process to thin the remaining first oxide layer to expose the top of the silicon nitride layer;

[0011] Step 4. Performing an etching process to remove the top of the silicon nitride layer and a portion of the side wall to expose the top of the silicon oxide layer;

[0012] Step 5. Performing a grinding process to thin the remaining first oxide layer and remove the top of the silicon oxide layer and the hard mask layer until the top surface of the gate polysilicon layer stops.

[0013] Optionally, the hard mask layer covers the gate polysilicon layer, the silicon oxide layer covers the hard mask layer, and the silicon nitride layer covers the silicon oxide layer.

[0014] In a second aspect, the present application provides a semiconductor structure, which is manufactured by the method for improving the height difference between NMOS and PMOS as described in the present application.

[0015] In a third aspect, the present application provides a semiconductor device, which adopts the semiconductor structure as described in the present application.

[0016] In a fourth aspect, the present application provides a method for improving the height difference between NMOS and PMOS, comprising the following steps:

[0017] Step 1. Provide an intermediate product, which at least includes a PMOS region and an NMOS region, and a first oxide layer covering the polysilicon gate structure formed on the PMOS region and the NMOS region, the polysilicon gate structure including a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed in sequence from inside to outside;

[0018] Step 2. Perform a grinding process to grind the first oxide layer so that the surface of the first oxide layer is flush;

[0019] Step 3. Perform an etching process to thin the remaining first oxide layer to expose the top of the silicon nitride layer;

[0020] Step 4. Perform an etching process to remove the top of the silicon nitride layer and a portion of the side wall to expose the top of the silicon oxide layer;

[0021] Step 5. Perform a grinding process to thin the remaining first oxide layer and remove the top of the silicon oxide layer to expose the hard mask layer;

[0022] Step 6. Perform an etching process to remove the top of the hard mask layer and remove a portion of the side wall of the silicon nitride layer, the silicon oxide layer and the hard mask layer to expose the top surface of the gate polysilicon layer;

[0023] Step 7. Perform a grinding process to thin the remaining first oxide layer until the top surface of the gate polysilicon layer stops.

[0024] The method makes the grinding result more controllable, which helps to obtain a more uniform and flat surface when finally grinding to the top surface of the gate polysilicon layer. In addition, since the removal of each layer is more accurate, the risk of damage to the gate polysilicon layer caused by excessive grinding or etching is reduced, thereby improving the reliability of the product.

[0025] Optionally, in step 7, a second oxide layer is deposited above the gate polysilicon layer before the grinding process is performed. After step 6 is performed, the method additionally includes a key step of depositing a thin second oxide layer. The oxide deposition in this step does not need to be too thick, and the main purpose is to facilitate subsequent grinding operations. Considering that the first oxide layer may be damaged in the previous dry etching step, resulting in insufficient retention. If grinding is performed directly, the process accuracy may be affected due to increased control difficulty. Therefore, by depositing this thin layer of second oxide layer, the difficulty of the grinding process can be effectively alleviated, making the planarization process easier to achieve, thereby ensuring the stability and controllability of the entire process flow.

[0026] Optionally, the second oxide layer is of the same material as the first oxide layer. The same material can reduce CMP loading.

[0027] Optionally, the hard mask layer is covered outside the gate polysilicon layer, the silicon oxide layer is covered outside the hard mask layer, and the silicon nitride layer is covered outside the silicon oxide layer.

[0028] In a fifth aspect, a semiconductor structure is provided, which is manufactured by the method for improving the height difference between NMOS and PMOS as described in the present application.

[0029] In a sixth aspect, a semiconductor device is provided, which employs the semiconductor structure as described in the present application.

[0030] The unexpected benefits of the present application are as follows:

[0031] (1) No need to modify the layout of integrated semiconductors, effectively adjusting the height difference between NMOS and PMOS:

[0032] This method can precisely adjust the height difference between NMOS and PMOS regions without changing the existing layout through a combination of chemical mechanical polishing (CMP) and dry etching. This technology not only simplifies the production process, but also avoids the design complexity and cost increase caused by modifying the layout of semiconductors, thereby significantly improving production efficiency and product yield.

[0033] (2) Reducing pattern loading, optimizing ILD0 CMP process:

[0034] By optimizing the process and using advanced CMP technology, the present application effectively reduces the impact of pattern loading on the ILD0 (first dielectric layer) CMP process. This not only reduces the unevenness and scratches in the CMP process, but also improves the flatness and consistency of the ILD0 layer, providing a more reliable foundation for subsequent transistor manufacturing and interconnection.

[0035] (3) Simplifying the process, reducing the number of masks and process costs:

[0036] The present application discards the traditional PREB (pre-exposure baking) process, thereby reducing the number of masks and process steps. This change not only simplifies the production process, but also significantly reduces the manufacturing cost and time cost. At the same time, since the PREB process may introduce errors and uncertainties, the quality and reliability of the product have been further improved.

[0037] (4) Eliminate the height difference between NMOS and PMOS, improve the uniformity of CMP grinding:

[0038] By twice CMP process and high selectivity OX / SIN (oxide / nitride) dry etching technology, the multi-layer structure on the top of the gate is completely removed, thereby eliminating the height difference between NMOS and PMOS caused by EPI (epitaxial growth) process. This technology not only improves the performance and consistency of the transistor, but also further reduces the load effect in the CMP process by means of single CMP polishing layer, and improves the uniformity and precision of polishing.

[0039] In summary, the present application realizes the multiple technical effects of accurately adjusting the height difference between NMOS and PMOS, reducing the pattern load, optimizing the ILD0 CMP process, reducing the manufacturing cost and time cost, and improving the product quality and reliability by means of the innovative CMP and dry etching combined process, the optimized CMP process, the simplified process steps, and the improved polishing uniformity, without changing the layout. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A schematic diagram of a semiconductor structure with height difference between NMOS and PMOS in the prior art;

[0041] Figure 2 A flowchart of the method for improving the height difference between NMOS and PMOS in Example 1;

[0042] Figure 3 A schematic diagram of the intermediate product in the embodiments of the present application;

[0043] Figure 4 A schematic diagram of the structure after step 2 in Example 1 to Example 3 is executed;

[0044] Figure 5 A schematic diagram of the structure after step 3 in Example 1 to Example 3 is executed;

[0045] Figure 6 A schematic diagram of the structure after step 4 in Example 1 to Example 3 is executed;

[0046] Figure 7 A schematic diagram of the structure after step 5 in Example 1 is executed, and after step 7 in Example 2 and Example 3 is executed;

[0047] Figure 8 A flowchart of the method for improving the height difference between NMOS and PMOS in Example 2;

[0048] Figure 9 A schematic diagram of the structure after step 5 in Example 2 and Example 3 is executed;

[0049] Figure 10 A schematic diagram of the structure after step 6 in Example 2 and Example 3 is executed;

[0050] Figure 11 This is a flowchart of the method for improving the height difference between NMOS and PMOS as described in Example 3;

[0051] Figure 12 This is a schematic diagram of the structure after an oxide layer is deposited in step 7 of Example 3;

[0052] In the figure: 1-first oxide layer, 2-silicon nitride layer, 3-silicon oxide layer, 4-hard mask layer, 5-gate polysilicon layer, 6-second oxide layer. Detailed Implementation

[0053] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0054] Example 1

[0055] like Figure 2 As shown, a method for improving the height difference between NMOS and PMOS transistors achieves height adjustment without altering the existing layout, simplifying the manufacturing process and improving production efficiency and product yield. The method includes the following steps:

[0056] Step 1. Provide an intermediate product (i.e., from wafer preparation to polysilicon gate structure formation, at which point the gate of the transistor device is not yet fully formed). The intermediate product includes at least a PMOS region and an NMOS region. A polysilicon gate structure and a first oxide layer 1 covering the polysilicon gate structure are formed on both the PMOS and NMOS regions. The polysilicon gate structure includes a gate polysilicon layer 5, a hard mask layer 4, a silicon oxide layer 3, and a silicon nitride layer 2, formed sequentially from the inside out. See also... Figure 3 In this process, a hard mask layer 4 covers the outside of the gate polysilicon layer 5, a silicon oxide layer 3 covers the outside of the hard mask layer 4, and a silicon nitride layer 2 covers the outside of the silicon oxide layer 3.

[0057] Step 2. Perform a polishing process to polish the first oxide layer 1 until its surface is flush. See [link to relevant documentation]. Figure 4 The grinding process ensures the uniformity and precision of the grinding process.

[0058] Step 3. Perform an etching process to thin the remaining first oxide layer 1 to expose the top of the silicon nitride layer 2. See [link to etching process]. Figure 5The high-selectivity etching of the oxide ensures that the etching rate of the oxide is higher than that of other materials, thereby protecting the non-oxide materials.

[0059] Step 4. Perform an etching process to remove the top of the silicon nitride layer 2 and a portion of the sidewall (with a certain amount of OE (over-etching), which refers to the additional etching performed after reaching the main etching target to ensure complete removal of all target materials), to expose the top of the silicon oxide layer 3, as shown in Figure 6 The high-selectivity etching of the SIN ensures that the etching rate of the silicon nitride is higher than that of other materials, effectively removing the silicon nitride layer while minimizing the etching impact on other materials.

[0060] Step 5. Perform a grinding process to thin the remaining first oxide layer 1 and remove the top of the silicon oxide layer 3 and the hard mask layer 4 until the top surface of the gate polysilicon layer 5 stops, as shown in Figure 7 , ensuring high precision control.

[0061] In the embodiments of the present application, the etching process adopts a dry etching process.

[0062] In the embodiments of the present application, the grinding process adopts a chemical mechanical polishing process.

[0063] In one possible embodiment, the hard mask layer adopts a silicon nitride material.

[0064] The method can accurately adjust the height difference between the NMOS and PMOS regions without changing the existing layout through the combination of chemical mechanical polishing and dry etching. This technology not only simplifies the production process, but also avoids the design complexity and cost increase that may be caused by modifying the layout of the semiconductor, thereby significantly improving production efficiency and product yield.

[0065] The method effectively reduces the impact of pattern loading on the ILD0 CMP process by optimizing the process and adopting advanced CMP technology. This not only reduces the problems of unevenness and scratches in the CMP process, but also improves the flatness and consistency of the ILD0 layer, providing a more reliable foundation for subsequent transistor manufacturing and interconnection.

[0066] The method discards the traditional PREB process, thereby reducing the number of masks and process steps. This change not only simplifies the production process, but also significantly reduces the manufacturing cost and time cost. At the same time, since the PREB process may introduce errors and uncertainties, the quality and reliability of the product have also been further improved.

[0067] The method can completely remove the multi-layer structure on the top of the gate by twice CMP process and high selectivity OX / SIN dry etching technology, thereby eliminating the height difference between NMOS and PMOS regions caused by EPI process. The technology not only improves the performance and consistency of the transistor, but also further reduces the load effect in the CMP process by means of single CMP polishing layer, thereby improving the uniformity and precision of polishing.

[0068] In the first embodiment, a semiconductor structure is made by the method for improving the height difference between NMOS and PMOS as in the first embodiment.

[0069] In the first embodiment, a semiconductor device is made by the semiconductor structure as in the first embodiment.

[0070] Embodiment 2

[0071] As shown in Figure 8 , a method for improving the height difference between NMOS and PMOS realizes height difference adjustment without changing the existing layout, simplifies the production process, and improves production efficiency and product yield. The method comprises the following steps:

[0072] Step 1. Provide an intermediate product (i.e. from wafer preparation to polysilicon gate structure formation, at this time the gate of the transistor device has not been completely formed), the intermediate product at least includes a PMOS region and an NMOS region, the PMOS region and the NMOS region are both formed with a polysilicon gate structure, the polysilicon gate structure includes a gate polysilicon layer 5, a hard mask layer 4 covering the outside of the gate polysilicon layer 5, a silicon oxide layer 3 covering the outside of the hard mask layer 4, and a silicon nitride layer 2 covering the outside of the silicon oxide layer 3; the silicon nitride layer 2 is covered with a first oxide layer 1, see Figure 3 .

[0073] Step 2. Perform a polishing process to polish the first oxide layer 1 so that the surface of the first oxide layer 1 is flush, see Figure 4 .

[0074] Step 3. Perform an etching process to thin the remaining first oxide layer 1 to expose the top of the silicon nitride layer 2, see Figure 5 . The high selectivity etching of the oxide ensures that the etching rate of the oxide is higher than that of other materials, thereby protecting the non-oxide materials.

[0075] Step 4. Perform an etching process to remove the top of the silicon nitride layer 2 and a portion of the side wall (with a certain OE amount (i.e. over-etching amount), which refers to the additional etching amount after reaching the main etching target to ensure complete removal of all target materials), to expose the top of the silicon oxide layer 3, see Figure 6By using SIN high selectivity etching, which ensures that the etching rate of silicon nitride is higher than that of other materials, the silicon nitride layer is effectively removed while the etching impact on other materials is reduced.

[0076] Step 5. Perform a grinding process to thin the remaining first oxide layer 1 and remove the top of the silicon oxide layer 3 to expose the hard mask layer 4, as shown in Figure 9 .

[0077] Step 6. Perform an etching process to remove the top of the hard mask layer 4 and remove part of the side wall of the silicon nitride layer 2 and the silicon oxide layer 3 to expose the top surface of the gate polysilicon layer 5, as shown in Figure 10 .

[0078] Step 7. Perform a grinding process to thin the remaining first oxide layer 1 until the top surface of the gate polysilicon layer 5 stops, as shown in Figure 7 .

[0079] The method described in this embodiment two has more steps when removing each layer (i.e. the step 5 in embodiment one is divided into three steps, i.e. steps 5 to 7 in embodiment two) compared to embodiment one. The advantage of this division is that the grinding result can be more controllable, which helps to obtain a more uniform and flat surface when grinding to the top surface of the gate polysilicon layer. In addition, since the removal of each layer is more precise, the risk of damage to the gate polysilicon layer due to excessive grinding or etching is reduced, thereby improving the reliability of the product.

[0080] In this embodiment two, the etching process uses a dry etching process, and the grinding process uses a chemical mechanical polishing process.

[0081] In this embodiment two, a semiconductor structure is made using the improved NMOS and PMOS height difference method as in this embodiment two.

[0082] In this embodiment two, a semiconductor device is made using the semiconductor structure as in this embodiment two.

[0083] Embodiment three

[0084] As shown in Figure 11 , an improved NMOS and PMOS height difference method realizes height difference adjustment without changing the existing layout, simplifies the production process, and improves production efficiency and product yield. The method includes the following steps:

[0085] Step 1. Provide an intermediate product (i.e. from wafer preparation to polysilicon gate structure formation, at this time the gate of the transistor device has not been completely formed), the intermediate product at least includes PMOS region and NMOS region, the PMOS region and the NMOS region are formed with polysilicon gate structure, the polysilicon gate structure includes gate polysilicon layer 5, hard mask layer 4 covering outside the gate polysilicon layer 5, silicon oxide layer 3 covering outside the hard mask layer 4, and silicon nitride layer 2 covering outside the silicon oxide layer 3; The first oxide layer 1 is covered outside the silicon nitride layer 2, see Figure 3 .

[0086] Step 2. Perform a grinding process to grind the first oxide layer 1 so that the surface of the first oxide layer 1 is flush, see Figure 4 .

[0087] Step 3. Perform an etching process to thin the remaining first oxide layer 1 to expose the top of the silicon nitride layer 2, see Figure 5 . Use high selectivity etching of oxide to ensure that the etching rate of oxide is higher than that of other materials, and protect non-oxide materials.

[0088] Step 4. Perform an etching process to remove the top of the silicon nitride layer 2 and a part of the side wall (with a certain OE amount (over-etching amount), the OE amount refers to the additional etching amount after reaching the main etching target, in order to ensure complete removal of all target materials), to expose the top of the silicon oxide layer 3, see Figure 6 . Use high selectivity etching of SIN to ensure that the etching rate of silicon nitride is higher than that of other materials, effectively remove the silicon nitride layer, while reducing the etching effect on other materials.

[0089] Step 5. Perform a grinding process to thin the remaining first oxide layer 1 and remove the top of the silicon oxide layer 3 to expose the hard mask layer 4, see Figure 9 .

[0090] Step 6. Perform an etching process to remove the top of the hard mask layer 4 and remove part of the side wall of the silicon nitride layer 2 and the silicon oxide layer 3 to expose the top surface of the gate polysilicon layer 5, see Figure 10 .

[0091] Step 7. Deposit the second oxide layer 6 above the gate polysilicon layer 5, see Figure 12 . Perform a grinding process to grind until the top surface of the gate polysilicon layer 5 stops, see Figure 7 .

[0092] In the third embodiment, after the step 6 is completed, the method described in the third embodiment is additionally added with a key step, i.e. depositing a thin second oxide layer 6, compared with the method described in the second embodiment. The oxide deposition in this step does not need to be too thick, and the main purpose is to facilitate the subsequent grinding operation. Considering that the first oxide layer 1 may be lost in the previous dry etching step, resulting in insufficient retention. If direct grinding is performed, the process accuracy may be affected due to the increased control difficulty. Therefore, by depositing this thin second oxide layer 6, the difficulty of the grinding process can be effectively alleviated, so that the planarization process is easier to achieve, thereby ensuring the stability and controllability of the entire process flow.

[0093] In the third embodiment, the second oxide layer 6 and the first oxide layer 1 are made of the same material, such as silicon dioxide, which can reduce the CMP loading.

[0094] In the third embodiment, the etching process adopts a dry etching process, and the grinding process adopts a chemical mechanical polishing process.

[0095] In the third embodiment, a semiconductor structure is made by using the improved NMOS and PMOS height difference method as in the third embodiment.

[0096] In the third embodiment, a semiconductor device is made by using the semiconductor structure as in the third embodiment.

[0097] The present application realizes the accurate adjustment of the NMOS and PMOS height difference without changing the semiconductor layout by the innovative grinding and etching combined process, the optimized grinding process, the simplified process steps, and the improved grinding uniformity, etc., reduces the pattern loading, optimizes the ILD0 CMP process, reduces the manufacturing cost and time cost, and improves the product quality and reliability.

[0098] The above embodiments are the preferred embodiments of the present application, but the embodiments of the present application are not limited by the above embodiments, and any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present application are equivalent replacement methods, and are all included in the protection scope of the present application.

Claims

1. A method of improving NMOS and PMOS height difference, characterized by, The method comprises the following steps: Step 1. providing an intermediate product, the intermediate product comprising at least a PMOS region and an NMOS region, the PMOS region and the NMOS region each being formed with a polysilicon gate structure and a first oxide layer (1) covering the polysilicon gate structure, the polysilicon gate structure comprising, from inside to outside, a gate polysilicon layer (5), a hard mask layer (4), a silicon oxide layer (3) and a silicon nitride layer (2); Step 2. performing a grinding process to grind the first oxide layer (1) so that the surface of the first oxide layer (1) is flush; Step 3. performing an etching process to thin the remaining first oxide layer (1) to expose the top of the silicon nitride layer (2); Step 4. performing an etching process to remove the top of the silicon nitride layer (2) and a part of the side wall to expose the top of the silicon oxide layer (3); Step 5. performing a grinding process to thin the remaining first oxide layer (1) and remove the top of the silicon oxide layer (3) and the hard mask layer (4) until the top surface of the gate polysilicon layer (5) stops.

2. The method of claim 1, wherein, The hard mask layer (4) covers the gate polysilicon layer (5), the silicon oxide layer (3) covers the hard mask layer (4), and the silicon nitride layer (2) covers the silicon oxide layer (3).

3. A semiconductor structure, characterized by: The semiconductor structure is made by the method for improving the height difference between NMOS and PMOS as claimed in claim 1 or 2.

4. A semiconductor device, characterized by The semiconductor structure is made by the method as claimed in claim 3.

5. A method of improving NMOS and PMOS height difference, characterized by, The method comprises the following steps: Step 1. providing an intermediate product, the intermediate product comprising at least a PMOS region and an NMOS region, the PMOS region and the NMOS region each being formed with a polysilicon gate structure and a first oxide layer (1) covering the polysilicon gate structure, the polysilicon gate structure comprising, from inside to outside, a gate polysilicon layer (5), a hard mask layer (4), a silicon oxide layer (3) and a silicon nitride layer (2); Step 2. performing a grinding process to grind the first oxide layer (1) so that the surface of the first oxide layer (1) is flush; Step 3. performing an etching process to thin the remaining first oxide layer (1) to expose the top of the silicon nitride layer (2); Step 4. performing an etching process to remove the top of the silicon nitride layer (2) and a part of the side wall to expose the top of the silicon oxide layer (3); Step 5. performing a grinding process to thin the remaining first oxide layer (1) and remove the top of the silicon oxide layer (3) to expose the hard mask layer (4); Step 6. performing an etching process to remove the top of the hard mask layer (4) and remove a part of the side wall of the silicon nitride layer (2) and the silicon oxide layer (3) to expose the top surface of the gate polysilicon layer (5); Step 7. depositing a second oxide layer (6) above the gate polysilicon layer (5), performing a grinding process to thin the remaining first oxide layer (1) until the top surface of the gate polysilicon layer (5) stops.

6. The method of claim 5, wherein The second oxide layer (6) is of the same material as the first oxide layer (1).

7. The method of claim 5, wherein the method is improved by, The hard mask layer (4) is covered outside the gate polysilicon layer (5), the silicon oxide layer (3) is covered outside the hard mask layer (4), and the silicon nitride layer (2) is covered outside the silicon oxide layer (3).

8. A semiconductor structure, characterized by: The semiconductor structure is made by the method for improving the height difference between NMOS and PMOS as claimed in any one of claims 5 to 7.

9. A semiconductor device, characterized by The semiconductor structure is made by the method for improving the height difference between NMOS and PMOS as claimed in any one of claims 5 to 7.

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