Photovoltaic cell, manufacturing method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a photovoltaic cell and a manufacturing method thereof, and a photovoltaic module. The first electrodes are located on the surface of the substrate and arranged at intervals in the first direction, the second electrodes are arranged at intervals in the second direction, and the first direction intersects with the second direction; the surface of the substrate comprises an overlapping area provided with a first electrode and a second electrode simultaneously, and the second electrode is arranged on the side, away from the substrate, of the first electrode located in the overlapping area. The dielectric layer is at least located between the second electrode and the first electrode, holes are formed in the dielectric layer located in the overlapping area, and the first electrode and / or the second electrode are / is contained in at least part of the holes, so that the first electrode is in contact with the second electrode, and the electrical performance of the photovoltaic cell is at least improved.

Description

Technical Field

[0001] This application relates to the photovoltaic field, and in particular to a photovoltaic cell and its manufacturing method, and a photovoltaic module. Background Technology

[0002] Photovoltaic cells, as a sustainable and clean energy source, are being used more and more widely. A photovoltaic cell is a device that uses the photovoltaic principle to generate charge carriers, converting solar energy into electrical energy. Electrodes are typically used in photovoltaic cells to extract these charge carriers, thus efficiently utilizing the electrical energy. Currently, the mainstream types of photovoltaic cells include BC cells (BackContact), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell), and heterojunction cells (Heterojunction with Intrinsic Thin-film, abbreviated as HIT or HJT).

[0003] However, to further transport and collect the photogenerated carriers generated in photovoltaic cells, electrodes are formed within the cells, and other film layers are also designed into them. Therefore, to comprehensively improve the electrical performance of photovoltaic cells, the coordination between the electrodes and other film layers requires further research. Summary of the Invention

[0004] This application provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module, which at least helps to improve the electrical performance of the photovoltaic cell.

[0005] According to some embodiments of this application, one aspect of this application provides a photovoltaic cell, comprising: a substrate; a plurality of first electrodes and a plurality of second electrodes arranged at intervals along a first direction on the surface of the substrate, the first direction and the second direction intersecting; wherein, the surface of the substrate includes an overlapping region where the first electrodes and the second electrodes are simultaneously disposed, and the second electrode is disposed on the side of the first electrode in the overlapping region away from the substrate; a dielectric layer, at least located between the second electrodes and the first electrodes, and the dielectric layer in the overlapping region having pores, at least a portion of the pores accommodating the first electrode and / or the second electrode, such that the first electrode and the second electrode are in contact.

[0006] In some embodiments, the first electrode has a bottom end and a top end along a third direction, the bottom end being closer to the substrate, and the third direction being the thickness direction of the substrate; in the dielectric layer located in the overlapping region, the thickness of the dielectric layer on the surface located at the bottom end is greater than or equal to the thickness of the dielectric layer on the surface located at the top end.

[0007] In some embodiments, in the dielectric layer located in the overlapping region, the thickness of the dielectric layer located on the side of the first electrode gradually decreases along the direction from the bottom end to the top end.

[0008] In some embodiments, the surface of the substrate further includes a first region on which the first electrode is disposed; the dielectric layer is also located on the first region and on the surface of the first electrode away from the substrate.

[0009] In some embodiments, the ratio of the area of ​​the overlapping region to the area of ​​the first region is 0.005% to 1.705%.

[0010] In some embodiments, the surface of the substrate further includes a second region on which the second electrode is disposed; the dielectric layer is also located on the second region and between the second electrode and the substrate.

[0011] In some embodiments, the surface of the substrate further includes a third region, which is a region where the first electrode and the second electrode are not disposed; the dielectric layer is also located on the third region.

[0012] In some embodiments, the surface of the substrate further includes a protection zone in addition to the overlapping region, the protection zone being a region where the first electrode is not disposed, and the dielectric layer is located on at least a portion of the protection zone; wherein the ratio of the thickness of the dielectric layer located in the protection zone to the thickness of the dielectric layer located in the overlapping region is 30% to 50%.

[0013] In some embodiments, the thickness of the dielectric layer located in the protected area is 30 nm to 200 nm.

[0014] In some embodiments, the photovoltaic cell further includes: a transparent conductive layer located between the dielectric layer and the substrate, and between the first electrode and the substrate.

[0015] In some embodiments, the thickness of the transparent conductive layer is 20 nm to 200 nm.

[0016] In some embodiments, the material of the first electrode and / or the material of the second electrode comprises a metal or a mixture of a metal and an organic polymer; wherein the metal comprises at least one of Ag, Al, Cu, Mg, Mo, W, Cr, Ni or Sn.

[0017] In some embodiments, the material of the dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or magnesium fluoride.

[0018] In some embodiments, the width of the overlapping region in the extension direction perpendicular to the first electrode is 5 μm to 40 μm.

[0019] In some embodiments, the substrate includes: a substrate, one surface of which includes a fourth region and a fifth region alternately arranged along the first direction; a first semiconductor layer and a first doped layer, the first semiconductor layer being located on the fourth region and the first doped layer being located on the side of the first semiconductor layer away from the substrate; a second semiconductor layer and a second doped layer, the second semiconductor layer being located on the fifth region and the second doped layer being located on the side of the second semiconductor layer away from the substrate, the second doped layer and the first doped layer being doped with different types of doping elements; a first electrode including a first current collector located on the fourth region and a second current collector located on the fifth region, the first current collector being electrically connected to the first doped layer and the second current collector being electrically connected to the second doped layer; wherein, the first semiconductor layer and the second semiconductor layer are tunneling layers, and the first doped layer and the second doped layer are doped polycrystalline silicon layers; or, the first semiconductor layer and the second semiconductor layer are intrinsic amorphous silicon layers, and the first doped layer and the second doped layer are doped amorphous silicon layers; or, the first semiconductor layer is the tunneling layer, the first doped layer is the doped polycrystalline silicon layer, the second semiconductor layer is the intrinsic amorphous silicon layer, and the second doped layer is the doped amorphous silicon layer.

[0020] In some embodiments, the substrate includes: a substrate having two surfaces opposite each other along a third direction; a semiconductor layer located on one of the two surfaces; a doped layer located on the side of the semiconductor layer away from the substrate; the first electrode includes a first current collector located on the side of the doped layer away from the substrate, and a second current collector located on the other of the two surfaces; wherein the semiconductor layer is a tunneling layer and the doped layer is a doped polycrystalline silicon layer; or, the semiconductor layer is an intrinsic amorphous silicon layer and the doped layer is a doped amorphous silicon layer.

[0021] According to some embodiments of this application, another aspect of this application provides a method for manufacturing a photovoltaic cell, comprising: providing a substrate; forming a plurality of first electrodes spaced apart along a first direction on the surface of the substrate; forming an initial dielectric layer on the surface jointly formed by the substrate and the first electrodes; forming a plurality of second electrodes spaced apart along a second direction on the surface of the initial dielectric layer, wherein the first direction and the second direction intersect; wherein the surface of the substrate includes an overlap region where the first electrodes and the second electrodes are simultaneously disposed, and during the formation of the second electrodes, the initial dielectric layer located in the overlap region is transformed into a porous dielectric layer, and at least a portion of the pores accommodate the first electrodes and / or the second electrodes, such that the first electrodes and the second electrodes are in contact.

[0022] In some embodiments, the initial medium layer is formed by a deposition process; wherein the deposition process is performed at a temperature of 100°C to 300°C and for a duration of 10 min to 120 min.

[0023] In some embodiments, the step of forming the second electrode includes: forming a plurality of initial second electrodes spaced apart along the second direction on the surface of the initial dielectric layer; and sequentially performing a drying process and a curing process on the initial second electrodes to transform the initial second electrodes into the second electrode; wherein the drying process is performed at a temperature of 100°C to 200°C for a duration of 1 min to 10 min, the curing process is performed at a temperature of 60°C to 250°C for a duration of 0 min to 60 min.

[0024] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: a battery string, which is formed by connecting a plurality of photovoltaic cells as described in any one of the above claims, or by connecting a plurality of photovoltaic cells formed by the manufacturing method of photovoltaic cells as described in any one of the above claims; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0025] The technical solution provided in this application has at least the following advantages: First, the first electrode is designed to make direct ohmic contact with the surface of the substrate. Furthermore, while retaining the dielectric layer located between the first and second electrodes, the dielectric layer located in the overlapping region is designed to have pores, and at least a portion of the pores accommodate the first and / or second electrodes to ensure ohmic contact between the first and second electrodes. Thus, on the one hand, the direct ohmic contact between the first electrode and the substrate surface facilitates the control of a good contact morphology between the first electrode and the substrate, thereby improving the collection efficiency of photogenerated carriers in the substrate. On the other hand, it allows for the use of low-cost, low-burn-through or non-burn-through conductive materials for the first electrode, ensuring direct contact between the first electrode and the substrate surface without causing significant damage to the substrate, and reducing the fabrication cost of the first electrode. Furthermore, before the formation of the second electrode, a dielectric layer can protect the first electrode, reducing the risk of damage or contamination and improving its yield. Moreover, by utilizing a porous dielectric layer located in the overlap region to ensure ohmic contact between the first and second electrodes, the second electrode can also be made from low-cost, low-burn-through or non-burn-through conductive materials, further reducing its fabrication cost. Therefore, this multi-faceted approach contributes to a comprehensive improvement in the electrical performance of photovoltaic cells. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a partial top view of a photovoltaic cell provided in an embodiment of this application; Figure 2 for Figure 1 The diagram shows a partial cross-sectional view of the photovoltaic cell along the first cross-sectional direction AA1. Figure 3 for Figure 1 The diagram shows a partial cross-sectional view of the photovoltaic cell along the second cross-section direction BB1. Figure 4 for Figure 1 The diagram shows a partial cross-sectional view of the photovoltaic cell along the third section direction CC1. Figure 5This is another partial top view schematic diagram of a photovoltaic cell provided in an embodiment of this application; Figure 6 This is a partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application; Figure 7 This is another partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application; Figure 8 This is another partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application; Figure 9 A process flow diagram of a method for manufacturing a photovoltaic cell according to another embodiment of this application; Figure 10 A partial cross-sectional view of a semi-finished cell after the formation of the initial dielectric layer in a photovoltaic cell manufacturing method provided in another embodiment of this application, along the first cross-sectional direction AA1. Figure 11 Provided for yet another embodiment of this application Figure 1 A partial 3D schematic diagram of the battery string in the corresponding photovoltaic module; Figure 12 Provided for yet another embodiment of this application Figure 11 A partial cross-sectional schematic diagram of the corresponding photovoltaic module; Figure 13 Provided for yet another embodiment of this application Figure 5 A partial 3D schematic diagram of the battery string in the corresponding photovoltaic module; Figure 14 Provided for yet another embodiment of this application Figure 13 A partial cross-sectional schematic diagram of the corresponding photovoltaic module.

[0028] Explanation of reference numerals in the attached figures: 100. Substrate; 110. First region; 120. Second region; 130. Overlapping region; 140. Third region; 101. First electrode; 111. Bottom end; 121. Top end; 131. First current collector electrode; 141. Second current collector electrode; 102. Second electrode; 103. Dielectric layer; 113. Pore; 123. Initial dielectric layer; 104. Transparent conductive layer; 105. Substrate; 115. Fourth region; 12 5. Fifth region; 135. Surface; 1351. First surface; 1352. Second surface; 106. Semiconductor layer; 116. First semiconductor layer; 126. Second semiconductor layer; 136. Second intrinsic amorphous silicon layer; 107. Doped layer; 117. First doped layer; 127. Second doped layer; 137. Second doped amorphous silicon layer; 40. Photovoltaic cell; 41. Encapsulating film; 42. Cover plate; 43. Solder ribbon. Detailed Implementation

[0029] As can be seen from the background technology, the electrical performance of photovoltaic cells needs to be improved.

[0030] This application provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module. In the photovoltaic cell, a first electrode is designed to be in direct ohmic contact with the surface of the substrate. Furthermore, while retaining the dielectric layer located between the first electrode and the second electrode, the dielectric layer located in the overlapping area is designed to have pores, and at least a portion of the pores accommodate the first electrode and / or the second electrode to ensure ohmic contact between the first electrode and the second electrode. Thus, on the one hand, the direct ohmic contact between the first electrode and the substrate surface facilitates the control of a good contact morphology between the first electrode and the substrate, thereby improving the collection efficiency of photogenerated carriers in the substrate. On the other hand, it allows for the use of low-cost, low-burn-through or non-burn-through conductive materials for the first electrode, ensuring direct contact between the first electrode and the substrate surface without causing significant damage to the substrate, and reducing the fabrication cost of the first electrode. Furthermore, before the formation of the second electrode, a dielectric layer can protect the first electrode, reducing the risk of damage or contamination and improving its yield. Moreover, by utilizing a porous dielectric layer located in the overlap region to ensure ohmic contact between the first and second electrodes, the second electrode can also be made from low-cost, low-burn-through or non-burn-through conductive materials, further reducing its fabrication cost. Therefore, this multi-faceted approach contributes to a comprehensive improvement in the electrical performance of photovoltaic cells.

[0031] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0034] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0035] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0036] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0037] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0038] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0039] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0041] This application provides a photovoltaic cell according to one embodiment. The photovoltaic cell provided by this application will be described in detail below with reference to the accompanying drawings.

[0042] Reference Figure 1 and Figure 2 The photovoltaic cell includes: a substrate 100; a plurality of first electrodes 101 arranged at intervals along a first direction X and a plurality of second electrodes 102 arranged at intervals along a second direction Y on the surface of the substrate 100, wherein the first direction X and the second direction Y intersect; wherein the surface of the substrate 100 includes an overlap region 130 on which the first electrodes 101 and the second electrodes 102 are simultaneously disposed, and the second electrodes 102 are disposed on the side of the first electrodes 101 away from the substrate 100 in the overlap region 130; a dielectric layer 103, at least located between the second electrodes 102 and the first electrodes 101, and having pores 113 in the dielectric layer 103 in the overlap region 130, wherein at least a portion of the pores 113 accommodate the first electrodes 101 and / or the second electrodes 102, such that the first electrodes 101 and the second electrodes 102 are in contact. Thus, the dielectric layer 103 in the overlap region 130 can be considered as a film layer discontinuously distributed between the first electrodes 101 and the second electrodes 102.

[0043] in, Figure 1This is a partial top view of a photovoltaic cell provided in an embodiment of this application. Figure 2 for Figure 1 The diagram shows a partial cross-sectional view of the photovoltaic cell along the first cross-sectional direction AA1. Furthermore, Figure 1 The image clearly illustrates the positional arrangement of the first electrode 101 and the second electrode 102 on the surface of the substrate 100, but the dielectric layer is not shown.

[0044] It is worth noting that in current mainstream electrode designs, to achieve ohmic contact between the first electrode and the substrate surface, the first electrode needs to penetrate other film layers located on the surface of the substrate 100, such as a dielectric layer. Therefore, the raw materials for the first electrode typically employ high-cost, high-burn-through conductive materials, which require high-temperature sintering and annealing, and are prone to excessive erosion of parts of the film layer located in the substrate, affecting the performance of that film layer. Furthermore, the contact morphology between the first electrode and the substrate surface is difficult to control. Moreover, no additional film layer is designed at the contact point between the first and second electrodes.

[0045] In contrast, in a photovoltaic cell provided in one embodiment of this application, the first electrode 101 can be designed to directly make ohmic contact with the surface of the substrate 100. Furthermore, while retaining the dielectric layer 103 located between the first electrode 101 and the second electrode 102, the dielectric layer 103 located in the overlap region 130 is designed to have pores 113, and at least a portion of the pores 113 accommodate the first electrode 101 and / or the second electrode 102, ensuring ohmic contact between the first electrode 101 and the second electrode 102. Thus, on the one hand, the direct ohmic contact between the first electrode 101 and the surface of the substrate 100 facilitates control of a good contact morphology between the first electrode 101 and the substrate 100, thereby improving the collection efficiency of photogenerated carriers in the substrate 100 by the first electrode 101. On the other hand, it allows the use of low-cost, low-burn-through conductive materials or non-burn-through conductive materials for the raw materials of the first electrode 101, ensuring direct contact between the first electrode 101 and the surface of the substrate 100 without causing significant damage to the substrate 100. Moreover, it reduces the fabrication cost of the first electrode 101. On the one hand, cost is a concern; on the other hand, before the second electrode 102 is formed, the first electrode 101 can be protected by the dielectric layer 103 to reduce the risk of damage or contamination to the first electrode 101, thereby improving the yield of the first electrode 101. Furthermore, by using the dielectric layer 103 with pores 113 located in the overlap region 130 to ensure ohmic contact between the first electrode 101 and the second electrode 102, the raw materials for the second electrode 102 can be low-cost low-burn-through conductive materials or non-burn-through conductive materials, thus reducing the manufacturing cost of the second electrode 102. Therefore, this multi-faceted approach is beneficial for comprehensively improving the electrical performance of photovoltaic cells.

[0046] It should be noted that in the photovoltaic cell provided in one embodiment of this application, the dielectric layer 103 may be located not only in front of the first electrode 101 and the second electrode 102, but also in other areas on the surface of the substrate 100, so that the dielectric layer 103 can play a role in reducing reflection or protection. The dielectric layer 103 will be described later. Based on this, the dielectric layer 103 between the first electrode 101 and the second electrode 102, that is, the dielectric layer 103 located in the overlap region 130, is designed to have pores 113. This is beneficial to ensure the ohmic contact between the first electrode 101 and the second electrode 102 without removing the dielectric layer 103 located in the overlap region 130, and to avoid the etching damage to the first electrode when removing the dielectric layer located in the overlap region, and to simplify the fabrication process of the photovoltaic cell.

[0047] The photovoltaic cell provided in one embodiment of this application will be described in more detail below with reference to the accompanying drawings.

[0048] In some embodiments, continue to refer to Figure 2 The first electrode 101 has a bottom end 111 and a top end 121 along the third direction Z. The bottom end 111 is closer to the substrate 100. The third direction Z is the thickness direction of the substrate 100. In the dielectric layer 103 located in the overlapping region 130, the thickness of the dielectric layer 103 located on the surface of the bottom end 111 is greater than or equal to the thickness of the dielectric layer 103 located on the surface of the top end 121.

[0049] It should be noted that, Figure 2 The bottom end 111 and the top end 121 in the first electrode 101 are divided by dashed lines, and Figure 2 The bottom end 111 and the top end 121 are only relative examples, and there is no limitation on the proportion of the bottom end 111 and the top end 121 in the first electrode 101.

[0050] It is worth noting that, based on the manufacturing process of the first electrode 101, the cross-sectional shape of the first electrode 101 along the extension direction perpendicular to the first electrode 101 can be approximately semi-elliptical. In other words, along the direction gradually moving away from the substrate 100, the cross-sectional width of at least a portion of the first electrode 101 gradually decreases. In practical applications, the cross-sectional shape of the first electrode along the extension direction perpendicular to the first electrode can also be approximately rectangular.

[0051] Furthermore, when the cross-sectional shape of the first electrode is semi-elliptical, the top end of the first electrode may include a top surface with a larger width in the first direction and a side surface that slopes towards the center of the top end.

[0052] In some cases, based on the surface morphology of the first electrode 101, when designing the dielectric layer 103 on the surface of the first electrode 101, a thicker dielectric layer 103 is designed at the bottom end 111, which is beneficial to improve the protective effect of the dielectric layer 103 on the surface contact between the first electrode 101 and the substrate 100; at least a thinner dielectric layer 103 is designed on the side of the top end 121, which is beneficial to reduce the difficulty of forming pores 113 in the dielectric layer 103, so as to further ensure the ohmic contact between the second electrode 102 and the first electrode 101.

[0053] Furthermore, when the first electrode 101 protrudes from the surface of the substrate 100, the coverage of the dielectric layer 103 at the step changes due to the manufacturing process of the dielectric layer 103. This makes it easier to form a thicker dielectric layer 103 at the bottom 111 and a thinner dielectric layer 103 at least on the side of the top 121. It is worth noting that even when the width of the top surface of the top 121 is small, a thinner dielectric layer 103 will also be formed on the top surface of the top 121. In practical applications, when the width of the top surface of the top is large, a thicker dielectric layer, for example, one with a thickness substantially the same as the dielectric layer at the bottom, will also be formed on the top surface of the top.

[0054] In some examples, continue to refer to Figure 2 In the dielectric layer 103 located in the overlapping region 130, the thickness of the dielectric layer 103 located on the side of the first electrode 101 gradually decreases along the direction from the bottom end 111 to the top end 121. It is worth noting that when the first electrode 101 protrudes from the surface of the substrate 100, and the cross-sectional width of at least a portion of the first electrode 101 gradually decreases along the direction gradually away from the substrate 100, the dielectric layer 103 has the characteristic of becoming thinner towards the top. The thinner thickness is more advantageous when designing the second electrode 102, so that the dielectric layer 103 located between the second electrode 102 and the first electrode 101 has pores 113.

[0055] It should be noted that the side surface of the first electrode 101 includes the surface of the bottom end 111 and the side surface of the top end 121. In actual application, based on the difference in the width of the top surface of the top end, the thickness of the dielectric layer on the top surface of the top end may be less than the thickness of the dielectric layer on the side surface of the top end, and the thickness of the dielectric layer on the top surface of the top end may also be basically the same as the thickness of the dielectric layer on the bottom end.

[0056] The following provides a detailed description of the layout and location of the dielectric layer 103 on the substrate 100.

[0057] In some embodiments, in conjunction with reference Figure 1 and Figure 3 , Figure 3 for Figure 1The photovoltaic cell shown is a partial cross-sectional schematic diagram along the second cross-sectional direction BB1. The surface of the substrate 100 may also include a first region 110 on which the first electrode 101 is disposed; the dielectric layer 103 is also located on the first region 110 and on the surface of the first electrode 101 away from the substrate 100.

[0058] It should be noted that the first region 110 can be considered as the area where the first electrode 101 is disposed but the second electrode 102 is not disposed. In other words, the first region 110 can be considered as the area where the first electrode 101 is located except for the portion located in the overlapping region 130, that is, the area where the portion of the first electrode 101 is not covered by the second electrode 102. Thus, if the dielectric layer 103 is designed to be located in the overlapping region 130 and the first region 110, the dielectric layer 103 will cover the entire surface of the first electrode 101, and the surface of the first electrode 101 not covered by the second electrode 102 will also be covered by the dielectric layer 103.

[0059] Generally, the first electrode 101 contains a large amount of metallic material, which has a strong reflective ability to incident light. The dielectric layer 103 is designed to be located in the overlapping region 130 and the first region 110. The dielectric layer 103 can reduce the reflectivity of incident light irradiating the region where the first electrode 101 is located. That is, the anti-reflection effect of the dielectric layer 103 prevents incident light from directly irradiating the surface of the first electrode 101, so as to avoid a large amount of incident light reflected by the first electrode 101 from propagating in a direction away from the substrate 100 and not being utilized by the substrate 100. This is conducive to allowing more incident light to be absorbed and utilized by the substrate 100. On the other hand, the dielectric layer 103 can protect the entire first electrode 101.

[0060] It is worth emphasizing that, compared to the dielectric layer 103 located in the overlapping region 130, which has pores 113, the dielectric layer 103 located in the first region 110 has a higher density and better insulation properties. In other words, the dielectric layer 103 located in the first region 110 has almost no pores that can achieve electrical conduction. Alternatively, the dielectric layer 103 located in the overlapping region 130 can be regarded as a film layer that is discontinuously distributed between the first electrode 101 and the second electrode 102, while the dielectric layer 103 located in the first region 110 can be regarded as a film layer that is continuously distributed on the surface of the substrate 100. Furthermore, the thickness of the dielectric layer 103 located in the first region 110 is substantially the same as the thickness of the dielectric layer 103 located in the overlapping region 130.

[0061] Based on this, only the dielectric layer 103 located between the second electrode 102 and the first electrode 101 is designed, that is, the dielectric layer 103 located in the overlap region 130 has pores 113 that can achieve electrical conduction. This is beneficial because when preparing the dielectric layer 103, the first electrode 101 and the second electrode 102 can be ohmic contacted without removing the dielectric layer 103 located in the overlap region 130. Moreover, it can avoid the etching damage to the first electrode when removing the dielectric layer located in the overlap region, and can simplify the photovoltaic cell manufacturing process.

[0062] In some cases, continue to combine references Figure 1 and Figure 3 The ratio of the area of ​​the overlapping area 130 to the area of ​​the first area 110 can be 0.005% to 1.705%, for example, it can be 0.05%, 0.1%, 0.15%, 0.2%, 0.25%, 0.3%, 0.35%, 0.4%, 0.45%, 0.5%, 0.55%, 0.6%, 0.65%, 0.7%, 0.75%, 0.8%, 0.85%, 0.9%, 0.95%, 1%, 1.05%, 1.1%, 1.15%, 1.2%, 1.25%, 1.3%, 1.35%, 1.4%, 1.45%, 1.5%, 1.55%, 1.6%, 1.65%, or 1.7%, etc.

[0063] It is worth noting that the area of ​​the overlapping region 130 can be considered as the layout area occupied by the overlapping portions of a single first electrode 101 and a single second electrode 102 on the surface of the substrate 100, and the area of ​​the first region 110 can be considered as the layout area occupied by a single first electrode 101 on the surface of the substrate 100. Designing the ratio of the area of ​​the overlapping region 130 to the area of ​​the first region 110 to be 0.005% to 1.705% is beneficial in ensuring that the single first electrode 101 and the single second electrode 102 have suitable contact areas, and that different regions in the single first electrode 101 can respectively achieve ohmic contact with multiple second electrodes 102, thereby ensuring that the second electrodes 102 have a good current-collecting effect on the charge carriers in the first electrode 101.

[0064] In some embodiments, in conjunction with reference Figures 1 to 4 , Figure 4 for Figure 1 The photovoltaic cell shown is a partial cross-sectional view along the third cross-sectional direction CC1. The surface of the substrate 100 may also include a second region 120 on which a second electrode 102 is disposed; the dielectric layer 103 is also located on the second region 120 and between the second electrode 102 and the substrate 100.

[0065] It should be noted that the second region 120 can be considered as the region where the second electrode 102 is disposed but the first electrode 101 is not disposed. In other words, the second region 120 can be considered as the region where the second electrode 102 is located except for the portion located in the overlapping region 130, that is, the region where the portion of the second electrode 102 that does not overlap with the first electrode 101 is located. Thus, if the dielectric layer 103 is designed to be located in the overlapping region 130 and the second region 120, then the second electrode 102 can be considered as being located on the side of the dielectric layer 103 away from the substrate 100, that is, not only is there a dielectric layer 103 including pores 113 disposed between the second electrode 102 and the first electrode 101, but there is also a dielectric layer 103 disposed between the portion of the second electrode 102 that does not overlap with the first electrode 101 and the substrate 100.

[0066] It is worth emphasizing that, compared to the dielectric layer 103 located in the overlap region 130, which has pores 113, the dielectric layer 103 located in the second region 120 has a higher density and better insulation properties. In other words, the dielectric layer 103 located in the second region 120 has almost no pores that can achieve electrical conduction. Alternatively, the dielectric layer 103 located in the overlap region 130 can be regarded as a film layer that is discontinuously distributed between the first electrode 101 and the second electrode 102, while the dielectric layer 103 located in the second region 120 can be regarded as a film layer that is continuously distributed on the surface of the substrate 100.

[0067] Furthermore, while enhancing the anti-reflection effect on incident light with the dielectric layer 103, the second electrode 102 is designed to be located above the dielectric layer 103. This ensures that the second electrode 102 is not covered by the dielectric layer 103, and the dielectric layer 103 does not cause failure issues when subsequently connecting the second electrodes 102 of adjacent photovoltaic cells using solder ribbons. In other words, the second electrode 102 is designed to be exposed above the dielectric layer 103 to facilitate effective electrical connection of the solder ribbon to the second electrode 102. Moreover, compared to forming an anti-reflection dielectric layer on the surfaces of the first and second electrodes and then removing the dielectric layer on the surface of the second electrode, the photovoltaic cell provided in this embodiment eliminates the need to remove the dielectric layer on the surface of the second electrode 102. This avoids etching damage to the second electrode 102 and simplifies the photovoltaic cell fabrication process.

[0068] In some cases, in conjunction with references Figures 1 to 4 The dielectric layer 103 is located on the first region 110, the second region 120 and the overlapping region 130. Unlike the entire surface of the first electrode 101 away from the substrate 100, which is covered by the dielectric layer 103, the entire second electrode 102 can be regarded as located on the side of the dielectric layer 103 away from the substrate 100. The dielectric layer 103 between the second electrode 102 and the first electrode 101 has pores 113 so that the second electrode 102 and the first electrode 101 can be in ohmic contact.

[0069] In some embodiments, in conjunction with reference Figures 1 to 4 The surface of the substrate 100 may further include a third region 140, which is a region where the first electrode 101 and the second electrode 102 are not disposed; the dielectric layer 103 is also located on the third region 140. In this way, the substrate 100 can be protected by the dielectric layer 103 located in the third region 140, and the risk of light incident on the third region 140 being reflected can be reduced, thereby improving the absorption and utilization of light by the substrate 100 located in the third region 140.

[0070] It is worth emphasizing that, compared to the dielectric layer 103 located in the overlap region 130, which has pores 113, the dielectric layer 103 located in the third region 140 has a higher density and better insulation properties. In other words, the dielectric layer 103 located in the third region 140 has almost no pores that can achieve electrical conduction. Alternatively, the dielectric layer 103 located in the overlap region 130 can be regarded as a film layer that is discontinuously distributed between the first electrode 101 and the second electrode 102, while the dielectric layer 103 located in the third region 140 can be regarded as a film layer that is continuously distributed on the surface of the substrate 100.

[0071] In some cases, continue to combine references Figures 1 to 4 The dielectric layer 103 may be located on the first region 110, the second region 120, the overlapping region 130 and the third region 140. In other words, the dielectric layer 103 may be located on the entire surface of the substrate 100, and a first electrode 101 is disposed between the dielectric layer 103 and the substrate 100, and a second electrode 102 is disposed on the side of the dielectric layer 103 away from the substrate 100.

[0072] In some embodiments, in conjunction with reference Figures 1 to 4 The surface of the substrate 100 may also include a protection zone other than the overlapping region 130. The protection zone is a region where the first electrode 101 is not disposed, and the dielectric layer 103 is located on at least a portion of the protection zone. The ratio of the thickness of the dielectric layer 103 in the protection zone to the thickness of the dielectric layer 103 in the overlapping region 130 may be 30% to 50%, for example, it may be 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, or 49%, etc.

[0073] It should be noted that the protected area includes at least one of the second region 120 and the third region 140. Furthermore, compared to the dielectric layer 103 located in the overlapping region 130, which has pores 113, the dielectric layer 103 located in the protected area, for example, the dielectric layer 103 located in either the second region 120 or the third region 140, has a higher density. In other words, the dielectric layer 103 located in either the second region 120 or the third region 140 has almost no pores that allow for electrical conduction; that is, the dielectric layer 103 located in either the second region 120 or the third region 140 has good insulation properties, preventing unnecessary electrical connections between the subsequent first electrode 101 and other conductive components. Moreover, the dielectric layer 103 located in either the second region 120 or the third region 140 can serve as an anti-reflection layer to reduce the reflectivity of incident light, significantly increasing the area of ​​the substrate 100 that can be used for efficient absorption of incident light, thereby reducing optical reflection loss and increasing the current density of the photovoltaic cell. In addition, the dielectric layer 103 can cover the entire surface formed by the substrate 100 and the first electrode 101.

[0074] It is worth noting that, since the first electrode 101 is already designed on the surface of the substrate 100 before the dielectric layer 103 is designed, the surface formed by the substrate 100 and the first electrode 101 is raised in the area where the first electrode 101 is located. Due to the manufacturing process of the dielectric layer 103, the coverage of the dielectric layer 103 at the raised area is changed, resulting in the thickness of the dielectric layer 103 in the protected area being greater than the thickness of at least a portion of the dielectric layer 103 in the overlapping area 130, and the thickness of the dielectric layer 103 in the protected area being greater than the thickness of at least a portion of the dielectric layer 103 in the first area 110. Based on the control of the manufacturing process of the dielectric layer 103, the ratio of the thickness of the dielectric layer 103 in the protected area to the thickness of the dielectric layer 103 in the overlapping area 130 can be designed to be 30% to 50%. This is beneficial to ensure that a thicker dielectric layer 103 is provided on the protected area to improve the protection and anti-reflection effect on the substrate 100, while a thinner dielectric layer 103 is provided on the overlapping area 130 to reduce the difficulty of forming pores 113 in the dielectric layer 103 located in the overlapping area 130, so as to further ensure the ohmic contact between the second electrode 102 and the first electrode 101.

[0075] In some cases, the thickness of the dielectric layer 103 located in the protected area can be 30nm~200nm, for example, it can be 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm or 190nm, etc.

[0076] In some embodiments, reference Figures 2 to 4The photovoltaic cell may also include: a transparent conductive layer 104 located between the dielectric layer 103 and the substrate 100 and between the first electrode 101 and the substrate 100.

[0077] It is worth noting that the transparent conductive layer 104 is used to assist the electrical connection between the first electrode 101 and the substrate 100. Before designing the first electrode 101, the transparent conductive layer 104 can be disposed at least in the region used to fabricate the first electrode 101, i.e., the first region 110. Generally, in addition to the first region 110, the transparent conductive layer 104 is also disposed around the first region 110 on the surface of the substrate 100. In other words, the orthographic projection of the first electrode 101 on the substrate 100 lies within the orthographic projection of the transparent conductive layer 104 on the substrate 100, and the orthographic projection area of ​​the transparent conductive layer 104 on the substrate 100 can be greater than or equal to the orthographic projection area of ​​the first electrode 101 on the substrate 100.

[0078] Furthermore, the dielectric layer 103 between the first electrode 101 and the second electrode 102, i.e. the dielectric layer 103 located in the overlap region 130, is designed to have pores 113. This is beneficial to ensure ohmic contact between the first electrode 101 and the second electrode 102 without removing the dielectric layer 103 located in the overlap region 130. This not only avoids etching damage to the first electrode when removing the dielectric layer located in the overlap region, but also avoids etching damage to the transparent conductive layer in contact with the first electrode. It reduces the risk of additional defects forming from multiple film layers, thereby further ensuring that the photovoltaic cell has excellent electrical performance.

[0079] In some cases, refer to Figure 1 Photovoltaic cells can be cells with electrodes on both sides, such as TOPCON cells, PERC cells, or heterojunction cells. Based on this, the first electrodes 101 on the same surface of the substrate 100 have the same polarity, and the transparent conductive layer 104 (refer to...) Figure 2 It can be located on the entire surface of the substrate 100.

[0080] In other cases, refer to Figure 5 , Figure 5 This is another partial top view schematic diagram of a photovoltaic cell provided in an embodiment of this application. The photovoltaic cell can be a cell with an electrode on one side, such as a BC cell. Based on this, the polarities of two adjacent first electrodes 101 along the first direction X are different. For example, the first electrode 101 includes a first current collector 131 and a second current collector 141. There is a gap between the transparent conductive layer 104 that contacts the two first electrodes 101 with different polarities. In other words, the transparent conductive layer 104 (refer to...) Figure 2 () can correspond one-to-one with the first electrode 101.

[0081] It should be noted that, Figure 2 It can also be regarded as Figure 5 The diagram shows a partial cross-sectional view of the photovoltaic cell along the first cross-sectional direction AA1. Figure 3 It can also be regarded as Figure 5 The diagram shows a partial cross-sectional view of the photovoltaic cell along the second cross-section direction BB1. Figure 4 It can also be regarded as Figure 5 The diagram shows a partial cross-sectional view of the photovoltaic cell along the third section direction CC1. In some cases, continue to refer to Figures 2 to 4 The thickness of the transparent conductive layer 104 can be 20nm to 200nm, for example, it can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm or 190nm, etc.

[0082] In some embodiments, in conjunction with reference Figures 1 to 5 The material of the first electrode 101 may include a metal or a mixture of a metal and an organic polymer.

[0083] In some embodiments, in conjunction with reference Figures 1 to 5 The material of the second electrode 102 may include metal or a mixture of metal and organic polymer.

[0084] In both of the above embodiments, the metal may include at least one of Ag, Al, Cu, Mg, Mo, W, Cr, Ni or Sn.

[0085] In some embodiments, in conjunction with reference Figures 1 to 5 The material of the dielectric layer 103 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or magnesium fluoride.

[0086] In some embodiments, in conjunction with reference Figures 1 to 5 The dielectric layer 103 can be a single-layer structure or a multilayer structure.

[0087] In some embodiments, in conjunction with reference Figures 1 to 5 The refractive index of the dielectric layer 103 can be 1.46 to 2.5, for example, it can be 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, 2, 2.05, 2.1, 2.15, 2.2, 2.25, 2.3, 2.35, 2.4 or 2.45, etc.

[0088] In some embodiments, in conjunction with reference Figures 1 to 3The width of the overlapping region 130 in the extension direction perpendicular to the first electrode 101 can be 5μm to 40μm, for example, it can be 10μm, 15μm, 20μm, 25μm, 30μm or 35μm. It should be noted that the overlapping region 130 is the area where the first electrode 101 and the second electrode 102 overlap, and the width of the overlapping region 130 can be regarded as the width of the first electrode 101, so the width of the first electrode 101 can also be 5μm to 40μm.

[0089] In some embodiments, in conjunction with reference Figures 1 to 3 Along the third direction Z, the height of the first electrode 101 can be 5μm to 30μm, for example, it can be 10μm, 15μm, 20μm or 25μm. Wherein, the third direction Z is the thickness direction of the substrate 100.

[0090] It should be noted that, along the cross-section perpendicular to the extension direction of the first electrode 101, the cross-sectional shape of the first electrode 101 can be approximately semi-elliptical or rectangular. Based on this, the height of the first electrode 101 can be regarded as the average height of different parts of the first electrode 101.

[0091] Based on the different designs inside the substrate 100, photovoltaic cells can include at least the following two major types.

[0092] In some embodiments, reference Figure 6 , Figure 6 This is a partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application. The substrate 100 may include: a substrate 105, one surface 135 of which includes a fourth region 115 and a fifth region 125 arranged alternately along a first direction X; a first semiconductor layer 116 and a first doped layer 117, the first semiconductor layer 116 being located on the fourth region 115 and the first doped layer 117 being located on the side of the first semiconductor layer 116 away from the substrate 105; a second semiconductor layer 126 and a second doped layer 127, the second semiconductor layer 126 being located on the fifth region 125 and the second doped layer 127 being located on the side of the second semiconductor layer 126 away from the substrate 105, the second doped layer 127 and the first doped layer 117 being doped with different types of doping elements; a first electrode 101 including a first current collector electrode 131 located in the fourth region 115 and a second current collector electrode 141 located in the fifth region 125, the first current collector electrode 131 being electrically connected to the first doped layer 117, and the second current collector electrode 141 being electrically connected to the second doped layer 127. Thus, the photovoltaic cell can be regarded as a BC cell, with the first electrode 101 and the second electrode 102 disposed on only one surface of the substrate 100 (see reference). Figure 5 The first electrode 101 includes a first current collector 131 and a second current collector 141 with different polarities.

[0093] The following provides a detailed explanation of the types of BC batteries.

[0094] In some cases, the first semiconductor layer 116 and the second semiconductor layer 126 can be tunneling layers, and the first doped layer 117 and the second doped layer 127 can be doped polycrystalline silicon layers. In this way, the photovoltaic cell is a TBC cell (TOPCon BackContact, referring to a cross-passivated back contact cell).

[0095] In other cases, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is an HBC cell (Heterojunction Back Contact).

[0096] In some cases, the first semiconductor layer 116 can be a tunneling layer, the first doped layer 117 can be a doped polycrystalline silicon layer, the second semiconductor layer 126 can be an intrinsic amorphous silicon layer, and the second doped layer 127 can be a doped amorphous silicon layer. In practical applications, the first semiconductor layer can also be an intrinsic amorphous silicon layer, the first doped layer can be a doped amorphous silicon layer, the second semiconductor layer can be a tunneling layer, and the second doped layer can be a doped polycrystalline silicon layer. In this way, the photovoltaic cell is a heterojunction tunnel oxide passivated contact hybrid passivated back contact solar cell (HTBC).

[0097] In all the above scenarios, one of the second doped layer 127 and the first doped layer 117 is doped with an N-type dopant element, and the other of the second doped layer 127 and the first doped layer 117 is doped with a P-type dopant element.

[0098] In some examples, the N-type dopant can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type semiconductor substrate is doped with a P-type element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0099] In other embodiments, reference is made to... Figure 7 or Figure 8The substrate 100 may include: a substrate 105 having two surfaces 135 opposite each other along a third direction Z; a semiconductor layer 106 located on one of the two surfaces 135; a doped layer 107 located on the side of the semiconductor layer 106 away from the substrate 105; and a first electrode 101 including a first current collector 131 located on the side of the doped layer 107 away from the substrate 105, and a second current collector 141 located on the other of the two surfaces 135. Thus, the photovoltaic cell can be considered as a cell with electrodes on both sides.

[0100] in, Figure 7 This is another partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application. Figure 8 This is another partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application.

[0101] It should be noted that the substrate 105 has two surfaces 135 opposite each other along the third direction Z, which can be a first surface 1351 and a second surface 1352, respectively. In some examples, continue to refer to Figure 7 or Figure 8 Semiconductor layer 106, doped layer 107 and first current collector 131 are located on first surface 1351, and second current collector 141 is located on second surface 1352.

[0102] The following provides a detailed description of the types of batteries with electrodes on both sides.

[0103] In some cases, refer to Figure 7 Semiconductor layer 106 can be a tunneling layer, and doped layer 107 can be a doped polycrystalline silicon layer. Thus, the photovoltaic cell is a TOPCON cell.

[0104] In other cases, refer to Figure 8 Semiconductor layer 106 is an intrinsic amorphous silicon layer, and doped layer 107 is a doped amorphous silicon layer.

[0105] In some examples, continue to refer to Figure 8 The semiconductor layer 106 is a first intrinsic amorphous silicon layer, and the doped layer 107 is a first doped amorphous silicon layer. The first intrinsic amorphous silicon layer and the first doped amorphous silicon layer are stacked on the first surface 1351. The substrate 100 may further include: a second intrinsic amorphous silicon layer 136 located on the second surface 1352; a second doped amorphous silicon layer 137 located on the side of the second intrinsic amorphous silicon layer 136 away from the second surface 1352; and a second current collector 141 located on the side of the second doped amorphous silicon layer 137 away from the second intrinsic amorphous silicon layer 136. Thus, the photovoltaic cell is a heterojunction cell.

[0106] In the various embodiments described above, the material of the tunneling layer may include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride.

[0107] In summary, the design firstly establishes a direct ohmic contact between the first electrode 101 and the surface of the substrate 100. Furthermore, while retaining the dielectric layer 103 located between the first electrode 101 and the second electrode 102, the dielectric layer 103 in the overlap region 130 is designed to have pores 113, with at least a portion of the pores 113 accommodating the first electrode 101 and / or the second electrode 102, ensuring ohmic contact between the first electrode 101 and the second electrode 102. This approach, on the one hand, allows the first electrode 101 to directly contact the surface of the substrate 100, which helps control the contact morphology between the first electrode 101 and the substrate 100, thereby improving the collection efficiency of photogenerated carriers in the substrate 100 by the first electrode 101. On the other hand, it allows the first electrode 101 to be made from low-cost, low-burn-through conductive materials or non-burn-through conductive materials, ensuring direct contact between the first electrode 101 and the surface of the substrate 100 without causing significant damage to the substrate 100. Moreover, it reduces the fabrication cost of the first electrode 101. On the one hand, cost is a concern; on the other hand, before the second electrode 102 is formed, the first electrode 101 can be protected by the dielectric layer 103 to reduce the risk of damage or contamination to the first electrode 101, thereby improving the yield of the first electrode 101. Furthermore, by using the dielectric layer 103 with pores 113 located in the overlap region 130 to ensure ohmic contact between the first electrode 101 and the second electrode 102, the raw materials for the second electrode 102 can be low-cost low-burn-through conductive materials or non-burn-through conductive materials, thus reducing the manufacturing cost of the second electrode 102. Therefore, this multi-faceted approach is beneficial for comprehensively improving the electrical performance of photovoltaic cells.

[0108] Another embodiment of this application provides a method for manufacturing a photovoltaic cell, used to form the photovoltaic cell provided in the foregoing embodiment. The method for manufacturing a photovoltaic cell according to another embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiment will not be repeated here.

[0109] Combination Figures 1 to 10 , Figure 9 The present application provides a process flow diagram of a method for manufacturing a photovoltaic cell according to another embodiment of the present application. The method for manufacturing a photovoltaic cell includes at least the following steps: S1: Reference Figure 1 , Figures 5 to 8 Either of them provides a base 100.

[0110] S2: Reference Figure 1 or Figure 5 A plurality of first electrodes 101 are formed on the surface of the substrate 100 at intervals along the first direction X.

[0111] S3: Reference Figure 10 , Figure 10 This is a partial cross-sectional view of a semi-finished cell after the formation of an initial dielectric layer in a photovoltaic cell manufacturing method provided in another embodiment of this application, along the first cross-sectional direction AA1, showing that an initial dielectric layer 123 is formed on the surface jointly formed by the substrate 100 and the first electrode 101.

[0112] S4: Refer to Figure 10 and Figure 2 A plurality of second electrodes 102 are formed on the surface of the initial dielectric layer 123 at intervals along the second direction Y, wherein the first direction X and the second direction Y intersect; wherein the surface of the substrate 100 includes an overlap region 130 in which the first electrode 101 and the second electrode 102 are simultaneously disposed; during the formation of the second electrode 102, the initial dielectric layer 123 located in the overlap region 130 is transformed into a dielectric layer 103 with pores 113, and at least a portion of the pores 113 contain the first electrode 101 and / or the second electrode 102, such that the first electrode 101 and the second electrode 102 are in contact.

[0113] It is worth noting that the step of forming the initial dielectric layer 123 is interspersed between the steps of forming the first electrode 101 and forming the second electrode 102. First, after forming the first electrode 101, since the first electrode 101 protrudes from the surface of the substrate 100, the surface formed by the substrate 100 and the first electrode 101 together has an uneven morphology. Based on this, when preparing the initial dielectric layer 123, due to the reduced coverage of the film at the abrupt change or step, the initial dielectric layer 123 formed on the overlapping region 130 will be thinner, and it will be difficult to form a dense initial dielectric layer 123 on the overlapping region 130. In other words, the interior of the initial dielectric layer 123 formed on the overlapping region 130 is itself relatively loose. Furthermore, after forming the initial dielectric layer 123, the second electrode 102 is formed. This allows the thinner and more porous initial dielectric layer 123 located in the overlap region 130 to be easily penetrated by the second electrode 102. The thermal stress during the formation of the second electrode 102 also contributes to the formation of pores 113 within the initial dielectric layer 123 in the overlap region 130, which accommodate the first electrode 101 and / or the second electrode 102. Thus, ohmic contact between the first electrode 101 and the second electrode 102 can be achieved without additional processing to remove the dielectric layer 103 between the first electrode 101 and the second electrode 102, avoiding etching damage to the first electrode 101. This simplifies the photovoltaic cell manufacturing process and reduces manufacturing costs.

[0114] Furthermore, the initial dielectric layer 123 located outside the overlapping region 130 can be considered as a dielectric layer 103 without pores that allow for electrical conduction, thus providing insulation and anti-reflection effects, thereby reducing the reflectivity of incident light and improving the absorption and utilization of light by the substrate 100. Based on this, in another embodiment of the photovoltaic cell manufacturing method provided in this application, the process of forming the dielectric layer 103 that provides insulation and anti-reflection effects can be integrated into the steps of forming the first electrode 101 and forming the second electrode 102, thereby simplifying the photovoltaic cell manufacturing process as much as possible.

[0115] For example, compared to the technical solution of forming a dielectric layer that provides insulation and anti-reflection effects before forming the first electrode, which requires the first electrode to have high burn-through properties to achieve surface ohmic contact between the dielectric layer and the substrate, in another embodiment of the photovoltaic cell manufacturing method provided in this application, the first electrode 101, which has surface ohmic contact with the substrate 100, is directly formed before forming the initial dielectric layer 123. This not only helps to control a good contact morphology between the first electrode 101 and the substrate 100, thereby improving the collection efficiency of photogenerated carriers in the substrate 100 by the first electrode 101, but also allows the raw materials for the first electrode 101 to be low-cost low-burn-through conductive materials or non-burn-through conductive materials. This ensures that the first electrode 101 can directly contact the surface of the substrate 100 without causing significant damage to the substrate 100, and also reduces the manufacturing cost of the first electrode 101. Furthermore, before forming the second electrode 102, the first electrode 101 can be protected by the dielectric layer 103 to reduce the risk of damage or contamination to the first electrode 101, thereby improving the yield of the first electrode 101.

[0116] Compared to the technical solution where the first and second electrodes are formed first, followed by the formation of the dielectric layer that provides insulation and anti-reflection effects, the dielectric layer on the surface of the second electrode needs to be removed to facilitate the subsequent electrical connection of the second electrodes in two adjacent photovoltaic cells with solder ribbons. In another embodiment of the photovoltaic cell manufacturing method provided in this application, the second electrode 102 is formed outside the dielectric layer 103. Therefore, the second electrode 102 is not blocked by the dielectric layer 103, and there is no need to use an additional process to remove the dielectric layer 103. This avoids etching damage to the second electrode 102, which helps to simplify the manufacturing process of photovoltaic cells and reduce the manufacturing cost of photovoltaic cells. Moreover, it can ensure good electrical connection performance between the subsequent solder ribbons and the second electrode 102.

[0117] In some cases, the raw materials for the second electrode 102 can also be low-cost low-burn-through conductive materials or non-burn-through conductive materials to reduce the manufacturing cost of the second electrode 102.

[0118] The following will describe in more detail a method for manufacturing a photovoltaic cell according to an embodiment of this application, with reference to the accompanying drawings.

[0119] In some embodiments, in conjunction with reference Figure 5 and Figure 6 The step of providing substrate 100 may include: providing substrate 105, one surface 135 of substrate 105 including a fourth region 115 and a fifth region 125 arranged alternately along a first direction X; forming a first semiconductor layer 116 on the fourth region 115, forming a first doped layer 117 on the side of the first semiconductor layer 116 away from substrate 105; forming a second semiconductor layer 126 on the fifth region 125, forming a second doped layer 127 on the side of the second semiconductor layer 126 away from substrate 105, wherein the second doped layer 127 and the first doped layer 117 are doped with different types of doping elements.

[0120] Based on this, the step of forming the first electrode 101 includes: forming a first current collector 131 on the side of the first doped layer 117 away from the fourth region 115, and the first current collector 131 and the first doped layer 117 are electrically connected; forming a second current collector 141 on the side of the second doped layer 127 away from the fifth region 125, and the second current collector 141 and the second doped layer 127 are electrically connected; the first electrode 101 includes a first current collector 131 and a second current collector 141 with different polarities. Thus, the photovoltaic cell can be regarded as a BC cell, with the first electrode 101 and the second electrode 102 disposed on only one surface of the substrate 100. It should be noted that the fourth region 115 and the fifth region 125 are both types of the first region 110.

[0121] The following provides a detailed description of the materials of the first semiconductor layer 116, the first doped layer 117, the second semiconductor layer 126, and the second doped layer 127, and the types of photovoltaic cells.

[0122] In some cases, the first semiconductor layer 116 and the second semiconductor layer 126 can be tunneling layers, and the first doped layer 117 and the second doped layer 127 can be doped polycrystalline silicon layers. In this way, the photovoltaic cell is a TBC cell.

[0123] In other cases, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is an HBC cell.

[0124] In some cases, the first semiconductor layer 116 can be a tunneling layer, the first doped layer 117 can be a doped polycrystalline silicon layer, the second semiconductor layer 126 can be an intrinsic amorphous silicon layer, and the second doped layer 127 can be a doped amorphous silicon layer. In practical applications, the first semiconductor layer can also be an intrinsic amorphous silicon layer, the first doped layer can be a doped amorphous silicon layer, the second semiconductor layer can be a tunneling layer, and the second doped layer can be a doped polycrystalline silicon layer. In this case, the photovoltaic cell is an HTBC cell.

[0125] It should be noted that in the photovoltaic cell manufacturing method provided in another embodiment of this application, the formation process steps of the first semiconductor layer 116, the first doped layer 117, the second semiconductor layer 126 and the second doped layer 127 are not subject to too many restrictions and can be adjusted according to the actual process.

[0126] In some cases, continue to refer to Figure 6 After providing the substrate 100 and before forming the first electrode 101, the method for manufacturing a photovoltaic cell may further include: forming a transparent conductive layer 104 on the surface of the substrate 100, and subsequently forming the first electrode 101 on the side of the transparent conductive layer 104 away from the substrate.

[0127] In other embodiments, reference is made to... Figure 7 or Figure 8 The step of providing substrate 100 may include: providing substrate 105 having two surfaces 135 opposite each other in a third direction Z; forming a semiconductor layer 106 on one of the two surfaces 135, such as the first surface 1351; and forming a doped layer 107 on the side of the semiconductor layer 106 away from the substrate 105.

[0128] Based on this, the step of forming the first electrode 101 includes: forming a first current collector 131 on the side of the doped layer 107 away from the substrate 105, and the first current collector 131 and the first doped layer 117 are electrically connected; forming a second current collector 141 on the other of the two surfaces 135, such as the second surface 1352; the first electrode 101 includes the first current collector 131 and the second current collector 141. Thus, the photovoltaic cell can be regarded as a cell with electrodes on both sides. It should be noted that the manufacturing method of the photovoltaic cell provided in another embodiment of this application does not limit the formation order of the first current collector 131 and the second current collector 141.

[0129] In some cases, the step of forming the first current collector 131 and then the second current collector 141 may include: first forming an initial first current collector on the side of the doped layer 107 away from the substrate 105, and then drying the initial first current collector; then forming an initial second current collector on the other of the two surfaces 135, such as the second surface 1352, and then drying the initial second current collector; finally curing both the initial first current collector and the initial second current collector to transform the initial first current collector into the first current collector 131 and the initial second current collector into the second current collector 141. It is worth noting that the initial first current collector is dried before the initial second current collector is formed to reduce its fluidity and viscosity. This helps to avoid damage to the initial first current collector when flipping the semi-finished battery. For example, it prevents the initial first current collector from remaining on the conveyor belt when it comes into contact with the conveyor belt. After the initial second current collector is formed, the initial first current collector and the initial second current collector are solidified together, which also helps to simplify the manufacturing process of the first electrode 101.

[0130] The following provides a detailed description of the materials of semiconductor layer 106 and doped layer 107 and the type of photovoltaic cell.

[0131] In some cases, refer to Figure 7 Semiconductor layer 106 can be a tunneling layer, and doped layer 107 can be a doped polycrystalline silicon layer. Thus, the photovoltaic cell is a TOPCON cell.

[0132] In other cases, refer to Figure 8 Semiconductor layer 106 is an intrinsic amorphous silicon layer, and doped layer 107 is a doped amorphous silicon layer.

[0133] In some examples, continue to refer to Figure 8 The semiconductor layer 106 is a first intrinsic amorphous silicon layer, and the doped layer 107 is a first doped amorphous silicon layer. The first intrinsic amorphous silicon layer and the first doped amorphous silicon layer are stacked on the first surface 1351. The photovoltaic cell also includes: a second intrinsic amorphous silicon layer 136 located on the second surface 1352; a second doped amorphous silicon layer 137 located on the side of the second intrinsic amorphous silicon layer 136 away from the second surface 1352; and a second current collector 141 located on the side of the second doped amorphous silicon layer 137 away from the second intrinsic amorphous silicon layer 136. Thus, the photovoltaic cell is an HJT cell. The manufacturing method of a photovoltaic cell provided in another embodiment of this application will be described in detail below, using the final formed photovoltaic cell as an example of an HJT cell.

[0134] In some embodiments, reference Figure 10An initial medium layer 123 is formed using a deposition process; wherein the processing temperature of the deposition process can be 100℃~300℃, for example, 110℃, 120℃, 130℃, 140℃, 150℃, 160℃, 170℃, 180℃, 190℃, 200℃, 210℃, 220℃, 230℃, 240℃, 250℃, 260℃, 270℃, 280℃ or 290℃, etc.; the processing time of the deposition process can be 10min~120min, for example, 20min, 30min, 40min, 50min, 60min, 70min, 80min, 90min, 100min or 110min, etc.

[0135] In some cases, the deposition process for forming the initial dielectric layer 123 can be PECVD (Plasma Enhanced Chemical Vapor Deposition), HWCVD (Hot Wire Assisted Chemical Vapor Deposition), or ALD (Atomic Layer Deposition).

[0136] In some cases, the thickness of the initial dielectric layer 123 can be 60nm to 200nm, for example, it can be 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm or 190nm, etc.

[0137] In some embodiments, in conjunction with reference Figure 10 and Figure 2 The step of forming the second electrode 102 may include: forming a plurality of initial second electrodes arranged at intervals along the second direction Y on the surface of the initial dielectric layer 123; and sequentially performing drying and curing treatments on the initial second electrodes to transform them into the second electrode 102; wherein the drying treatment temperature is 100℃~200℃ and the drying treatment time is 1min~10min, the curing treatment temperature is 60℃~250℃ and the curing treatment time is 0min~60min.

[0138] It is worth noting that the processing temperatures during drying and curing are higher than room temperature, making the already thin initial dielectric layer 123 in the overlap region 130 susceptible to thermal stress, which in turn leads to the formation of pores 113 within the film. Furthermore, the second electrode 102 further penetrates into the porous initial dielectric layer 123, and the first electrode 101 may also be squeezed into the pores 113 under the influence of thermal stress, thus enabling ohmic contact between the first electrode 101 and the second electrode 102 even with the dielectric layer 103 present.

[0139] In some cases, the drying temperature can be 110℃, 120℃, 130℃, 140℃, 150℃, 160℃, 170℃, 180℃ or 190℃, etc.

[0140] In some cases, the drying time can be 2 min, 3 min, 4 min, 5 min, 6 min, 7 min, 8 min or 9 min, etc.

[0141] In some cases, the curing temperature can be 70℃, 80℃, 90℃, 100℃, 110℃, 120℃, 130℃, 140℃, 150℃, 160℃, 170℃, 180℃, 190℃, 200℃, 210℃, 220℃, 230℃ or 240℃, etc.

[0142] In some cases, the curing time is 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min or 55 min, etc.

[0143] The following is another embodiment of the photovoltaic cell manufacturing method provided in this application, which involves forming an HJT cell, namely... Figure 8 The specific embodiments of the photovoltaic cells shown, and their comparative examples: Example 1 Back contact battery 1 is prepared by the following steps: (1) N-type silicon wafers are selected. The resistivity of N-type silicon wafers is about 0.5Ω·m~8Ω·m. The thickness of N-type single crystal silicon wafers in the third direction Z is about 100μm~200μm. The short side length of N-type silicon wafers can be 182mm and the long side length of N-type silicon wafers can be 210mm.

[0144] (2) Cleaning and texturing of N-type silicon wafers. For example, cleaning can be performed by using a 5% diluted hydrofluoric acid solution to remove the surface oxide layer; texturing can be performed by using potassium hydroxide, sodium hydroxide or tetramethylammonium hydroxide plus alcohol to form a shallow pyramid structure on the surface of N-type silicon wafers by utilizing the anisotropic etching of single crystal silicon to obtain substrate 105.

[0145] (3) The substrate 105 is placed in a vacuum chamber, and then silane gas is introduced into the vacuum chamber. An intrinsic amorphous silicon layer, i.e., semiconductor layer 106, is formed on the entire area of ​​the first surface 1351 of the substrate 105 by plasma chemical vapor deposition. Then, silane gas, hydrogen gas and phosphine gas are introduced into the vacuum chamber, and a doped amorphous silicon layer, i.e., doped layer 107, with N-type doping elements is formed on the intrinsic amorphous silicon layer by plasma chemical vapor deposition.

[0146] (4) The semi-finished battery formed after step (3) is flipped over, the tray carrying the semi-finished battery is replaced, and then silane gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer, namely the second intrinsic amorphous silicon layer 136, is formed on the entire area of ​​the second surface 1352 of the substrate 105 by plasma chemical vapor deposition process; then silane gas, hydrogen and diborane gas are introduced into the vacuum chamber, and a doped amorphous silicon layer doped with P-type doping elements, namely the second doped amorphous silicon layer 137, is formed on the intrinsic amorphous silicon layer by plasma chemical vapor deposition process to obtain the substrate 100.

[0147] (5) A transparent conductive layer 104 is formed on the intrinsic amorphous silicon layer located on the first surface 1351 and the second surface 1352 by using RPD (reactive plasma deposition) or magnetron sputtering process to form a film. The thickness of the transparent conductive layer 104 can be 20nm~200nm.

[0148] (6) Through one or more printing steps, including but not limited to screen printing, stencil printing, laser transfer, or copper plating, an initial first current collector electrode is formed on the first region and overlapping region of the second surface 1352. The width of the initial first current collector electrode can be 5μm~40μm, and the height of the initial first current collector electrode can be 5μm~30μm. The initial first current collector electrode is dried once at a temperature of 100℃~200℃ for a duration of 1min~10min. Then, through one or more printing steps, an initial second current collector electrode is formed on the first region and overlapping region of the first surface 1351. The width of the current collector electrode can be 5μm~40μm, and the height of the initial second current collector electrode can be 5μm~30μm. The initial second current collector electrode is dried once at a temperature of 100℃~200℃ for a duration of 1min~10min. The initial first current collector electrode and the initial second current collector electrode are cured once at a temperature of 60℃~250℃ for a duration of 0min~60min. The initial first current collector electrode is transformed into the first current collector electrode 131, and the initial second current collector electrode is transformed into the second current collector electrode 141, thereby completing the manufacturing of the first electrode 101.

[0149] (7) An initial dielectric layer 123 is deposited on the first surface 1351 and the second surface 1352 after the formation of the first electrode 101 using PECVD, HWCVD or ALD processes. The initial dielectric layer can be a single-layer structure or a stacked structure including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or magnesium fluoride.

[0150] (8) A second electrode 102 is formed on the semi-finished battery formed after step (7). Specifically, through one or more printing steps, the printing process includes, but is not limited to, screen printing, stencil printing, laser transfer, or copper electroplating, an initial second electrode is formed on the second region and overlapping region of the second surface 1352. This initial second electrode can be called the initial first bus electrode. The ratio of the area of ​​the overlapping region to the area of ​​the first region can be 0.005% to 1.705%. The initial second electrode formed on the second surface 1352, i.e., the initial first bus electrode, is dried once. The process parameters of the drying process can be the same as those of the drying process in step (6). Then, an initial second electrode is also formed on the second region and overlapping region of the first surface 1351 through one or more printing steps. It can be called the initial second bus electrode; the initial second electrode formed on the first surface 1351, i.e. the initial second bus electrode, is subjected to a drying process once. The process parameters of the drying process can be the same as those of the drying process in step (6); the initial second electrodes located on the two surfaces 135, i.e. the initial first bus electrode and the initial second bus electrode, are subjected to a curing process once. The curing temperature is 60℃~250℃ and the curing time is 0min~60min. The initial first bus electrode is converted into the first bus electrode and the initial second bus electrode is converted into the second bus electrode. The second electrode 102 includes the first bus electrode and the second bus electrode to complete the manufacturing of the second electrode 102.

[0151] Comparative Example 1 Back contact battery 2 is prepared by the following steps: Steps (1) to (6) are the same as in Example 1, and will not be repeated here.

[0152] (7) Before forming a dielectric layer that has an anti-reflection effect, a second electrode is formed directly on the surface formed by the first electrode and the substrate.

[0153] (8) A dielectric layer with anti-reflection effect is formed on the semi-finished battery formed after step (7). Thus, when adjacent photovoltaic cells are electrically connected by solder ribbons, the solder ribbons cannot achieve effective electrical connection with the second electrode due to the obstruction of the dielectric layer.

[0154] Comparative Example 2 Back contact battery 3 is prepared by the following steps: Steps (1) to (6) are the same as in Example 1, and will not be repeated here.

[0155] (7) Before forming a dielectric layer that has an anti-reflection effect, a second electrode is formed directly on the surface formed by the first electrode and the substrate.

[0156] (8) A dielectric layer that has an anti-reflection effect is formed on the semi-finished battery formed after step (7).

[0157] (9) Remove the dielectric layer on the surface of the second electrode so that the subsequent solder ribbon can achieve effective electrical connection with the exposed second electrode. In this step, the removal process is prone to causing etching damage to the second electrode, and may also cause etching damage to the doped amorphous silicon layer on the transparent conductive layer, which can easily reduce the electrical connection performance of the subsequent solder ribbon and the second electrode, as well as reduce the electrical performance of the photovoltaic cell.

[0158] Table 1 shows the electrical performance indices for back contact battery 1, back contact battery 2, and back contact battery 3.

[0159] Note: VOC represents open-circuit voltage, FF represents fill factor, Rs represents series resistance, Jsc represents short-circuit current, eta represents photoelectric conversion efficiency, and welding pull force represents the connection strength between the welding strip and the second electrode.

[0160] The experimental results show that, in Example 1, using the back-contact battery manufacturing method provided in an embodiment of this application, the design of interleaving the step of forming the initial dielectric layer 123 between the steps of forming the first electrode 101 and forming the second electrode 102 improves various electrical performance indices of the final photovoltaic cell. For example, the open-circuit voltage, fill factor, short-circuit current, and photoelectric conversion efficiency are all increased, and the series resistance is reduced. Moreover, the subsequent solder ribbon can be directly soldered to the second electrode, which helps to improve the welding pull force between the solder ribbon and the second electrode.

[0161] Another embodiment of this application provides a photovoltaic module for converting received light energy into electrical energy. The photovoltaic module provided in another embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0162] Reference Figures 1 to 8 ,as well as Figures 11 to 14 The photovoltaic module includes: a battery string, which is formed by connecting multiple photovoltaic cells 40 provided in the foregoing embodiments, or by connecting photovoltaic cells 40 formed by the manufacturing method of multiple photovoltaic cells provided in the foregoing embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 facing away from the battery string.

[0163] in, Figure 11 Provided for yet another embodiment of this application Figure 1 A partial 3D schematic diagram of the battery string in the corresponding photovoltaic module; Figure 12 Provided for yet another embodiment of this application Figure 11A partial cross-sectional schematic diagram of the corresponding photovoltaic module; Figure 13 Provided for yet another embodiment of this application Figure 5 A partial 3D schematic diagram of the battery string in the corresponding photovoltaic module; Figure 14 Provided for yet another embodiment of this application Figure 13 A partial cross-sectional schematic diagram of the corresponding photovoltaic module.

[0164] In some embodiments, in conjunction with reference Figures 1 to 4 , Figure 7 , Figure 8 as well as Figure 11 and Figure 12 The photovoltaic cell 40 is a cell with electrodes on both sides, including but not limited to TOPcon cells, PERC cells or HJT cells.

[0165] It should be noted that multiple photovoltaic cells 40 can be electrically connected to each other via solder strips 43. Figure 11 and Figure 12 This illustration only shows one possible positional relationship between photovoltaic cells 40, where the photovoltaic cells 40 have second electrodes of the same polarity, for example, the first bus electrodes are arranged in the same direction, or the first surfaces 1351 of each photovoltaic cell 40 with the first bus electrode are all arranged facing the same side, so that the solder ribbon 43 connects different sides of two adjacent photovoltaic cells 40 respectively. In other embodiments, the photovoltaic cells can also be arranged with second electrodes of different polarities facing the same side, that is, the first electrodes of multiple adjacent photovoltaic cells located on the same side are arranged in the order of first bus electrode, second bus electrode, first bus electrode, second bus electrode, and so on, then the solder ribbon connects two adjacent photovoltaic cells on the same side.

[0166] In other embodiments, in conjunction with reference to Figures 2 to 6 ,as well as Figure 13 and Figure 14 The photovoltaic cells 40 are BC cells, including but not limited to HBC cells, TBC cells, or HTBC cells.

[0167] It should be noted that multiple photovoltaic cells 40 can be electrically connected to each other via solder strips 43. Figure 13 and Figure 14 This illustration only shows one positional relationship between the photovoltaic cells 40, where the side of each photovoltaic cell 40 with the second electrode 102 is arranged facing the same side, so that the solder ribbon 43 connects the same side of two adjacent photovoltaic cells 40 respectively. In other embodiments, the photovoltaic cells may also be arranged such that the second electrodes of two adjacent photovoltaic cells are located on different sides, in which case the solder ribbon connects two adjacent photovoltaic cells on different sides.

[0168] In some embodiments, the photovoltaic cells 40 are electrically connected in the form of a single cell or multiple segments to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The photovoltaic cells 40 can be a single cell or a sliced ​​cell, where a sliced ​​cell refers to a cell formed by cutting a complete single cell.

[0169] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the photovoltaic cell 40, and the second encapsulating layer covers the other of the front or back sides of the photovoltaic cell 40. Specifically, at least one of the first or second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, an EPE film, or a PVP film. Here, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film + POE film + EVA film; and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0170] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0171] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0172] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of the embodiments of this application. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this application; therefore, the scope of protection of the embodiments of this application should be determined by the scope defined in the claims.

Claims

1. A photovoltaic cell, characterized in that, include: Base; A plurality of first electrodes are located on the surface of the substrate and are spaced apart along a first direction, and a plurality of second electrodes are spaced apart along a second direction, wherein the first direction and the second direction intersect. The surface of the substrate includes an overlapping area where the first electrode and the second electrode are simultaneously disposed, and the second electrode is disposed on the side of the first electrode located away from the substrate in the overlapping area. A dielectric layer, at least between the second electrode and the first electrode, and having pores in the overlapping region, wherein at least a portion of the pores accommodate the first electrode and / or the second electrode, such that the first electrode and the second electrode are in contact.

2. The photovoltaic cell according to claim 1, characterized in that, The first electrode has a bottom end and a top end along a third direction, the bottom end being closer to the substrate, and the third direction being the thickness direction of the substrate; in the dielectric layer located in the overlapping region, the thickness of the dielectric layer on the surface located at the bottom end is greater than or equal to the thickness of the dielectric layer on the surface located at the top end.

3. The photovoltaic cell according to claim 2, characterized in that, In the dielectric layer located in the overlapping region, the thickness of the dielectric layer located on the side of the first electrode gradually decreases along the direction from the bottom end to the top end.

4. The photovoltaic cell according to claim 1, characterized in that, The surface of the substrate further includes a first region on which the first electrode is disposed; the dielectric layer is also located on the first region and on the surface of the first electrode away from the substrate.

5. The photovoltaic cell according to claim 4, characterized in that, The ratio of the area of ​​the overlapping region to the area of ​​the first region is 0.005% to 1.705%.

6. The photovoltaic cell according to claim 1, characterized in that, The surface of the substrate further includes a second region on which the second electrode is disposed; the dielectric layer is also located on the second region and between the second electrode and the substrate.

7. The photovoltaic cell according to claim 1, characterized in that, The surface of the substrate further includes a third region, which is a region where the first electrode and the second electrode are not disposed; the dielectric layer is also located on the third region.

8. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The surface of the substrate also includes a protection zone other than the overlapping area. The protection zone is a region where the first electrode is not disposed, and the dielectric layer is located on at least a portion of the protection zone. The ratio of the thickness of the medium layer located in the protected area to the thickness of the medium layer located in the overlapping area is 30% to 50%.

9. The photovoltaic cell according to claim 8, characterized in that, The thickness of the dielectric layer located in the protected area is 30nm~200nm.

10. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, Also includes: A transparent conductive layer is located between the dielectric layer and the substrate, and between the first electrode and the substrate.

11. The photovoltaic cell according to claim 10, characterized in that, The thickness of the transparent conductive layer is 20nm~200nm.

12. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The material of the first electrode and / or the material of the second electrode comprises a metal or a mixture of a metal and an organic polymer; wherein the metal comprises at least one of Ag, Al, Cu, Mg, Mo, W, Cr, Ni or Sn.

13. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or magnesium fluoride.

14. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The width of the overlapping region in the extension direction perpendicular to the first electrode is 5 μm to 40 μm.

15. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The substrate includes: A substrate, one surface of which includes a fourth region and a fifth region arranged alternately along the first direction; A first semiconductor layer and a first doped layer, wherein the first semiconductor layer is located on the fourth region and the first doped layer is located on the side of the first semiconductor layer away from the substrate; A second semiconductor layer and a second doped layer, the second semiconductor layer being located on the fifth region, the second doped layer being located on the side of the second semiconductor layer away from the substrate, the second doped layer and the first doped layer being doped with different types of doping elements; The first electrode includes a first current collector electrode located in the fourth region and a second current collector electrode located in the fifth region. The first current collector electrode is electrically connected to the first doped layer, and the second current collector electrode is electrically connected to the second doped layer. Wherein, the first semiconductor layer and the second semiconductor layer are tunneling layers, and the first doped layer and the second doped layer are doped polycrystalline silicon layers; or, the first semiconductor layer and the second semiconductor layer are intrinsic amorphous silicon layers, and the first doped layer and the second doped layer are doped amorphous silicon layers; or, the first semiconductor layer is the tunneling layer, the first doped layer is the doped polycrystalline silicon layer, the second semiconductor layer is the intrinsic amorphous silicon layer, and the second doped layer is the doped amorphous silicon layer.

16. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The substrate includes: The substrate has two surfaces opposite each other along a third direction; A semiconductor layer is located on one of the two surfaces; A doped layer is located on the side of the semiconductor layer away from the substrate; The first electrode includes a first current collector located on the side of the doped layer away from the substrate, and a second current collector located on the other of the two surfaces; Wherein, the semiconductor layer is a tunneling layer and the doped layer is a doped polycrystalline silicon layer; or, the semiconductor layer is an intrinsic amorphous silicon layer and the doped layer is a doped amorphous silicon layer.

17. A method for manufacturing a photovoltaic cell, characterized in that, include: Provide a base; A plurality of first electrodes are formed on the surface of the substrate at intervals along a first direction; An initial dielectric layer is formed on the surface formed by the substrate and the first electrode. A plurality of second electrodes are formed on the surface of the initial dielectric layer at intervals along a second direction, wherein the first direction and the second direction intersect. The substrate surface includes an overlapping region where the first electrode and the second electrode are simultaneously disposed. During the formation of the second electrode, the initial dielectric layer located in the overlapping region is transformed into a porous dielectric layer, and at least a portion of the pores accommodate the first electrode and / or the second electrode, thereby making the first electrode and the second electrode in contact.

18. The method for manufacturing a photovoltaic cell according to claim 17, characterized in that, The initial medium layer is formed by a deposition process; wherein the deposition process is carried out at a temperature of 100℃ to 300℃ and for a duration of 10 min to 120 min.

19. The method for manufacturing a photovoltaic cell according to claim 17, characterized in that, The steps for forming the second electrode include: A plurality of initial second electrodes are formed on the surface of the initial dielectric layer at intervals along the second direction; The initial second electrode is subjected to drying and curing processes in sequence to transform it into the second electrode. The drying process is carried out at a temperature of 100℃ to 200℃ and for a duration of 1 min to 10 min. The curing process is carried out at a temperature of 60℃ to 250℃ and for a duration of 0 min to 60 min.

20. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple photovoltaic cells as described in any one of claims 1 to 16, or by connecting multiple photovoltaic cells formed by the manufacturing method of the photovoltaic cells as described in any one of claims 17 to 19; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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