Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to the technical field of solar cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a silicon wafer, a dielectric layer, a P-type doped polycrystalline silicon carbide layer, a P-type doped polycrystalline silicon layer and an N-type doped polycrystalline silicon carbide layer. The backlight surface of the silicon wafer is provided with first areas and second areas which are alternately arranged, and separation areas are arranged between the adjacent first areas and second areas. The dielectric layer is arranged on the backlight surface and is disconnected along the separation area, and the first area and the second area are covered with the dielectric layer. And the P-type doped polycrystalline silicon carbide layer is arranged on one surface, deviating from the silicon wafer, of the dielectric layer in the first region. And the P-type doped polycrystalline silicon layer is arranged on one surface, deviating from the dielectric layer, of the P-type doped polycrystalline silicon carbide layer. And the N-type doped polycrystalline silicon carbide layer is arranged on one surface, deviating from the silicon wafer, of the dielectric layer in the second region.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a solar cell and its preparation method, and a photovoltaic module. Background Technology

[0002] Since there are no electrodes on the light-receiving surface of a full back electrode contact solar cell, there is no problem with shading, so the photoelectric conversion efficiency of the cell can easily reach over 24.5%.

[0003] Fully back-contact solar cells typically consist of a P-type silicon doped layer and an N-type silicon doped layer disposed on the back surface of a silicon wafer, and metal electrodes that make ohmic contact with each of these silicon doped layers. In this structure, the metal electrodes are prone to metal recombination, as they are in ohmic contact with the silicon doped layers while simultaneously making direct contact with the silicon wafer, limiting the improvement of conversion efficiency in fully back-contact solar cells. Summary of the Invention

[0004] To address the aforementioned technical problems, this application discloses a solar cell and its fabrication method, as well as a photovoltaic module. The first region of the solar cell employs a dielectric layer, a P-type doped polycrystalline silicon carbide layer, and another P-type doped polycrystalline silicon layer to form a P-region passivated contact structure. The second region employs a dielectric layer and an N-type doped polycrystalline silicon carbide layer to form an N-region passivated contact structure. The use of passivated contact structures in both the first and second regions is beneficial for improving the conversion efficiency of the solar cell.

[0005] In a first aspect, embodiments of this application provide a solar cell, comprising:

[0006] A silicon wafer, wherein the backlight surface of the silicon wafer has alternating first and second regions, and a separating region is provided between adjacent first and second regions;

[0007] A dielectric layer is disposed on the backlight surface and is broken along the dividing region, and the dielectric layer is covered on both the first region and the second region;

[0008] A P-type doped polycrystalline silicon carbide layer is located in the first region, and the P-type doped polycrystalline silicon carbide layer is disposed on the side of the dielectric layer opposite to the silicon wafer;

[0009] A p-type doped polycrystalline silicon layer, wherein the p-type doped polycrystalline silicon layer is disposed on the side of the p-type doped polycrystalline silicon carbide layer opposite to the dielectric layer; and

[0010] An N-type doped polycrystalline silicon carbide layer is located in the second region, and the N-type doped polycrystalline silicon carbide layer is disposed on the side of the dielectric layer opposite to the silicon wafer.

[0011] Optionally, the solar cell further includes a doped layer, a first functional layer, a second functional layer, a first electrode, and a second electrode;

[0012] The doped layer and the first functional layer are sequentially stacked on the light-receiving surface away from the silicon wafer, and the doped layer has the same conductivity type as the silicon wafer.

[0013] The second functional layer is disposed on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separating region;

[0014] The first electrode penetrates the second functional layer and makes an ohmic contact with the N-type doped polycrystalline silicon carbide layer; the second electrode penetrates the second functional layer and makes an ohmic contact with the P-type doped polycrystalline silicon layer.

[0015] Optionally, the silicon wafer is an N-type silicon wafer, and the doping layer is an N-type doped layer;

[0016] And / or, the dielectric layer is a silicon oxide layer;

[0017] And / or, the thickness of the dielectric layer is 0.1 nm to 5 nm;

[0018] And / or, the thickness of the P-type doped polycrystalline silicon carbide layer is 30 nm to 100 nm;

[0019] And / or, the doping concentration of the P-type doped polycrystalline silicon carbide layer is 3 × 10⁻⁶. 19 atoms / cm 3 ~5×10 20 atoms / cm 3 ;

[0020] And / or, the thickness of the P-type doped polycrystalline silicon layer is 50 nm to 200 nm;

[0021] And / or, the doping concentration of the P-type doped polysilicon layer is 3 × 10⁻⁶. 19 atoms / cm 3 ~5×10 20 atoms / cm 3 ;

[0022] And / or, the thickness of the N-type doped polycrystalline silicon carbide layer is 30 nm to 100 nm;

[0023] And / or, the doping concentration of the N-type doped polycrystalline silicon carbide layer is 4 × 10⁻⁶. 20 atoms / cm 3 ~2×10 21 atoms / cm 3 ;

[0024] And / or, the diffusion sheet resistance of the doped layer is 200 Ω / sq to 500 Ω / sq;

[0025] And / or, the surface doping concentration of the doped layer is 5 × 10⁻⁶. 17 atoms / cm 3 ~5×10 20 atoms / cm 3 ;

[0026] And / or, the first functional layer includes a first silicon oxide passivation layer and a first antireflection layer stacked sequentially away from the silicon wafer;

[0027] And / or, the second functional layer includes a second silicon oxide passivation layer and a second antireflection layer stacked sequentially away from the silicon wafer.

[0028] Secondly, embodiments of this application provide a method for fabricating a solar cell as described in the first aspect, comprising the following steps:

[0029] A dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are fabricated on the backlight surface of the silicon wafer; wherein the dielectric layer and the P-type doped amorphous silicon carbide layer are sequentially stacked on the backlight surface away from the silicon wafer, and the P-type doped amorphous silicon layer and the first mask layer are sequentially stacked on the P-type doped amorphous silicon carbide layer outside the second region away from the silicon wafer, and the P-type doped amorphous silicon carbide layer in the second region is exposed;

[0030] An N-type doped amorphous silicon layer and a second mask layer are sequentially stacked on the backlight surface, facing away from the silicon wafer. The N-type doped amorphous silicon layer covers the exposed P-type doped amorphous silicon carbide layer. The doping concentration C1 of the N-type doped amorphous silicon layer and the doping concentration C2 of the P-type doped amorphous silicon carbide layer satisfy the following relationship: C1 / C2≥5.

[0031] The dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer are separated from the N-type doped amorphous silicon layer along the separation region;

[0032] The silicon wafer is subjected to annealing treatment; wherein, the P-type doped amorphous silicon layer crystallizes into the P-type doped polycrystalline silicon layer, the P-type doped amorphous silicon carbide layer on the first region crystallizes into the P-type doped polycrystalline silicon carbide layer; and the P-type doped amorphous silicon carbide layer stacked with the N-type doped amorphous silicon layer is transformed into the N-type doped polycrystalline silicon carbide layer.

[0033] Optionally, prior to the step of annealing the silicon wafer, the method for fabricating the solar cell further includes the following steps:

[0034] The light-receiving surface of the silicon wafer is subjected to diffusion of doping elements to form a doped layer; wherein the doped layer has the same conductivity type as the silicon wafer;

[0035] The step of annealing the silicon wafer includes:

[0036] After the doped layer is formed, the silicon wafer is annealed in an oxygen-containing atmosphere, and the N-type doped amorphous silicon layer is oxidized into a doped glass layer.

[0037] Optionally, after the step of annealing the silicon wafer, the method for fabricating the solar cell further includes the following steps:

[0038] Remove the second mask layer, the doped glass layer, and the first mask layer.

[0039] Optionally, after the step of removing the second mask layer, the doped glass layer, and the first mask layer, the method for fabricating the solar cell further includes the following steps:

[0040] A first functional layer is deposited on the light-receiving surface; wherein the first functional layer is disposed on the side of the doped layer opposite to the silicon wafer;

[0041] A second functional layer is deposited on the backlight surface; wherein the second functional layer is disposed on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separation region;

[0042] A first electrode and a second electrode are formed on the side of the second functional layer opposite to the silicon wafer; wherein the first electrode penetrates the second functional layer and makes ohmic contact with the N-type doped polycrystalline silicon carbide layer, and the second electrode penetrates the second functional layer and makes ohmic contact with the P-type doped polycrystalline silicon layer.

[0043] Optionally, the step of depositing the first functional layer on the light-receiving surface includes:

[0044] A first silicon oxide passivation layer is grown on the side of the doped layer opposite to the silicon wafer by a thermal oxidation method.

[0045] And / or, the step of depositing the second functional layer on the backlight surface includes:

[0046] A second silicon oxide passivation layer is grown on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separation region by a thermal oxidation method.

[0047] Optionally, the step of fabricating the dielectric layer, the P-type doped amorphous silicon carbide layer, the P-type doped amorphous silicon layer, and the first mask layer on the back surface of the silicon wafer includes:

[0048] A dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are sequentially stacked on the back surface of the silicon wafer, facing away from the silicon wafer.

[0049] Remove the first mask layer on the second region to expose the P-type doped amorphous silicon layer on the second region;

[0050] Remove the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer on the second region.

[0051] Optionally, the step of removing the first mask layer on the second region to expose the P-type doped amorphous silicon layer on the second region includes:

[0052] A nanosecond or picosecond ultraviolet laser is used to pattern and open windows in the first mask layer on the second region to form a second window region with a width of 100μm to 1000μm;

[0053] The step of removing the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer in the second region includes:

[0054] The second window area is etched to remove the exposed P-type doped amorphous silicon layer, while retaining the first mask layer.

[0055] Alternatively, the step of removing the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer on the second region includes:

[0056] The light-receiving surface of the silicon wafer is etched on one side to remove the coating layer of the first mask layer on the light-receiving surface and edge of the silicon wafer.

[0057] The silicon wafer is subjected to wet etching to remove the P-type doped amorphous silicon layer, the P-type doped amorphous silicon carbide layer, and the dielectric layer on the light-receiving surface and edge of the silicon wafer.

[0058] The second window area is etched to remove the exposed P-type doped amorphous silicon layer, while retaining the first mask layer on the back surface of the silicon wafer.

[0059] Optionally, the step of separating the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer from the N-type doped amorphous silicon layer along the separating region includes:

[0060] A first windowed region is formed by using a laser to create a window in the separated region; wherein the first windowed region extends from the second mask layer along a direction close to the silicon wafer to the P-type doped amorphous silicon carbide layer.

[0061] The first windowed area is etched; after etching, the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are separated along the first windowed area.

[0062] Optionally, the step of using a laser to perform windowing processing in the partitioned area to form the first windowed area includes:

[0063] Laser windowing is performed using green or infrared laser light to open at least the second mask layer, the P-type doped amorphous silicon carbide layer, and the junction of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, forming a first windowed area with a width of 10 μm to 60 μm.

[0064] The step of etching the first windowed area includes:

[0065] The light-receiving surface of the silicon wafer is etched on one side to remove the second mask layer, the N-type doped amorphous silicon layer, the first mask layer, the P-type doped amorphous silicon layer, the P-type doped amorphous silicon carbide layer, and the dielectric layer on the light-receiving surface and edge of the silicon wafer, while retaining the second mask layer on the backlight surface.

[0066] The back surface of the silicon wafer is wet-etched to etch the first window area; at the same time, the light-receiving surface of the silicon wafer is texturized.

[0067] Alternatively, the step of etching the first windowed area includes:

[0068] The light-receiving surface of the silicon wafer is etched on one side to remove the second mask layer on the light-receiving surface and edge of the silicon wafer, while retaining the second mask layer on the backlight surface.

[0069] The back surface of the silicon wafer is wet-etched to etch the first window area; at the same time, the light-receiving surface of the silicon wafer is etched to remove the N-type doped amorphous silicon layer coating on the light-receiving surface and edges of the silicon wafer, and the light-receiving surface of the silicon wafer is texturized.

[0070] Optionally, the silicon wafer is an N-type silicon wafer, and the doping layer is an N-type doped layer;

[0071] And / or, the dielectric layer is a silicon oxide layer;

[0072] And / or, the thickness of the dielectric layer is 0.1 nm to 5 nm;

[0073] And / or, the thickness of the P-type doped amorphous silicon carbide layer is 30 nm to 100 nm;

[0074] And / or, the doping concentration of the P-type doped amorphous silicon carbide layer is (8~20)×10⁻⁶. 19 atoms / cm3;

[0075] And / or, the thickness of the P-type doped amorphous silicon layer is 50 nm to 200 nm;

[0076] And / or, the first mask layer is a silicon oxide layer;

[0077] And / or, the thickness of the first mask layer is 20nm to 100nm;

[0078] And / or, the thickness of the N-type doped amorphous silicon layer is 30 nm to 100 nm;

[0079] And / or, the doping concentration of the N-type doped amorphous silicon layer is (1~2)×10⁻⁶. 21 atoms / cm 3 ;

[0080] And / or, the second mask layer is a silicon oxide layer;

[0081] And / or, the thickness of the second mask layer is 10nm to 50nm.

[0082] Thirdly, embodiments of this application provide a photovoltaic module, including a solar cell as described in the first aspect or a solar cell prepared by the method described in the second aspect.

[0083] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0084] This application provides a solar cell. The first region of the solar cell uses a dielectric layer, a P-type doped polycrystalline silicon carbide layer, and another P-type doped polycrystalline silicon layer to form a P-region passivation contact structure. The second region uses a dielectric layer and an N-type doped polycrystalline silicon carbide layer to form an N-region passivation contact structure. Both the first and second regions use passivation contact structures to improve the passivation effect and open-circuit voltage. A separating region is provided between the first and second regions to separate the P-region passivation contact structure and the N-region passivation contact structure to avoid leakage problems, which is beneficial to improving the conversion efficiency of the solar cell.

[0085] Compared to passivated contact structures with only doped polycrystalline silicon layers, the N-region and P-region passivated contact structures of this application, which incorporate N-type doped polycrystalline silicon carbide and P-type doped polycrystalline silicon carbide layers, are more stable and can effectively block slurry erosion, ensuring passivation while reducing thickness. Furthermore, silicon carbide has a larger bandgap than polycrystalline silicon; at the same thickness, it absorbs fewer free carriers and less long-wavelength photons reflected back into the silicon wafer, thus improving conversion efficiency.

[0086] Furthermore, the P-region passivation contact structure of this application has a P-type doped polycrystalline silicon carbide layer and a P-type doped polycrystalline silicon layer. This is because P-type doping is more difficult to achieve heavy doping than N-type doping, and P-type doped polycrystalline silicon carbide layer is more difficult to achieve heavy doping than P-type doped polycrystalline silicon layer. The passivation contact structure with only P-type doped polycrystalline silicon carbide layer is difficult to form good contact with the metal electrode. On the one hand, adding P-type doped polycrystalline silicon layer can reduce the contact resistance with the metal electrode, and on the other hand, it can reduce the lateral resistance, thereby improving the conversion efficiency of the solar cell. Attached Figure Description

[0087] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0088] Figure 1 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application;

[0089] Figure 2 This is a flowchart of a method for preparing a solar cell provided in Embodiment 1 of this application.

[0090] Explanation of reference numerals in the attached figures:

[0091] 100. Solar cell; 110. Silicon wafer; 111. Backlighting surface; A1. First region; A2. Second region; A3. Separation region; 112. Light-receiving surface; 120. Dielectric layer; 130. P-type doped polycrystalline silicon carbide layer; 140. P-type doped polycrystalline silicon carbide layer; 150. N-type doped polycrystalline silicon carbide layer; 160. Doped layer; 170. First functional layer; 171. First silicon oxide passivation layer; 172. First antireflection layer; 180. Second functional layer; 181. Second silicon oxide passivation layer; 182. Second antireflection layer; 190a. First electrode; 190b. Second electrode. Detailed Implementation

[0092] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0093] In this invention, the terms "set up" or "equipped with" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral structure; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium, or it can refer to an internal connection between two devices, elements, or components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0094] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0095] The back surface of the all-back electrode contact solar cell in the related technology adopts a passivated contact structure to improve performance. The polycrystalline silicon layer in the passivated contact structure is relatively unstable and is easily eroded by the paste used to make the electrode during the sintering process. Therefore, the thickness of the polycrystalline silicon layer is often relatively thick. A thick polycrystalline silicon layer will lead to severe parasitic absorption of light, which will affect the efficiency of the solar cell.

[0096] On the other hand, if doped polycrystalline silicon carbide is used to replace the doped polycrystalline silicon layer in the P-region passivation contact structure and the N-region passivation contact structure, due to the characteristics of P-type doping, it is difficult for the P-type doped silicon carbide layer to be heavily doped. The lower the doping concentration, the worse the contact performance between the doped silicon carbide layer and the metal electrode, resulting in poor contact between the P-type doped polycrystalline silicon carbide layer and the metal electrode, increased contact resistance, and difficulty in improving the performance of solar cells.

[0097] Based on the above analysis, this application provides a solar cell with a more stable structure consisting of an N-type doped polycrystalline silicon carbide layer and a P-type doped polycrystalline silicon carbide layer. This structure effectively blocks the erosion of the paste, allowing for thinning while maintaining passivation. Secondly, because silicon carbide has a larger bandgap than polycrystalline silicon, at the same thickness, it absorbs fewer free carriers and less long-wavelength photons reflected back into the silicon wafer, thus improving conversion efficiency. Furthermore, adding a P-type doped polycrystalline silicon layer to the P-region passivation contact structure reduces both the contact resistance with the metal electrode and the lateral resistance, thereby improving the solar cell's conversion efficiency.

[0098] The first aspect, such as Figure 1 As shown, this application provides a solar cell 100, including a silicon wafer 110, a dielectric layer 120, a P-type doped polycrystalline silicon carbide layer 130, a P-type doped polycrystalline silicon carbide layer 140, and an N-type doped polycrystalline silicon carbide layer 150.

[0099] Optionally, silicon wafer 110 is an N-type silicon wafer or a P-type silicon wafer.

[0100] The backlight surface 111 of the silicon wafer 110 has alternating first regions A1 and second regions A2, with a separating region A3 between adjacent first regions A1 and second regions A2. For example, on the backlight surface 111, the first region A1, the separating region A3, the second region A2, the separating region A3, the first region A1, the separating region A3, the second region A2, and so on are arranged.

[0101] The dielectric layer 120 is disposed on the backlight surface 111 and is interrupted along the partition region A3. The dielectric layer 120 is covered on both the first region A1 and the second region A2. The term "interrupted" means that the dielectric layer 120 is separated into more than one partition region A3.

[0102] The P-type doped polycrystalline silicon carbide layer 130 is located in the first region A1. The P-type doped polycrystalline silicon carbide layer 130 is disposed on the side of the dielectric layer 120 facing away from the silicon wafer 110.

[0103] P-type doped polycrystalline silicon layer 140 is disposed on the side of P-type doped polycrystalline silicon carbide layer 130 opposite to dielectric layer 120.

[0104] The N-type doped polycrystalline silicon carbide layer 150 is located in the second region A2. The N-type doped polycrystalline silicon carbide layer 150 is disposed on the side of the dielectric layer 120 facing away from the silicon wafer 110.

[0105] The first region A1 of the solar cell 100 uses a dielectric layer 120, a P-type doped polycrystalline silicon carbide layer 130, and a P-type doped polycrystalline silicon carbide layer 140 to form a P-region passivation contact structure. The second region A2 uses a dielectric layer 120 and an N-type doped polycrystalline silicon carbide layer 150 to form an N-region passivation contact structure. Both the first region A1 and the second region A2 use passivation contact structures for passivation contact, and a separating region A3 is provided between the first region A1 and the second region A2 to separate the N-region passivation contact structure and the P-region passivation contact structure, so as to suppress leakage current and improve the conversion efficiency of the solar cell 100.

[0106] Compared with the passivation contact structure in related technologies that only has a doped polycrystalline silicon layer, the N-region passivation contact structure and P-region passivation contact structure of this application, which add an N-type doped polycrystalline silicon carbide layer 150 and a P-type doped polycrystalline silicon carbide layer 130, are more stable and can effectively block the erosion of the slurry, and can reduce the thickness while ensuring the passivation effect.

[0107] Secondly, an N-type doped polycrystalline silicon carbide layer 150 and a P-type doped polycrystalline silicon carbide layer 130 are introduced. Since the band gap of silicon carbide is larger than that of polycrystalline silicon, at the same thickness, the absorption of free carriers is less, and the absorption of long-wavelength photons that are transmitted through the silicon wafer 110 and reflected back into the silicon wafer 110 is less, which is beneficial to improving the conversion efficiency.

[0108] Furthermore, the P-region passivation contact structure of this application has a P-type doped polycrystalline silicon carbide layer 130 and a P-type doped polycrystalline silicon layer 140. This is because P-type doping is more difficult to achieve heavy doping than N-type doping, and the P-type doped polycrystalline silicon carbide layer 130 is more difficult to achieve heavy doping than the P-type doped polycrystalline silicon layer 140. The passivation contact structure with only the P-type doped polycrystalline silicon carbide layer 130 is difficult to form a good contact with the metal electrode. On the other hand, the addition of the P-type doped polycrystalline silicon layer 140 can reduce the contact resistance with the metal electrode and reduce the lateral resistance, thereby improving the conversion efficiency of the solar cell 100.

[0109] like Figure 1 As shown, the solar cell 100 further includes a doped layer 160, a first functional layer 170, a second functional layer 180, a first electrode 190a, and a second electrode 190b.

[0110] A doped layer 160 and a first functional layer 170 are sequentially stacked on the light-receiving surface 112 of the silicon wafer 110, facing away from the silicon wafer 110. The doped layer 160 has the same conductivity type as the silicon wafer 110. The doped layer 160 can serve as a front surface field, which improves the passivation effect.

[0111] The second functional layer 180 is disposed on the side of the P-type doped polycrystalline silicon layer 140 facing away from the silicon wafer 110, the side of the N-type doped polycrystalline silicon carbide layer 150 facing away from the silicon wafer 110, and the separation region A3. For example, the second functional layer 180 may be a passivation layer, an anti-reflection layer, or at least one of passivation and anti-reflection layers. The material of the second functional layer 180 may be at least one of silicon oxide, silicon nitride, or silicon oxynitride. By selecting the material for fabricating the second functional layer 180, the second functional layer 180 disposed on the separation region A3 can have a leakage protection function.

[0112] The first electrode 190a penetrates the second functional layer 180 and makes a 150-ohm contact with the N-type doped polycrystalline silicon carbide layer. The second electrode 190b penetrates the second functional layer 180 and makes a 140-ohm contact with the P-type doped polycrystalline silicon layer to achieve current transmission.

[0113] Optionally, silicon wafer 110 is an N-type silicon wafer, and doped layer 160 is an N-type doped layer;

[0114] And / or, the diffusion sheet resistance of the doped layer 160 is 200Ω / sq to 500Ω / sq, including any point value within the diffusion sheet resistance range, such as 200Ω / sq, 300Ω / sq or 500Ω / sq;

[0115] And / or, the surface doping concentration of the doped layer 160 is 5 × 10⁻⁶. 17 atoms / cm 3 ~5×10 20 atoms / cm 3 This includes any point within the range of surface doping concentrations, for example, 5 × 10⁻⁶. 17 atoms / cm 3 1×10 19 atoms / cm 3 Or 5×10 20 atoms / cm 3 ;

[0116] The N-type doped layer can be an N-type doped high-low junction formed by phosphorus diffusion. The N-type doped high-low junction acts as a front surface field, which improves the passivation effect.

[0117] In this application, the material of the dielectric layer 120 may include at least one of various dielectric materials, such as silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer 120 may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, can minimize the recombination loss of minority carriers on the semiconductor substrate surface, and is a thin film with excellent durability for subsequent high-temperature processes.

[0118] The dielectric layer 120 acts as a barrier for electrons and holes, combining with the P-type doped polycrystalline silicon carbide layers 130, 140, and 150 to prevent minority carriers from passing through. The dielectric layer 120 can also function as a pinhole channel, allowing carriers within the solar cell 100 to move freely and selectively pass through the P-type doped polycrystalline silicon carbide layers 130, 140, and 150, thus reducing minority carrier recombination losses. Furthermore, the dielectric layer 120 can serve as a diffusion barrier to prevent dopants from the P-type doped polycrystalline silicon carbide layers 130, 140, and 150 from diffusing into the silicon wafer 110.

[0119] Preferably, the dielectric layer 120 is a silicon oxide layer;

[0120] And / or, the thickness of the dielectric layer 120 is 0.1 nm to 5 nm, including any value within this thickness range, such as 0.1 nm, 3 nm or 5 nm.

[0121] Preferably, the thickness of the P-type doped polycrystalline silicon carbide layer 130 is 30 nm to 100 nm, including any value within this thickness range, such as 30 nm, 50 nm or 100 nm.

[0122] And / or, the doping concentration of the P-type doped polycrystalline silicon carbide layer 130 is 3 × 10⁻⁶. 19 atoms / cm 3 ~5×10 20 atoms / cm 3 This includes any point within the doping concentration range, for example, 3 × 10⁻⁶. 19 atoms / cm 3 1×10 20 atoms / cm 3 Or 5×10 20 atoms / cm 3 ;

[0123] And / or, the thickness of the P-type doped polysilicon layer 140 is 50 nm to 200 nm, including any value within this thickness range, such as 50 nm, 150 nm or 200 nm.

[0124] And / or, the doping concentration of the P-type doped polysilicon layer 140 is 3 × 10⁻⁶. 19 atoms / cm 3 ~5×10 20 atoms / cm 3 This includes any point within the doping concentration range, for example, 3 × 10⁻⁶. 19 atoms / cm 3 1×10 20 atoms / cm 3 Or 5×10 20 atoms / cm 3 .

[0125] The P-type doped polycrystalline silicon carbide layer 130 can effectively block the slurry erosion, allowing the P-type doped polycrystalline silicon layer 140 to be thinned to a minimum thickness of 50 nm. While thinning the P-type doped polycrystalline silicon layer 140, the passivation effect is ensured, and the parasitic absorption caused by polycrystalline silicon is reduced.

[0126] Preferably, the thickness of the N-type doped polycrystalline silicon carbide layer 150 is 30 nm to 100 nm, including any value within this thickness range, such as 30 nm, 50 nm or 100 nm.

[0127] And / or, the doping concentration of the N-type doped polycrystalline silicon carbide layer 150 is 4 × 10⁻⁶. 20 atoms / cm 3 ~2×10 21 atoms / cm 3 This includes any point within the doping concentration range, for example, 4 × 10⁻⁶. 20 atoms / cm 3 1×10 21 atoms / cm 3 Or 2×10 21 atoms / cm 3 .

[0128] Due to the characteristics of N-type doping, the doping concentration of the N-type doped polycrystalline silicon carbide layer 150 can easily achieve heavy doping, reaching a doping concentration of 4 × 10⁻⁶. 20 atoms / cm 3 ~2×10 21 atoms / cm 3 The N-type doped polycrystalline silicon carbide layer 150 has a sufficiently high doping concentration to ensure the contact performance between the N-region passivation contact structure and the metal electrode. Therefore, the N-region passivation contact structure can avoid using a polycrystalline silicon layer, thus avoiding the parasitic absorption problems caused by polycrystalline silicon. Due to the characteristics of silicon carbide, the N-type doped polycrystalline silicon carbide layer 150, even at relatively thin thicknesses (30 nm to 100 nm), can still effectively prevent slurry erosion.

[0129] Preferably, the first functional layer 170 includes a first silicon oxide passivation layer 171 and a first antireflection layer 172 stacked sequentially away from the silicon wafer 110;

[0130] And / or, the second functional layer 180 includes a second silicon oxide passivation layer 181 and a second antireflection layer 182 stacked sequentially away from the silicon wafer 110.

[0131] The first silicon oxide passivation layer 171 and the second silicon oxide passivation layer 181 can be fabricated in a single oxidation process, simplifying the manufacturing process.

[0132] In some embodiments, the thickness of the first silicon oxide passivation layer 171 is 2 nm to 5 nm, including any value within this thickness range, such as 2 nm, 3 nm, or 5 nm. The silicon oxide passivation layer is suitable for passivating the light-receiving surface 112 of the N-type silicon wafer 110. The first antireflection layer 172 is selected from at least one of a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer. The total thickness of the first antireflection layer 172 is 60 nm to 150 nm, including any value within this thickness range, such as 60 nm, 100 nm, or 150 nm.

[0133] In some embodiments, the thickness of the second silicon oxide passivation layer 181 is 1 nm to 8 nm, including any value within this thickness range, such as 1 nm, 5 nm, or 8 nm. The second antireflection layer 182 is selected from at least one of a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer, and the total thickness of the second antireflection layer 182 is 60 nm to 130 nm, including any value within this thickness range, such as 60 nm, 100 nm, or 130 nm.

[0134] Secondly, embodiments of this application provide a method for fabricating a solar cell as described in the first aspect, comprising the following steps:

[0135] A dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are fabricated on the backlight side of a silicon wafer. The dielectric layer and the P-type doped amorphous silicon carbide layer are stacked sequentially on the backlight side away from the silicon wafer. The P-type doped amorphous silicon layer and the first mask layer are stacked sequentially on the P-type doped amorphous silicon carbide layer outside the second region away from the silicon wafer. The P-type doped amorphous silicon carbide layer in the second region is exposed.

[0136] An N-type doped amorphous silicon layer and a second mask layer are sequentially stacked on the backlight side, away from the silicon wafer. The N-type doped amorphous silicon layer covers the exposed P-type doped amorphous silicon carbide layer. The doping concentration C1 of the N-type doped amorphous silicon layer and the doping concentration C2 of the P-type doped amorphous silicon carbide layer satisfy the following relationship: C1 / C2≥5.

[0137] The dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are separated along the partition region.

[0138] The silicon wafer is annealed; wherein, the P-type doped amorphous silicon layer crystallizes into a P-type doped polycrystalline silicon layer, the P-type doped amorphous silicon carbide layer in the first region crystallizes into a P-type doped polycrystalline silicon carbide layer; and the P-type doped amorphous silicon carbide layer stacked with the N-type doped amorphous silicon layer is transformed into an N-type doped polycrystalline silicon carbide layer.

[0139] The following is a detailed analysis of the fabrication method of this solar cell:

[0140] The fabrication method of this solar cell first involves creating a dielectric layer, a P-type doped amorphous silicon carbide layer, and a first mask layer on the back surface. The fabricated P-type doped amorphous silicon layer and the first mask layer are then sequentially stacked on top of the P-type doped amorphous silicon carbide layer outside the second region, away from the silicon wafer. This exposes the P-type doped amorphous silicon carbide layer in the second region, allowing the subsequently deposited N-type doped amorphous silicon layer to contact the exposed P-type doped amorphous silicon carbide layer. Here, "outside the second region" refers to the first region and the separating region.

[0141] Since the second region is fabricated as an N-region passivated contact structure, the conductivity type of the P-type doped amorphous silicon carbide layer on the second region needs to be transformed. Therefore, after fabricating the N-type doped amorphous silicon layer and the second mask layer, a portion of the N-type doped amorphous silicon layer is stacked with the exposed P-type doped amorphous silicon carbide layer. This portion of the N-type doped amorphous silicon layer can serve as the dopant source for this portion of the P-type doped amorphous silicon carbide layer. Compared to the doping element used for P-type doping, such as boron, the doping element used for N-type doping, such as phosphorus, has a higher diffusion rate and solid solubility in silicon wafers than boron. This application utilizes the difference between P-type and N-type doping, selecting the doping concentration C1 of the N-type doped amorphous silicon layer and the doping concentration C2 of the P-type doped amorphous silicon carbide layer to satisfy the following relationship: C1 / C2≥5. This ensures that the N-type doped amorphous silicon layer causes a conductivity transformation in the P-type doped amorphous silicon carbide layer during the subsequent annealing process, thereby solving the problem of fabricating an N-region passivated contact structure based on a P-type doped amorphous silicon carbide layer.

[0142] It is understandable that if the fabricated N-type doped amorphous silicon layer covers the entire backlight surface, the first mask layer can separate the N-type doped amorphous silicon layer outside the second region from the P-type doped amorphous silicon layer, preventing them from contacting each other and affecting each other.

[0143] In order to obtain mutually separated N-region passivation contact structures and P-region passivation contact structures, after fabricating the N-type doped amorphous silicon layer, the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer are separated from the N-type doped amorphous silicon layer along the separation region to suppress leakage of solar cells.

[0144] Finally, an annealing process is performed to create N-region passivated contact structures and P-region passivated contact structures. The main characteristics of the annealing step are as follows:

[0145] First, the preparation method separates the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer along the separation region before annealing, so as to avoid the formation of conductive films with opposite conductivity types during the annealing process.

[0146] Secondly, compared to the two high-temperature annealing processes required in related technologies, this application only requires one annealing process, reducing the number of high-temperature processes, thereby saving energy and reducing damage to silicon wafers caused by high temperatures;

[0147] More importantly, in this annealing step, the N-type doped amorphous silicon layer causes the conductivity type of the P-type doped amorphous silicon carbide layer to change, thereby creating an N-region passivated contact structure on the basis of the P-type doped amorphous silicon carbide layer.

[0148] In summary, this solar cell fabrication method involves fewer high-temperature steps. By transforming the conductivity of the P-type doped amorphous silicon layer through an N-type doped amorphous silicon layer, the method eliminates the need for mask slurry, avoiding contamination and process complexity issues associated with slurry. This simplifies the fabrication process for back-contact solar cells with P- and N-region passivated contact structures. The resulting solar cell exhibits high conversion efficiency, low leakage current, and low metal electrode contact resistance.

[0149] Furthermore, prior to the annealing step of the silicon wafer, the method for fabricating this solar cell also includes the following steps:

[0150] The light-receiving surface of a silicon wafer is diffused with doping elements to form a doped layer; the doped layer has the same conductivity type as the silicon wafer.

[0151] The steps for annealing silicon wafers include:

[0152] After the doped layer is formed, the silicon wafer is annealed in an oxygen-containing atmosphere, and the N-type doped amorphous silicon layer is oxidized into a doped glass layer.

[0153] The fabrication method of this solar cell involves diffusion to form a doped layer, followed immediately by annealing, thus achieving diffusion and annealing in a single high-temperature process. In contrast, related technologies separate diffusion and annealing, requiring two separate high-temperature processes. This application simplifies the process flow, reduces the number of high-temperature processes, is more energy-efficient, and minimizes damage to the silicon wafer caused by the high-temperature processes.

[0154] To facilitate the removal of the N-type doped amorphous silicon layer, this step oxidizes the N-type doped amorphous silicon layer into a doped glass layer, namely a phosphosilicate glass layer. During the oxidation process, the second mask layer covering the N-type doped amorphous silicon layer does not block the oxygen source from oxidizing the N-type doped amorphous silicon layer.

[0155] Furthermore, after the step of annealing the silicon wafer, the method for fabricating this solar cell also includes the following steps:

[0156] Remove the second mask layer, the doped glass layer, and the first mask layer.

[0157] As mentioned in the above analysis, the N-region passivated contact structure can avoid the use of a polycrystalline silicon layer, thus avoiding the parasitic absorption problem caused by the polycrystalline silicon layer. Therefore, it is necessary to remove the N-type doped amorphous silicon layer. In the previous step, the N-type doped amorphous silicon layer was oxidized to a doped glass layer. If the N-type doped amorphous silicon layer is a phosphorus-doped amorphous silicon layer, then the doped glass layer is a phosphorus-silicon glass layer. In this step, the doped glass layer is removed together with the second mask layer and the first mask layer.

[0158] Furthermore, after the steps of removing the second mask layer, the doped glass layer, and the first mask layer, the method for fabricating this solar cell also includes the following steps:

[0159] A first functional layer is deposited on the light-receiving surface; wherein the first functional layer is disposed on the side of the doped layer that faces away from the silicon wafer;

[0160] A second functional layer is deposited on the backlight surface; wherein the second functional layer is disposed on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separation region;

[0161] A first electrode and a second electrode are fabricated on the side of the second functional layer that is away from the silicon wafer; wherein the first electrode penetrates the second functional layer and makes ohmic contact with the N-type doped polycrystalline silicon carbide layer, and the second electrode penetrates the second functional layer and makes ohmic contact with the P-type doped polycrystalline silicon layer.

[0162] For example, the first functional layer and the second functional layer can be a passivation layer, an anti-reflection layer, a passivation and anti-reflection layer, a conductive layer, or other film layers that give the solar cell additional functions.

[0163] The first electrode can be a silver electrode or an aluminum electrode, and the second electrode can be a silver electrode, a silver-aluminum electrode, or an aluminum electrode. The first and second electrodes are generally fabricated by screen printing a paste, followed by sintering to complete metallization. During the sintering process, the paste erodes the passivation contact structures of both the P-region and N-region, a process also known as ablation. The role of the P-type doped polycrystalline silicon carbide layer and the N-type doped polycrystalline silicon carbide layer is precisely to block the paste during this step, preventing damage to the dielectric layer.

[0164] Optionally, the step of depositing the first functional layer on the light-receiving surface includes:

[0165] A first silicon oxide passivation layer is grown on the side of the doped layer away from the silicon wafer by a thermal oxidation method.

[0166] And / or, the step of depositing a second functional layer on the backlight surface includes:

[0167] A second silicon oxide passivation layer is grown on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separating region using a thermal oxidation method.

[0168] The thermal oxidation method refers to a method of growing silicon oxide by reacting silicon material with an oxidant in a heated environment. Preferably, the thermal oxidation process is carried out simultaneously on both the light-receiving and back-light-receiving surfaces. For the back-light-receiving surface, since the separating region is a non-diffused area, the thermal oxidation method forms a second silicon oxide passivation layer, effectively reducing interfacial recombination in this region and ensuring the passivation effect.

[0169] Further, the steps of fabricating a dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer on the back surface of the silicon wafer include:

[0170] A dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are sequentially stacked on the back side of a silicon wafer, away from the silicon wafer.

[0171] Remove the first mask layer on the second region to expose the P-type doped amorphous silicon layer on the second region;

[0172] Remove the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer in the second region.

[0173] In this step, a dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are first fabricated covering the entire backlight surface. Then, the first mask layer and the P-type doped amorphous silicon layer on the second region are selectively removed to obtain the exposed P-type doped amorphous silicon carbide layer on the second region.

[0174] In addition, a dielectric layer and a P-type doped amorphous silicon carbide layer can be fabricated first to cover the entire backlight surface. Then, the P-type doped amorphous silicon carbide layer and the first mask layer can be fabricated only outside the second region using a mask, which can also result in a P-type doped amorphous silicon carbide layer exposed on the second region.

[0175] Optionally, the step of removing the first mask layer on the second region to expose the P-type doped amorphous silicon layer on the second region includes:

[0176] A nanosecond or picosecond ultraviolet laser is used to pattern and open windows in the first mask layer on the second region, forming a second window region with a width of 100μm to 1000μm.

[0177] Because the second window area is relatively wide, the laser used for opening the window must meet the requirement of low damage, so nanosecond or picosecond ultraviolet lasers are selected.

[0178] The step of removing the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer on the second region includes:

[0179] The second window area is etched to remove the exposed P-type doped amorphous silicon layer, while retaining the first mask layer.

[0180] Specifically, by first laser windowing followed by alkaline etching, the P-type doped amorphous silicon carbide layer on the second region is exposed. During the removal process, the P-type doped amorphous silicon carbide layer in the second region blocks the dielectric layer in that region. Because the P-type doped amorphous silicon carbide layer is alkali-resistant, it can serve as a mask layer for the dielectric layer, allowing it to be retained after the alkaline etching step. Subsequent steps do not require the fabrication of a dielectric layer, simplifying the process flow.

[0181] Furthermore, since the first mask layer fabricated in the previous step covers the entire backlight surface, the first mask layer outside the second region after patterning and windowing will be retained. This part of the first mask layer will also be retained in the alkaline etching step to separate the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer when depositing the N-type doped amorphous silicon layer in the subsequent process. This will prevent the elements doped in the N-type doped amorphous silicon layer from diffusing into the P-type doped amorphous silicon layer during the annealing process.

[0182] Alternatively, the step of removing the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer on the second region includes:

[0183] The light-receiving surface of the silicon wafer is etched on one side to remove the first mask layer on the light-receiving surface and edge of the silicon wafer.

[0184] Wet etching is performed on the silicon wafer to remove the P-type doped amorphous silicon layer, the P-type doped amorphous silicon carbide layer, and the dielectric layer on the light-receiving surface and edges of the silicon wafer.

[0185] The second window area is etched to remove the exposed P-type doped amorphous silicon layer, while retaining the first mask layer on the back surface of the silicon wafer.

[0186] Specifically, the first mask layer is first removed by hydrofluoric acid on one side, and then the P-type doped amorphous silicon layer, P-type doped amorphous silicon carbide layer and dielectric layer are removed by alkaline etching. Then, the second window area is etched by alkaline etching to remove the exposed P-type doped amorphous silicon layer, and the P-type doped amorphous silicon layer, P-type doped amorphous silicon carbide layer and dielectric layer are removed from the light-receiving surface and edge of the silicon wafer.

[0187] Alternatively, the first mask layer, the P-type doped amorphous silicon layer, the P-type doped amorphous silicon carbide layer, and the dielectric layer can be simultaneously removed by applying a mixed solution of hydrofluoric acid and nitric acid to one side of the light-receiving surface. Then, the exposed P-type doped amorphous silicon layer is removed by etching the second window area with an alkaline solution. Removing the coating layer prevents it from affecting the performance of the solar cell.

[0188] Further, the step of separating the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer from the N-type doped amorphous silicon layer along the separating region includes:

[0189] A first windowed region is formed by using a laser to create a window in the separated area; wherein, the first windowed region extends from the second mask layer along the direction close to the silicon wafer to the P-type doped amorphous silicon carbide layer;

[0190] The first window region is etched; after etching, the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are separated along the first window region.

[0191] After laser windowing, the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, which have opposite conductivity types, have been initially separated. Etching of the first windowed area further separates the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, effectively suppressing leakage in the solar cell.

[0192] Optionally, the step of using a laser to perform windowing in the partitioned area to form the first windowed area includes:

[0193] Laser windowing is performed using green or infrared laser light to open at least the second mask layer, the P-type doped amorphous silicon carbide layer, and the junction of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer. The width of the first windowed region is 10 μm to 60 μm, including any point value within this width range, such as 10 μm, 30 μm, or 60 μm.

[0194] Because the width of the first window area is relatively narrow, the damage caused by the laser is small, and green or infrared lasers can be used for laser windowing.

[0195] This laser windowing process removes at least the P-type doped amorphous silicon carbide layer, the P-type doped amorphous silicon layer, the first mask layer, the N-type doped amorphous silicon layer, and the second mask layer from the spacer region.

[0196] Optionally, the etching step of the first window area includes:

[0197] The light-receiving surface of the silicon wafer is etched on one side to remove the second mask layer, N-type doped amorphous silicon layer, first mask layer, P-type doped amorphous silicon layer, P-type doped amorphous silicon carbide layer and dielectric layer on the light-receiving surface and edge of the silicon wafer, while retaining the second mask layer on the backlight surface.

[0198] Wet etching is performed on the back surface of the silicon wafer to etch the first window area; at the same time, texturing is performed on the light-receiving surface of the silicon wafer.

[0199] The etching process is preferably a two-step etching process. The first step is to etch the light-receiving surface on one side. The single-side etching can be carried out by a mixed solution of hydrofluoric acid and nitric acid to remove the second mask layer, N-type doped amorphous silicon layer, first mask layer, P-type doped amorphous silicon layer, P-type doped amorphous silicon carbide layer and dielectric layer on the light-receiving surface and edge of the silicon wafer layer layer by layer.

[0200] The second step involves simultaneously performing wet etching on both the light-receiving and backlighting surfaces. This wet etching process is preferably alkaline etching, thereby etching the first windowed area. The main purpose of wet etching is to further separate the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, which have opposite conductivity types. It is understood that the dielectric layer in the intervening region may not have been windowed during the laser windowing process to form the first windowed area; this wet etching ensures that the dielectric layer in the intervening region is separated. During alkaline etching, although the alkali can also slowly etch the second mask layer made of silicon oxide, the thickness of the second mask layer is sufficient. After the first windowed area is etched, the second mask layer on the backlighting surface only sacrifices a portion of its thickness but is not completely etched, thus maintaining protection for other layers on the backlighting surface.

[0201] The alkaline etching process can simultaneously texturize the light-receiving surface by adding texturing additives to the etching solution, thereby forming a textured morphology that improves the performance of solar cells. This integrates etching the first window area, removing the coating, and texturing into one step, simplifying the process flow.

[0202] Alternatively, if the overlay of the first mask layer, the P-type doped amorphous silicon layer, the P-type doped amorphous silicon carbide layer, and the dielectric layer has been removed prior to this step, the etching step of the first window region includes:

[0203] The light-receiving surface of the silicon wafer is etched on one side to remove the second mask layer on the light-receiving surface and edge of the silicon wafer, while retaining the second mask layer on the backlight surface.

[0204] Wet etching is performed on the back surface of the silicon wafer to etch the first window area; at the same time, the light-receiving surface of the silicon wafer is etched to remove the N-type doped amorphous silicon layer on the light-receiving surface and edge of the silicon wafer, and the light-receiving surface of the silicon wafer is texturized.

[0205] The above steps are also performed in two steps. The first step, single-sided etching, can be performed using hydrofluoric acid, and the second step, wet etching, can be performed using alkali.

[0206] Preferably, the thickness of the P-type doped amorphous silicon carbide layer is 30 nm to 100 nm, including any value within this thickness range, such as 30 nm, 50 nm or 100 nm.

[0207] And / or, the doping concentration of the P-type doped amorphous silicon carbide layer is (8–20) × 10⁻⁶.19 atoms / cm 3 This includes any point within the doping concentration range, for example, 8 × 10⁻⁶. 19 atoms / cm 3 1×10 20 atoms / cm 3 Or 2×10 21 atoms / cm 3 ;

[0208] And / or, the thickness of the P-type doped amorphous silicon layer is 50 nm to 200 nm, including any value within this thickness range, such as 50 nm, 100 nm or 200 nm.

[0209] A lower doping concentration can be used in P-type doped amorphous silicon carbide layers because the P-type doped polycrystalline silicon layer after crystallization can form good contact with the metal electrode, thus reducing the doping concentration requirement for P-type doped amorphous silicon carbide layers. The lower doping concentration of P-type doped amorphous silicon carbide layers also makes it easier for N-type doped amorphous silicon layers to change their conductivity type during annealing.

[0210] Preferably, the first mask layer is a silicon oxide layer;

[0211] And / or, the thickness of the first mask layer is 20nm to 100nm, including any value within that thickness range, such as 20nm, 50nm or 100nm.

[0212] This thickness of silicon oxide layer serves as the first mask layer, preventing complete removal during alkaline etching. It is then used in subsequent steps to separate the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer, and is easily removed during subsequent cleaning.

[0213] Preferably, the thickness of the N-type doped amorphous silicon layer is 30 nm to 100 nm, including any value within this thickness range, such as 30 nm, 50 nm or 100 nm.

[0214] And / or, the doping concentration of the N-type doped amorphous silicon layer is (1~2)×10⁻⁶. 21 atoms / cm 3 This includes any point within the doping concentration range, for example, 1 × 10⁻⁶. 21 atoms / cm 3 1.5×10 21 atoms / cm 3 Or 2×10 21 atoms / cm 3 .

[0215] Preferably, the second mask layer is a silicon oxide layer;

[0216] And / or, the thickness of the second mask layer is 10nm to 50nm, including any value within that thickness range, such as 10nm, 30nm or 50nm.

[0217] This thickness of silicon oxide layer serves as a second mask layer, protecting the N-type doped amorphous silicon layer during the etching process and making it easy to remove during subsequent cleaning.

[0218] Thirdly, embodiments of this application provide a photovoltaic module, including a solar cell as described in the first aspect or a solar cell prepared by the method described in the second aspect.

[0219] The technical solution of the present invention will now be described in conjunction with the embodiments and accompanying drawings.

[0220] Example 1

[0221] like Figure 2 As shown in the figure, this embodiment provides a method for fabricating a solar cell, the steps of which are as follows:

[0222] S1. Polishing the backlight and light-receiving surfaces of the silicon wafer: An N-type silicon wafer with a resistivity of 1 Ω·cm to 2 Ω·cm is used. The wafer has a backlight and a light-receiving surface arranged in opposite directions. The backlight surface has multiple first regions and multiple second regions, which are alternately arranged with separating regions between adjacent first and second regions. Alkali polishing is used to remove the mechanical damage layer from the backlight and light-receiving surfaces of the silicon wafer, followed by RCA cleaning.

[0223] S2. On the back surface of the silicon wafer, a dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are stacked sequentially away from the silicon wafer: A 1.5 nm silicon oxide layer is grown on the back surface as a dielectric layer using PECVD deposition, followed by the sequential deposition of a 20 nm intrinsic amorphous silicon carbide layer, a 40 nm P-type doped amorphous silicon carbide layer, a 120 nm P-type doped amorphous silicon layer, and finally a 40 nm thick silicon oxide mask, i.e., the first mask layer, is deposited on the P-type doped amorphous silicon.

[0224] S3. Remove the first mask layer on the second region to expose the P-type doped amorphous silicon layer on the second region: Use an ultraviolet picosecond laser to pattern and open a window in the second region to form a second window region with a width of 600μm, open the first mask layer on the second region, retain the first mask layer on the first region, and expose the P-type doped amorphous silicon layer on the second region.

[0225] S4. Remove the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer on the second region: Use KOH to etch the second window region to remove the exposed P-type doped amorphous layer on the second region to expose the P-type doped amorphous silicon carbide layer on the second region. This cleaning step requires retaining the first mask layer, which separates the N-type doped amorphous silicon layer from the P-type doped amorphous silicon layer after the N-type doped amorphous silicon layer is deposited.

[0226] S5. An N-type doped amorphous silicon layer and a second mask layer are sequentially stacked on the backlight side, away from the silicon wafer. The N-type doped amorphous silicon layer covers the exposed P-type doped amorphous silicon carbide layer. A 50nm N-type doped amorphous silicon layer is deposited on the backlight side using PECVD. The N-type doped amorphous silicon layer covers the exposed P-type doped amorphous silicon carbide layer and the remaining first mask layer on the side away from the P-type doped amorphous silicon layer. Then, a 20nm thick silicon oxide layer, i.e., the second mask layer, is deposited on the side of the N-type doped amorphous silicon layer away from the silicon wafer.

[0227] S6. Use a laser to perform windowing in the separation area to form the first windowed area: Use a 532nm laser to perform laser windowing in the separation area. The first windowed area extends from the second mask layer along the direction close to the silicon wafer to the P-type doped amorphous silicon carbide layer. Windowing is performed on the second mask layer, the junction of the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer, and the P-type doped amorphous silicon carbide layer. The window width is 30μm.

[0228] S7. Etch the first window area. After etching, the dielectric layer, P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer and N-type doped amorphous silicon layer are separated along the first window area. Use a mixed solution of hydrofluoric acid and nitric acid to perform single-sided etching on the light-receiving surface of the silicon wafer to remove the coatings of the second mask layer, N-type doped amorphous silicon layer, first mask layer, P-type doped amorphous silicon layer, P-type doped amorphous silicon carbide layer, and dielectric layer on the light-receiving surface and edges of the silicon wafer, while retaining the second mask layer on the backlight surface. Use alkali and texturing additives to perform wet etching on the backlight surface of the silicon wafer to etch the first window area. After etching, the dielectric layer, P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer and N-type doped amorphous silicon layer are separated along the first window area; simultaneously, texturing is performed on the light-receiving surface of the silicon wafer. Finally, clean the silicon wafer with hydrochloric acid to remove metal ions.

[0229] S8. The silicon wafer undergoes diffusion of doping elements on the light-receiving surface to form a doped layer. The wafer is then annealed using a gradient heating process: first, phosphorus oxychloride is introduced at 840°C for phosphorus diffusion, forming a lightly doped phosphorus layer on the light-receiving surface. Then, the wafer is subjected to gradient annealing in nitrogen and oxygen atmospheres at temperatures of 910°C and 940°C, respectively. After annealing, the P-type doped amorphous silicon layer crystallizes into a P-type doped polycrystalline silicon layer, and the P-type doped amorphous silicon carbide layer in the first region crystallizes into a P-type doped polycrystalline silicon carbide layer. The P-type doped amorphous silicon carbide layer stacked with the N-type doped amorphous silicon layer transforms into an N-type doped polycrystalline silicon carbide layer with a thickness of 60 nm and a doping concentration of 1 × 10⁻⁶. 21 atoms / cm 3 The total thickness of the P-type doped polycrystalline silicon layer and the P-type doped polycrystalline silicon carbide layer is 160 nm, and the doping concentration is 1 × 10⁻⁶. 20 atoms / cm 3 The dielectric layer, the P-type doped polycrystalline silicon carbide layer, and the P-type doped polycrystalline silicon layer together form the P-region passivation contact structure, while the dielectric layer and the N-type doped polycrystalline silicon carbide layer form the N-region passivation contact structure. During high-temperature oxygen annealing, the N-type doped amorphous silicon layer is oxidized to a phosphorosillicate glass (PSG) layer, i.e., a doped glass layer.

[0230] S9. Remove the second mask layer, the doped glass layer, and the first mask layer: Use hydrofluoric acid to remove the doped glass layer, and then perform RCA cleaning to remove the second mask layer and the remaining first mask layer.

[0231] S10. Deposit a first functional layer on the light-receiving surface and a second functional layer on the backlighting surface: A silicon oxide passivation layer with a thickness of 3 nm is grown on both the backlighting and light-receiving surfaces using a thermal oxidation method. This is the first silicon oxide passivation layer and the second silicon oxide passivation layer. The first silicon oxide passivation layer is formed on the side of the doped layer facing away from the silicon wafer. The second silicon oxide passivation layer is formed on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and on the separating region.

[0232] Silicon nitride, silicon oxynitride, and silicon oxide composite films are deposited on the backlight and light-receiving surfaces using PECVD to form the first and second antireflection layers, respectively. These layers also provide passivation. Both the first and second antireflection layers are 100 nm thick. The first antireflection layer is formed on the side of the first silicon oxide passivation layer facing away from the silicon wafer. The first silicon oxide passivation layer and the first antireflection layer together form the first functional layer. The second antireflection layer is formed on the side of the second silicon oxide passivation layer facing away from the silicon wafer. The second silicon oxide passivation layer and the second antireflection layer together form the second functional layer.

[0233] S11. Fabricate a first electrode and a second electrode on the side of the second functional layer facing away from the silicon wafer: Silver paste is printed onto the side of the second functional layer in the second region facing away from the silicon wafer using screen printing, and silver-aluminum paste is printed onto the side of the second functional layer in the first region facing away from the silicon wafer, forming patterned metal grid lines for current collection. The silicon wafer is then subjected to high-temperature sintering to obtain the first electrode and the second electrode; wherein, the first electrode penetrates the second functional layer and makes ohmic contact with the N-type doped polycrystalline silicon carbide layer, and the second electrode penetrates the second functional layer and makes ohmic contact with the P-type doped polycrystalline silicon layer.

[0234] S12. Light injection into solar cells: Post-processing of solar cells using light injection.

[0235] Example 2

[0236] The only difference between this embodiment and Embodiment 1 is that:

[0237] In step S1, a P-type silicon wafer with a resistivity of 0.5 Ω·cm to 7 Ω·cm is used.

[0238] In step S8, the diffusion of dopant elements onto the light-receiving surface of the silicon wafer to form a doped layer is not performed. Only the silicon wafer is annealed. Specifically, step S8 in this embodiment is as follows: the silicon wafer is subjected to gradient annealing in a nitrogen atmosphere and an oxygen atmosphere, with annealing temperatures of 910°C and 940°C, respectively. After annealing, the P-type doped amorphous silicon layer crystallizes into a P-type doped polycrystalline silicon layer, and the P-type doped amorphous silicon carbide layer in the first region crystallizes into a P-type doped polycrystalline silicon carbide layer; the P-type doped amorphous silicon carbide layer stacked with the N-type doped amorphous silicon layer transforms into an N-type doped polycrystalline silicon carbide layer.

[0239] In step S10, aluminum oxide passivation layers, namely a first aluminum oxide passivation layer and a second aluminum oxide passivation layer, are grown on the back surface and the light-receiving surface respectively using ALD (Atomic Layer Deposition). A first antireflection layer is formed on the side of the first aluminum oxide passivation layer facing away from the silicon wafer. The first aluminum oxide passivation layer and the first antireflection layer constitute a first functional layer. A second antireflection layer is formed on the side of the second aluminum oxide passivation layer facing away from the silicon wafer. The second aluminum oxide passivation layer and the second antireflection layer constitute a second functional layer.

[0240] Example 3

[0241] The only difference between this embodiment and Embodiment 1 is that the thickness of the P-type doped amorphous silicon deposited in step S2 is 50 nm. The total thickness of the P-type doped polycrystalline silicon layer and the P-type doped polycrystalline silicon carbide layer in step S8 is 90 nm.

[0242] Example 4

[0243] The only difference between this embodiment and embodiment 1 is that step S8 does not involve the diffusion of doping elements onto the light-receiving surface to form a doped layer; that is, no doped layer is formed on the light-receiving surface.

[0244] Example 5

[0245] The only difference between this embodiment and Embodiment 1 is that, in step S10, a silicon oxide passivation layer with a thickness of 3 nm is not grown on the backlight surface and the light-receiving surface respectively using the thermal oxidation method; that is, the first silicon oxide passivation layer and the second silicon oxide passivation layer are not fabricated. Therefore, the first antireflection layer is formed on the side of the doped layer facing away from the silicon wafer, and the second antireflection layer is formed on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separating region.

[0246] Comparative Example 1

[0247] The difference between this comparative example and Example 1 is that the relationship between the doping concentration C1 of the N-type doped amorphous silicon layer and the doping concentration C2 of the P-type doped amorphous silicon carbide layer in step S5 is C1 / C2 = 2.

[0248] Comparative Example 2

[0249] The method for fabricating a back-contact solar cell provided in this comparative example includes:

[0250] Step a: Perform double-sided polishing on the silicon wafer;

[0251] Step b: A first dielectric layer, a P-type doped polysilicon layer, and a laser blocking layer are stacked from the inside to the outside on the back surface of the silicon wafer. During the formation of the P-type doped polysilicon layer, a first silicon oxide layer is simultaneously formed on the P-type doped polysilicon layer.

[0252] Step c: Remove the laser blocking layer and the first silicon oxide layer in the first region of the back surface of the silicon wafer by laser, wherein the first region is alternately arranged with the second region where the laser blocking layer and the first silicon oxide layer are retained;

[0253] Step d: Remove the first dielectric layer and the P-type doped polysilicon layer in the first region by alkaline polishing;

[0254] Step e: In the first region of the backlight surface of the silicon wafer, a second dielectric layer and an N-type doped polysilicon layer are formed in an alternating manner, which are isolated from the first dielectric layer and the P-type doped polysilicon layer. Simultaneously, the spacer region adjacent to the second region in the first region and the light-receiving surface of the silicon wafer are texturized to form a textured structure on the spacer region and the light-receiving surface of the silicon wafer. The spacer region is used to isolate the adjacent P-type doped polysilicon layer and N-type doped polysilicon layer.

[0255] Step f: Remove the laser blocking layer and the first silicon oxide layer on the second region by acid cleaning.

[0256] Comparative Example 3

[0257] The difference between this comparative example and Example 1 is that step S7 is not performed, that is, the first window area is not etched.

[0258] Comparative Example 4

[0259] The difference between this comparative example and Example 1 is that in step S9, after removing the second mask layer and the remaining first mask layer, the silicon oxide mask on the backlight side is first removed by single-sided hydrofluoric acid, and then the P-type doped polysilicon layer on the backlight side is removed by alkaline washing (silicon carbide is stable and can resist alkaline corrosion, so it serves as a barrier layer), while retaining the bottom layer of P-type and N-type silicon carbide. Then, the PSG on the light-receiving side is removed by hydrofluoric acid and hydrochloric acid cleaning.

[0260] Solar cell performance testing

[0261] The solar cells prepared in each embodiment and comparative example were tested, and the test results are shown in Table 1.

[0262] Table 1: Test results of solar cells prepared in each embodiment and comparative example

[0263]

[0264] As shown in Table 1, the conversion efficiency of Comparative Example 1 is 0.66% lower than that of Example 1. The main reason is that the ratio of the doping concentration C1 of the N-type doped amorphous silicon layer to the doping concentration C2 of the P-type doped amorphous silicon carbide layer is lower. The lower doping concentration of the N-type doped amorphous silicon layer affects the contact performance and passivation performance of the solar cell, which in turn affects the conversion efficiency, open circuit voltage, fill factor and series resistance of the solar cell.

[0265] The solar cell in Comparative Example 2 uses a first dielectric layer and a P-type doped polycrystalline silicon layer, as well as a second dielectric layer and an N-type doped polycrystalline silicon layer for passivation. This results in a slight decrease in open-circuit voltage, fill factor, and short-circuit current density. The decrease in open-circuit voltage and fill factor compared to Example 1 is mainly due to the relatively unstable properties of the P-type and N-type doped polycrystalline silicon layers, which have a certain impact on their structure and even the first and second dielectric layers during the sintering of the metal paste. The decrease in short-circuit current density is due to the stronger light absorption capacity of polycrystalline silicon compared to silicon carbide. Furthermore, to avoid burn-through of the paste, the doped polycrystalline silicon layer needs to have a larger thickness, which further affects the solar cell's light absorption.

[0266] Comparative Example 3 did not etch the first window area, and the film structures on the first and second regions were not completely isolated. As a result, the solar cell in this comparative example had a significantly lower conversion efficiency, a significantly lower open-circuit voltage, a significantly lower short-circuit current density and a significantly lower fill factor, and a significantly higher leakage current compared to Example 1. The main reason is that the film structures on the first and second regions became conductive, leading to leakage problems.

[0267] In Comparative Example 4, the P-region passivation contact structure only has a dielectric layer and a P-type doped polycrystalline silicon carbide layer. It is difficult to achieve high concentration doping of the silicon carbide layer, and the doping concentration of the P-type doped silicon carbide layer is relatively low. The contact between the second electrode and the P-type doped silicon carbide layer will be slightly poor, resulting in an increase in series resistance, a decrease in fill factor, and ultimately a low conversion efficiency.

[0268] Compared to Example 1, Example 2 uses a P-type silicon wafer. The minority carrier lifetime of the P-type silicon wafer is lower than that of the N-type silicon wafer, which results in a slightly lower conversion efficiency, open-circuit voltage and fill factor in Example 2 compared to Example 1 which uses an N-type silicon wafer.

[0269] Compared to Example 1, Example 3 reduced the thickness of the P-type doped amorphous silicon, resulting in a thinner P-type doped polycrystalline silicon layer formed by annealing. This reduced the absorption of long wavelengths by the P-type doped polycrystalline silicon layer on the backlight side, allowing more photons to be reflected back into the silicon wafer for secondary absorption, leading to a slight increase in short-circuit current density. However, the conversion efficiency was 0.04% lower, mainly due to the thinner P-type doped polycrystalline silicon layer, resulting in higher lateral and contact resistances, as well as a higher series resistance, which in turn caused a slight decrease in the fill factor.

[0270] In Example 4, no doped layer was fabricated compared to Example 1. No electric field was formed on the light-receiving surface, and charge carriers only separated and migrated from the light-receiving surface to the back-light-receiving surface under the influence of the back-light-receiving surface field. Example 4 had disadvantages in open-circuit voltage, short-circuit current density, and fill factor, and its conversion efficiency was 0.16% lower than that of Example 1.

[0271] Example 5 lacks the first silicon oxide passivation layer and the second silicon oxide passivation layer to passivate the light-receiving surface and the isolation P-region passivation contact structure and N-region passivation contact structure, resulting in increased recombination and a significant decrease in open-circuit voltage and fill factor.

[0272] The foregoing has provided a detailed description of a solar cell, its preparation method, and a photovoltaic module disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the solar cell, its preparation method, the photovoltaic module, and its core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A solar cell, characterized in that, include: A silicon wafer, wherein the backlight surface of the silicon wafer has alternating first and second regions, and a separating region is provided between adjacent first and second regions; A dielectric layer is disposed on the backlight surface and is broken along the dividing region, and the dielectric layer is covered on both the first region and the second region; A P-type doped polycrystalline silicon carbide layer is located in the first region, and the P-type doped polycrystalline silicon carbide layer is disposed on the side of the dielectric layer opposite to the silicon wafer; A P-type doped polycrystalline silicon layer is disposed on the side of the P-type doped polycrystalline silicon carbide layer that is away from the dielectric layer; as well as An N-type doped polycrystalline silicon carbide layer is located in the second region, and the N-type doped polycrystalline silicon carbide layer is disposed on the side of the dielectric layer opposite to the silicon wafer.

2. The solar cell according to claim 1, characterized in that, The solar cell further includes a doped layer, a first functional layer, a second functional layer, a first electrode, and a second electrode; The doped layer and the first functional layer are stacked sequentially on the light-receiving surface of the silicon wafer away from the silicon wafer, and the doped layer has the same conductivity type as the silicon wafer; The second functional layer is disposed on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separating region; The first electrode penetrates the second functional layer and makes an ohmic contact with the N-type doped polycrystalline silicon carbide layer; the second electrode penetrates the second functional layer and makes an ohmic contact with the P-type doped polycrystalline silicon layer.

3. The solar cell according to claim 2, characterized in that, The silicon wafer is an N-type silicon wafer, and the doping layer is an N-type doping layer; And / or, the dielectric layer is a silicon oxide layer; And / or, the thickness of the dielectric layer is 0.1 nm to 5 nm; And / or, the thickness of the P-type doped polycrystalline silicon carbide layer is 30 nm to 100 nm; And / or, the doping concentration of the P-type doped polycrystalline silicon carbide layer is 3 × 10⁻⁶. 19 atoms / cm 3 ~5×10 20 atoms / cm 3 ; And / or, the thickness of the P-type doped polycrystalline silicon layer is 50 nm to 200 nm; And / or, the doping concentration of the P-type doped polysilicon layer is 3 × 10⁻⁶. 19 atoms / cm 3 ~5×10 20 atoms / cm 3 ; And / or, the thickness of the N-type doped polycrystalline silicon carbide layer is 30 nm to 100 nm; And / or, the doping concentration of the N-type doped polycrystalline silicon carbide layer is 4 × 10⁻⁶. 20 atoms / cm 3 ~2×10 21 atoms / cm 3 ; And / or, the diffusion sheet resistance of the doped layer is 200 Ω / sq to 500 Ω / sq; And / or, the surface doping concentration of the doped layer is 5 × 10⁻⁶. 17 atoms / cm 3 ~5×10 20 atoms / cm 3 ; And / or, the first functional layer includes a first silicon oxide passivation layer and a first antireflection layer stacked sequentially away from the silicon wafer; And / or, the second functional layer includes a second silicon oxide passivation layer and a second antireflection layer stacked sequentially away from the silicon wafer.

4. A method for preparing a solar cell as described in any one of claims 1 to 3, characterized in that, Includes the following steps: A dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are fabricated on the backlight surface of the silicon wafer; wherein the dielectric layer and the P-type doped amorphous silicon carbide layer are sequentially stacked on the backlight surface away from the silicon wafer, and the P-type doped amorphous silicon layer and the first mask layer are sequentially stacked on the P-type doped amorphous silicon carbide layer outside the second region away from the silicon wafer, and the P-type doped amorphous silicon carbide layer in the second region is exposed; An N-type doped amorphous silicon layer and a second mask layer are sequentially stacked on the backlight surface, facing away from the silicon wafer. The N-type doped amorphous silicon layer covers the exposed P-type doped amorphous silicon carbide layer. The doping concentration C1 of the N-type doped amorphous silicon layer and the doping concentration C2 of the P-type doped amorphous silicon carbide layer satisfy the following relationship: C1 / C2≥5. The dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer are separated from the N-type doped amorphous silicon layer along the separation region; The silicon wafer is subjected to annealing treatment; wherein, the P-type doped amorphous silicon layer crystallizes into the P-type doped polycrystalline silicon layer, the P-type doped amorphous silicon carbide layer on the first region crystallizes into the P-type doped polycrystalline silicon carbide layer; and the P-type doped amorphous silicon carbide layer stacked with the N-type doped amorphous silicon layer is transformed into the N-type doped polycrystalline silicon carbide layer.

5. The method for preparing a solar cell according to claim 4, characterized in that, Before the step of annealing the silicon wafer, the method for fabricating the solar cell further includes the following steps: The light-receiving surface of the silicon wafer is subjected to diffusion of doping elements to form a doped layer; wherein the doped layer has the same conductivity type as the silicon wafer; The step of annealing the silicon wafer includes: After the doped layer is formed, the silicon wafer is annealed in an oxygen-containing atmosphere, and the N-type doped amorphous silicon layer is oxidized into a doped glass layer.

6. The method for preparing a solar cell according to claim 5, characterized in that, Following the step of annealing the silicon wafer, the method for fabricating the solar cell further includes the following steps: Remove the second mask layer, the doped glass layer, and the first mask layer.

7. The method for preparing a solar cell according to claim 6, characterized in that, After the step of removing the second mask layer, the doped glass layer, and the first mask layer, the method for fabricating the solar cell further includes the following steps: A first functional layer is deposited on the light-receiving surface; wherein the first functional layer is disposed on the side of the doped layer opposite to the silicon wafer; A second functional layer is deposited on the backlight surface; wherein the second functional layer is disposed on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separation region; A first electrode and a second electrode are formed on the side of the second functional layer opposite to the silicon wafer; wherein the first electrode penetrates the second functional layer and makes ohmic contact with the N-type doped polycrystalline silicon carbide layer, and the second electrode penetrates the second functional layer and makes ohmic contact with the P-type doped polycrystalline silicon layer.

8. The method for preparing a solar cell according to claim 7, characterized in that, The step of depositing the first functional layer on the light-receiving surface includes: A first silicon oxide passivation layer is grown on the side of the doped layer opposite to the silicon wafer by a thermal oxidation method. And / or, the step of depositing the second functional layer on the backlight surface includes: A second silicon oxide passivation layer is grown on the side of the P-type doped polycrystalline silicon layer facing away from the silicon wafer, the side of the N-type doped polycrystalline silicon carbide layer facing away from the silicon wafer, and the separation region by a thermal oxidation method.

9. The method for preparing a solar cell according to claim 4, characterized in that, The step of fabricating the dielectric layer, the P-type doped amorphous silicon carbide layer, the P-type doped amorphous silicon layer, and the first mask layer on the back surface of the silicon wafer includes: A dielectric layer, a P-type doped amorphous silicon carbide layer, a P-type doped amorphous silicon layer, and a first mask layer are sequentially stacked on the back surface of the silicon wafer, facing away from the silicon wafer. Remove the first mask layer on the second region to expose the P-type doped amorphous silicon layer on the second region; Remove the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer on the second region.

10. The method for preparing a solar cell according to claim 9, characterized in that, The step of removing the first mask layer on the second region to expose the P-type doped amorphous silicon layer on the second region includes: A nanosecond or picosecond ultraviolet laser is used to pattern and open windows in the first mask layer on the second region to form a second window region with a width of 100μm to 1000μm; The step of removing the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer in the second region includes: The second window area is etched to remove the exposed P-type doped amorphous silicon layer, while retaining the first mask layer. Alternatively, the step of removing the exposed P-type doped amorphous silicon layer to expose the P-type doped amorphous silicon carbide layer on the second region includes: The light-receiving surface of the silicon wafer is etched on one side to remove the coating layer of the first mask layer on the light-receiving surface and edge of the silicon wafer. The silicon wafer is subjected to wet etching to remove the P-type doped amorphous silicon layer, the P-type doped amorphous silicon carbide layer, and the dielectric layer on the light-receiving surface and edge of the silicon wafer. The second window area is etched to remove the exposed P-type doped amorphous silicon layer, while retaining the first mask layer on the back surface of the silicon wafer.

11. The method for preparing a solar cell according to any one of claims 4 to 10, characterized in that, The step of separating the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer from the N-type doped amorphous silicon layer along the separating region includes: A first windowed region is formed by using a laser to create a window in the separated region; wherein the first windowed region extends from the second mask layer along a direction close to the silicon wafer to the P-type doped amorphous silicon carbide layer. The first windowed area is etched; after etching, the dielectric layer, the P-type doped amorphous silicon carbide layer, and the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are separated along the first windowed area.

12. The method for preparing a solar cell according to claim 11, characterized in that, The step of using a laser to perform windowing processing in the separated area to form a first windowed area includes: Laser windowing is performed using green or infrared laser light to open at least the second mask layer, the P-type doped amorphous silicon carbide layer, and the junction of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, forming a first windowed area with a width of 10 μm to 60 μm. The step of etching the first windowed area includes: The light-receiving surface of the silicon wafer is etched on one side to remove the second mask layer, the N-type doped amorphous silicon layer, the first mask layer, the P-type doped amorphous silicon layer, the P-type doped amorphous silicon carbide layer, and the dielectric layer on the light-receiving surface and edge of the silicon wafer, while retaining the second mask layer on the backlight surface. The back surface of the silicon wafer is wet-etched to etch the first window area; at the same time, the light-receiving surface of the silicon wafer is texturized. Alternatively, the step of etching the first windowed area includes: The light-receiving surface of the silicon wafer is etched on one side to remove the second mask layer on the light-receiving surface and edge of the silicon wafer, while retaining the second mask layer on the backlight surface. The back surface of the silicon wafer is wet-etched to etch the first window area; at the same time, the light-receiving surface of the silicon wafer is etched to remove the N-type doped amorphous silicon layer coating on the light-receiving surface and edges of the silicon wafer, and the light-receiving surface of the silicon wafer is texturized.

13. The method for preparing a solar cell according to claim 7, characterized in that, The silicon wafer is an N-type silicon wafer, and the doping layer is an N-type doping layer; And / or, the dielectric layer is a silicon oxide layer; And / or, the thickness of the dielectric layer is 0.1 nm to 5 nm; And / or, the thickness of the P-type doped amorphous silicon carbide layer is 30 nm to 100 nm; And / or, the doping concentration of the P-type doped amorphous silicon carbide layer is (8~20)×10⁻⁶. 19 atoms / cm 3 ; And / or, the thickness of the P-type doped amorphous silicon layer is 50 nm to 200 nm; And / or, the first mask layer is a silicon oxide layer; And / or, the thickness of the first mask layer is 20nm to 100nm; And / or, the thickness of the N-type doped amorphous silicon layer is 30 nm to 100 nm; And / or, the doping concentration of the N-type doped amorphous silicon layer is (1~2)×10⁻⁶. 21 atoms / cm 3 ; And / or, the second mask layer is a silicon oxide layer; And / or, the thickness of the second mask layer is 10nm to 50nm.

14. A photovoltaic module, characterized in that, The solar cell includes those prepared by any one of claims 1 to 3 or by any one of claims 4 to 13.

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