Solar cell, method for preparing solar cell and photovoltaic module

Abstract

The invention discloses a solar cell, a method for preparing the solar cell and a photovoltaic module, and belongs to the field of solar cells. The solar cell comprises a silicon substrate, the silicon substrate is provided with a front surface and a back surface which are oppositely arranged, and the back surface comprises first areas and second areas which are alternately arranged; the doping type of the first doping layer is the same as that of the silicon substrate, and the orthographic projection of the first doping layer on the back surface is located in the first region; the second doping layer is located on the face, away from the silicon substrate, of the first doping layer, and the doping type of the second doping layer is the same as that of the first doping layer; the first passivation layer is arranged on the first area, the first passivation layer is located on the face, away from the silicon substrate, of the second doping layer, and the first passivation layer is in direct contact with the silicon substrate on the second area; and the first electrode is in electric contact with the first doped layer. The back surface of the solar cell can achieve a good passivation effect, and the contact effect of the metal region on the back surface is good.

Description

Technical Field

[0001] This application belongs to the field of solar cells, and particularly relates to a solar cell, a method for preparing a solar cell, and a photovoltaic module. Background Technology

[0002] Tunnel oxide passivated contact (TOPCon) solar cells have become the mainstream product for industrial solar cell manufacturers due to their excellent passivated contact structure, which can effectively reduce carrier recombination losses at the metal contacts on the back of the cell.

[0003] The combination of a highly doped polycrystalline silicon layer (Poly silicon layer) and an extremely thin tunnel oxide (SiOx) layer gives TOPCon solar cells excellent surface and chemical passivation effects. However, the polycrystalline silicon layer formed on the tunnel oxide layer can introduce parasitic absorption, leading to a decrease in the short-circuit current of the solar cell. Furthermore, the quality of the tunnel oxide layer and the doped polycrystalline silicon layer can also affect the stability of the cell's passivation effect.

[0004] Therefore, current solar cells still need improvement. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a solar cell, a method for manufacturing a solar cell, and a photovoltaic module.

[0006] In a first aspect, this application provides a solar cell, comprising:

[0007] A silicon substrate having a front side and a back side disposed opposite to each other, the back side comprising an alternately arranged first region and a second region;

[0008] A first doped layer, wherein the first doped layer has the same doping type as the silicon substrate, and the orthographic projection of the first doped layer on the back side is located in the first region;

[0009] A second doped layer is located on the side of the first doped layer away from the silicon substrate, and the doping type of the second doped layer is the same as that of the silicon substrate;

[0010] A first passivation layer is located on the side of the second doped layer away from the silicon substrate in the first region, and in the second region, the first passivation layer is in direct contact with the silicon substrate.

[0011] The first electrode is in electrical contact with the first doped layer.

[0012] According to the solar cell of this application, the back side of the solar cell can achieve a good passivation effect, and the contact effect of the metal area on the back side is good.

[0013] According to one embodiment of this application, the silicon substrate protrudes in the first region in a direction away from the silicon substrate relative to the second region, and / or the silicon substrate is recessed in the second region in a direction closer to the silicon substrate relative to the first region.

[0014] According to one embodiment of this application, the height difference between the surface of the silicon substrate in the first region and the surface of the silicon substrate in the second region is 3 μm to 5 μm.

[0015] According to one embodiment of this application, the first passivation layer covers the second doped layer and the side surface of the first doped layer.

[0016] According to an embodiment of this application, the first doped layer satisfies at least one of the following conditions:

[0017] The thickness of the first doped layer is 300 nm to 500 nm;

[0018] The sheet resistance of the first doped layer is 70Ω / sq to 150Ω / sq;

[0019] The doping element of the first doped layer includes phosphorus.

[0020] The doping concentration of the first doped layer is 1×10 18 cm -3 ~1×10 19 cm -3 .

[0021] According to one embodiment of this application, the doping element of the second doped layer includes phosphorus; and / or, the thickness of the second doped layer is 2 nm to 10 nm.

[0022] According to one embodiment of this application, the first passivation layer comprises aluminum oxide; and / or, the thickness of the first passivation layer is 2 nm to 10 nm.

[0023] According to one embodiment of this application, the doping concentration of the second doped layer is less than the doping concentration of the first doped layer.

[0024] According to one embodiment of this application, the first doped layer and the second doped layer have different crystal structures.

[0025] According to one embodiment of this application, it also includes:

[0026] A first anti-reflection layer is located on the side of the first passivation layer away from the silicon substrate;

[0027] A third doped layer is located on the front side of the silicon substrate, and the doping type of the third doped layer is opposite to that of the first doped layer.

[0028] A second passivation layer is located on the side of the third doped layer away from the silicon substrate;

[0029] A second antireflection layer is located on the side of the second passivation layer away from the silicon substrate;

[0030] The second electrode is in electrical contact with the third doped layer.

[0031] According to one embodiment of this application, at least one of the following conditions is met:

[0032] The first antireflective layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride;

[0033] The thickness of the first antireflective layer is 10nm to 130nm;

[0034] The doping element of the third doped layer includes boron.

[0035] The doping concentration of the third doped layer is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 ;

[0036] The sheet resistance of the third doped layer is 50Ω / sq to 400Ω / sq;

[0037] The second passivation layer comprises aluminum oxide;

[0038] The thickness of the second passivation layer is 2nm to 10nm;

[0039] The second antireflective layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride;

[0040] The thickness of the second antireflective layer is 10nm to 130nm.

[0041] Secondly, this application provides a method for preparing a solar cell, the method comprising:

[0042] A silicon substrate is provided, the silicon substrate having a front side and a back side disposed opposite to each other, the back side comprising an alternately arranged first region and a second region;

[0043] Phosphorus diffusion is performed on the back side of the silicon substrate to form a full-layer first doped layer;

[0044] A second doped layer is formed on the side of the first doped layer away from the silicon substrate, and the first doped layer, the second doped layer, and the silicon substrate have the same doping type.

[0045] Remove the second doped layer and the first doped layer from the second region;

[0046] A first passivation layer is formed on the back side. In the first region, the first passivation layer is located on the side of the second doped layer away from the silicon substrate. In the second region, the first passivation layer is in direct contact with the silicon substrate.

[0047] A first electrode is formed in the first region on the back side, and the first electrode is in electrical contact with the first doped layer.

[0048] Therefore, the solar cells prepared using this method possess all the characteristics and advantages of the solar cells described above, which will not be repeated here.

[0049] According to one embodiment of this application, the second doped layer is formed by the following steps:

[0050] A phosphorus-doped amorphous silicon layer is deposited on the side of the first doped layer away from the silicon substrate;

[0051] Under an inert atmosphere, the phosphorus-doped amorphous silicon layer is subjected to laser annealing to form a second doped layer with phosphorus doping.

[0052] A silicon oxide mask is formed in the first region, the silicon oxide mask being located on the side of the second doped layer away from the silicon substrate.

[0053] According to one embodiment of this application, at least one of the following conditions is met:

[0054] Using silane and phosphine as reactant gases, a phosphorus-doped amorphous silicon layer is deposited at 400℃~500℃.

[0055] The thickness of the phosphorus-doped amorphous silicon layer is 5 nm to 20 nm.

[0056] The thickness of the silicon oxide mask is 5nm to 10nm;

[0057] Phosphorus diffusion was performed using POCl3 as a diffusion source to form a first doped layer with a thickness of 300 nm to 500 nm;

[0058] Forming the first electrode includes: printing electrode paste; and performing laser-assisted sintering.

[0059] According to one embodiment of this application, laser annealing is performed using an ultraviolet picosecond laser or a green picosecond laser. The ultraviolet picosecond laser has a spot power of 3W to 20W, a spot diameter of 100μm to 150μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s. The green picosecond laser has a spot power of 5W to 50W, a spot diameter of 100μm to 500μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s.

[0060] According to one embodiment of this application, forming a silicon oxide mask in the first region includes: performing laser oxidation treatment on the second doped layer in the first region under an air atmosphere, so that the second doped layer is partially oxidized to form the silicon oxide mask;

[0061] Laser oxidation treatment is performed using either ultraviolet picosecond laser or green picosecond laser. The ultraviolet picosecond laser has a spot power of 3W to 20W, a spot diameter of 100μm to 150μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s. The green picosecond laser has a spot power of 5W to 50W, a spot diameter of 100μm to 500μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s.

[0062] According to one embodiment of this application, it also includes:

[0063] Using BCl3 and / or BBr3 as diffusion sources, boron diffusion is performed on the front side of the silicon substrate to form a third doped layer. The boron diffusion temperature is 900℃~1100℃.

[0064] A second passivation layer is formed on the side of the third doped layer away from the silicon substrate;

[0065] A first antireflection layer is formed on the side of the first passivation layer away from the silicon substrate;

[0066] A second antireflection layer is formed on the side of the second passivation layer away from the silicon substrate;

[0067] A second electrode is formed on the front side, and the second electrode is in electrical contact with the third doped layer.

[0068] Thirdly, this application provides a photovoltaic module, which includes the solar cell described in the first aspect above.

[0069] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0070] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0071] Figure 1 This is a schematic diagram of the structure of the solar cell provided in the embodiments of this application;

[0072] Figure 2 This is one of the partial flowcharts for preparing solar cells provided in the embodiments of this application;

[0073] Figure 3 This is a second partial flowchart of the solar cell fabrication process provided in the embodiments of this application;

[0074] Figure 4 This is the third partial flowchart of the solar cell fabrication process provided in the embodiments of this application;

[0075] Figure 5 This is the fourth partial flowchart of the solar cell fabrication process provided in the embodiments of this application.

[0076] Figure label:

[0077] 1: Silicon substrate; 2: Third doped layer; 3: First doped layer; 4: Second doped layer; 5: First passivation layer; 6: First antireflection layer; 7: Second electrode; 8: First electrode; 9: Second passivation layer; 10: Second antireflection layer; 11: First region; 12: Second region; 13: Borosilicate glass layer; 14: Phosphosilicate glass layer; 15: Phosphorus-doped amorphous silicon layer; 16: Silicon oxide mask. Detailed Implementation

[0078] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0079] In one aspect of this application, a solar cell is provided. In some embodiments of this application, reference is made to... Figure 1 The solar cell includes a silicon substrate 1, a first doped layer 3, a second doped layer 4, a first passivation layer 5, and a first electrode 8. The silicon substrate 1 and the first doped layer 3 have the same doping type. (Reference) Figure 1The silicon substrate 1 has a front side and a back side arranged opposite to each other. The back side includes an alternately arranged first region 11 and a second region 12. The front side corresponds to the light-receiving surface of the solar cell, and the back side corresponds to the back-lighting surface of the solar cell. When the solar cell is in use, the front side faces the light source, and the back side faces away from the light source. Electrodes are provided on the first region 11, and no electrodes are provided on the second region 12.

[0080] In some embodiments of this application, the doping concentration of the first doped layer 3 can be 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 For example, the doping concentration of the first doped layer can be 1×10⁻⁶. 18 cm -3 3×10 18 cm -3 5×10 18 cm -3 7×10 18 cm -3 9×10 18 cm -3 Or 1×10 19 cm -3 .

[0081] In some embodiments of this application, reference is made to Figure 1 The second doped layer 4 is located on the side of the first doped layer 3 away from the silicon substrate 1. The orthographic projection of the second doped layer 4 on the back side is located in the first region 11. The second doped layer 4 and the first doped layer 3 have the same doping type. The first passivation layer 5 is located on the back side of the silicon substrate 1. In the first region 11, the first passivation layer 5 is located on the side of the second doped layer 4 away from the silicon substrate 1. In the second region 12, the first passivation layer 5 is in direct contact with the silicon substrate 1. The first electrode 8 is in contact with the first doped layer 3. Thus, the back side of the solar cell can achieve a good passivation effect, and the solar cell has a good back contact effect.

[0082] The principle behind the good passivation and contact effect achieved on the back side of the solar cell proposed in this application is explained in detail below:

[0083] The second doped layer 4 and the first doped layer 3 form a heterojunction, which enhances the interfacial electric field strength, hinders the recombination of minority carriers (holes in this case), and improves the passivation quality of the solar cell.

[0084] For the back passivation contact structure of the first region 11 (metal region), the doping concentration of the first doped layer 3 is low, which can significantly improve the passivation effect of the metal region; in order to optimize the contact effect of the back metal region, the second doped layer 4 is used for selective contact optimization in the back metal region; on the second region 12, the first passivation layer 5 can play a passivation role and reduce the recombination rate.

[0085] In some specific embodiments of this application, the silicon substrate 1 can be an N-type silicon wafer, and the resistivity of the silicon substrate 1 can be 0.3 Ω·cm to 7 Ω·cm.

[0086] In some embodiments of this application, reference is made to Figure 1 The first doped layer 3 is in direct contact with the back side, that is, the first doped layer 3 is disposed on the surface of the silicon substrate 1, and the first doped layer 3 is located on the first region 11.

[0087] In some embodiments of this application, both the silicon substrate 1 and the first doped layer 3 are N-type doped, and the doping concentration of the first doped layer 3 is greater than that of the silicon substrate 1.

[0088] In some embodiments of this application, the doping element of the silicon substrate 1 may include phosphorus.

[0089] In some embodiments of this application, the doping element of the first doped layer 3 includes phosphorus.

[0090] In some embodiments of this application, the doping concentration of the first doped layer 3 can be 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 For example, the doping concentration of the first doped layer can be 1×10⁻⁶. 18 cm -3 3×10 18 cm -3 5×10 18 cm -3 7×10 18 cm -3 9×10 18 cm -3 Or 1×10 19 cm -3 .

[0091] In some embodiments of this application, the thickness of the first doped layer 3 is ≤500nm. In some embodiments of this application, the thickness of the first doped layer 3 can be 300nm to 500nm, for example, the thickness of the first doped layer 3 can be 300nm, 350nm, 400nm, 450nm, or 500nm. It should be noted that the thickness of the first doped layer 3 refers to the distance between the surface of the first doped layer in contact with the second doped layer 4 and the surface of the first doped layer 3 in contact with the silicon substrate 1. With the thickness of the first doped layer 3 within the above range, it can, to a certain extent, prevent the first electrode from penetrating the first doped layer, thereby preventing the first electrode from directly contacting the silicon substrate.

[0092] In some embodiments of this application, the sheet resistance of the first doped layer 3 is 70 Ω / sq to 150 Ω / sq. For example, the sheet resistance of the first doped layer 3 can be 70 Ω / sq, 80 Ω / sq, 100 Ω / sq, 110 Ω / sq, 130 Ω / sq, or 150 Ω / sq. Thus, the first doped layer has a suitable sheet resistance, which improves the passivation effect of the back metal region while achieving a certain degree of contact effect.

[0093] In some embodiments of this application, the doping element of the second doped layer 4 includes phosphorus.

[0094] In some embodiments of this application, the thickness of the second doped layer 4 is 2 nm to 10 nm. For example, the thickness of the second doped layer 4 can be 2 nm, 3 nm, 5 nm, 7 nm, 9 nm, or 10 nm. A thickness within the above range can effectively improve the back-side contact effect; furthermore, it can form a heterojunction with the first doped layer 3, hindering minority carrier recombination and thus further enhancing the passivation effect.

[0095] In some embodiments of this application, the doping concentration of the second doped layer 4 is less than the doping concentration of the first doped layer 3.

[0096] In some embodiments of this application, the doping concentration of the first doped layer 3 can be 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The doping concentration of the second doped layer 4 can be 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 For example, the doping concentration of the first doped layer can be 1 × 10⁻⁶. 18 cm -3 3×10 18 cm -3 5×10 18 cm -3 7×1018 cm -3 9×10 18 cm -3 Or 1×10 19 cm -3 The doping concentration of the second doped layer 4 can be 1×10⁻⁶. 17 cm -3 3×10 17 cm -3 5×10 17 cm -3 7×10 17 cm -3 9×10 17 cm -3 Or 1×10 18 cm -3 .

[0097] On the first region 11 of the metal region on the back side, selective contact optimization is performed by the second doped layer 4. The partitioning achieves a good passivation effect while improving the back contact. The doping concentration of the second doped layer 4 is less than that of the first doped layer 3. The second doped layer 4 and the first doped layer 3 form a heterojunction, which enhances the interfacial electric field strength and hinders minority carrier recombination, thereby improving the passivation quality.

[0098] In some embodiments of this application, the crystal structures of the second doped layer 4 and the first doped layer 3 are different.

[0099] For example, the first doped layer 3 is monocrystalline silicon, which can be formed by diffusion of a doping source on the silicon substrate 1. The second doped layer 4 can be polycrystalline silicon. Under an inert atmosphere, a doped amorphous silicon layer is first formed, and the doped amorphous silicon layer is subjected to laser annealing treatment. The silicon atoms of the amorphous silicon thin film are activated and reorganized, transforming into a polycrystalline silicon thin film, thus obtaining the second doped layer 4 of polycrystalline silicon.

[0100] On the first region 11 of the metal region on the back side, the second doped layer 4 and the first doped layer 3 have different crystal structures. The second doped layer 4 and the first doped layer 3 form a heterojunction, which enhances the interfacial electric field strength and hinders minority carrier recombination, thereby improving the passivation quality.

[0101] In some embodiments of this application, the first passivation layer 5 comprises aluminum oxide. In the second region (non-metallic region), the first passivation layer 5 is in direct contact with the back surface of the silicon substrate 1. The high concentration of negative charge in the aluminum oxide adsorbs minority carriers (holes) from the silicon substrate 1 to its surface. Due to the low electron concentration in the silicon substrate 1, the aluminum oxide adsorbs a large number of holes to the surface of the silicon substrate 1. The hole concentration on the surface of the silicon substrate 1 is much higher than the electron concentration, forming a p-type inversion layer. In the p-type inversion layer, electrons are minority carriers; reducing their concentration reduces the recombination rate, thus achieving a good passivation effect. A positively charged electric field is formed on the surface of the silicon substrate 1, and the aluminum oxide can effectively passivate the film layer where positive charges act as charge carriers.

[0102] In some embodiments of this application, the first passivation layer 5 may be an aluminum oxide layer.

[0103] In some embodiments of this application, reference is made to Figure 1 The first passivation layer 5 covers the sides of the second doped layer 4 and the sides of the first doped layer 3. Therefore, passivating the sides with the first passivation layer helps improve the overall passivation effect of the solar cell.

[0104] In some embodiments of this application, the thickness of the first passivation layer 5 is 2nm to 10nm. For example, the thickness of the first passivation layer 5 can be 2nm, 3nm, 5nm, 6nm, 7nm, 9nm, or 10nm. A thinner first passivation layer can effectively reduce the recombination loss of electrons and holes in the second region and has less impact on current transport, thereby helping to further improve the performance of the solar cell.

[0105] In some embodiments of this application, the thickness of the first passivation layer 5 can be 2 nm to 7 nm. In some embodiments of this application, the thickness of the first passivation layer 5 can be 3 nm to 6 nm.

[0106] In some embodiments of this application, the silicon substrate 1 protrudes in the first region 11 in a direction away from the silicon substrate 1 relative to the second region 12, and the silicon substrate 1 is recessed in the second region 12 in a direction closer to the silicon substrate 1 relative to the first region 11. That is, the silicon substrate 1 forms a boss in the first region 11 and a groove in the second region 12. There is a height difference between the silicon substrate 1 in the first region 11 and the second region 12, with the silicon substrate 1 in the first region 11 being thicker and the silicon substrate 1 in the second region 12 being thinner.

[0107] In some embodiments of this application, the height difference between the surface of the silicon substrate 1 in the first region 11 and the surface of the silicon substrate 1 in the second region 12 is 3 μm to 5 μm.

[0108] refer to Figure 1The distance between the surface of silicon substrate 1 in the first region 11 and the first surface is a, the distance between the surface of silicon substrate 1 in the second region 12 and the first surface is b, a > b, and the height difference between the surface of silicon substrate 1 in the first region 11 and the surface of silicon substrate 1 in the second region 12 is ab = 3μm ~ 5μm.

[0109] For example, ab can be 3μm, 3.5μm, 4μm, 4.5μm or 5μm. The back side of the silicon substrate 1 is basically undamaged, which is beneficial to further improve the passivation effect.

[0110] In some embodiments of this application, reference is made to Figure 1 The first electrode 8 is located on the first region 11, and the first electrode 8 penetrates the first passivation layer 5 and the second doped layer 4 to make electrical contact with the first doped layer 3.

[0111] In some embodiments of this application, the first electrode 8 may be a silver electrode. In some embodiments of this application, the first electrode 8 may include a back main gate and a back sub-gate.

[0112] In some embodiments of this application, reference is made to Figure 1 The solar cell may also include a first antireflection layer 6, which is located on the side of the first passivation layer 5 away from the silicon substrate 1. The first antireflection layer can reduce the reflectivity of incident light and improve the light utilization efficiency of the solar cell.

[0113] In some embodiments of this application, the first antireflective layer 6 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments of this application, the first antireflective layer 6 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In other embodiments, the first antireflective layer 6 may include multiple stacked film layers. In some embodiments of this application, the first antireflective layer 6 may include at least two of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

[0114] In some embodiments of this application, the thickness of the first antireflection layer 6 is 10 nm to 130 nm. For example, the thickness of the first antireflection layer 6 can be 10 nm, 30 nm, 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, or 130 nm. In some embodiments of this application, the thickness of the first antireflection layer 6 can be 60 nm to 130 nm.

[0115] In some embodiments of this application, reference is made to Figure 1 The solar cell may include a third doped layer 2, which is located on the front side of the silicon substrate 1. The third doped layer acts as an emitter, forming a PN junction with the N-type silicon wafer, and can generate photocurrent under illumination, thereby realizing the photoelectric conversion function of the solar cell.

[0116] In some embodiments of this application, the doping element of the third doped layer 2 includes boron.

[0117] In some embodiments of this application, the doping concentration of the third doped layer 2 is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 For example, the doping concentration of the third doped layer 2 can be 1×10⁻⁶. 18 cm -3 5×10 18 cm -3 1×10 19 cm -3 5×10 19 cm -3 Or 1×10 20 cm -3 Therefore, the third doped layer has good conductivity, which is beneficial for current transmission.

[0118] In some specific embodiments, the boron doping concentration in the third doped layer 2 is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0119] In some embodiments of this application, the sheet resistance of the third doped layer 2 is 50Ω / sq to 400Ω / sq. For example, the sheet resistance of the third doped layer 2 can be 50Ω / sq, 80Ω / sq, 100Ω / sq, 150Ω / sq, 200Ω / sq, 300Ω / sq or 400Ω / sq.

[0120] In some embodiments of this application, reference is made to Figure 1 The solar cell also includes a second passivation layer 9, which is located on the side of the third doped layer 2 away from the silicon substrate 1.

[0121] In some embodiments of this application, the second passivation layer 9 includes aluminum oxide, which can play a good role in positive passivation, thereby helping to further improve the performance of the solar cell.

[0122] In some embodiments of this application, the thickness of the second passivation layer 9 is 2nm to 10nm. For example, the thickness of the second passivation layer 9 can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, or 10nm. In some embodiments of this application, the thickness of the second passivation layer 9 can be 2nm to 7nm. In other embodiments, the thickness of the second passivation layer 9 can be 3nm to 6nm.

[0123] In some embodiments of this application, reference is made to Figure 1 The solar cell may also include a second antireflection layer 10, which is located on the side of the second passivation layer 9 away from the silicon substrate 1.

[0124] In some embodiments of this application, the second antireflective layer 10 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments of this application, the second antireflective layer 10 can be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In other embodiments, the second antireflective layer 10 can include multiple stacked film layers. In some embodiments of this application, the second antireflective layer 10 can include at least two of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

[0125] In some embodiments of this application, the thickness of the second antireflection layer 10 is 10 nm to 130 nm. For example, the thickness of the second antireflection layer 10 can be 10 nm, 30 nm, 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, or 130 nm. In some embodiments of this application, the thickness of the second antireflection layer 10 can be 60 nm to 130 nm.

[0126] In some embodiments of this application, reference is made to Figure 1 The front side of the silicon substrate 1 has a textured structure, and the third doped layer 2, the second passivation layer 9, and the second antireflection layer 10 above the silicon substrate 1 can also have textured structures.

[0127] In some embodiments of this application, reference is made to Figure 1 The solar cell also includes a second electrode 7, which is located on the front side of the silicon substrate 1 and is in electrical contact with the third doped layer 2.

[0128] In some embodiments of this application, reference is made to Figure 1 The second electrode 7 penetrates the second antireflection layer 10 and the second passivation layer 9 to contact the third doped layer 2. (Reference) Figure 1 The second electrode 7 does not penetrate the third doped layer 2.

[0129] In some embodiments of this application, the second electrode 7 may be a silver electrode. In some embodiments of this application, the second electrode 7 may include a front-side main gate and a front-side sub-gate.

[0130] In another aspect of this application, a method for fabricating a solar cell is proposed, which can fabricate the aforementioned solar cell. In some embodiments of this application, reference is made to... Figures 2 to 5 The method for preparing the aforementioned solar cell may include the following steps:

[0131] S100: Provides silicon substrate 1.

[0132] refer to Figure 2 The silicon substrate 1 has a front side and a back side disposed opposite to each other. The back side includes an alternately arranged first region 11 and a second region 12. In subsequent fabrication processes, electrodes are formed on the first region 11, while no electrodes are formed on the second region 12.

[0133] The silicon substrate 1 can be an N-type silicon wafer with a resistivity of 0.3 Ω·cm to 7 Ω·cm.

[0134] In some embodiments of this application, the silicon substrate may be a monocrystalline silicon wafer or a polycrystalline silicon wafer.

[0135] Before phosphorus diffusion, the silicon substrate 1 can be texturized on both sides, as shown in the reference. Figure 2 Alkali solution can be used for texturing to form a pyramid texture on the front and back sides of the silicon substrate 1. The pyramid size can be 0.5μm to 3μm.

[0136] In some embodiments of this application, reference is made to Figure 2 A third doped layer 2 and a borosilicate glass layer (BSG) 13 can be formed on the front side of the silicon substrate 1 by tubular diffusion. The doping types of the third doped layer 2 and the first doped layer 3 are opposite.

[0137] In some embodiments of this application, BCl3 and / or BBr3 can be used as diffusion sources to perform boron diffusion on the front side of the silicon substrate 1 to form a third doped layer 2, and the boron diffusion temperature is 900℃~1100℃.

[0138] In some embodiments of this application, BCl3 or BBr3 can be used as a diffusion source for boron diffusion, allowing boron to enter the silicon substrate and form a boron-doped silicon layer of a certain depth.

[0139] In some embodiments of this application, the boron diffusion temperature can be 900°C, 950°C, 1000°C, 1050°C, or 1100°C. At these temperatures, boron can be doped into the silicon substrate 1 to form a third doped layer 2. During the boron diffusion process, a borosilicate glass (BSG) layer 13 is formed on the surface of the first doped layer 3. The doping type of the first doped layer 3 is opposite to that of the third doped layer 2, while the doping type of the first doped layer 3 is the same as that of the silicon substrate 1.

[0140] In some embodiments of this application, the sheet resistance of the third doped layer 2 can be 50 Ω / sq to 400 Ω / sq, and the doping concentration of the third doped layer 2 can be 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0141] In some embodiments of this application, the thickness of the borosilicate glass layer 13 can be 30 nm to 150 nm.

[0142] It should be noted that during the boron diffusion process, boron also diffuses into the back and sides of the silicon substrate, forming a borosilicate glass layer on the surface. Figure 2 Not shown in the diagram. Before phosphorus diffusion, the silicon wafer can first pass through a single-sided HF chain machine to remove the borosilicate glass layer on the back and sides of the silicon substrate. Then, it passes through a tank machine for alkaline polishing of the back side to remove the edge junctions and back-side diffusion, retaining the BSG and boron junction (third doped layer) on the front side, as shown. Figure 2 As shown. Alkali polishing on the back can remove the pyramidal texture of the back, leaving the back with a flat structure, such as... Figure 2 As shown.

[0143] S200: Phosphorus diffusion is performed on the back side of the silicon substrate 1 to form a full-layer first doped layer 3.

[0144] refer to Figure 3 After alkaline polishing of the back side, phosphorus diffusion is performed on the back side of the silicon substrate 1 to form a full-layer first doped layer 3. In some embodiments of this application, phosphorus diffusion can be performed using POCl3 as a diffusion source via tubular diffusion to form a first doped layer with a thickness of 300 nm to 500 nm. Phosphorus diffusion forms a doping concentration of 1 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The first doped layer within the range is beneficial to improving the passivation effect of the back metal region.

[0145] In some embodiments of this application, the sheet resistance of the first doped layer is 70Ω / sq to 150Ω / sq.

[0146] In some embodiments of this application, reference is made to Figure 3 During phosphorus diffusion, a phosphosilicate glass (PSG) layer 14 is formed on the outermost layer. In some embodiments of this application, the thickness of the phosphosilicate glass layer 14 can be 2 nm to 10 nm.

[0147] In some embodiments of this application, reference is made to Figure 3 After phosphorus diffusion, the entire phosphosilicate glass layer 14 on the back side can be removed using a single-sided HF chain device.

[0148] S300: A second doped layer 4 is formed on the side of the first doped layer 3 away from the silicon substrate 1.

[0149] In some embodiments of this application, the second doped layer 4 is formed by the following steps:

[0150] A phosphorus-doped amorphous silicon layer 15 is deposited on the side of the first doped layer 3 away from the silicon substrate 1;

[0151] Under an inert atmosphere, the phosphorus-doped amorphous silicon layer 15 is subjected to laser annealing to form a second doped layer 4 with phosphorus doping.

[0152] A silicon oxide mask 16 is formed in the first region, and the silicon oxide mask 16 is located on the side of the second doped layer 4 away from the silicon substrate 1.

[0153] In some embodiments of this application, reference is made to Figure 3 After removing the phosphorus-silicon glass layer 14 on the back side, a phosphorus-doped amorphous silicon layer 15 can be deposited on the side of the first doped layer 3 away from the silicon substrate 1.

[0154] In some embodiments of this application, silane (SiH4) and phosphine (PH3) can be used as reactant gases to deposit a phosphorus-doped amorphous silicon layer 15 at 400°C to 500°C. In some embodiments of this application, the temperature for depositing the phosphorus-doped amorphous silicon layer can be 400°C, 430°C, 450°C, 480°C, or 500°C.

[0155] In some embodiments of this application, the flow rate of silane can be 2000 sccm to 5000 sccm. For example, the flow rate of silane can be 2000 sccm, 2500 sccm, 3000 sccm, 3500 sccm, 4000 sccm, 4500 sccm or 5000 sccm.

[0156] In some embodiments of this application, the flow rate of phosphine can be 2000 sccm to 5000 sccm. For example, the flow rate of phosphine can be 2000 sccm, 2500 sccm, 3000 sccm, 3500 sccm, 4000 sccm, 4500 sccm or 5000 sccm.

[0157] When the flow rates of silane and phosphine are within the above range, it is beneficial to form a high-quality film layer, which is beneficial to improving the overall performance of the solar cell.

[0158] In some embodiments of this application, the thickness of the phosphorus-doped amorphous silicon layer 15 is 5 nm to 20 nm. For example, the thickness of the phosphorus-doped amorphous silicon layer 15 can be 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, 18 nm or 20 nm.

[0159] In some embodiments of this application, the phosphorus-doped amorphous silicon layer 15 on the first region 11 is subjected to laser annealing under an inert atmosphere, and the amorphous silicon is converted into polycrystalline silicon to form the second doped layer 4.

[0160] In some embodiments of this application, reference is made to Figure 4Laser annealing can be performed on the phosphorus-doped amorphous silicon layer 15 on the first region 11 under an inert atmosphere to activate the phosphorus element in the phosphorus-doped amorphous silicon layer 15 on the first region 11, forming a second doped layer 4, thereby optimizing the contact and passivation effects of the metal region. In some embodiments of this application, the inert atmosphere may include at least one of nitrogen (N2) and argon (Ar).

[0161] In some embodiments of this application, ultraviolet picosecond lasers or green picosecond lasers can be used to perform laser annealing on the phosphorus-doped amorphous silicon layer in the first region.

[0162] In some embodiments of this application, an ultraviolet picosecond laser can be used to perform laser annealing on the phosphorus-doped amorphous silicon layer 15 on the first region 11. The ultraviolet picosecond laser spot power can be 3W to 20W, the spot diameter can be 100μm to 150μm, the frequency can be 500kHz to 600kHz, and the scan speed can be 40000mm / s to 70000mm / s. In some specific embodiments, the ultraviolet picosecond laser spot power can be 3W, 5W, 8W, 10W, 12W, 15W, 17W or 20W, the spot diameter can be 100μm, 110μm, 120μm, 140μm or 150μm, the frequency can be 500kHz, 510kHz, 530kHz, 550kHz, 580kHz or 600kHz, and the scan speed can be 40000mm / s, 50000mm / s, 60000mm / s or 70000mm / s.

[0163] In some embodiments of this application, a green picosecond laser can be used to perform laser annealing on the phosphorus-doped amorphous silicon layer 15 on the first region 11. The green picosecond laser spot power is 5W to 50W, the spot diameter is 100μm to 500μm, the frequency is 500kHz to 600kHz, and the scan speed is 40000mm / s to 70000mm / s. In some specific embodiments, the green picosecond laser spot power can be 5W, 10W, 20W, 30W, or 50W; the spot diameter can be 100μm, 200μm, 300μm, 400μm, or 500μm; the frequency can be 500kHz, 530kHz, 550kHz, 570kHz, or 600kHz; and the scan speed can be 40000mm / s, 50000mm / s, 60000mm / s, or 70000mm / s.

[0164] Laser annealing of the phosphorus-doped amorphous silicon layer in the first region using ultraviolet picosecond laser or green picosecond laser can activate phosphorus elements, thereby improving the passivation and contact effects of the back metal region.

[0165] In some embodiments of this application, a silicon oxide mask 16 is formed on the first region 11, as shown in the reference. Figure 4 The silicon oxide mask 16 is located on the side of the second doped layer 4 away from the silicon substrate 1. During the subsequent alkaline etching process, the silicon oxide mask can play a certain protective role, preventing the second doped layer from being etched.

[0166] In some embodiments of this application, the thickness of the silicon oxide mask 16 can be 5 nm to 10 nm. For example, the thickness of the silicon oxide mask 16 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. During the subsequent alkaline etching process, the mask of the above thickness can play a better protective role and more effectively prevent the second doped layer from being etched by the alkaline solution.

[0167] In some embodiments of this application, a silicon oxide mask 16 may be deposited on the side of the second doped layer 4 away from the silicon substrate 1.

[0168] In some other embodiments of this application, the second doped layer may be partially oxidized to form a silicon oxide mask. In some specific embodiments of this application, reference is made to... Figure 4 Forming a silicon oxide mask 16 on the first region 11 includes: performing laser oxidation on the second doped layer 4 on the first region 11 in an air atmosphere, so that the second doped layer 4 is partially oxidized to form a silicon oxide mask 16.

[0169] In some embodiments of this application, ultraviolet picosecond laser or green picosecond laser can be used to perform laser oxidation treatment on the second doped layer 4 on the first region 11.

[0170] In some embodiments of this application, an ultraviolet picosecond laser can be used to perform laser oxidation treatment on the second doped layer 4 on the first region 11. The ultraviolet picosecond laser spot power can be 3W to 20W, the spot diameter can be 100μm to 150μm, the frequency can be 500kHz to 600kHz, and the scan rate can be 40000mm / s to 70000mm / s. In some specific embodiments, the ultraviolet picosecond laser spot power can be 3W, 5W, 8W, 10W, 12W, 15W, 17W, or 20W, the spot diameter can be 100μm, 110μm, 120μm, 140μm, or 150μm, the frequency can be 500kHz, 510kHz, 530kHz, 550kHz, 580kHz, or 600kHz, and the scan rate can be 40000mm / s, 50000mm / s, 60000mm / s, or 70000mm / s.

[0171] In some embodiments of this application, a green picosecond laser can be used to perform laser oxidation treatment on the second doped layer 4 on the first region 11. The green picosecond laser spot power is 5W to 50W, the spot diameter is 100μm to 500μm, the frequency is 500kHz to 600kHz, and the scan rate is 40000mm / s to 70000mm / s. In some specific embodiments, the green picosecond laser spot power can be 5W, 10W, 20W, 30W, or 50W; the spot diameter can be 100μm, 200μm, 300μm, 400μm, or 500μm; the frequency can be 500kHz, 530kHz, 550kHz, 570kHz, or 600kHz; and the scan rate can be 40000mm / s, 50000mm / s, 60000mm / s, or 70000mm / s.

[0172] Laser oxidation of the second doped layer in the first region can be performed using ultraviolet picosecond laser or green picosecond laser. This process can partially oxidize the second doped layer to form a silicon oxide mask. The silicon oxide mask can then protect the second doped layer from being etched by the alkaline solution during the subsequent alkaline etching process.

[0173] S400: Remove the second doped layer 4 and the first doped layer 3 on the second region 12.

[0174] In some embodiments of this application, reference is made to Figure 4 Alkali etching can be performed using a tank-type equipment to remove the second doped layer 4 and the first doped layer 3 on the second region 12. During the etching process, the front and edge plating will also be removed.

[0175] In some embodiments of this application, reference is made to Figure 4 During alkaline etching, a portion of the silicon substrate 1 on the second region 12 can be etched away, creating a height difference between the silicon substrate 1 on the second region 12 and the first region 11. This allows for the complete removal of the first doped layer on the second region, thereby improving the passivation effect of the second region.

[0176] In some embodiments of this application, during alkaline etching, the silicon oxide mask 16 on the first region 11 can play a certain protective role, and the first doped layer 3 and the second doped layer 4 on the first region 11 are retained.

[0177] In some embodiments of this application, the alkaline etching time can be 300s to 500s, the temperature can be 50℃ to 90℃, and the volume concentration of alkali (sodium hydroxide and / or potassium hydroxide) in the etching solution used for alkaline etching can be 0.5% to 2%, and the volume concentration of additives can be 0.5% to 1%.

[0178] In some embodiments of this application, acid etching is performed to remove the silicon oxide mask 16 on the first region 11, as shown in the reference. Figure 4 After alkaline etching, acid etching can be performed to remove the silicon oxide mask 16 on the first region 11. In some embodiments of this application, an HF solution can be used to remove the silicon oxide mask 16 on the first region 11 and the borosilicate glass layer 13 on the front side of the silicon substrate 1.

[0179] S500: A first passivation layer 5 is formed on the back side.

[0180] In some embodiments of this application, the first passivation layer 5 may include aluminum oxide. In some specific embodiments, the first passivation layer 5 may be an aluminum oxide layer.

[0181] In some embodiments of this application, in the first region 11, the first passivation layer 5 is located on the side of the second doped layer 4 away from the silicon substrate 1, and in the second region 12, the first passivation layer 5 is in direct contact with the silicon substrate 1.

[0182] In some embodiments of this application, reference is made to Figure 5 The method for preparing solar cells also includes forming a second passivation layer 9 on the side of the third doped layer 2 away from the silicon substrate 1.

[0183] In some embodiments of this application, an aluminum oxide passivation layer can be deposited on both the front and back sides using ALD (atomic layer deposition) single insertion. The thickness of the first passivation layer and the thickness of the second passivation layer can each be independently 2 nm to 10 nm.

[0184] In some embodiments of this application, reference is made to Figure 5 The method for fabricating a solar cell further includes: forming a first antireflection layer 6 on the side of the first passivation layer 5 away from the silicon substrate 1; and forming a second antireflection layer 10 on the side of the second passivation layer 9 away from the silicon substrate 1. In some specific embodiments, antireflection layers can be deposited on the front and back sides respectively using PECVD (plasma-enhanced chemical vapor deposition), and the antireflection layers can be one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide.

[0185] S600: A first electrode 8 is formed in the first region 11 on the back side.

[0186] In some embodiments of this application, forming the first electrode 8 includes the following steps: printing electrode paste; and performing laser-assisted sintering. Laser-assisted sintering can further improve the back-side contact effect, thereby further enhancing the performance of the solar cell.

[0187] In some embodiments of this application, the first electrode 8 is in electrical contact with the first doped layer 3.

[0188] In some embodiments of this application, silver electrode paste, including a back main grid and a back sub-grid, can be printed on the back side by screen printing, and then laser-assisted sintering technology can be used to sinter the paste to optimize the back contact effect.

[0189] In some embodiments of this application, reference is made to Figure 5 The method for fabricating a solar cell further includes forming a second electrode 7. In some embodiments of this application, the second electrode 7 is in electrical contact with the third doped layer 2.

[0190] In some embodiments of this application, forming the second electrode 7 may include the following steps: printing electrode paste; and performing laser-assisted sintering. In some embodiments of this application, silver electrode paste, including the front main grid and the front sub-grid, can be printed on the front side by screen printing, and then the paste can be sintered using laser-assisted sintering technology.

[0191] In some embodiments of this application, a 1064nm laser or a 532nm green light can be used to perform laser-assisted sintering of the slurry. In some embodiments of this application, the laser width can be 100μm. In other embodiments, the laser width can be 1mm to 2mm.

[0192] After the first and second electrodes are formed, the solar cells can be tested, sorted, and selected.

[0193] The method proposed in this application for fabricating solar cells involves directly diffusing phosphorus onto a silicon substrate to form a first doped layer. This avoids parasitic absorption caused by growing a separate polycrystalline silicon layer, optimizing the back-side passivation effect. The low doping concentration of the first doped layer effectively improves the passivation effect of the back-side metal region. Forming a second doped layer on the side of the first doped layer away from the silicon substrate improves the back-side contact effect. Furthermore, the second doped layer can form a heterojunction with the low-doped first doped layer, simultaneously enhancing the interfacial electric field strength and hindering minority carrier recombination, thus improving passivation quality. The non-metallic region on the back side is directly passivated using a film containing alumina. Alumina adsorbs minority carriers (holes) from the silicon substrate to the surface. The hole concentration adsorbed on the surface by alumina is much higher than the electron concentration on the silicon substrate surface, forming a p-type inversion layer. Since electrons are minority carriers, the reduced concentration lowers the recombination rate, resulting in better passivation. Furthermore, laser-assisted sintering of the electrode paste during the back-side electrode fabrication process further improves the back-side contact effect.

[0194] In another aspect, this application proposes a photovoltaic module. In some embodiments of this application, the photovoltaic module may include the solar cells described above. Thus, the photovoltaic module possesses all the features and advantages of the solar cells described above.

[0195] In some embodiments of this application, a photovoltaic module may include multiple solar cells as described above, and the multiple solar cells may be connected in series or in parallel to form a photovoltaic module.

[0196] The present application will be described below through specific embodiments. Those skilled in the art will understand that the specific embodiments below are merely illustrative and do not limit the scope of the present application in any way. Furthermore, in the following embodiments, unless otherwise specified, the materials and equipment used are commercially available. If specific processing conditions and methods are not explicitly described in the later embodiments, conditions and methods known in the art can be used for processing.

[0197] Example 1

[0198] 1. Double-sided texturing: N-type silicon wafer with a resistivity of 1Ω·cm; alkaline texturing is used to form a pyramid texture on the front and back sides of the silicon wafer, with a pyramid size of 1μm.

[0199] 2. Preparation of P+ emitter (third doped layer): Boron diffusion was performed using BCl3 as the diffusion source via tubular diffusion at a controlled temperature of 950℃. The sheet resistance of the third doped layer was 300 Ω / sq, the BSG thickness was 100 nm, and the doping concentration was 5 × 10⁻⁶. 19 cm -3 .

[0200] 3. HF chain + tank alkaline polishing: The silicon wafer first passes through a single-sided HF chain machine to remove the BSG on the back and sides. Then, it passes through a tank machine to perform alkaline polishing on the back to remove the edge junctions and back wrapping, while retaining the BSG and boron junctions on the front.

[0201] 4. Preparation of the back N+ layer (first doped layer): Phosphorus diffusion was performed using POCl3 as the diffusion source via tubular diffusion to form the first doped layer with a doping depth of 100 nm and a low doping concentration of 5 × 10⁻⁶ nm. 18 cm -3 The sheet resistance is 100Ω / sq, and the outermost layer is a PSG mask with a thickness of 5nm.

[0202] 5. HF chain type: Remove the PSG mask from the entire back side and the PSG coating around the perimeter.

[0203] 6. Preparation of phosphorus-doped amorphous silicon layer on the back side: Phosphorus-doped amorphous silicon layer with a thickness of 10 nm was prepared by PECVD method, with SiH4 and PH3 as the reaction gases and the temperature of 450℃.

[0204] 7. Laser annealing and silicon oxide mask fabrication: The phosphorus-doped amorphous silicon layer in the metal region (first region) is annealed and activated using a laser to form a second doped layer. Then, the second doped layer is laser-oxidized to prepare a 5nm thick silicon oxide mask, which provides some protection during subsequent alkaline etching. The conditions for laser annealing and laser oxidation are as follows: green picosecond laser spot power of 10W, spot diameter of 100μm, frequency of 500kHz, and scan rate of 45000mm / s.

[0205] 8. Alkaline etching in a tank + HF: Alkaline etching removes the phosphorus-doped amorphous silicon layer and the underlying first doped layer from the front, edge-coated, and back non-metallic areas (second region). HF solution is used to remove the silicon oxide mask and BSG from the front of the silicon substrate in the metal region. The first doped layer and the upper second doped layer in the metal region are retained, improving the passivation and contact effects of the metal region. The alkaline tank treatment time is 400 s, the temperature is 60℃, and the volume concentration of alkali in the etching solution is 1.5%, and the volume concentration of additives is 1%.

[0206] 9. Preparation of front and back passivation layers: Using ALD single insertion, an aluminum oxide passivation layer with a thickness of 3nm is deposited on the front and back sides respectively.

[0207] 10. Preparation of front and back antireflection layers: Antireflection layers were deposited on the front and back sides using PECVD. The material of the antireflection layers was silicon oxynitride, and the thickness was 80 nm.

[0208] 11. Screen-printed metal electrodes: Metal electrode paste is printed on the front and back sides using screen printing, including the main and sub-gates on the front and back sides.

[0209] 12. Laser-assisted sintering technology: Laser-assisted sintering technology is used to optimize the sintering of electrode slurry on the front and back of the battery. The laser wavelength is 1064nm and the laser width is 100μm.

[0210] 13. Testing and sorting: Testing, sorting, and selecting the solar cells.

[0211] Comparative Example 1

[0212] Unlike Example 1, no second doped layer was prepared in Comparative Example 1. That is, no second doped layer was formed in the metal region (first region) in Comparative Example 1, and the alumina passivation layer in the metal region was in direct contact with the first doped layer. The other steps and parameters in Comparative Example 1 were consistent with those in Example 1.

[0213] The performance of the solar cells prepared in the test examples and comparative examples was tested. The composite current density of the sample in Example 1 was 5 fA / cm². 2 ~6fA / cm 2 Within the range, the contact resistivity is 5 mΩ / cm2 ~10mΩ / cm 2 Within the range; the composite current density of the sample in Comparative Example 1 is 15 fA / cm. 2 ~20fA / cm 2 Within the range, the contact resistivity is 80 mΩ / cm 2 ~100mΩ / cm 2 Within the specified range. Therefore, it can be seen that the solar cell proposed in this application has excellent back-side passivation and contact performance.

[0214] In summary, the method proposed in this application for fabricating solar cells has the following advantages: In this application, an N-poly layer (N-type doped polycrystalline silicon layer) does not need to be grown on the back side of the silicon oxide tunneling oxide layer, thus eliminating parasitic absorption on the back side caused by the growth of the polycrystalline silicon layer and improving the efficiency of the solar cell. A low-doped first doped layer in the metal region provides good passivation, and the second doped layer can selectively optimize the passivation and contact effects of the metal region. A passivation layer containing aluminum oxide is used for the non-metallic region on the back side, achieving good passivation of the non-metallic region. Direct phosphorus diffusion onto the silicon substrate forms a low-doped first doped layer, followed by deposition of a phosphorus-doped amorphous silicon layer and laser activation treatment to form the second doped layer. This process is simple, produces high-quality films, and helps improve yield and reduce production costs.

[0215] In the description of this application, the terms "front", "back", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and do not require this application to be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0216] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples, without contradiction. Additionally, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0217] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A solar cell, characterized in that, include: A silicon substrate having a front side and a back side disposed opposite to each other, the back side comprising an alternately arranged first region and a second region; A first doped layer, wherein the first doped layer has the same doping type as the silicon substrate, and the orthographic projection of the first doped layer on the back side is located in the first region; A second doped layer is located on the side of the first doped layer away from the silicon substrate, and the doping type of the second doped layer is the same as that of the silicon substrate; A first passivation layer is located on the side of the second doped layer away from the silicon substrate in the first region, and in the second region, the first passivation layer is in direct contact with the silicon substrate. The first electrode is in electrical contact with the first doped layer.

2. The solar cell according to claim 1, characterized in that, The silicon substrate protrudes in the first region in a direction away from the silicon substrate relative to the second region, and / or the silicon substrate is recessed in the second region in a direction closer to the silicon substrate relative to the first region.

3. The solar cell according to claim 2, characterized in that, The height difference between the surface of the silicon substrate in the first region and the surface of the silicon substrate in the second region is 3 μm to 5 μm.

4. The solar cell according to claim 1, characterized in that, The first passivation layer covers the second doped layer and the sides of the first doped layer.

5. The solar cell according to claim 1, characterized in that, The first doped layer satisfies at least one of the following conditions: The thickness of the first doped layer is 300 nm to 500 nm; The sheet resistance of the first doped layer is 70Ω / sq to 150Ω / sq; The doping element of the first doped layer includes phosphorus. The doping concentration of the first doped layer is 1×10 18 cm -3 ~1×10 19 cm -3 .

6. The solar cell according to claim 1, characterized in that, The second doped layer includes phosphorus as a doping element; and / or the thickness of the second doped layer is 2 nm to 10 nm.

7. The solar cell according to claim 1, characterized in that, The first passivation layer comprises aluminum oxide; and / or the thickness of the first passivation layer is 2 nm to 10 nm.

8. The solar cell according to claim 1, characterized in that, The doping concentration of the second doped layer is less than that of the first doped layer.

9. The solar cell according to claim 1, characterized in that, The first doped layer and the second doped layer have different crystal structures.

10. The solar cell according to any one of claims 1-9, characterized in that, Also includes: A first anti-reflection layer is located on the side of the first passivation layer away from the silicon substrate; A third doped layer is located on the front side of the silicon substrate, and the doping type of the third doped layer is opposite to that of the first doped layer. A second passivation layer is located on the side of the third doped layer away from the silicon substrate; A second antireflection layer is located on the side of the second passivation layer away from the silicon substrate; The second electrode is in electrical contact with the third doped layer.

11. The solar cell according to claim 10, characterized in that, At least one of the following conditions must be met: The first antireflective layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride; The thickness of the first antireflective layer is 10nm to 130nm; The doping element of the third doped layer includes boron. The doping concentration of the third doped layer is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 ; The sheet resistance of the third doped layer is 50Ω / sq to 400Ω / sq; The second passivation layer comprises aluminum oxide; The thickness of the second passivation layer is 2nm to 10nm; The second antireflective layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride; The thickness of the second antireflective layer is 10nm to 130nm.

12. A method for preparing a solar cell, characterized in that, include: A silicon substrate is provided, the silicon substrate having a front side and a back side disposed opposite to each other, the back side comprising an alternately arranged first region and a second region; Phosphorus diffusion is performed on the back side of the silicon substrate to form a full-layer first doped layer; A second doped layer is formed on the side of the first doped layer away from the silicon substrate, and the first doped layer, the second doped layer, and the silicon substrate have the same doping type. Remove the second doped layer and the first doped layer from the second region; A first passivation layer is formed on the back side. In the first region, the first passivation layer is located on the side of the second doped layer away from the silicon substrate. In the second region, the first passivation layer is in direct contact with the silicon substrate. A first electrode is formed in the first region on the back side, and the first electrode is in electrical contact with the first doped layer.

13. The method according to claim 12, characterized in that, The second doped layer is formed by the following steps: A phosphorus-doped amorphous silicon layer is deposited on the side of the first doped layer away from the silicon substrate; Under an inert atmosphere, the phosphorus-doped amorphous silicon layer is subjected to laser annealing to form a second doped layer with phosphorus doping. A silicon oxide mask is formed in the first region, the silicon oxide mask being located on the side of the second doped layer away from the silicon substrate.

14. The method according to claim 13, characterized in that, At least one of the following conditions must be met: Using silane and phosphine as reactant gases, a phosphorus-doped amorphous silicon layer is deposited at 400℃~500℃. The thickness of the phosphorus-doped amorphous silicon layer is 5 nm to 20 nm. The thickness of the silicon oxide mask is 5nm to 10nm; Phosphorus diffusion was performed using POCl3 as a diffusion source to form a first doped layer with a thickness of 300 nm to 500 nm; Forming the first electrode includes: printing electrode paste; and performing laser-assisted sintering.

15. The method according to claim 13, characterized in that, Laser annealing is performed using either ultraviolet picosecond laser or green picosecond laser. The ultraviolet picosecond laser has a spot power of 3W to 20W, a spot diameter of 100μm to 150μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s. The green picosecond laser has a spot power of 5W to 50W, a spot diameter of 100μm to 500μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s.

16. The method according to claim 13, characterized in that, Forming a silicon oxide mask in the first region includes: performing laser oxidation treatment on the second doped layer in the first region under an air atmosphere, so that the second doped layer is partially oxidized to form the silicon oxide mask; Laser oxidation treatment is performed using either ultraviolet picosecond laser or green picosecond laser. The ultraviolet picosecond laser has a spot power of 3W to 20W, a spot diameter of 100μm to 150μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s. The green picosecond laser has a spot power of 5W to 50W, a spot diameter of 100μm to 500μm, a frequency of 500kHz to 600kHz, and a scan speed of 40000mm / s to 70000mm / s.

17. The method according to any one of claims 12-16, characterized in that, Also includes: Using BCl3 and / or BBr3 as diffusion sources, boron diffusion is performed on the front side of the silicon substrate to form a third doped layer. The boron diffusion temperature is 900℃~1100℃. A second passivation layer is formed on the side of the third doped layer away from the silicon substrate; A first antireflection layer is formed on the side of the first passivation layer away from the silicon substrate; A second antireflection layer is formed on the side of the second passivation layer away from the silicon substrate; A second electrode is formed on the front side, and the second electrode is in electrical contact with the third doped layer.

18. A photovoltaic module, characterized in that, The solar cell includes any one of claims 1-11.

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