Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method of the solar cell. The solar cell comprises a semiconductor substrate, a first conductive structure, a second conductive structure and a controllable resistance insulating layer. The semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, and the first surface comprises first regions and second regions which are alternately arranged; the first conductive structure is at least arranged in the first region; the second conductive structure is at least arranged in the second region; the conductive type of the first conductive structure is opposite to that of the second conductive structure; the first conductive structure and the second conductive structure have an overlapping region along a direction vertical to the first surface; the controllable resistance insulating layer is located in the overlapping region and arranged between the first conductive structure and the second conductive structure. According to the solar cell, micro electric leakage can be realized through the controllable resistance insulating layer, so that the hot spot effect of the solar cell is relieved, the overall power generation efficiency of the solar cell is relatively stable, and the controllable resistance insulating layer is relatively convenient to process and prepare and relatively low in processing cost.

Description

Technical Field

[0001] This application relates to the technical field of photovoltaic modules, and in particular to solar cells and methods for preparing solar cells. Background Technology

[0002] Back-contact batteries, with their electrodes located on the back and no metal obstruction on the front, allow 100% light penetration into the active layer, significantly increasing short-circuit current and photoelectric conversion efficiency, leading to their widespread use and mass production. However, because the current is concentrated on the back, excessive current can easily trigger hotspots. Hotspots increase the battery's internal resistance, impede current flow, and consequently reduce overall power generation efficiency, accelerate component aging, and increase reliability risks such as fires, significantly increasing operating and maintenance costs. Related technologies often employ laser grooving to deposit composite layers or embedding micron-sized copper foil to conduct current, making the manufacturing process complex, time-consuming, and costly. Summary of the Invention

[0003] Therefore, it is necessary to provide a solar cell that addresses the problem of time-consuming, complex, and costly processing of back-contact solar cells to reduce hot spot effects.

[0004] A solar cell comprising:

[0005] A semiconductor substrate includes a first surface and a second surface disposed opposite to each other, the first surface including alternating first regions and second regions;

[0006] A first conductive structure is provided at least in the first region;

[0007] A second conductive structure is provided at least in the second region; the conductivity type of the first conductive structure is opposite to that of the second conductive structure; the first conductive structure and the second conductive structure have an overlapping area along a direction perpendicular to the first surface;

[0008] A controllable resistance insulating layer is located in the overlapping area and disposed between the first conductive structure and the second conductive structure.

[0009] In some embodiments, the controllable resistance insulating layer is a doped semiconductor layer; the doping element of the doped semiconductor layer is boron or phosphorus, and the concentration of the doping element is 5E18-1E21 at / cm³. 3 .

[0010] In some embodiments, in the overlapping region, along a direction perpendicular to the first surface, the second conductive structure, the controllable resistance insulating layer, and the first conductive structure are sequentially stacked, and the first conductive structure is disposed on the side close to the semiconductor substrate.

[0011] The side of the controllable resistance insulating layer closest to the second conductive structure is flush with the end face of the first conductive structure closest to the second conductive structure.

[0012] In some embodiments, in the overlapping region, along a direction perpendicular to the first surface, the second conductive structure, the controllable resistance insulating layer, and the first conductive structure are sequentially stacked, and the first conductive structure is disposed on the side close to the semiconductor substrate.

[0013] The side of the controllable resistance insulating layer closest to the first conductive structure is flush with the end face of the second conductive structure closest to the first conductive structure.

[0014] In some embodiments, the controllable resistance insulating layer, along its thickness h1 perpendicular to the first surface, satisfies the following condition:

[0015] 5nm≤h1≤15nm.

[0016] In some embodiments, the ratio of the width d1 of the controllable resistive insulating layer along the first direction to the width d2 of the first region along the first direction is between 0.05 and 0.2; the first direction is the direction from the first region to the second region.

[0017] In some embodiments, the solar cell includes a first transparent conductive layer;

[0018] The first transparent conductive layer is disposed on the side of the first conductive structure opposite to the semiconductor substrate; and there is a first gap between the orthographic projection of the first transparent conductive layer and the orthographic projection of the controllable resistance insulating layer.

[0019] In some embodiments, the solar cell includes a second transparent conductive layer;

[0020] The second transparent conductive layer is disposed on the side of the second conductive structure opposite to the semiconductor substrate; and there is a second gap between the orthographic projection of the second transparent conductive layer and the orthographic projection of the controllable resistance insulating layer.

[0021] In some embodiments, the first conductive structure includes a first passivation layer and a first doped semiconductor layer stacked together; and the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate.

[0022] In some embodiments, the second conductive structure includes a second passivation layer and a second doped semiconductor layer stacked together; and the second passivation layer is disposed on the side of the second doped semiconductor layer close to the semiconductor substrate.

[0023] In some embodiments, the thickness h1 of the controllable resistive insulating layer perpendicular to the first surface and the thickness h2 of the second passivation layer perpendicular to the first surface satisfy the following condition:

[0024] 0.5h2≤h1≤h2.

[0025] In some embodiments, the second passivation layer includes a first sublayer, a second sublayer, and a third sublayer connected in sequence;

[0026] The first sublayer is in contact with the semiconductor substrate;

[0027] The second sublayer extends along a first direction, which intersects the extension direction of the first surface;

[0028] The third sub-layer is in contact with the side of the controllable resistance insulating layer that is away from the first conductive structure.

[0029] In some embodiments, the controllable resistance insulating layer is in contact with the second sublayer on the side near the second conductive structure.

[0030] In some embodiments, the controllable resistance insulating layer has a continuous structure.

[0031] This application also provides a method for preparing a solar cell, comprising:

[0032] Forming a semiconductor substrate;

[0033] A first conductive structure is formed in a first region on a first surface of the semiconductor substrate;

[0034] A controllable resistance insulating layer is formed in a predetermined region on the side of the first conductive structure away from the semiconductor substrate;

[0035] A second conductive structure is formed on the side of the controllable resistance insulating layer opposite to the first conductive structure and in the second region of the first surface;

[0036] The preset area is the overlapping area of ​​the first conductive structure and the second conductive structure, and the second area and the first area are arranged alternately.

[0037] In some embodiments, the step of forming a controllable resistance insulating layer in a predetermined region on the side of the first conductive structure opposite to the semiconductor substrate specifically includes:

[0038] Forming a crystalline silicon substrate;

[0039] Boron is doped onto the crystalline silicon substrate to form the controllable resistance insulating layer, and the boron doping current is greater than 0 and less than 2000 sccm. The crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon, or nanocrystalline silicon; or

[0040] The controllable resistance insulating layer is formed by doping phosphorus on the crystalline silicon substrate, and the phosphorus doping flow rate is greater than 0 and less than 2000 sccm. The crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon or nanocrystalline silicon.

[0041] The aforementioned solar cell has a controllable resistance insulating layer in the overlapping area of ​​the first conductive structure and the second conductive structure. This controllable resistance insulating layer itself can achieve micro-leakage, thereby alleviating the hot spot effect of the solar cell and making the overall power generation efficiency of the solar cell more stable. Furthermore, the controllable resistance insulating layer is easy to process and prepare, which reduces the time required for the preparation process and reduces the cost. Attached Figure Description

[0042] Figure 1 The diagram shows the structure of a solar cell provided in some embodiments of this application.

[0043] Figure 2 for Figure 1 A magnified view of a portion at point A shown.

[0044] Figure 3 For preparation Figure 1 The diagram shows the first state of the solar cell.

[0045] Figure 4 For preparation Figure 1 The diagram shows the second state of the solar cell.

[0046] Figure 5 For preparation Figure 1 The diagram shows the third state of the solar cell.

[0047] Figure 6 For preparation Figure 1 The diagram shows the fourth state of the solar cell.

[0048] Figure 7 For preparation Figure 1 The diagram shows the fifth state of the solar cell.

[0049] Figure 8 For preparation Figure 1 The diagram shows the sixth state of the solar cell.

[0050] Figure 9 For preparation Figure 1 The diagram shows the seventh state of the solar cell.

[0051] Figure 10 For preparation Figure 1 The diagram shows the eighth state of the solar cell.

[0052] Figure 11 A schematic diagram of a method for fabricating a solar cell according to some embodiments of this application is shown.

[0053] Reference numerals: 100-Semiconductor substrate; 110-First surface; 111-First region; 112-Second region; 120-Second surface; 200-First conductive structure; 210-First passivation layer; 220-First doped semiconductor layer; 300-Second conductive structure; 310-Second passivation layer; 311-First sublayer; 312-Second sublayer; 313-Third sublayer; 320-Second doped semiconductor layer; 400-Controllable resistance insulating layer; 410-Mask; 500-First transparent conductive layer; 600-Second transparent conductive layer; 710-First spacing; 720-Second spacing; 810-First electrode; 820-Second electrode; 910-Third passivation layer; 920-Fourth passivation layer. Detailed Implementation

[0054] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0055] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0056] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0057] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0058] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0059] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0060] See Figure 1 as well as Figure 2 , Figure 1 A schematic diagram of the structure of a solar cell provided in some embodiments of this application is shown. Figure 2 It shows Figure 1 A magnified view of a portion at point A shown.

[0061] The solar cell provided in some embodiments of this application includes a semiconductor substrate 100, a first conductive structure 200, a second conductive structure 300, and a controllable resistance insulating layer 400. The semiconductor substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other. The first surface 110 includes alternating first regions 111 and second regions 112. The first conductive structure 200 is at least disposed in the first region 111; the second conductive structure 300 is at least disposed in the second region 112; the conductivity type of the first conductive structure 200 is opposite to that of the second conductive structure 300; the first conductive structure 200 and the second conductive structure 300 have an overlapping region along a direction perpendicular to the first surface 110; the controllable resistance insulating layer 400 is located in the overlapping region and disposed between the first conductive structure 200 and the second conductive structure 300; exemplarily, the direction perpendicular to the first surface 110 is... Figure 1 and Figure 2 The yy' direction in the middle.

[0062] The aforementioned solar cell has a controllable resistance insulating layer 400 in the overlapping area of ​​the first conductive structure 200 and the second conductive structure 300. This controllable resistance insulating layer 400 itself can achieve micro-leakage, thereby alleviating the hot spot effect of the solar cell and making the overall power generation efficiency of the solar cell more stable. Furthermore, the controllable resistance insulating layer 400 is relatively easy to process and prepare, which reduces the time required for the preparation process and has a lower cost.

[0063] The solar cells provided in this application can alleviate the problem of hot spot effect in solar cell modules with low cost by relying on existing process routes.

[0064] In some embodiments, the controllable resistance insulating layer 400 is a doped semiconductor layer; the doping element is boron or phosphorus, and the concentration of the doping element is 5E18-1E21 at / cm³. 3 When region 111 is an N-region and region 112 is a P-region, the dopant element can be boron. When region 111 is a P-region and region 112 is an N-region, the dopant element can be phosphorus. This is achieved by limiting the concentration of the dopant element to 5E18-1E21 at / cm³. 3 Within a certain range, the doping concentration is appropriately balanced, neither too high (resulting in a large short-circuit current between the first conductive structure 200 and the second conductive structure 300) nor too low (resulting in a weak micro-leakage effect). This doping concentration range allows for the formation of a weak PN junction between the controllable resistance insulating layer 400 and the first region 111, achieving the micro-leakage effect. This range also reduces inter-cell and batch variations, ensuring that the resistance of the controllable resistance insulating layer 400 fluctuates slightly within a certain range, which is beneficial for processing and fabrication in actual production lines.

[0065] In some embodiments, the concentration of the dopant element is 5E18 at / cm³. 3 In some of these embodiments, the concentration of the dopant element is 1E21 at / cm³. 3 In some embodiments, the concentration of the dopant element is 1E20 at / cm³. 3 .

[0066] Please see Figure 1 and Figure 2 In some embodiments, in the overlapping area, along a direction perpendicular to the first surface 110, the second conductive structure 300, the controllable resistance insulating layer 400, and the first conductive structure 200 are sequentially stacked, and the first conductive structure 200 is disposed on the side close to the semiconductor substrate 100; the side of the controllable resistance insulating layer 400 close to the second conductive structure 300 is flush with the end face of the first conductive structure 200 close to the second conductive structure 300.

[0067] By aligning the side of the controllable resistance insulating layer 400 near the second conductive structure 300 with the end face of the first conductive structure 200 near the second conductive structure 300, that is, by making the two sides flush... Figure 1 and Figure 2 The right edges in the xx' direction coincide, which makes the controllable resistance insulating layer 400 easier to process and prepare. It can be patterned using laser equipment, which reduces the processing time.

[0068] Please see Figure 1 and Figure 2 In some embodiments, in the overlapping area, along a direction perpendicular to the first surface 110, the second conductive structure 300, the controllable resistance insulating layer 400, and the first conductive structure 200 are sequentially stacked, and the first conductive structure 200 is disposed on the side close to the semiconductor substrate 100; the side of the controllable resistance insulating layer 400 close to the first conductive structure 200 is flush with the end face of the second conductive structure 300 close to the first conductive structure 200.

[0069] By aligning the side of the controllable resistance insulating layer 400 near the first conductive structure 200 with the end face of the second conductive structure 300 near the first conductive structure 200, that is, by making the two sides flush... Figure 1 and Figure 2 The left edges in the xx' direction coincide, which makes the controllable resistance insulating layer 400 easier to process and prepare. It can be patterned using laser equipment, which reduces the processing time.

[0070] Please see Figure 2In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 along the perpendicular surface 110 satisfies the condition: 5nm ≤ h1 ≤ 15nm. By limiting the thickness h1 of the controllable resistance insulating layer 400 along the perpendicular surface 110 to a range greater than or equal to 5nm and less than or equal to 15nm, the thickness of the controllable resistance insulating layer 400 is made more reasonable. It can achieve a micro-leakage effect when the battery experiences hot spot effect, at least partially conducting the first conductive structure 200 and the second conductive structure 300, thereby reducing the current transmitted by the battery, alleviating the hot spot effect, and the processing and preparation process is also more convenient.

[0071] In some embodiments, the thickness h1 of the controllable resistor insulating layer 400 perpendicular to the first surface 110 is 5 nm, ensuring that the thickness of the controllable resistor insulating layer 400 is not too thin. This effectively ensures that the first conductive structure 200 and the second conductive structure 300 are in an insulating state during normal battery operation, and also facilitates processing, preventing complete etching away during subsequent mask removal. In some embodiments, the thickness h1 of the controllable resistor insulating layer 400 perpendicular to the first surface 110 is 15 nm, ensuring that the thickness of the controllable resistor insulating layer 400 is not too thick. This allows the controllable resistor insulating layer 400 to achieve a micro-leakage effect when the battery experiences a hot spot effect, at least partially conducting the first conductive structure 200 and the second conductive structure 300 to alleviate the hot spot effect. It also prevents the resistance of the controllable resistor insulating layer 400 from being too high, thus avoiding impacting the battery's series resistance and photoelectric conversion efficiency. In some embodiments, the thickness h1 of the controllable resistor insulating layer 400 perpendicular to the first surface 110 is 10 nm. Of course, in some embodiments, the thickness h1 of the controllable resistance insulating layer 400 along the first surface 110 can also be 6nm, 8nm, 12nm, 14nm, etc.

[0072] Please see Figure 1 and combined Figure 2 In some embodiments, the ratio of the width d1 of the controllable resistive insulating layer 400 along the first direction to the width d2 of the first region 111 along the first direction is between 0.05 and 0.2; the first direction is the direction from the first region 111 to the second region 112; exemplarily, the first direction is... Figure 1 and Figure 2In the xx' direction. By setting the ratio of the width d1 of the controllable resistor insulating layer 400 along the first direction to the width d2 of the first region 111 along the first direction between 0.05 and 0.2, the width ratio of the controllable resistor insulating layer 400 to the width of the first region 111 is reasonable, neither too large nor too small. When the battery is working normally, it can effectively insulate the first conductive structure 200 and the second conductive structure 300. When the battery experiences a hot spot effect, it can also achieve a micro-leakage effect by itself, at least partially conducting part of the first conductive structure 200 and the second conductive structure 300 to alleviate the hot spot effect.

[0073] In some embodiments, the ratio of the width d1 of the controllable resistive insulating layer 400 along the first direction to the width d2 of the first region 111 along the first direction is 0.05. In some embodiments, the ratio of the width d1 of the controllable resistive insulating layer 400 along the first direction to the width d2 of the first region 111 along the first direction is 0.2. In some embodiments, the ratio of the width d1 of the controllable resistive insulating layer 400 along the first direction to the width d2 of the first region 111 along the first direction is 0.1.

[0074] Please see Figure 1 and Figure 2 In some embodiments, the solar cell includes a first transparent conductive layer 500; the first transparent conductive layer 500 is disposed on the side of the first conductive structure 200 facing away from the semiconductor substrate 100; and there is a first gap 710 between the orthographic projection of the first transparent conductive layer 500 and the orthographic projection of the controllable resistance insulating layer 400. By providing the first transparent conductive layer 500, incident light can be transmitted to a greater extent, thereby achieving the function of collecting and transporting charge carriers. The first gap 710 between the orthographic projection of the first transparent conductive layer 500 and the orthographic projection of the controllable resistance insulating layer 400 disconnects them, preventing a short circuit between the first conductive structure 200 and the second conductive structure 300 through the first transparent conductive layer 500.

[0075] Please see Figure 1 and Figure 2In some embodiments, the solar cell includes a second transparent conductive layer 600; the second transparent conductive layer 600 is disposed on the side of the second conductive structure 300 facing away from the semiconductor substrate 100; and there is a second gap 720 between the orthographic projection of the second transparent conductive layer 600 and the orthographic projection of the controllable resistance insulating layer 400. By providing the second transparent conductive layer 600, incident light can be transmitted to a greater extent, thereby achieving the function of collecting and transporting charge carriers. The second gap 720 between the orthographic projection of the second transparent conductive layer 600 and the orthographic projection of the controllable resistance insulating layer 400 disconnects them, preventing a short circuit between the first conductive structure 200 and the second conductive structure 300 through the second transparent conductive layer 600.

[0076] Please see Figure 1 In some embodiments, the first conductive structure 200 includes a first passivation layer 210 and a first doped semiconductor layer 220 stacked together; and the first passivation layer 210 is disposed between the first doped semiconductor layer 220 and the semiconductor substrate 100. Through the cooperation of the first passivation layer 210 and the first doped semiconductor layer 220, the technical effects of efficient carrier selective collection and surface passivation in the first region 111 are achieved.

[0077] In some embodiments, the first passivation layer 210 may be a tunneling passivation layer or an intrinsic amorphous silicon layer.

[0078] In some embodiments, the first doped semiconductor layer 220 may be at least one of a doped polycrystalline silicon layer, a doped monocrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0079] Please see Figure 1 In some embodiments, the second conductive structure 300 includes a second passivation layer 310 and a second doped semiconductor layer 320 stacked together; and the second passivation layer 310 is disposed on the side of the second doped semiconductor layer 320 close to the semiconductor substrate 100. Through the cooperation of the second passivation layer 310 and the second doped semiconductor layer 320, the technical effects of efficient carrier selective collection and surface passivation in the second region 112 are achieved.

[0080] In some embodiments, the second passivation layer 310 may be a tunneling passivation layer or an intrinsic amorphous silicon layer.

[0081] In some embodiments, the second doped semiconductor layer 320 may be at least one of a doped polycrystalline silicon layer, a doped monocrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0082] Please see Figure 2In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 perpendicular to the first surface 110 and the thickness h2 of the second passivation layer 310 perpendicular to the first surface 110 satisfy the condition: 0.5h2≤h1≤h2.

[0083] By limiting the thickness h1 of the controllable resistance insulating layer 400 along the perpendicular side 110 to be greater than or equal to 0.5 times h2 and less than or equal to 1 times h2, the thickness ratio of the controllable resistance insulating layer 400 to the second passivation layer 310 is more reasonable, which can achieve better micro-leakage effect.

[0084] In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 perpendicular to the first surface 110 is equal to 0.5 times the thickness h2 of the second passivation layer 310 perpendicular to the first surface 110. In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 perpendicular to the first surface 110 is equal to the thickness h2 of the second passivation layer 310 perpendicular to the first surface 110. In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 perpendicular to the first surface 110 is equal to 0.8 times the thickness h2 of the second passivation layer 310 perpendicular to the first surface 110.

[0085] Please see Figure 1 and Figure 2 In some embodiments, the second passivation layer 310 includes a first sublayer 311, a second sublayer 312, and a third sublayer 313 connected in sequence; the first sublayer 311 is in contact with the semiconductor substrate 100; the second sublayer 312 extends along a first direction, which intersects the extension direction of the first surface 110; the third sublayer 313 is in contact with the side of the controllable resistance insulating layer 400 opposite to the first conductive structure 200. In fabricating the solar cell provided in this application embodiment, by first depositing and forming the controllable resistance insulating layer 400, and then depositing and forming the second passivation layer 310, the second passivation layer 310 can form the first sublayer 311, the second sublayer 312, and the third sublayer 313 in different deposited regions. That is, the controllable resistance insulating layer 400 is prepared first. This allows the controllable resistance insulating layer 400 to act as a sacrificial layer for the first region 111 during laser etching, thereby protecting the first conductive structure 200 of the first region 111.

[0086] Please see Figure 1 and Figure 2In some embodiments, the controllable resistance insulating layer 400 is in contact with the second sublayer 312 on the side near the second conductive structure 300. This is achieved by first depositing the controllable resistance insulating layer 400 and then depositing the second passivation layer 310, thus ensuring that the side of the controllable resistance insulating layer 400 near the second conductive structure 300 is in contact with the second sublayer 312. When a hot spot effect occurs in the battery, a micro-leakage will occur between the controllable resistance insulating layer 400 and the second sublayer 312, thereby mitigating the damage caused by the hot spot effect to the battery.

[0087] Please see Figure 1 and Figure 2 In some embodiments, the controllable resistance insulating layer 400 is a continuous structure. By setting the controllable resistance insulating layer 400 as a continuous structure, the processing and preparation of the controllable resistance insulating layer 400 is simpler and more convenient. Compared with the traditional structure that achieves current conduction by laser grooving, surface plating of composite layers, or embedding micron-sized copper foil, the processing and preparation is simpler, the time required for the preparation process is reduced, and the cost is lower.

[0088] This application discloses a method for fabricating a solar cell; please refer to [link to relevant documentation]. Figure 11 , Figure 11 The flowchart illustrates a method for fabricating a solar cell according to some embodiments of this application. The method for fabricating a solar cell includes:

[0089] S10: Forming a semiconductor substrate 100;

[0090] S20: A first conductive structure 200 is formed in a first region 111 of a first surface 110 of a semiconductor substrate 100;

[0091] S30: A controllable resistance insulating layer 400 is formed in a predetermined region on the side of the first conductive structure 200 away from the semiconductor substrate 100.

[0092] S40: A second conductive structure 300 is formed on the side of the controllable resistance insulating layer 400 away from the first conductive structure 200 and in the second region 112 of the first surface 110; wherein, the preset region is the overlapping area of ​​the first conductive structure 200 and the second conductive structure 300, and the second region 112 and the first region 111 are arranged alternately.

[0093] After the first conductive structure 200 is fabricated, a controllable resistance insulating structure is formed on the side of the first conductive structure 200 away from the semiconductor substrate 100. Through processing, a controllable resistance insulating layer 400 is finally formed in a preset area, and a second conductive structure 300 is finally formed in the second region 112 of the semiconductor substrate 100. Since the controllable resistance insulating layer 400 is located in the overlapping area of ​​the first conductive structure 200 and the second conductive structure 300, micro-leakage can be achieved by the controllable resistance insulating layer 400 itself, thereby alleviating the hot spot effect of the solar cell and making the overall power generation efficiency of the solar cell more stable. Furthermore, since the controllable resistance insulating layer 400 is relatively easy to fabricate, the fabrication time required is reduced, and the cost is low.

[0094] In some embodiments, the step of forming a controllable resistance insulating layer 400 in a predetermined region on the side of the first conductive structure 200 facing away from the semiconductor substrate 100 specifically includes:

[0095] Forming a crystalline silicon substrate;

[0096] Boron is doped onto a crystalline silicon substrate to form a controllable resistance insulating layer 400, wherein the boron doping current is greater than 0 and less than 2000 sccm, and the crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon, or nanocrystalline silicon; or

[0097] A phosphorus-doped layer 400 is formed on a crystalline silicon substrate to form a controllable resistance insulating layer, wherein the phosphorus doping current is greater than 0 and less than 2000 sccm, and the crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon or nanocrystalline silicon.

[0098] When region 111 is an N-region and region 112 is a P-region, boron is doped onto the crystalline silicon substrate. When region 111 is a P-region and region 112 is an N-region, phosphorus is doped onto the crystalline silicon substrate.

[0099] A controllable resistance insulating layer 400 is formed by doping boron or phosphorus on a crystalline silicon substrate, with the boron or phosphorus doping flux being greater than 0 and less than 2000 sccm, thereby ensuring that the concentration of the doped elements in the final controllable resistance insulating layer 400 is between 5E18 and 1E21 at / cm. 3 The doping concentration is thus appropriately balanced, neither too high, resulting in a large short-circuit current between the first conductive structure 200 and the second conductive structure 300, nor too low, weakening the micro-leakage effect. This range of doping concentration allows for the formation of a weak PN junction between the controllable resistivity insulating layer 400 and the first region 111, achieving the micro-leakage effect. Within this range, differences between solar cells and batches can also be reduced, ensuring that the resistance of the controllable resistivity insulating layer 400 fluctuates slightly within a certain range, which is beneficial for processing and preparation on actual production lines.

[0100] It should be understood that, in the embodiments of this application, at least some steps in the preparation method may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0101] The following reference Figures 3-10 Instructions for preparation as follows Figure 1 The steps of the solar cell shown are illustrated below:

[0102] In this embodiment, the semiconductor substrate 100 is a single-crystal N-type silicon wafer. Of course, in other embodiments, it can also be other types, such as P-type silicon wafers, etc., and there is no special limitation on this.

[0103] (1) The semiconductor substrate 100 is polished using a tank polishing machine. A double-sided polished wafer with a base size of 15-30 μm is formed on the surface of the semiconductor substrate 100, and the final morphology is as follows. Figure 3 As shown.

[0104] (2) On the first surface 110 of the semiconductor substrate 100, that is, the backlight surface, a first passivation layer 210 and an intrinsic polysilicon layer are formed inside the phosphorus diffusion furnace tube. The thickness of the first passivation layer 210 is 1.2-1.8 nm, and the thickness of the intrinsic polysilicon layer is 90-300 nm.

[0105] (3) In the phosphorus expansion furnace tube, the intrinsic polycrystalline silicon layer is doped to form a first doped semiconductor layer 220. The first doped semiconductor layer 220 can be an N-type polycrystalline silicon material layer, and a phosphorus silicon glass layer is formed on the surface of the first doped semiconductor layer 220.

[0106] (4) In a tank cleaning machine, the phosphosilicate glass on the surface of the semiconductor substrate 100 is cleaned, and RCA cleaning is performed on the surface of the semiconductor substrate 100 at the same time. After removing the phosphosilicate glass, the sheet resistance is 30Ω / sq-70Ω / sq, and the final morphology is as follows. Figure 4 As shown.

[0107] (5) On the first surface 110 of the semiconductor substrate 100, a controllable resistance insulating structure and a mask 410 are deposited by PECVD. The thickness of the controllable resistance insulating structure can be 5-15 nm, and the boron doping flux is 0-2000 / or the p doping flux is 0-2000. The thickness of the mask 410 can be 70-110 nm, and the mask 410 can be a silicon nitride mask 410. The final morphology is as follows: Figure 5 As shown.

[0108] (6) A laser is used to pattern the controllable resistive insulating structure and the mask 410, exposing the second region 112, which is the region corresponding to the P+ region. The remaining part of the first passivation layer 210 and the first doped semiconductor layer 220 form the first conductive structure 200, with the final morphology as shown. Figure 6 As shown.

[0109] (7) The chain cleaning machine removes the controllable resistance insulation structure and the winding of the mask plate 410. In the tank cleaning machine, the slotted area of ​​the first surface 110 and the second surface 120 are subjected to a flocking process to make a small flocked structure. Finally, the mask plate 410 is removed or partially removed in the HF tank, and the final morphology is as follows. Figure 7 As shown.

[0110] (8) In the CVD equipment, a third passivation layer 910 is deposited on the second surface 120. The third passivation layer 910 can be an intrinsic amorphous silicon layer, and the thickness of the third passivation layer 910 can be 5-20 nm. Subsequently, a second passivation layer 310 and a second doped semiconductor layer 320 are deposited sequentially on the first surface 110. The second passivation layer 310 can be an intrinsic amorphous silicon layer, and the thickness of the second passivation layer 310 can be 5-20 nm. The second doped semiconductor layer 320 can be a boron-doped amorphous silicon layer, and the thickness of the second doped semiconductor layer 320 can be 15-35 nm. Finally, a fourth passivation layer 920 is deposited on the second surface 120. The fourth passivation layer 920 can be a silicon nitride layer, and the thickness of the fourth passivation layer 920 can be 70-85 nm. The final morphology is as follows. Figure 8 As shown.

[0111] (9) A laser is used to remove or partially remove the second passivation layer 310 and the second doped semiconductor layer 320 deposited on the surface of the first region 111 (N+ region), exposing the area where the first semiconductor layer contacts the first transparent conductive layer 500. The second passivation layer 310 and the second doped semiconductor layer 320 above the second region 112 (P+ region) form the second conductive structure 300. During this laser processing, the controllable resistance insulating layer 400 can serve as a sacrificial layer for the first region 111, thereby protecting the first conductive structure 200 of the first region 111 and ensuring the passivation effect of the first conductive structure 200.

[0112] (10) In the chain cleaning machine, the first side 110 of the battery cell is placed face down into the HF tank to remove the oxide layer and controllable resistance insulation structure in the laser grooving area of ​​step (9). Finally, it is placed in the water tank for cleaning and drying, and the final morphology is as follows. Figure 9 As shown.

[0113] (11) In a PVD apparatus, a transparent conductive structure is formed on the surface of the first surface 110. The thickness of the transparent conductive structure can be 70-100 nm.

[0114] (12) Use screen printing to print etching paste on the isolation area. The isolation area can be located at the junction of the P+ / N+ area or above the N+ area. The location of the isolation area is the area of ​​the first spacing and the second spacing.

[0115] (13) Use a tank cleaning machine to clean the tank. Figure 9 The solar cell structure shown is immersed in a low concentration of alkali and hydrogen peroxide to remove the etching paste and the transparent conductive structure beneath it in step (12) to complete the P+ / N+ insulation. This results in the formation of a first transparent conductive layer 500 and a second transparent conductive layer 600. A first gap exists between the orthographic projection of the first transparent conductive layer 500 and the orthographic projection of the controllable resistance insulating layer 400, and a second gap exists between the orthographic projection of the second transparent conductive layer 600 and the orthographic projection of the controllable resistance insulating layer 400. The final morphology is as follows: Figure 10 As shown.

[0116] (14) Using screen printing, the sub-gate of the first electrode 810 and the sub-gate of the second electrode 820 are formed. After drying, insulating adhesive is printed at positions of different polarities to complete the insulation between the main and sub-gates of different polarities. After drying, the main gate is printed, and finally cured. The collection of electrons and holes is completed, and the final solar cell structure is as follows: Figure 1 As shown.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, The solar cell includes: The semiconductor substrate (100) includes a first surface (110) and a second surface (120) disposed opposite to each other, wherein the first surface (110) includes an alternately arranged first region (111) and a second region (112). The first conductive structure (200) is at least provided in the first region (111). The second conductive structure (300) is at least provided in the second region (112); the conductivity type of the first conductive structure (200) is opposite to that of the second conductive structure (300); the first conductive structure (200) and the second conductive structure (300) have an overlapping area along the direction perpendicular to the first surface (110); A controllable resistance insulating layer (400) is located in the overlapping area and disposed between the first conductive structure (200) and the second conductive structure (300).

2. The solar cell according to claim 1, characterized in that, The controllable resistance insulating layer (400) is a doped semiconductor layer; the doping element of the doped semiconductor layer is boron or phosphorus, and the concentration of the doping element is 5E18-1E21 at / cm³. 3 .

3. The solar cell according to claim 1, characterized in that, In the overlapping area, along a direction perpendicular to the first surface (110), the second conductive structure (300), the controllable resistance insulating layer (400), and the first conductive structure (200) are stacked sequentially, and the first conductive structure (200) is disposed on the side close to the semiconductor substrate (100). The side of the controllable resistance insulating layer (400) near the second conductive structure (300) is flush with the end face of the first conductive structure (200) near the second conductive structure (300).

4. The solar cell according to claim 1, characterized in that, In the overlapping area, along a direction perpendicular to the first surface (110), the second conductive structure (300), the controllable resistance insulating layer (400), and the first conductive structure (200) are stacked sequentially, and the first conductive structure (200) is disposed on the side close to the semiconductor substrate (100). The side of the controllable resistance insulating layer (400) near the first conductive structure (200) is flush with the end face of the second conductive structure (300) near the first conductive structure (200).

5. The solar cell according to claim 1, characterized in that, The controllable resistance insulating layer (400) along its thickness h1 perpendicular to the first surface (110) satisfies the following condition: 5nm≤h1≤15nm.

6. The solar cell according to claim 1, characterized in that, The ratio of the width d1 of the controllable resistance insulating layer (400) along the first direction to the width d2 of the first region (111) along the first direction is between 0.05 and 0.2; the first direction is the direction from the first region (111) to the second region (112).

7. The solar cell according to claim 1, characterized in that, The solar cell includes a first transparent conductive layer (500); The first transparent conductive layer (500) is disposed on the side of the first conductive structure (200) away from the semiconductor substrate (100); and there is a first gap (710) between the orthographic projection of the first transparent conductive layer (500) and the orthographic projection of the controllable resistance insulating layer (400).

8. The solar cell according to claim 1, characterized in that, The solar cell includes a second transparent conductive layer (600). The second transparent conductive layer (600) is disposed on the side of the second conductive structure (300) away from the semiconductor substrate (100); and there is a second spacing (720) between the orthographic projection of the second transparent conductive layer (600) and the orthographic projection of the controllable resistance insulating layer (400).

9. The solar cell according to claim 1, characterized in that, The first conductive structure (200) includes a first passivation layer (210) and a first doped semiconductor layer (220) stacked together; and the first passivation layer (210) is disposed between the first doped semiconductor layer (220) and the semiconductor substrate (100).

10. The solar cell according to claim 9, characterized in that, The second conductive structure (300) includes a second passivation layer (310) and a second doped semiconductor layer (320) stacked together; and the second passivation layer (310) is disposed on the side of the second doped semiconductor layer (320) close to the semiconductor substrate (100).

11. The solar cell according to claim 10, characterized in that, The thickness h1 of the controllable resistance insulating layer (400) perpendicular to the first surface (110) and the thickness h2 of the second passivation layer (310) perpendicular to the first surface (110) satisfy the following condition: 0.5h2≤h1≤h2.

12. The solar cell according to claim 10, characterized in that, The second passivation layer (310) includes a first sublayer (311), a second sublayer (312), and a third sublayer (313) connected in sequence. The first sublayer (311) is in contact with the semiconductor substrate (100); The second sublayer (312) extends along a first direction, which intersects the extension direction of the first surface (110); The third sublayer (313) is in contact with the side of the controllable resistance insulating layer (400) opposite to the first conductive structure (200).

13. The solar cell according to claim 12, characterized in that, The controllable resistance insulating layer (400) is in contact with the second sublayer (312) on the side near the second conductive structure (300).

14. The solar cell according to any one of claims 1-11, characterized in that, The controllable resistance insulating layer (400) has a continuous structure.

15. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell includes: Forming a semiconductor substrate (100); A first conductive structure (200) is formed in a first region (111) of a first surface (110) of the semiconductor substrate (100). A controllable resistance insulating layer (400) is formed in a predetermined region on the side of the first conductive structure (200) opposite to the semiconductor substrate (100). A second conductive structure (300) is formed on the side of the controllable resistance insulating layer (400) opposite to the first conductive structure (200) and in the second region (112) of the first surface (110). The preset area is the overlapping area of ​​the first conductive structure (200) and the second conductive structure (300), and the second area (112) and the first area (111) are arranged alternately.

16. The method for preparing a solar cell according to claim 15, characterized in that, The step of forming a controllable resistance insulating layer (400) in a predetermined region on the side of the first conductive structure (200) opposite to the semiconductor substrate (100) specifically includes: Forming a crystalline silicon substrate; Boron is doped onto the crystalline silicon substrate to form the controllable resistance insulating layer (400), and the boron doping current is greater than 0 and less than 2000 sccm. The crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon, or nanocrystalline silicon; or The controllable resistance insulating layer (400) is formed by doping phosphorus on the crystalline silicon substrate, and the phosphorus doping flow rate is greater than 0 and less than 2000 sccm. The crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon or nanocrystalline silicon.

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